5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 * Linux IPU driver for MX51:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <linux/types.h>
33 #include <linux/err.h>
35 #include <asm/errno.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
41 extern struct mxc_ccm_reg *mxc_ccm;
42 extern u32 *ipu_cpmem_base;
44 struct ipu_ch_param_word {
50 struct ipu_ch_param_word word[2];
53 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
55 #define _param_word(base, w) \
56 (((struct ipu_ch_param *)(base))->word[(w)].data)
58 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
60 int off = (bit) % 32; \
61 _param_word(base, w)[i] |= (v) << off; \
62 if (((bit) + (size) - 1) / 32 > i) { \
63 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
67 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
69 int off = (bit) % 32; \
70 u32 mask = (1UL << size) - 1; \
71 u32 temp = _param_word(base, w)[i]; \
72 temp &= ~(mask << off); \
73 _param_word(base, w)[i] = temp | (v) << off; \
74 if (((bit) + (size) - 1) / 32 > i) { \
75 temp = _param_word(base, w)[i + 1]; \
76 temp &= ~(mask >> (32 - off)); \
77 _param_word(base, w)[i + 1] = \
78 temp | ((v) >> (off ? (32 - off) : 0)); \
82 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
85 int off = (bit) % 32; \
86 u32 mask = (1UL << size) - 1; \
87 u32 temp1 = _param_word(base, w)[i]; \
88 temp1 = mask & (temp1 >> off); \
89 if (((bit)+(size) - 1) / 32 > i) { \
90 temp2 = _param_word(base, w)[i + 1]; \
91 temp2 &= mask >> (off ? (32 - off) : 0); \
92 temp1 |= temp2 << (off ? (32 - off) : 0); \
98 void clk_enable(struct clk *clk)
101 if (clk->usecount++ == 0) {
107 void clk_disable(struct clk *clk)
110 if (!(--clk->usecount)) {
117 int clk_get_usecount(struct clk *clk)
122 return clk->usecount;
125 u32 clk_get_rate(struct clk *clk)
133 struct clk *clk_get_parent(struct clk *clk)
141 int clk_set_rate(struct clk *clk, unsigned long rate)
143 if (clk && clk->set_rate)
144 clk->set_rate(clk, rate);
148 long clk_round_rate(struct clk *clk, unsigned long rate)
150 if (clk == NULL || !clk->round_rate)
153 return clk->round_rate(clk, rate);
156 int clk_set_parent(struct clk *clk, struct clk *parent)
158 clk->parent = parent;
160 return clk->set_parent(clk, parent);
164 static int clk_ipu_enable(struct clk *clk)
166 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
169 reg = __raw_readl(clk->enable_reg);
170 reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
171 __raw_writel(reg, clk->enable_reg);
173 /* Handshake with IPU when certain clock rates are changed. */
174 reg = __raw_readl(&mxc_ccm->ccdr);
175 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
176 __raw_writel(reg, &mxc_ccm->ccdr);
178 /* Handshake with IPU when LPM is entered as its enabled. */
179 reg = __raw_readl(&mxc_ccm->clpcr);
180 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
181 __raw_writel(reg, &mxc_ccm->clpcr);
186 static void clk_ipu_disable(struct clk *clk)
188 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
191 reg = __raw_readl(clk->enable_reg);
192 reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
193 __raw_writel(reg, clk->enable_reg);
196 * No handshake with IPU whe dividers are changed
197 * as its not enabled.
199 reg = __raw_readl(&mxc_ccm->ccdr);
200 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
201 __raw_writel(reg, &mxc_ccm->ccdr);
203 /* No handshake with IPU when LPM is entered as its not enabled. */
204 reg = __raw_readl(&mxc_ccm->clpcr);
205 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
206 __raw_writel(reg, &mxc_ccm->clpcr);
211 static struct clk ipu_clk = {
214 .enable_reg = (u32 *)(CCM_BASE_ADDR +
215 offsetof(struct mxc_ccm_reg, CCGR5)),
216 .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
217 .enable = clk_ipu_enable,
218 .disable = clk_ipu_disable,
223 struct clk *g_ipu_clk;
224 unsigned char g_ipu_clk_enabled;
225 struct clk *g_di_clk[2];
226 struct clk *g_pixel_clk[2];
227 unsigned char g_dc_di_assignment[10];
228 uint32_t g_channel_init_mask;
229 uint32_t g_channel_enable_mask;
231 static int ipu_dc_use_count;
232 static int ipu_dp_use_count;
233 static int ipu_dmfc_use_count;
234 static int ipu_di_use_count[2];
237 u32 *ipu_dc_tmpl_reg;
239 /* Static functions */
241 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
243 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
246 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
248 return ((uint32_t) ch >> (6 * type)) & 0x3F;
251 /* Either DP BG or DP FG can be graphic window */
252 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
254 return (dma_chan == 23 || dma_chan == 27);
257 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
259 return ((dma_chan >= 23) && (dma_chan <= 29));
263 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
266 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
270 #define idma_is_valid(ch) (ch != NO_DMA)
271 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
272 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
274 static void ipu_pixel_clk_recalc(struct clk *clk)
276 u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
280 clk->rate = (clk->parent->rate * 16) / div;
283 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
290 * Fractional part is 4 bits,
291 * so simply multiply by 2^4 to get fractional part.
293 tmp = (clk->parent->rate * 16);
296 if (div < 0x10) /* Min DI disp clock divider is 1 */
302 if ((tmp/div1 - tmp/div) < rate / 4)
307 return (clk->parent->rate * 16) / div;
310 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
312 u32 div = (clk->parent->rate * 16) / rate;
314 __raw_writel(div, DI_BS_CLKGEN0(clk->id));
316 /* Setup pixel clock timing */
317 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
319 clk->rate = (clk->parent->rate * 16) / div;
323 static int ipu_pixel_clk_enable(struct clk *clk)
325 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
326 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
327 __raw_writel(disp_gen, IPU_DISP_GEN);
332 static void ipu_pixel_clk_disable(struct clk *clk)
334 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
335 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
336 __raw_writel(disp_gen, IPU_DISP_GEN);
340 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
342 u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
344 if (parent == g_ipu_clk)
345 di_gen &= ~DI_GEN_DI_CLK_EXT;
346 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
347 di_gen |= DI_GEN_DI_CLK_EXT;
351 __raw_writel(di_gen, DI_GENERAL(clk->id));
352 ipu_pixel_clk_recalc(clk);
356 static struct clk pixel_clk[] = {
360 .recalc = ipu_pixel_clk_recalc,
361 .set_rate = ipu_pixel_clk_set_rate,
362 .round_rate = ipu_pixel_clk_round_rate,
363 .set_parent = ipu_pixel_clk_set_parent,
364 .enable = ipu_pixel_clk_enable,
365 .disable = ipu_pixel_clk_disable,
371 .recalc = ipu_pixel_clk_recalc,
372 .set_rate = ipu_pixel_clk_set_rate,
373 .round_rate = ipu_pixel_clk_round_rate,
374 .set_parent = ipu_pixel_clk_set_parent,
375 .enable = ipu_pixel_clk_enable,
376 .disable = ipu_pixel_clk_disable,
382 * This function resets IPU
389 reg = (u32 *)SRC_BASE_ADDR;
390 value = __raw_readl(reg);
391 value = value | SW_IPU_RST;
392 __raw_writel(value, reg);
396 * This function is called by the driver framework to initialize the IPU
399 * @param dev The device structure for the IPU passed in by the
402 * @return Returns 0 on success or negative error code on error
406 unsigned long ipu_base;
407 #if defined CONFIG_MX51
410 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
411 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
413 __raw_writel(0xF00, reg_hsc_mcd);
415 /* CSI mode reserved*/
416 temp = __raw_readl(reg_hsc_mxt_conf);
417 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
419 temp = __raw_readl(reg_hsc_mxt_conf);
420 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
423 ipu_base = IPU_CTRL_BASE_ADDR;
424 ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
425 ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
427 g_pixel_clk[0] = &pixel_clk[0];
428 g_pixel_clk[1] = &pixel_clk[1];
430 g_ipu_clk = &ipu_clk;
431 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
435 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
436 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
437 clk_enable(g_ipu_clk);
442 __raw_writel(0x807FFFFF, IPU_MEM_RST);
443 while (__raw_readl(IPU_MEM_RST) & 0x80000000)
446 ipu_init_dc_mappings();
448 __raw_writel(0, IPU_INT_CTRL(5));
449 __raw_writel(0, IPU_INT_CTRL(6));
450 __raw_writel(0, IPU_INT_CTRL(9));
451 __raw_writel(0, IPU_INT_CTRL(10));
454 ipu_dmfc_init(DMFC_NORMAL, 1);
456 /* Set sync refresh channels as high priority */
457 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
459 /* Set MCU_T to divide MCU access window into 2 */
460 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
462 clk_disable(g_ipu_clk);
467 void ipu_dump_registers(void)
469 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
470 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
471 debug("IDMAC_CHA_EN1 = \t0x%08X\n",
472 __raw_readl(IDMAC_CHA_EN(0)));
473 debug("IDMAC_CHA_EN2 = \t0x%08X\n",
474 __raw_readl(IDMAC_CHA_EN(32)));
475 debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
476 __raw_readl(IDMAC_CHA_PRI(0)));
477 debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
478 __raw_readl(IDMAC_CHA_PRI(32)));
479 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
480 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
481 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
482 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
483 debug("DMFC_WR_CHAN = \t0x%08X\n",
484 __raw_readl(DMFC_WR_CHAN));
485 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
486 __raw_readl(DMFC_WR_CHAN_DEF));
487 debug("DMFC_DP_CHAN = \t0x%08X\n",
488 __raw_readl(DMFC_DP_CHAN));
489 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
490 __raw_readl(DMFC_DP_CHAN_DEF));
491 debug("DMFC_IC_CTRL = \t0x%08X\n",
492 __raw_readl(DMFC_IC_CTRL));
493 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
494 __raw_readl(IPU_FS_PROC_FLOW1));
495 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
496 __raw_readl(IPU_FS_PROC_FLOW2));
497 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
498 __raw_readl(IPU_FS_PROC_FLOW3));
499 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
500 __raw_readl(IPU_FS_DISP_FLOW1));
504 * This function is called to initialize a logical IPU channel.
506 * @param channel Input parameter for the logical channel ID to init.
508 * @param params Input parameter containing union of channel
509 * initialization parameters.
511 * @return Returns 0 on success or negative error code on fail
513 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
518 debug("init channel = %d\n", IPU_CHAN_ID(channel));
520 if (g_ipu_clk_enabled == 0) {
521 g_ipu_clk_enabled = 1;
522 clk_enable(g_ipu_clk);
526 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
527 printf("Warning: channel already initialized %d\n",
528 IPU_CHAN_ID(channel));
531 ipu_conf = __raw_readl(IPU_CONF);
535 if (params->mem_dc_sync.di > 1) {
540 g_dc_di_assignment[1] = params->mem_dc_sync.di;
541 ipu_dc_init(1, params->mem_dc_sync.di,
542 params->mem_dc_sync.interlaced);
543 ipu_di_use_count[params->mem_dc_sync.di]++;
545 ipu_dmfc_use_count++;
548 if (params->mem_dp_bg_sync.di > 1) {
553 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
554 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
555 params->mem_dp_bg_sync.out_pixel_fmt);
556 ipu_dc_init(5, params->mem_dp_bg_sync.di,
557 params->mem_dp_bg_sync.interlaced);
558 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
561 ipu_dmfc_use_count++;
564 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
565 params->mem_dp_fg_sync.out_pixel_fmt);
569 ipu_dmfc_use_count++;
572 printf("Missing channel initialization\n");
576 /* Enable IPU sub module */
577 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
578 if (ipu_dc_use_count == 1)
579 ipu_conf |= IPU_CONF_DC_EN;
580 if (ipu_dp_use_count == 1)
581 ipu_conf |= IPU_CONF_DP_EN;
582 if (ipu_dmfc_use_count == 1)
583 ipu_conf |= IPU_CONF_DMFC_EN;
584 if (ipu_di_use_count[0] == 1) {
585 ipu_conf |= IPU_CONF_DI0_EN;
587 if (ipu_di_use_count[1] == 1) {
588 ipu_conf |= IPU_CONF_DI1_EN;
591 __raw_writel(ipu_conf, IPU_CONF);
598 * This function is called to uninitialize a logical IPU channel.
600 * @param channel Input parameter for the logical channel ID to uninit.
602 void ipu_uninit_channel(ipu_channel_t channel)
605 uint32_t in_dma, out_dma = 0;
608 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
609 debug("Channel already uninitialized %d\n",
610 IPU_CHAN_ID(channel));
615 * Make sure channel is disabled
616 * Get input and output dma channels
618 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
619 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
621 if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
622 idma_is_set(IDMAC_CHA_EN, out_dma)) {
624 "Channel %d is not disabled, disable first\n",
625 IPU_CHAN_ID(channel));
629 ipu_conf = __raw_readl(IPU_CONF);
631 /* Reset the double buffer */
632 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
633 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
634 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
635 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
640 ipu_di_use_count[g_dc_di_assignment[1]]--;
642 ipu_dmfc_use_count--;
645 ipu_dp_uninit(channel);
647 ipu_di_use_count[g_dc_di_assignment[5]]--;
650 ipu_dmfc_use_count--;
653 ipu_dp_uninit(channel);
656 ipu_dmfc_use_count--;
662 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
664 if (ipu_dc_use_count == 0)
665 ipu_conf &= ~IPU_CONF_DC_EN;
666 if (ipu_dp_use_count == 0)
667 ipu_conf &= ~IPU_CONF_DP_EN;
668 if (ipu_dmfc_use_count == 0)
669 ipu_conf &= ~IPU_CONF_DMFC_EN;
670 if (ipu_di_use_count[0] == 0) {
671 ipu_conf &= ~IPU_CONF_DI0_EN;
673 if (ipu_di_use_count[1] == 0) {
674 ipu_conf &= ~IPU_CONF_DI1_EN;
677 __raw_writel(ipu_conf, IPU_CONF);
680 clk_disable(g_ipu_clk);
681 g_ipu_clk_enabled = 0;
686 static inline void ipu_ch_param_dump(int ch)
689 struct ipu_ch_param *p = ipu_ch_param_addr(ch);
690 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
691 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
692 p->word[0].data[3], p->word[0].data[4]);
693 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
694 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
695 p->word[1].data[3], p->word[1].data[4]);
697 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
699 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
701 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
704 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
706 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
708 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
710 debug("Width0 %d+1, ",
711 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
712 debug("Width1 %d+1, ",
713 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
714 debug("Width2 %d+1, ",
715 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
716 debug("Width3 %d+1, ",
717 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
718 debug("Offset0 %d, ",
719 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
720 debug("Offset1 %d, ",
721 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
722 debug("Offset2 %d, ",
723 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
724 debug("Offset3 %d\n",
725 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
729 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
730 int red_width, int red_offset,
731 int green_width, int green_offset,
732 int blue_width, int blue_offset,
733 int alpha_width, int alpha_offset)
735 /* Setup red width and offset */
736 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
737 ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
738 /* Setup green width and offset */
739 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
740 ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
741 /* Setup blue width and offset */
742 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
743 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
744 /* Setup alpha width and offset */
745 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
746 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
749 static void ipu_ch_param_init(int ch,
750 uint32_t pixel_fmt, uint32_t width,
751 uint32_t height, uint32_t stride,
752 uint32_t u, uint32_t v,
753 uint32_t uv_stride, dma_addr_t addr0,
756 uint32_t u_offset = 0;
757 uint32_t v_offset = 0;
758 struct ipu_ch_param params;
760 memset(¶ms, 0, sizeof(params));
762 ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1);
764 if ((ch == 8) || (ch == 9) || (ch == 10)) {
765 ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1);
766 ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1);
768 ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1);
769 ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1);
772 ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3);
773 ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3);
776 case IPU_PIX_FMT_GENERIC:
777 /*Represents 8-bit Generic data */
778 ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */
779 ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */
780 ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */
783 case IPU_PIX_FMT_GENERIC_32:
784 /*Represents 32-bit Generic data */
786 case IPU_PIX_FMT_RGB565:
787 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
788 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
789 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
791 ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16);
793 case IPU_PIX_FMT_BGR24:
794 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
795 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
796 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
798 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
800 case IPU_PIX_FMT_RGB24:
801 case IPU_PIX_FMT_YUV444:
802 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
803 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
804 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
806 ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24);
808 case IPU_PIX_FMT_BGRA32:
809 case IPU_PIX_FMT_BGR32:
810 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
811 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
812 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
814 ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0);
816 case IPU_PIX_FMT_RGBA32:
817 case IPU_PIX_FMT_RGB32:
818 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
819 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
820 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
822 ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0);
824 case IPU_PIX_FMT_ABGR32:
825 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
826 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
828 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
830 case IPU_PIX_FMT_UYVY:
831 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
832 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */
833 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
835 case IPU_PIX_FMT_YUYV:
836 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
837 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */
838 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
840 case IPU_PIX_FMT_YUV420P2:
841 case IPU_PIX_FMT_YUV420P:
842 ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */
844 if (uv_stride < stride / 2)
845 uv_stride = stride / 2;
847 u_offset = stride * height;
848 v_offset = u_offset + (uv_stride * height / 2);
850 if ((ch == 8) || (ch == 9) || (ch == 10)) {
851 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15);
852 uv_stride = uv_stride*2;
854 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31);
857 case IPU_PIX_FMT_YVU422P:
858 /* BPP & pixel format */
859 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
860 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
862 if (uv_stride < stride / 2)
863 uv_stride = stride / 2;
865 v_offset = (v == 0) ? stride * height : v;
866 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
868 case IPU_PIX_FMT_YUV422P:
869 /* BPP & pixel format */
870 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
871 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
873 if (uv_stride < stride / 2)
874 uv_stride = stride / 2;
876 u_offset = (u == 0) ? stride * height : u;
877 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
879 case IPU_PIX_FMT_NV12:
880 /* BPP & pixel format */
881 ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */
882 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
884 u_offset = (u == 0) ? stride * height : u;
887 puts("mxc ipu: unimplemented pixel format\n");
893 ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1);
895 /* Get the uv offset from user when need cropping */
901 /* UBO and VBO are 22-bit */
902 if (u_offset/8 > 0x3fffff)
903 puts("The value of U offset exceeds IPU limitation\n");
904 if (v_offset/8 > 0x3fffff)
905 puts("The value of V offset exceeds IPU limitation\n");
907 ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8);
908 ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8);
910 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
911 memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params));
915 * This function is called to initialize a buffer for logical IPU channel.
917 * @param channel Input parameter for the logical channel ID.
919 * @param type Input parameter which buffer to initialize.
921 * @param pixel_fmt Input parameter for pixel format of buffer.
922 * Pixel format is a FOURCC ASCII code.
924 * @param width Input parameter for width of buffer in pixels.
926 * @param height Input parameter for height of buffer in pixels.
928 * @param stride Input parameter for stride length of buffer
931 * @param phyaddr_0 Input parameter buffer 0 physical address.
933 * @param phyaddr_1 Input parameter buffer 1 physical address.
934 * Setting this to a value other than NULL enables
935 * double buffering mode.
937 * @param u private u offset for additional cropping,
940 * @param v private v offset for additional cropping,
943 * @return Returns 0 on success or negative error code on fail
945 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
947 uint16_t width, uint16_t height,
949 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
950 uint32_t u, uint32_t v)
955 dma_chan = channel_2_dma(channel, type);
956 if (!idma_is_valid(dma_chan))
959 if (stride < width * bytes_per_pixel(pixel_fmt))
960 stride = width * bytes_per_pixel(pixel_fmt);
964 "Stride not 32-bit aligned, stride = %d\n", stride);
967 /* Build parameter memory data for DMA channel */
968 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
969 phyaddr_0, phyaddr_1);
971 if (ipu_is_dmfc_chan(dma_chan)) {
972 ipu_dmfc_set_wait4eot(dma_chan, width);
975 if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
976 ipu_ch_param_set_high_priority(dma_chan);
978 ipu_ch_param_dump(dma_chan);
980 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
982 reg |= idma_mask(dma_chan);
984 reg &= ~idma_mask(dma_chan);
985 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
987 /* Reset to buffer 0 */
988 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
994 * This function enables a logical channel.
996 * @param channel Input parameter for the logical channel ID.
998 * @return This function returns 0 on success or negative error code on
1001 int32_t ipu_enable_channel(ipu_channel_t channel)
1007 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1008 printf("Warning: channel already enabled %d\n",
1009 IPU_CHAN_ID(channel));
1012 /* Get input and output dma channels */
1013 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1014 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1016 if (idma_is_valid(in_dma)) {
1017 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1018 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1020 if (idma_is_valid(out_dma)) {
1021 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1022 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1025 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1026 (channel == MEM_FG_SYNC))
1027 ipu_dp_dc_enable(channel);
1029 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1035 * This function clear buffer ready for a logical channel.
1037 * @param channel Input parameter for the logical channel ID.
1039 * @param type Input parameter which buffer to clear.
1041 * @param bufNum Input parameter for which buffer number clear
1045 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1048 uint32_t dma_ch = channel_2_dma(channel, type);
1050 if (!idma_is_valid(dma_ch))
1053 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1055 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1056 __raw_writel(idma_mask(dma_ch),
1057 IPU_CHA_BUF0_RDY(dma_ch));
1060 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1061 __raw_writel(idma_mask(dma_ch),
1062 IPU_CHA_BUF1_RDY(dma_ch));
1065 __raw_writel(0x0, IPU_GPR); /* write one to set */
1069 * This function disables a logical channel.
1071 * @param channel Input parameter for the logical channel ID.
1073 * @param wait_for_stop Flag to set whether to wait for channel end
1074 * of frame or return immediately.
1076 * @return This function returns 0 on success or negative error code on
1079 int32_t ipu_disable_channel(ipu_channel_t channel)
1085 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1086 debug("Channel already disabled %d\n",
1087 IPU_CHAN_ID(channel));
1091 /* Get input and output dma channels */
1092 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1093 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1095 if ((idma_is_valid(in_dma) &&
1096 !idma_is_set(IDMAC_CHA_EN, in_dma))
1097 && (idma_is_valid(out_dma) &&
1098 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1101 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1102 (channel == MEM_DC_SYNC)) {
1103 ipu_dp_dc_disable(channel, 0);
1106 /* Disable DMA channel(s) */
1107 if (idma_is_valid(in_dma)) {
1108 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1109 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1110 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1112 if (idma_is_valid(out_dma)) {
1113 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1114 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1115 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1118 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1120 /* Set channel buffers NOT to be ready */
1121 if (idma_is_valid(in_dma)) {
1122 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1123 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1125 if (idma_is_valid(out_dma)) {
1126 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1127 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1133 uint32_t bytes_per_pixel(uint32_t fmt)
1136 case IPU_PIX_FMT_GENERIC: /*generic data */
1137 case IPU_PIX_FMT_RGB332:
1138 case IPU_PIX_FMT_YUV420P:
1139 case IPU_PIX_FMT_YUV422P:
1142 case IPU_PIX_FMT_RGB565:
1143 case IPU_PIX_FMT_YUYV:
1144 case IPU_PIX_FMT_UYVY:
1147 case IPU_PIX_FMT_BGR24:
1148 case IPU_PIX_FMT_RGB24:
1151 case IPU_PIX_FMT_GENERIC_32: /*generic data */
1152 case IPU_PIX_FMT_BGR32:
1153 case IPU_PIX_FMT_BGRA32:
1154 case IPU_PIX_FMT_RGB32:
1155 case IPU_PIX_FMT_RGBA32:
1156 case IPU_PIX_FMT_ABGR32:
1166 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1169 case IPU_PIX_FMT_RGB666:
1170 case IPU_PIX_FMT_RGB565:
1171 case IPU_PIX_FMT_BGR24:
1172 case IPU_PIX_FMT_RGB24:
1173 case IPU_PIX_FMT_BGR32:
1174 case IPU_PIX_FMT_BGRA32:
1175 case IPU_PIX_FMT_RGB32:
1176 case IPU_PIX_FMT_RGBA32:
1177 case IPU_PIX_FMT_ABGR32:
1178 case IPU_PIX_FMT_LVDS666:
1179 case IPU_PIX_FMT_LVDS888: