2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
15 #include <linux/aperture.h>
16 #include <linux/bitrev.h>
17 #include <linux/compiler.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/selection.h>
29 #include <linux/string.h>
34 #include <video/tgafb.h>
37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
39 #define TGA_BUS_TC(dev) 0
46 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
47 static int tgafb_set_par(struct fb_info *);
48 static void tgafb_set_pll(struct tga_par *, int);
49 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
50 unsigned, struct fb_info *);
51 static int tgafb_blank(int, struct fb_info *);
52 static void tgafb_init_fix(struct fb_info *);
54 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
55 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
56 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
57 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
59 static int tgafb_register(struct device *dev);
60 static void tgafb_unregister(struct device *dev);
62 static const char *mode_option;
63 static const char *mode_option_pci = "640x480@60";
64 static const char *mode_option_tc = "1280x1024@72";
67 static struct pci_driver tgafb_pci_driver;
68 static struct tc_driver tgafb_tc_driver;
71 * Frame buffer operations
74 static const struct fb_ops tgafb_ops = {
76 .fb_check_var = tgafb_check_var,
77 .fb_set_par = tgafb_set_par,
78 .fb_setcolreg = tgafb_setcolreg,
79 .fb_blank = tgafb_blank,
80 .fb_pan_display = tgafb_pan_display,
81 .fb_fillrect = tgafb_fillrect,
82 .fb_copyarea = tgafb_copyarea,
83 .fb_imageblit = tgafb_imageblit,
89 * PCI registration operations
91 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
92 static void tgafb_pci_unregister(struct pci_dev *);
94 static struct pci_device_id const tgafb_pci_table[] = {
95 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
98 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
100 static struct pci_driver tgafb_pci_driver = {
102 .id_table = tgafb_pci_table,
103 .probe = tgafb_pci_register,
104 .remove = tgafb_pci_unregister,
107 static int tgafb_pci_register(struct pci_dev *pdev,
108 const struct pci_device_id *ent)
112 ret = aperture_remove_conflicting_pci_devices(pdev, "tgafb");
116 return tgafb_register(&pdev->dev);
119 static void tgafb_pci_unregister(struct pci_dev *pdev)
121 tgafb_unregister(&pdev->dev);
123 #endif /* CONFIG_PCI */
127 * TC registration operations
129 static int tgafb_tc_register(struct device *);
130 static int tgafb_tc_unregister(struct device *);
132 static struct tc_device_id const tgafb_tc_table[] = {
133 { "DEC ", "PMAGD-AA" },
134 { "DEC ", "PMAGD " },
137 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
139 static struct tc_driver tgafb_tc_driver = {
140 .id_table = tgafb_tc_table,
144 .probe = tgafb_tc_register,
145 .remove = tgafb_tc_unregister,
149 static int tgafb_tc_register(struct device *dev)
151 int status = tgafb_register(dev);
157 static int tgafb_tc_unregister(struct device *dev)
160 tgafb_unregister(dev);
163 #endif /* CONFIG_TC */
167 * tgafb_check_var - Optional function. Validates a var passed in.
168 * @var: frame buffer variable screen structure
169 * @info: frame buffer structure that represents a single frame buffer
172 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
174 struct tga_par *par = (struct tga_par *)info->par;
176 if (par->tga_type == TGA_TYPE_8PLANE) {
177 if (var->bits_per_pixel != 8)
180 if (var->bits_per_pixel != 32)
183 var->red.length = var->green.length = var->blue.length = 8;
184 if (var->bits_per_pixel == 32) {
185 var->red.offset = 16;
186 var->green.offset = 8;
187 var->blue.offset = 0;
190 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
192 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
196 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
198 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
201 /* Some of the acceleration routines assume the line width is
202 a multiple of 8 bytes. */
203 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
210 * tgafb_set_par - Optional function. Alters the hardware state.
211 * @info: frame buffer structure that represents a single frame buffer
214 tgafb_set_par(struct fb_info *info)
216 static unsigned int const deep_presets[4] = {
222 static unsigned int const rasterop_presets[4] = {
228 static unsigned int const mode_presets[4] = {
234 static unsigned int const base_addr_presets[4] = {
241 struct tga_par *par = (struct tga_par *) info->par;
242 int tga_bus_pci = dev_is_pci(par->dev);
243 int tga_bus_tc = TGA_BUS_TC(par->dev);
244 u32 htimings, vtimings, pll_freq;
248 /* Encode video timings. */
249 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
250 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
251 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
252 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
253 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
254 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
255 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
256 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
257 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
259 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
260 htimings |= TGA_HORIZ_POLARITY;
261 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
262 vtimings |= TGA_VERT_POLARITY;
264 par->htimings = htimings;
265 par->vtimings = vtimings;
267 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
269 /* Store other useful values in par. */
270 par->xres = info->var.xres;
271 par->yres = info->var.yres;
272 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
273 par->bits_per_pixel = info->var.bits_per_pixel;
274 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
276 tga_type = par->tga_type;
278 /* First, disable video. */
279 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
281 /* Write the DEEP register. */
282 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
285 TGA_WRITE_REG(par, deep_presets[tga_type] |
286 (par->sync_on_green ? 0x0 : 0x00010000),
288 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
292 /* Write some more registers. */
293 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
294 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
295 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
297 /* Calculate & write the PLL. */
298 tgafb_set_pll(par, pll_freq);
300 /* Write some more registers. */
301 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
302 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
304 /* Init video timing regs. */
305 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
306 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
308 /* Initialise RAMDAC. */
309 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
311 /* Init BT485 RAMDAC registers. */
312 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
314 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
315 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
316 BT485_WRITE(par, 0x40, BT485_CMD_1);
317 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
318 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
320 /* Fill palette registers. */
321 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
322 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
324 for (i = 0; i < 256 * 3; i += 4) {
325 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
329 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
331 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
335 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
337 /* Init BT459 RAMDAC registers. */
338 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
339 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
340 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
341 (par->sync_on_green ? 0xc0 : 0x40));
343 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
345 /* Fill the palette. */
346 BT459_LOAD_ADDR(par, 0x0000);
347 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
349 for (i = 0; i < 256 * 3; i += 4) {
350 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
351 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
353 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
356 } else { /* 24-plane or 24plusZ */
358 /* Init BT463 RAMDAC registers. */
359 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
360 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
361 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
362 (par->sync_on_green ? 0xc0 : 0x40));
364 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
365 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
366 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
369 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
370 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
371 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
374 /* Fill the palette. */
375 BT463_LOAD_ADDR(par, 0x0000);
376 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
378 #ifdef CONFIG_HW_CONSOLE
379 for (i = 0; i < 16; i++) {
380 int j = color_table[i];
382 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
383 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
384 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
386 for (i = 0; i < 512 * 3; i += 4) {
388 for (i = 0; i < 528 * 3; i += 4) {
390 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
391 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
393 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
396 /* Fill window type table after start of vertical retrace. */
397 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
401 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
403 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
405 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
406 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
408 for (i = 0; i < 16; i++) {
409 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
410 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
411 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
416 /* Finally, enable video scan (and pray for the monitor... :-) */
417 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
422 #define DIFFCHECK(X) \
425 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
428 if (delta < min_diff) \
429 min_diff = delta, vm = m, va = a, vr = r; \
434 tgafb_set_pll(struct tga_par *par, int f)
436 int n, shift, base, min_diff, target;
437 int r,a,m,vm = 34, va = 1, vr = 30;
439 for (r = 0 ; r < 12 ; r++)
440 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
442 if (f > TGA_PLL_MAX_FREQ)
443 f = TGA_PLL_MAX_FREQ;
445 if (f >= TGA_PLL_MAX_FREQ / 2)
447 else if (f >= TGA_PLL_MAX_FREQ / 4)
452 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
453 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
455 for (r = 0 ; r < 10 ; r++)
456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
462 else if (f <= 200000) {
463 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
473 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
478 target = (f << shift) / TGA_PLL_BASE_FREQ;
479 min_diff = TGA_PLL_MAX_FREQ;
486 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
487 m = ((n + 3) / 7) - 1;
489 DIFFCHECK((m + 1) * 7);
491 DIFFCHECK((m + 1) * 7);
502 for (r = 0; r < 8; r++)
503 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
504 for (r = 0; r < 8 ; r++)
505 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
506 for (r = 0; r < 7 ; r++)
507 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
508 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
513 * tgafb_setcolreg - Optional function. Sets a color register.
514 * @regno: boolean, 0 copy local, 1 get_user() function
515 * @red: frame buffer colormap structure
516 * @green: The green value which can be up to 16 bits wide
517 * @blue: The blue value which can be up to 16 bits wide.
518 * @transp: If supported the alpha value which can be up to 16 bits wide.
519 * @info: frame buffer info structure
522 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
523 unsigned transp, struct fb_info *info)
525 struct tga_par *par = (struct tga_par *) info->par;
526 int tga_bus_pci = dev_is_pci(par->dev);
527 int tga_bus_tc = TGA_BUS_TC(par->dev);
535 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
536 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
537 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
538 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
539 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
540 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
541 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
542 BT459_LOAD_ADDR(par, regno);
543 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
544 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
545 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
546 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
549 u32 value = (regno << 16) | (regno << 8) | regno;
550 ((u32 *)info->pseudo_palette)[regno] = value;
552 BT463_LOAD_ADDR(par, regno);
553 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
554 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
555 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
556 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
564 * tgafb_blank - Optional function. Blanks the display.
565 * @blank: the blank mode we want.
566 * @info: frame buffer structure that represents a single frame buffer
569 tgafb_blank(int blank, struct fb_info *info)
571 struct tga_par *par = (struct tga_par *) info->par;
572 u32 vhcr, vvcr, vvvr;
575 local_irq_save(flags);
577 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
578 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
579 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
580 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
583 case FB_BLANK_UNBLANK: /* Unblanking */
584 if (par->vesa_blanked) {
585 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
586 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
587 par->vesa_blanked = 0;
589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
592 case FB_BLANK_NORMAL: /* Normal blanking */
593 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
597 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
598 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
599 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
600 par->vesa_blanked = 1;
603 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
604 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
606 par->vesa_blanked = 1;
609 case FB_BLANK_POWERDOWN: /* Poweroff */
610 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
611 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
612 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
613 par->vesa_blanked = 1;
617 local_irq_restore(flags);
627 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
629 struct tga_par *par = (struct tga_par *) info->par;
630 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
631 unsigned long rincr, line_length, shift, pos, is8bpp;
633 const unsigned char *data;
634 void __iomem *regs_base;
635 void __iomem *fb_base;
637 is8bpp = info->var.bits_per_pixel == 8;
641 width = image->width;
642 height = image->height;
643 vxres = info->var.xres_virtual;
644 vyres = info->var.yres_virtual;
645 line_length = info->fix.line_length;
646 rincr = (width + 7) / 8;
648 /* A shift below cannot cope with. */
649 if (unlikely(width == 0))
651 /* Crop the image to the screen. */
652 if (dx > vxres || dy > vyres)
654 if (dx + width > vxres)
656 if (dy + height > vyres)
659 regs_base = par->tga_regs_base;
660 fb_base = par->tga_fb_base;
662 /* Expand the color values to fill 32-bits. */
663 /* ??? Would be nice to notice colour changes elsewhere, so
664 that we can do this only when necessary. */
665 fgcolor = image->fg_color;
666 bgcolor = image->bg_color;
668 fgcolor |= fgcolor << 8;
669 fgcolor |= fgcolor << 16;
670 bgcolor |= bgcolor << 8;
671 bgcolor |= bgcolor << 16;
674 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
676 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
678 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
679 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
681 /* Acquire proper alignment; set up the PIXELMASK register
682 so that we only write the proper character cell. */
683 pos = dy * line_length;
690 shift = (pos & 7) >> 2;
694 data = (const unsigned char *) image->data;
696 /* Enable opaque stipple mode. */
698 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
699 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
700 regs_base + TGA_MODE_REG);
702 if (width + shift <= 32) {
703 unsigned long bwidth;
705 /* Handle common case of imaging a single character, in
706 a font less than or 32 pixels wide. */
708 /* Avoid a shift by 32; width > 0 implied. */
709 pixelmask = (2ul << (width - 1)) - 1;
711 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
714 bwidth = (width + 7) / 8;
716 for (i = 0; i < height; ++i) {
719 /* The image data is bit big endian; we need
721 for (j = 0; j < bwidth; ++j)
722 mask |= bitrev8(data[j]) << (j * 8);
724 __raw_writel(mask << shift, fb_base + pos);
730 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
731 } else if (shift == 0) {
732 unsigned long pos0 = pos;
733 const unsigned char *data0 = data;
734 unsigned long bincr = (is8bpp ? 8 : 8*4);
735 unsigned long bwidth;
737 /* Handle another common case in which accel_putcs
738 generates a large bitmap, which happens to be aligned.
739 Allow the tail to be misaligned. This case is
740 interesting because we've not got to hold partial
741 bytes across the words being written. */
745 bwidth = (width / 8) & -4;
746 for (i = 0; i < height; ++i) {
747 for (j = 0; j < bwidth; j += 4) {
749 mask |= bitrev8(data[j+0]) << (0 * 8);
750 mask |= bitrev8(data[j+1]) << (1 * 8);
751 mask |= bitrev8(data[j+2]) << (2 * 8);
752 mask |= bitrev8(data[j+3]) << (3 * 8);
753 __raw_writel(mask, fb_base + pos + j*bincr);
760 pixelmask = (1ul << (width & 31)) - 1;
762 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
765 pos = pos0 + bwidth*bincr;
766 data = data0 + bwidth;
767 bwidth = ((width & 31) + 7) / 8;
769 for (i = 0; i < height; ++i) {
771 for (j = 0; j < bwidth; ++j)
772 mask |= bitrev8(data[j]) << (j * 8);
773 __raw_writel(mask, fb_base + pos);
778 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
781 unsigned long pos0 = pos;
782 const unsigned char *data0 = data;
783 unsigned long bincr = (is8bpp ? 8 : 8*4);
784 unsigned long bwidth;
786 /* Finally, handle the generic case of misaligned start.
787 Here we split the write into 16-bit spans. This allows
788 us to use only one pixel mask, instead of four as would
789 be required by writing 24-bit spans. */
791 pixelmask = 0xffff << shift;
792 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
795 bwidth = (width / 8) & -2;
796 for (i = 0; i < height; ++i) {
797 for (j = 0; j < bwidth; j += 2) {
799 mask |= bitrev8(data[j+0]) << (0 * 8);
800 mask |= bitrev8(data[j+1]) << (1 * 8);
802 __raw_writel(mask, fb_base + pos + j*bincr);
809 pixelmask = ((1ul << (width & 15)) - 1) << shift;
811 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
814 pos = pos0 + bwidth*bincr;
815 data = data0 + bwidth;
816 bwidth = (width & 15) > 8;
818 for (i = 0; i < height; ++i) {
819 u32 mask = bitrev8(data[0]);
821 mask |= bitrev8(data[1]) << 8;
823 __raw_writel(mask, fb_base + pos);
829 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
832 /* Disable opaque stipple mode. */
834 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
835 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
836 regs_base + TGA_MODE_REG);
840 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
842 struct tga_par *par = (struct tga_par *) info->par;
843 u32 color, dx, dy, width, height, vxres, vyres;
844 u32 *palette = ((u32 *)info->pseudo_palette);
845 unsigned long pos, line_length, i, j;
846 const unsigned char *data;
847 void __iomem *fb_base;
851 width = image->width;
852 height = image->height;
853 vxres = info->var.xres_virtual;
854 vyres = info->var.yres_virtual;
855 line_length = info->fix.line_length;
857 /* Crop the image to the screen. */
858 if (dx > vxres || dy > vyres)
860 if (dx + width > vxres)
862 if (dy + height > vyres)
865 fb_base = par->tga_fb_base;
867 pos = dy * line_length + (dx * 4);
870 /* Now copy the image, color_expanding via the palette. */
871 for (i = 0; i < height; i++) {
872 for (j = 0; j < width; j++) {
873 color = palette[*data++];
874 __raw_writel(color, fb_base + pos + j*4);
881 * tgafb_imageblit - REQUIRED function. Can use generic routines if
882 * non acclerated hardware and packed pixel based.
883 * Copies a image from system memory to the screen.
885 * @info: frame buffer structure that represents a single frame buffer
886 * @image: structure defining the image.
889 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
891 unsigned int is8bpp = info->var.bits_per_pixel == 8;
893 /* If a mono image, regardless of FB depth, go do it. */
894 if (image->depth == 1) {
895 tgafb_mono_imageblit(info, image);
899 /* For copies that aren't pixel expansion, there's little we
900 can do better than the generic code. */
901 /* ??? There is a DMA write mode; I wonder if that could be
902 made to pull the data from the image buffer... */
903 if (image->depth == info->var.bits_per_pixel) {
904 cfb_imageblit(info, image);
908 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
909 if (!is8bpp && image->depth == 8) {
910 tgafb_clut_imageblit(info, image);
914 /* Silently return... */
918 * tgafb_fillrect - REQUIRED function. Can use generic routines if
919 * non acclerated hardware and packed pixel based.
920 * Draws a rectangle on the screen.
922 * @info: frame buffer structure that represents a single frame buffer
923 * @rect: structure defining the rectagle and operation.
926 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
928 struct tga_par *par = (struct tga_par *) info->par;
929 int is8bpp = info->var.bits_per_pixel == 8;
930 u32 dx, dy, width, height, vxres, vyres, color;
931 unsigned long pos, align, line_length, i, j;
932 void __iomem *regs_base;
933 void __iomem *fb_base;
938 height = rect->height;
939 vxres = info->var.xres_virtual;
940 vyres = info->var.yres_virtual;
941 line_length = info->fix.line_length;
942 regs_base = par->tga_regs_base;
943 fb_base = par->tga_fb_base;
945 /* Crop the rectangle to the screen. */
946 if (dx > vxres || dy > vyres || !width || !height)
948 if (dx + width > vxres)
950 if (dy + height > vyres)
953 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
955 /* ??? We could implement ROP_XOR with opaque fill mode
956 and a RasterOp setting of GXxor, but as far as I can
957 tell, this mode is not actually used in the kernel.
958 Thus I am ignoring it for now. */
959 if (rect->rop != ROP_COPY) {
960 cfb_fillrect(info, rect);
964 /* Expand the color value to fill 8 pixels. */
968 color |= color << 16;
969 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
970 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
973 color = ((u32 *)info->pseudo_palette)[color];
974 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
976 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
977 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
978 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
979 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
984 /* The DATA register holds the fill mask for block fill mode.
985 Since we're not stippling, this is all ones. */
986 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
988 /* Enable block fill mode. */
990 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
991 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
992 regs_base + TGA_MODE_REG);
995 /* We can fill 2k pixels per operation. Notice blocks that fit
996 the width of the screen so that we can take advantage of this
997 and fill more than one line per write. */
998 if (width == line_length) {
1003 /* The write into the frame buffer must be aligned to 4 bytes,
1004 but we are allowed to encode the offset within the word in
1005 the data word written. */
1006 align = (pos & 3) << 16;
1009 if (width <= 2048) {
1012 data = (width - 1) | align;
1014 for (i = 0; i < height; ++i) {
1015 __raw_writel(data, fb_base + pos);
1019 unsigned long Bpp = (is8bpp ? 1 : 4);
1020 unsigned long nwidth = width & -2048;
1023 fdata = (2048 - 1) | align;
1024 ldata = ((width & 2047) - 1) | align;
1026 for (i = 0; i < height; ++i) {
1027 for (j = 0; j < nwidth; j += 2048)
1028 __raw_writel(fdata, fb_base + pos + j*Bpp);
1030 __raw_writel(ldata, fb_base + pos + j*Bpp);
1036 /* Disable block fill mode. */
1037 __raw_writel((is8bpp
1038 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1039 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1040 regs_base + TGA_MODE_REG);
1044 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1045 * non acclerated hardware and packed pixel based.
1046 * Copies on area of the screen to another area.
1048 * @info: frame buffer structure that represents a single frame buffer
1049 * @area: structure defining the source and destination.
1052 /* Handle the special case of copying entire lines, e.g. during scrolling.
1053 We can avoid a lot of needless computation in this case. In the 8bpp
1054 case we need to use the COPY64 registers instead of mask writes into
1055 the frame buffer to achieve maximum performance. */
1058 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1059 u32 height, u32 width)
1061 struct tga_par *par = (struct tga_par *) info->par;
1062 void __iomem *tga_regs = par->tga_regs_base;
1063 unsigned long dpos, spos, i, n64;
1065 /* Set up the MODE and PIXELSHIFT registers. */
1066 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1067 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1070 n64 = (height * width) / 64;
1073 spos = (sy + height) * width;
1074 dpos = (dy + height) * width;
1076 for (i = 0; i < n64; ++i) {
1079 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1081 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1088 for (i = 0; i < n64; ++i) {
1089 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1091 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1098 /* Reset the MODE register to normal. */
1099 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1103 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1104 u32 height, u32 width)
1106 struct tga_par *par = (struct tga_par *) info->par;
1107 void __iomem *tga_regs = par->tga_regs_base;
1108 void __iomem *tga_fb = par->tga_fb_base;
1111 unsigned long i, n16;
1113 /* Set up the MODE and PIXELSHIFT registers. */
1114 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1115 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1118 n16 = (height * width) / 16;
1121 src = tga_fb + (sy + height) * width * 4;
1122 dst = tga_fb + (dy + height) * width * 4;
1124 for (i = 0; i < n16; ++i) {
1127 __raw_writel(0xffff, src);
1129 __raw_writel(0xffff, dst);
1133 src = tga_fb + sy * width * 4;
1134 dst = tga_fb + dy * width * 4;
1136 for (i = 0; i < n16; ++i) {
1137 __raw_writel(0xffff, src);
1139 __raw_writel(0xffff, dst);
1146 /* Reset the MODE register to normal. */
1147 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1150 /* The (almost) general case of backward copy in 8bpp mode. */
1152 copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1153 u32 height, u32 width, u32 line_length,
1154 const struct fb_copyarea *area)
1156 struct tga_par *par = (struct tga_par *) info->par;
1158 int depos, sepos, backward, last_step, step;
1161 void __iomem *tga_regs;
1162 void __iomem *tga_fb;
1164 /* Do acceleration only if we are aligned on 8 pixels */
1165 if ((dx | sx | width) & 7) {
1166 cfb_copyarea(info, area);
1170 yincr = line_length;
1176 backward = dy == sy && dx > sx && dx < sx + width;
1178 /* Compute the offsets and alignments in the frame buffer.
1179 More than anything else, these control how we do copies. */
1180 depos = dy * line_length + dx;
1181 sepos = sy * line_length + sx;
1187 /* Next copy full words at a time. */
1189 last_step = width % 32;
1191 /* Finally copy the unaligned head of the span. */
1192 mask_last = (1ul << last_step) - 1;
1199 last_step = -last_step;
1204 tga_regs = par->tga_regs_base;
1205 tga_fb = par->tga_fb_base;
1207 /* Set up the MODE and PIXELSHIFT registers. */
1208 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1209 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1212 for (i = 0; i < height; ++i) {
1217 sfb = tga_fb + sepos;
1218 dfb = tga_fb + depos;
1220 for (j = 0; j < n32; j++) {
1221 if (j < 2 && j + 1 < n32 && !backward &&
1222 !(((unsigned long)sfb | (unsigned long)dfb) & 63)) {
1224 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1226 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1231 } while (j + 1 < n32);
1235 __raw_writel(0xffffffff, sfb);
1237 __raw_writel(0xffffffff, dfb);
1244 sfb += last_step - step;
1245 dfb += last_step - step;
1246 __raw_writel(mask_last, sfb);
1248 __raw_writel(mask_last, dfb);
1256 /* Reset the MODE register to normal. */
1257 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1261 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1263 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1264 unsigned long line_length, bpp;
1268 width = area->width;
1269 height = area->height;
1272 vxres = info->var.xres_virtual;
1273 vyres = info->var.yres_virtual;
1274 line_length = info->fix.line_length;
1276 /* The top left corners must be in the virtual screen. */
1277 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1280 /* Clip the destination. */
1281 if (dx + width > vxres)
1283 if (dy + height > vyres)
1284 height = vyres - dy;
1286 /* The source must be completely inside the virtual screen. */
1287 if (sx + width > vxres || sy + height > vyres)
1290 bpp = info->var.bits_per_pixel;
1292 /* Detect copies of the entire line. */
1293 if (!(line_length & 63) && width * (bpp >> 3) == line_length) {
1295 copyarea_line_8bpp(info, dy, sy, height, width);
1297 copyarea_line_32bpp(info, dy, sy, height, width);
1300 /* ??? The documentation is unclear to me exactly how the pixelshift
1301 register works in 32bpp mode. Since I don't have hardware to test,
1302 give up for now and fall back on the generic routines. */
1304 cfb_copyarea(info, area);
1307 copyarea_8bpp(info, dx, dy, sx, sy, height,
1308 width, line_length, area);
1317 tgafb_init_fix(struct fb_info *info)
1319 struct tga_par *par = (struct tga_par *)info->par;
1320 int tga_bus_pci = dev_is_pci(par->dev);
1321 int tga_bus_tc = TGA_BUS_TC(par->dev);
1322 u8 tga_type = par->tga_type;
1323 const char *tga_type_name = NULL;
1324 unsigned memory_size;
1327 case TGA_TYPE_8PLANE:
1329 tga_type_name = "Digital ZLXp-E1";
1331 tga_type_name = "Digital ZLX-E1";
1332 memory_size = 2097152;
1334 case TGA_TYPE_24PLANE:
1336 tga_type_name = "Digital ZLXp-E2";
1338 tga_type_name = "Digital ZLX-E2";
1339 memory_size = 8388608;
1341 case TGA_TYPE_24PLUSZ:
1343 tga_type_name = "Digital ZLXp-E3";
1345 tga_type_name = "Digital ZLX-E3";
1346 memory_size = 16777216;
1349 if (!tga_type_name) {
1350 tga_type_name = "Unknown";
1351 memory_size = 16777216;
1354 strscpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1356 info->fix.type = FB_TYPE_PACKED_PIXELS;
1357 info->fix.type_aux = 0;
1358 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1359 ? FB_VISUAL_PSEUDOCOLOR
1360 : FB_VISUAL_DIRECTCOLOR);
1362 info->fix.smem_start = (size_t) par->tga_fb_base;
1363 info->fix.smem_len = memory_size;
1364 info->fix.mmio_start = (size_t) par->tga_regs_base;
1365 info->fix.mmio_len = 512;
1367 info->fix.xpanstep = 0;
1368 info->fix.ypanstep = 0;
1369 info->fix.ywrapstep = 0;
1371 info->fix.accel = FB_ACCEL_DEC_TGA;
1374 * These are needed by fb_set_logo_truepalette(), so we
1375 * set them here for 24-plane cards.
1377 if (tga_type != TGA_TYPE_8PLANE) {
1378 info->var.red.length = 8;
1379 info->var.green.length = 8;
1380 info->var.blue.length = 8;
1381 info->var.red.offset = 16;
1382 info->var.green.offset = 8;
1383 info->var.blue.offset = 0;
1387 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1389 /* We just use this to catch switches out of graphics mode. */
1390 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1394 static int tgafb_register(struct device *dev)
1396 static const struct fb_videomode modedb_tc = {
1397 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1398 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1399 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1402 static unsigned int const fb_offset_presets[4] = {
1403 TGA_8PLANE_FB_OFFSET,
1404 TGA_24PLANE_FB_OFFSET,
1406 TGA_24PLUSZ_FB_OFFSET
1409 const struct fb_videomode *modedb_tga = NULL;
1410 resource_size_t bar0_start = 0, bar0_len = 0;
1411 const char *mode_option_tga = NULL;
1412 int tga_bus_pci = dev_is_pci(dev);
1413 int tga_bus_tc = TGA_BUS_TC(dev);
1414 unsigned int modedbsize_tga = 0;
1415 void __iomem *mem_base;
1416 struct fb_info *info;
1417 struct tga_par *par;
1421 /* Enable device in PCI config. */
1422 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1423 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1427 /* Allocate the fb and par structures. */
1428 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1433 dev_set_drvdata(dev, info);
1435 /* Request the mem regions. */
1438 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1439 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1442 bar0_start = to_tc_dev(dev)->resource.start;
1443 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1445 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1446 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1450 /* Map the framebuffer. */
1451 mem_base = ioremap(bar0_start, bar0_len);
1453 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1457 /* Grab info about the card. */
1458 tga_type = (readl(mem_base) >> 12) & 0x0f;
1460 par->tga_mem_base = mem_base;
1461 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1462 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1463 par->tga_type = tga_type;
1465 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1467 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1469 /* Setup framebuffer. */
1470 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1471 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1472 info->fbops = &tgafb_ops;
1473 info->screen_base = par->tga_fb_base;
1474 info->pseudo_palette = par->palette;
1476 /* This should give a reasonable default video mode. */
1478 mode_option_tga = mode_option_pci;
1481 mode_option_tga = mode_option_tc;
1482 modedb_tga = &modedb_tc;
1486 tgafb_init_fix(info);
1488 ret = fb_find_mode(&info->var, info,
1489 mode_option ? mode_option : mode_option_tga,
1490 modedb_tga, modedbsize_tga, NULL,
1491 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1492 if (ret == 0 || ret == 4) {
1493 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1498 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1499 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1504 tgafb_set_par(info);
1506 if (register_framebuffer(info) < 0) {
1507 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1513 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1515 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1516 to_pci_dev(dev)->bus->number,
1517 PCI_SLOT(to_pci_dev(dev)->devfn),
1518 PCI_FUNC(to_pci_dev(dev)->devfn));
1521 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1523 fb_info(info, "%s frame buffer device at 0x%lx\n",
1524 info->fix.id, (long)bar0_start);
1529 fb_dealloc_cmap(&info->cmap);
1533 release_mem_region(bar0_start, bar0_len);
1535 framebuffer_release(info);
1539 static void tgafb_unregister(struct device *dev)
1541 resource_size_t bar0_start = 0, bar0_len = 0;
1542 int tga_bus_pci = dev_is_pci(dev);
1543 int tga_bus_tc = TGA_BUS_TC(dev);
1544 struct fb_info *info = NULL;
1545 struct tga_par *par;
1547 info = dev_get_drvdata(dev);
1552 unregister_framebuffer(info);
1553 fb_dealloc_cmap(&info->cmap);
1554 iounmap(par->tga_mem_base);
1556 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1557 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1560 bar0_start = to_tc_dev(dev)->resource.start;
1561 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1563 release_mem_region(bar0_start, bar0_len);
1564 framebuffer_release(info);
1567 static void tgafb_exit(void)
1569 tc_unregister_driver(&tgafb_tc_driver);
1570 pci_unregister_driver(&tgafb_pci_driver);
1574 static int tgafb_setup(char *arg)
1579 while ((this_opt = strsep(&arg, ","))) {
1582 if (!strncmp(this_opt, "mode:", 5))
1583 mode_option = this_opt+5;
1586 "tgafb: unknown parameter %s\n",
1593 #endif /* !MODULE */
1595 static int tgafb_init(void)
1599 char *option = NULL;
1601 if (fb_get_options("tgafb", &option))
1603 tgafb_setup(option);
1605 status = pci_register_driver(&tgafb_pci_driver);
1607 status = tc_register_driver(&tgafb_tc_driver);
1615 module_init(tgafb_init);
1616 module_exit(tgafb_exit);
1618 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1619 MODULE_LICENSE("GPL");