2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/delay.h>
44 #include <linux/init.h>
47 #include <linux/zorro.h>
50 #include <linux/pci.h>
53 #include <asm/amigahw.h>
56 #include <video/vga.h>
57 #include <video/cirrus.h>
59 /*****************************************************************
61 * debugging and utility macros
65 /* disable runtime assertions? */
66 /* #define CIRRUSFB_NDEBUG */
68 /* debugging assertions */
69 #ifndef CIRRUSFB_NDEBUG
70 #define assert(expr) \
72 printk("Assertion failed! %s,%s,%s,line=%d\n", \
73 #expr, __FILE__, __func__, __LINE__); \
79 #define MB_ (1024 * 1024)
81 /*****************************************************************
91 BT_PICCOLO, /* GD5426 */
92 BT_PICASSO, /* GD5426 or GD5428 */
93 BT_SPECTRUM, /* GD5426 or GD5428 */
94 BT_PICASSO4, /* GD5446 */
95 BT_ALPINE, /* GD543x/4x */
97 BT_LAGUNA, /* GD5462/64 */
98 BT_LAGUNAB, /* GD5465 */
102 * per-board-type information, used for enumerating and abstracting
103 * chip-specific information
104 * NOTE: MUST be in the same order as enum cirrus_board in order to
105 * use direct indexing on this array
106 * NOTE: '__initdata' cannot be used as some of this info
107 * is required at runtime. Maybe separate into an init-only and
110 static const struct cirrusfb_board_info_rec {
111 char *name; /* ASCII name of chipset */
112 long maxclock[5]; /* maximum video clock */
113 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
114 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
115 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
116 /* construct bit 19 of screen start address */
117 bool scrn_start_bit19 : 1;
119 /* initial SR07 value, then for each mode */
121 unsigned char sr07_1bpp;
122 unsigned char sr07_1bpp_mux;
123 unsigned char sr07_8bpp;
124 unsigned char sr07_8bpp_mux;
126 unsigned char sr1f; /* SR1F VGA initial register value */
127 } cirrusfb_board_info[] = {
132 /* the SD64/P4 have a higher max. videoclock */
133 135100, 135100, 85500, 85500, 0
137 .scrn_start_bit19 = true,
140 .sr07_1bpp_mux = 0xF6,
142 .sr07_8bpp_mux = 0xF7,
146 .name = "CL Piccolo",
149 90000, 90000, 90000, 90000, 90000
153 .scrn_start_bit19 = false,
160 .name = "CL Picasso",
163 90000, 90000, 90000, 90000, 90000
167 .scrn_start_bit19 = false,
174 .name = "CL Spectrum",
177 90000, 90000, 90000, 90000, 90000
181 .scrn_start_bit19 = false,
188 .name = "CL Picasso4",
190 135100, 135100, 85500, 85500, 0
194 .scrn_start_bit19 = true,
197 .sr07_1bpp_mux = 0xA6,
199 .sr07_8bpp_mux = 0xA7,
205 /* for the GD5430. GD5446 can do more... */
206 85500, 85500, 50000, 28500, 0
210 .scrn_start_bit19 = true,
213 .sr07_1bpp_mux = 0xA6,
215 .sr07_8bpp_mux = 0xA7,
221 135100, 200000, 200000, 135100, 135100
225 .scrn_start_bit19 = true,
234 /* taken from X11 code */
235 170000, 170000, 170000, 170000, 135100,
239 .scrn_start_bit19 = true,
242 .name = "CL Laguna AGP",
244 /* taken from X11 code */
245 170000, 250000, 170000, 170000, 135100,
249 .scrn_start_bit19 = true,
254 #define CHIP(id, btype) \
255 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
257 static struct pci_device_id cirrusfb_pci_table[] = {
258 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
259 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
260 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
261 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
262 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
263 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
264 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
265 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
266 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
267 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
268 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
271 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
273 #endif /* CONFIG_PCI */
277 enum cirrus_board type; /* Board type */
278 u32 regoffset; /* Offset of registers in first Zorro device */
279 u32 ramsize; /* Size of video RAM in first Zorro device */
280 /* If zero, use autoprobe on RAM device */
281 u32 ramoffset; /* Offset of video RAM in first Zorro device */
282 zorro_id ramid; /* Zorro ID of RAM device */
283 zorro_id ramid2; /* Zorro ID of optional second RAM device */
286 static const struct zorrocl zcl_sd64 = {
288 .ramid = ZORRO_PROD_HELFRICH_SD64_RAM,
291 static const struct zorrocl zcl_piccolo = {
293 .ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
296 static const struct zorrocl zcl_picasso = {
298 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
301 static const struct zorrocl zcl_spectrum = {
303 .ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
306 static const struct zorrocl zcl_picasso4_z3 = {
308 .regoffset = 0x00600000,
310 .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
313 static const struct zorrocl zcl_picasso4_z2 = {
315 .regoffset = 0x10000,
316 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
317 .ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
321 static const struct zorro_device_id cirrusfb_zorro_table[] = {
323 .id = ZORRO_PROD_HELFRICH_SD64_REG,
324 .driver_data = (unsigned long)&zcl_sd64,
326 .id = ZORRO_PROD_HELFRICH_PICCOLO_REG,
327 .driver_data = (unsigned long)&zcl_piccolo,
329 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
330 .driver_data = (unsigned long)&zcl_picasso,
332 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
333 .driver_data = (unsigned long)&zcl_spectrum,
335 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
336 .driver_data = (unsigned long)&zcl_picasso4_z3,
338 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
339 .driver_data = (unsigned long)&zcl_picasso4_z2,
343 MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
344 #endif /* CONFIG_ZORRO */
346 #ifdef CIRRUSFB_DEBUG
347 enum cirrusfb_dbg_reg_class {
351 #endif /* CIRRUSFB_DEBUG */
353 /* info about board */
354 struct cirrusfb_info {
356 u8 __iomem *laguna_mmio;
357 enum cirrus_board btype;
358 unsigned char SFR; /* Shadow of special function register */
363 u32 pseudo_palette[16];
365 void (*unmap)(struct fb_info *info);
369 static char *mode_option = "640x480@60";
371 /****************************************************************************/
372 /**** BEGIN PROTOTYPES ******************************************************/
374 /*--- Interface used by the world ------------------------------------------*/
375 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
376 struct fb_info *info);
378 /*--- Internal routines ----------------------------------------------------*/
379 static void init_vgachip(struct fb_info *info);
380 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
381 static void WGen(const struct cirrusfb_info *cinfo,
382 int regnum, unsigned char val);
383 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
384 static void AttrOn(const struct cirrusfb_info *cinfo);
385 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
386 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
389 unsigned char red, unsigned char green, unsigned char blue);
391 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
392 unsigned char *red, unsigned char *green,
393 unsigned char *blue);
395 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
396 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
397 u_short curx, u_short cury,
398 u_short destx, u_short desty,
399 u_short width, u_short height,
400 u_short line_length);
401 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
402 u_short x, u_short y,
403 u_short width, u_short height,
404 u32 fg_color, u32 bg_color,
405 u_short line_length, u_char blitmode);
407 static void bestclock(long freq, int *nom, int *den, int *div);
409 #ifdef CIRRUSFB_DEBUG
410 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
411 static void cirrusfb_dbg_print_regs(struct fb_info *info,
413 enum cirrusfb_dbg_reg_class reg_class, ...);
414 #endif /* CIRRUSFB_DEBUG */
416 /*** END PROTOTYPES ********************************************************/
417 /*****************************************************************************/
418 /*** BEGIN Interface Used by the World ***************************************/
420 static inline int is_laguna(const struct cirrusfb_info *cinfo)
422 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
425 static int opencount;
427 /*--- Open /dev/fbx ---------------------------------------------------------*/
428 static int cirrusfb_open(struct fb_info *info, int user)
430 if (opencount++ == 0)
431 switch_monitor(info->par, 1);
435 /*--- Close /dev/fbx --------------------------------------------------------*/
436 static int cirrusfb_release(struct fb_info *info, int user)
438 if (--opencount == 0)
439 switch_monitor(info->par, 0);
443 /**** END Interface used by the World *************************************/
444 /****************************************************************************/
445 /**** BEGIN Hardware specific Routines **************************************/
447 /* Check if the MCLK is not a better clock source */
448 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
450 struct cirrusfb_info *cinfo = info->par;
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
453 /* Read MCLK value */
454 mclk = (14318 * mclk) >> 3;
455 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
457 /* Determine if we should use MCLK instead of VCLK, and if so, what we
458 * should divide it by to get VCLK
461 if (abs(freq - mclk) < 250) {
462 dev_dbg(info->device, "Using VCLK = MCLK\n");
464 } else if (abs(freq - (mclk / 2)) < 250) {
465 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
472 static int cirrusfb_check_pixclock(struct fb_var_screeninfo *var,
473 struct fb_info *info)
477 struct cirrusfb_info *cinfo = info->par;
478 unsigned maxclockidx = var->bits_per_pixel >> 3;
480 /* convert from ps to kHz */
481 freq = PICOS2KHZ(var->pixclock ? : 1);
483 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
484 cinfo->multiplexing = 0;
486 /* If the frequency is greater than we can support, we might be able
487 * to use multiplexing for the video mode */
488 if (freq > maxclock) {
489 var->pixclock = KHZ2PICOS(maxclock);
491 while ((freq = PICOS2KHZ(var->pixclock)) > maxclock)
494 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
497 * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
500 if (var->bits_per_pixel == 8) {
501 switch (cinfo->btype) {
506 cinfo->multiplexing = 1;
510 cinfo->multiplexing = 1;
518 /* If we have a 1MB 5434, we need to put ourselves in a mode where
519 * the VCLK is double the pixel clock. */
520 cinfo->doubleVCLK = 0;
521 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
522 var->bits_per_pixel == 16) {
523 cinfo->doubleVCLK = 1;
529 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
530 struct fb_info *info)
533 /* memory size in pixels */
535 struct cirrusfb_info *cinfo = info->par;
537 switch (var->bits_per_pixel) {
541 var->green = var->red;
542 var->blue = var->red;
548 var->green = var->red;
549 var->blue = var->red;
553 var->red.offset = 11;
554 var->green.offset = 5;
555 var->blue.offset = 0;
557 var->green.length = 6;
558 var->blue.length = 5;
562 var->red.offset = 16;
563 var->green.offset = 8;
564 var->blue.offset = 0;
566 var->green.length = 8;
567 var->blue.length = 8;
571 dev_dbg(info->device,
572 "Unsupported bpp size: %d\n", var->bits_per_pixel);
576 pixels = info->screen_size * 8 / var->bits_per_pixel;
577 if (var->xres_virtual < var->xres)
578 var->xres_virtual = var->xres;
579 /* use highest possible virtual resolution */
580 if (var->yres_virtual == -1) {
581 var->yres_virtual = pixels / var->xres_virtual;
583 dev_info(info->device,
584 "virtual resolution set to maximum of %dx%d\n",
585 var->xres_virtual, var->yres_virtual);
587 if (var->yres_virtual < var->yres)
588 var->yres_virtual = var->yres;
590 if (var->xres_virtual * var->yres_virtual > pixels) {
591 dev_err(info->device, "mode %dx%dx%d rejected... "
592 "virtual resolution too high to fit into video memory!\n",
593 var->xres_virtual, var->yres_virtual,
594 var->bits_per_pixel);
598 /* truncate xoffset and yoffset to maximum if too high */
599 if (var->xoffset > var->xres_virtual - var->xres)
600 var->xoffset = var->xres_virtual - var->xres - 1;
601 if (var->yoffset > var->yres_virtual - var->yres)
602 var->yoffset = var->yres_virtual - var->yres - 1;
605 var->green.msb_right =
606 var->blue.msb_right =
609 var->transp.msb_right = 0;
612 if (var->vmode & FB_VMODE_DOUBLE)
614 else if (var->vmode & FB_VMODE_INTERLACED)
615 yres = (yres + 1) / 2;
618 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
619 "special treatment required! (TODO)\n");
623 if (cirrusfb_check_pixclock(var, info))
626 if (!is_laguna(cinfo))
627 var->accel_flags = FB_ACCELF_TEXT;
632 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
634 struct cirrusfb_info *cinfo = info->par;
635 unsigned char old1f, old1e;
637 assert(cinfo != NULL);
638 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
641 dev_dbg(info->device, "Set %s as pixclock source.\n",
642 (div == 2) ? "MCLK/2" : "MCLK");
644 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
648 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
650 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
653 /*************************************************************************
654 cirrusfb_set_par_foo()
656 actually writes the values for a new video mode into the hardware,
657 **************************************************************************/
658 static int cirrusfb_set_par_foo(struct fb_info *info)
660 struct cirrusfb_info *cinfo = info->par;
661 struct fb_var_screeninfo *var = &info->var;
662 u8 __iomem *regbase = cinfo->regbase;
665 const struct cirrusfb_board_info_rec *bi;
666 int hdispend, hsyncstart, hsyncend, htotal;
667 int yres, vdispend, vsyncstart, vsyncend, vtotal;
670 unsigned int control = 0, format = 0, threshold = 0;
672 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
673 var->xres, var->yres, var->bits_per_pixel);
675 switch (var->bits_per_pixel) {
677 info->fix.line_length = var->xres_virtual / 8;
678 info->fix.visual = FB_VISUAL_MONO10;
682 info->fix.line_length = var->xres_virtual;
683 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
688 info->fix.line_length = var->xres_virtual *
689 var->bits_per_pixel >> 3;
690 info->fix.visual = FB_VISUAL_TRUECOLOR;
693 info->fix.type = FB_TYPE_PACKED_PIXELS;
697 bi = &cirrusfb_board_info[cinfo->btype];
699 hsyncstart = var->xres + var->right_margin;
700 hsyncend = hsyncstart + var->hsync_len;
701 htotal = (hsyncend + var->left_margin) / 8;
702 hdispend = var->xres / 8;
703 hsyncstart = hsyncstart / 8;
704 hsyncend = hsyncend / 8;
706 vdispend = var->yres;
707 vsyncstart = vdispend + var->lower_margin;
708 vsyncend = vsyncstart + var->vsync_len;
709 vtotal = vsyncend + var->upper_margin;
711 if (var->vmode & FB_VMODE_DOUBLE) {
716 } else if (var->vmode & FB_VMODE_INTERLACED) {
717 vdispend = (vdispend + 1) / 2;
718 vsyncstart = (vsyncstart + 1) / 2;
719 vsyncend = (vsyncend + 1) / 2;
720 vtotal = (vtotal + 1) / 2;
735 if (cinfo->multiplexing) {
747 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
748 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
750 /* if debugging is enabled, all parameters get output before writing */
751 dev_dbg(info->device, "CRT0: %d\n", htotal);
752 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
754 dev_dbg(info->device, "CRT1: %d\n", hdispend);
755 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
757 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
758 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
760 /* + 128: Compatible read */
761 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
762 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
763 128 + ((htotal + 5) % 32));
765 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
766 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
769 if ((htotal + 5) & 32)
771 dev_dbg(info->device, "CRT5: %d\n", tmp);
772 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
774 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
775 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
777 tmp = 16; /* LineCompare bit #9 */
782 if (vsyncstart & 256)
784 if ((vdispend + 1) & 256)
790 if (vsyncstart & 512)
792 dev_dbg(info->device, "CRT7: %d\n", tmp);
793 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
795 tmp = 0x40; /* LineCompare bit #8 */
796 if ((vdispend + 1) & 512)
798 if (var->vmode & FB_VMODE_DOUBLE)
800 dev_dbg(info->device, "CRT9: %d\n", tmp);
801 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
803 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
804 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
806 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
807 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
809 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
810 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
812 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
813 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
815 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
816 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
818 dev_dbg(info->device, "CRT18: 0xff\n");
819 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
822 if (var->vmode & FB_VMODE_INTERLACED)
824 if ((htotal + 5) & 64)
826 if ((htotal + 5) & 128)
833 dev_dbg(info->device, "CRT1a: %d\n", tmp);
834 vga_wcrt(regbase, CL_CRT1A, tmp);
836 freq = PICOS2KHZ(var->pixclock);
837 if (var->bits_per_pixel == 24)
838 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
840 if (cinfo->multiplexing)
842 if (cinfo->doubleVCLK)
845 bestclock(freq, &nom, &den, &div);
847 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
848 freq, nom, den, div);
851 /* hardware RefClock: 14.31818 MHz */
852 /* formula: VClk = (OSC * N) / (D * (1+P)) */
853 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
855 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
856 cinfo->btype == BT_SD64) {
857 /* if freq is close to mclk or mclk/2 select mclk
860 int divMCLK = cirrusfb_check_mclk(info, freq);
863 cirrusfb_set_mclk_as_source(info, divMCLK);
865 if (is_laguna(cinfo)) {
866 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
867 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
868 unsigned short tile_control;
870 if (cinfo->btype == BT_LAGUNAB) {
871 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
872 tile_control &= ~0x80;
873 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
876 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
877 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
878 control = fb_readw(cinfo->laguna_mmio + 0x402);
879 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
882 threshold &= 0xffc0 & 0x3fbf;
888 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
889 if ((cinfo->btype == BT_SD64) ||
890 (cinfo->btype == BT_ALPINE) ||
891 (cinfo->btype == BT_GD5480))
894 /* Laguna chipset has reversed clock registers */
895 if (is_laguna(cinfo)) {
896 vga_wseq(regbase, CL_SEQRE, tmp);
897 vga_wseq(regbase, CL_SEQR1E, nom);
899 vga_wseq(regbase, CL_SEQRE, nom);
900 vga_wseq(regbase, CL_SEQR1E, tmp);
906 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
908 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
909 * address wrap, no compat. */
910 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
912 /* don't know if it would hurt to also program this if no interlaced */
913 /* mode is used, but I feel better this way.. :-) */
914 if (var->vmode & FB_VMODE_INTERLACED)
915 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
917 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
919 /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
920 /* enable display memory & CRTC I/O address for color mode */
922 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
924 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
926 WGen(cinfo, VGA_MIS_W, tmp);
928 /* text cursor on and start line */
929 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
930 /* text cursor end line */
931 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
933 /******************************************************
939 /* programming for different color depths */
940 if (var->bits_per_pixel == 1) {
941 dev_dbg(info->device, "preparing for 1 bit deep display\n");
942 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
945 switch (cinfo->btype) {
953 vga_wseq(regbase, CL_SEQR7,
954 cinfo->multiplexing ?
955 bi->sr07_1bpp_mux : bi->sr07_1bpp);
960 vga_wseq(regbase, CL_SEQR7,
961 vga_rseq(regbase, CL_SEQR7) & ~0x01);
965 dev_warn(info->device, "unknown Board\n");
969 /* Extended Sequencer Mode */
970 switch (cinfo->btype) {
974 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
975 vga_wseq(regbase, CL_SEQRF, 0xb0);
979 /* ## vorher d0 avoid FIFO underruns..? */
980 vga_wseq(regbase, CL_SEQRF, 0xd0);
993 dev_warn(info->device, "unknown Board\n");
997 /* pixel mask: pass-through for first plane */
998 WGen(cinfo, VGA_PEL_MSK, 0x01);
999 if (cinfo->multiplexing)
1000 /* hidden dac reg: 1280x1024 */
1003 /* hidden dac: nothing */
1005 /* memory mode: odd/even, ext. memory */
1006 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1007 /* plane mask: only write to first plane */
1008 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1011 /******************************************************
1017 else if (var->bits_per_pixel == 8) {
1018 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1019 switch (cinfo->btype) {
1027 vga_wseq(regbase, CL_SEQR7,
1028 cinfo->multiplexing ?
1029 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1034 vga_wseq(regbase, CL_SEQR7,
1035 vga_rseq(regbase, CL_SEQR7) | 0x01);
1040 dev_warn(info->device, "unknown Board\n");
1044 switch (cinfo->btype) {
1048 /* Fast Page-Mode writes */
1049 vga_wseq(regbase, CL_SEQRF, 0xb0);
1054 /* ### INCOMPLETE!! */
1055 vga_wseq(regbase, CL_SEQRF, 0xb8);
1066 dev_warn(info->device, "unknown board\n");
1070 /* mode register: 256 color mode */
1071 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1072 if (cinfo->multiplexing)
1073 /* hidden dac reg: 1280x1024 */
1076 /* hidden dac: nothing */
1080 /******************************************************
1086 else if (var->bits_per_pixel == 16) {
1087 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1088 switch (cinfo->btype) {
1091 vga_wseq(regbase, CL_SEQR7, 0x87);
1092 /* Fast Page-Mode writes */
1093 vga_wseq(regbase, CL_SEQRF, 0xb0);
1097 vga_wseq(regbase, CL_SEQR7, 0x27);
1098 /* Fast Page-Mode writes */
1099 vga_wseq(regbase, CL_SEQRF, 0xb0);
1105 /* Extended Sequencer Mode: 256c col. mode */
1106 vga_wseq(regbase, CL_SEQR7,
1107 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1111 vga_wseq(regbase, CL_SEQR7, 0x17);
1112 /* We already set SRF and SR1F */
1117 vga_wseq(regbase, CL_SEQR7,
1118 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1125 dev_warn(info->device, "unknown Board\n");
1129 /* mode register: 256 color mode */
1130 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1132 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1133 #elif defined(CONFIG_ZORRO)
1134 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1135 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1139 /******************************************************
1145 else if (var->bits_per_pixel == 24) {
1146 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1147 switch (cinfo->btype) {
1150 vga_wseq(regbase, CL_SEQR7, 0x85);
1151 /* Fast Page-Mode writes */
1152 vga_wseq(regbase, CL_SEQRF, 0xb0);
1156 vga_wseq(regbase, CL_SEQR7, 0x25);
1157 /* Fast Page-Mode writes */
1158 vga_wseq(regbase, CL_SEQRF, 0xb0);
1164 /* Extended Sequencer Mode: 256c col. mode */
1165 vga_wseq(regbase, CL_SEQR7, 0xa5);
1169 vga_wseq(regbase, CL_SEQR7, 0x15);
1170 /* We already set SRF and SR1F */
1175 vga_wseq(regbase, CL_SEQR7,
1176 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1183 dev_warn(info->device, "unknown Board\n");
1187 /* mode register: 256 color mode */
1188 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1189 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1193 /******************************************************
1195 * unknown/unsupported bpp
1200 dev_err(info->device,
1201 "What's this? requested color depth == %d.\n",
1202 var->bits_per_pixel);
1204 pitch = info->fix.line_length >> 3;
1205 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1208 tmp |= 0x10; /* offset overflow bit */
1210 /* screen start addr #16-18, fastpagemode cycles */
1211 vga_wcrt(regbase, CL_CRT1B, tmp);
1213 /* screen start address bit 19 */
1214 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1215 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1217 if (is_laguna(cinfo)) {
1219 if ((htotal + 5) & 256)
1223 if (hsyncstart & 256)
1227 if (vdispend & 1024)
1229 if (vsyncstart & 1024)
1232 vga_wcrt(regbase, CL_CRT1E, tmp);
1233 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1237 vga_wattr(regbase, CL_AR33, 0);
1239 /* [ EGS: SetOffset(); ] */
1240 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1243 if (is_laguna(cinfo)) {
1245 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1246 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1247 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1249 /* finally, turn on everything - turn off "FullBandwidth" bit */
1250 /* also, set "DotClock%2" bit where requested */
1253 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1254 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1258 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1259 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1261 #ifdef CIRRUSFB_DEBUG
1262 cirrusfb_dbg_reg_dump(info, NULL);
1268 /* for some reason incomprehensible to me, cirrusfb requires that you write
1269 * the registers twice for the settings to take..grr. -dte */
1270 static int cirrusfb_set_par(struct fb_info *info)
1272 cirrusfb_set_par_foo(info);
1273 return cirrusfb_set_par_foo(info);
1276 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1277 unsigned blue, unsigned transp,
1278 struct fb_info *info)
1280 struct cirrusfb_info *cinfo = info->par;
1285 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1287 red >>= (16 - info->var.red.length);
1288 green >>= (16 - info->var.green.length);
1289 blue >>= (16 - info->var.blue.length);
1293 v = (red << info->var.red.offset) |
1294 (green << info->var.green.offset) |
1295 (blue << info->var.blue.offset);
1297 cinfo->pseudo_palette[regno] = v;
1301 if (info->var.bits_per_pixel == 8)
1302 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1308 /*************************************************************************
1309 cirrusfb_pan_display()
1311 performs display panning - provided hardware permits this
1312 **************************************************************************/
1313 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1314 struct fb_info *info)
1318 unsigned char tmp, xpix;
1319 struct cirrusfb_info *cinfo = info->par;
1321 /* no range checks for xoffset and yoffset, */
1322 /* as fb_pan_display has already done this */
1323 if (var->vmode & FB_VMODE_YWRAP)
1326 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1328 base = var->yoffset * info->fix.line_length + xoffset;
1330 if (info->var.bits_per_pixel == 1) {
1331 /* base is already correct */
1332 xpix = (unsigned char) (var->xoffset % 8);
1335 xpix = (unsigned char) ((xoffset % 4) * 2);
1338 if (!is_laguna(cinfo))
1339 cirrusfb_WaitBLT(cinfo->regbase);
1341 /* lower 8 + 8 bits of screen start address */
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1345 /* 0xf2 is %11110010, exclude tmp bits */
1346 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1347 /* construct bits 16, 17 and 18 of screen start address */
1355 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1357 /* construct bit 19 of screen start address */
1358 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1359 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1360 if (is_laguna(cinfo))
1361 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1363 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1364 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1367 /* write pixel panning value to AR33; this does not quite work in 8bpp
1369 * ### Piccolo..? Will this work?
1371 if (info->var.bits_per_pixel == 1)
1372 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1377 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1380 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1381 * then the caller blanks by setting the CLUT (Color Look Up Table)
1382 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1383 * failed due to e.g. a video mode which doesn't support it.
1384 * Implements VESA suspend and powerdown modes on hardware that
1385 * supports disabling hsync/vsync:
1386 * blank_mode == 2: suspend vsync
1387 * blank_mode == 3: suspend hsync
1388 * blank_mode == 4: powerdown
1391 struct cirrusfb_info *cinfo = info->par;
1392 int current_mode = cinfo->blank_mode;
1394 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1396 if (info->state != FBINFO_STATE_RUNNING ||
1397 current_mode == blank_mode) {
1398 dev_dbg(info->device, "EXIT, returning 0\n");
1403 if (current_mode == FB_BLANK_NORMAL ||
1404 current_mode == FB_BLANK_UNBLANK)
1405 /* clear "FullBandwidth" bit */
1408 /* set "FullBandwidth" bit */
1411 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1412 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1414 switch (blank_mode) {
1415 case FB_BLANK_UNBLANK:
1416 case FB_BLANK_NORMAL:
1419 case FB_BLANK_VSYNC_SUSPEND:
1422 case FB_BLANK_HSYNC_SUSPEND:
1425 case FB_BLANK_POWERDOWN:
1429 dev_dbg(info->device, "EXIT, returning 1\n");
1433 vga_wgfx(cinfo->regbase, CL_GRE, val);
1435 cinfo->blank_mode = blank_mode;
1436 dev_dbg(info->device, "EXIT, returning 0\n");
1438 /* Let fbcon do a soft blank for us */
1439 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1442 /**** END Hardware specific Routines **************************************/
1443 /****************************************************************************/
1444 /**** BEGIN Internal Routines ***********************************************/
1446 static void init_vgachip(struct fb_info *info)
1448 struct cirrusfb_info *cinfo = info->par;
1449 const struct cirrusfb_board_info_rec *bi;
1451 assert(cinfo != NULL);
1453 bi = &cirrusfb_board_info[cinfo->btype];
1455 /* reset board globally */
1456 switch (cinfo->btype) {
1475 /* disable flickerfixer */
1476 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1479 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1482 /* from Klaus' NetBSD driver: */
1483 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1486 /* put blitter into 542x compat */
1487 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1492 /* Nothing to do to reset the board. */
1496 dev_err(info->device, "Warning: Unknown board type\n");
1500 /* make sure RAM size set by this point */
1501 assert(info->screen_size > 0);
1503 /* the P4 is not fully initialized here; I rely on it having been */
1504 /* inited under AmigaOS already, which seems to work just fine */
1505 /* (Klaus advised to do it this way) */
1507 if (cinfo->btype != BT_PICASSO4) {
1508 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1509 WGen(cinfo, CL_POS102, 0x01);
1510 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1512 if (cinfo->btype != BT_SD64)
1513 WGen(cinfo, CL_VSSM2, 0x01);
1515 /* reset sequencer logic */
1516 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1518 /* FullBandwidth (video off) and 8/9 dot clock */
1519 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1521 /* "magic cookie" - doesn't make any sense to me.. */
1522 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1523 /* unlock all extension registers */
1524 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1526 switch (cinfo->btype) {
1528 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1536 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1540 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1541 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1545 /* plane mask: nothing */
1546 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1547 /* character map select: doesn't even matter in gx mode */
1548 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1549 /* memory mode: chain4, ext. memory */
1550 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1552 /* controller-internal base address of video memory */
1554 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1556 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1557 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1559 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1560 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1561 /* graphics cursor Y position (..."... ) */
1562 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1563 /* graphics cursor attributes */
1564 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1565 /* graphics cursor pattern address */
1566 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1568 /* writing these on a P4 might give problems.. */
1569 if (cinfo->btype != BT_PICASSO4) {
1570 /* configuration readback and ext. color */
1571 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1572 /* signature generator */
1573 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1576 /* Screen A preset row scan: none */
1577 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1578 /* Text cursor start: disable text cursor */
1579 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1580 /* Text cursor end: - */
1581 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1582 /* text cursor location high: 0 */
1583 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1584 /* text cursor location low: 0 */
1585 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1587 /* Underline Row scanline: - */
1588 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1589 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1590 /* ext. display controls: ext.adr. wrap */
1591 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1593 /* Set/Reset registers: - */
1594 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1595 /* Set/Reset enable: - */
1596 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1597 /* Color Compare: - */
1598 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1599 /* Data Rotate: - */
1600 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1601 /* Read Map Select: - */
1602 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1603 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1604 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1605 /* Miscellaneous: memory map base address, graphics mode */
1606 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1607 /* Color Don't care: involve all planes */
1608 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1609 /* Bit Mask: no mask at all */
1610 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1612 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1614 /* (5434 can't have bit 3 set for bitblt) */
1615 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1617 /* Graphics controller mode extensions: finer granularity,
1618 * 8byte data latches
1620 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1622 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1623 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1624 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1625 /* Background color byte 1: - */
1626 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1627 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1629 /* Attribute Controller palette registers: "identity mapping" */
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1647 /* Attribute Controller mode: graphics mode */
1648 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1649 /* Overscan color reg.: reg. 0 */
1650 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1651 /* Color Plane enable: Enable all 4 planes */
1652 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1653 /* Color Select: - */
1654 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1656 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1658 /* BLT Start/status: Blitter reset */
1659 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1660 /* - " - : "end-of-reset" */
1661 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1664 WHDR(cinfo, 0); /* Hidden DAC register: - */
1668 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1670 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1671 static int IsOn = 0; /* XXX not ok for multiple boards */
1673 if (cinfo->btype == BT_PICASSO4)
1674 return; /* nothing to switch */
1675 if (cinfo->btype == BT_ALPINE)
1676 return; /* nothing to switch */
1677 if (cinfo->btype == BT_GD5480)
1678 return; /* nothing to switch */
1679 if (cinfo->btype == BT_PICASSO) {
1680 if ((on && !IsOn) || (!on && IsOn))
1685 switch (cinfo->btype) {
1687 WSFR(cinfo, cinfo->SFR | 0x21);
1690 WSFR(cinfo, cinfo->SFR | 0x28);
1695 default: /* do nothing */ break;
1698 switch (cinfo->btype) {
1700 WSFR(cinfo, cinfo->SFR & 0xde);
1703 WSFR(cinfo, cinfo->SFR & 0xd7);
1708 default: /* do nothing */
1712 #endif /* CONFIG_ZORRO */
1715 /******************************************/
1716 /* Linux 2.6-style accelerated functions */
1717 /******************************************/
1719 static int cirrusfb_sync(struct fb_info *info)
1721 struct cirrusfb_info *cinfo = info->par;
1723 if (!is_laguna(cinfo)) {
1724 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1730 static void cirrusfb_fillrect(struct fb_info *info,
1731 const struct fb_fillrect *region)
1733 struct fb_fillrect modded;
1735 struct cirrusfb_info *cinfo = info->par;
1736 int m = info->var.bits_per_pixel;
1737 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1738 cinfo->pseudo_palette[region->color] : region->color;
1740 if (info->state != FBINFO_STATE_RUNNING)
1742 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1743 cfb_fillrect(info, region);
1747 vxres = info->var.xres_virtual;
1748 vyres = info->var.yres_virtual;
1750 memcpy(&modded, region, sizeof(struct fb_fillrect));
1752 if (!modded.width || !modded.height ||
1753 modded.dx >= vxres || modded.dy >= vyres)
1756 if (modded.dx + modded.width > vxres)
1757 modded.width = vxres - modded.dx;
1758 if (modded.dy + modded.height > vyres)
1759 modded.height = vyres - modded.dy;
1761 cirrusfb_RectFill(cinfo->regbase,
1762 info->var.bits_per_pixel,
1763 (region->dx * m) / 8, region->dy,
1764 (region->width * m) / 8, region->height,
1766 info->fix.line_length, 0x40);
1769 static void cirrusfb_copyarea(struct fb_info *info,
1770 const struct fb_copyarea *area)
1772 struct fb_copyarea modded;
1774 struct cirrusfb_info *cinfo = info->par;
1775 int m = info->var.bits_per_pixel;
1777 if (info->state != FBINFO_STATE_RUNNING)
1779 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1780 cfb_copyarea(info, area);
1784 vxres = info->var.xres_virtual;
1785 vyres = info->var.yres_virtual;
1786 memcpy(&modded, area, sizeof(struct fb_copyarea));
1788 if (!modded.width || !modded.height ||
1789 modded.sx >= vxres || modded.sy >= vyres ||
1790 modded.dx >= vxres || modded.dy >= vyres)
1793 if (modded.sx + modded.width > vxres)
1794 modded.width = vxres - modded.sx;
1795 if (modded.dx + modded.width > vxres)
1796 modded.width = vxres - modded.dx;
1797 if (modded.sy + modded.height > vyres)
1798 modded.height = vyres - modded.sy;
1799 if (modded.dy + modded.height > vyres)
1800 modded.height = vyres - modded.dy;
1802 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1803 (area->sx * m) / 8, area->sy,
1804 (area->dx * m) / 8, area->dy,
1805 (area->width * m) / 8, area->height,
1806 info->fix.line_length);
1810 static void cirrusfb_imageblit(struct fb_info *info,
1811 const struct fb_image *image)
1813 struct cirrusfb_info *cinfo = info->par;
1814 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
1816 if (info->state != FBINFO_STATE_RUNNING)
1818 /* Alpine/SD64 does not work at 24bpp ??? */
1819 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
1820 cfb_imageblit(info, image);
1821 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1823 cfb_imageblit(info, image);
1825 unsigned size = ((image->width + 7) >> 3) * image->height;
1826 int m = info->var.bits_per_pixel;
1829 if (info->var.bits_per_pixel == 8) {
1830 fg = image->fg_color;
1831 bg = image->bg_color;
1833 fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
1834 bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
1836 if (info->var.bits_per_pixel == 24) {
1837 /* clear background first */
1838 cirrusfb_RectFill(cinfo->regbase,
1839 info->var.bits_per_pixel,
1840 (image->dx * m) / 8, image->dy,
1841 (image->width * m) / 8,
1844 info->fix.line_length, 0x40);
1846 cirrusfb_RectFill(cinfo->regbase,
1847 info->var.bits_per_pixel,
1848 (image->dx * m) / 8, image->dy,
1849 (image->width * m) / 8, image->height,
1851 info->fix.line_length, op);
1852 memcpy(info->screen_base, image->data, size);
1857 static int release_io_ports;
1859 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1860 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1861 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1863 static unsigned int cirrusfb_get_memsize(struct fb_info *info,
1864 u8 __iomem *regbase)
1867 struct cirrusfb_info *cinfo = info->par;
1869 if (is_laguna(cinfo)) {
1870 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1872 mem = ((SR14 & 7) + 1) << 20;
1874 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1875 switch ((SRF & 0x18)) {
1882 /* 64-bit DRAM data bus width; assume 2MB.
1883 * Also indicates 2MB memory on the 5430.
1889 dev_warn(info->device, "Unknown memory size!\n");
1892 /* If DRAM bank switching is enabled, there must be
1893 * twice as much memory installed. (4MB on the 5434)
1895 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1899 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1903 static void get_pci_addrs(const struct pci_dev *pdev,
1904 unsigned long *display, unsigned long *registers)
1906 assert(pdev != NULL);
1907 assert(display != NULL);
1908 assert(registers != NULL);
1913 /* This is a best-guess for now */
1915 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1916 *display = pci_resource_start(pdev, 1);
1917 *registers = pci_resource_start(pdev, 0);
1919 *display = pci_resource_start(pdev, 0);
1920 *registers = pci_resource_start(pdev, 1);
1923 assert(*display != 0);
1926 static void cirrusfb_pci_unmap(struct fb_info *info)
1928 struct pci_dev *pdev = to_pci_dev(info->device);
1929 struct cirrusfb_info *cinfo = info->par;
1931 if (cinfo->laguna_mmio == NULL)
1932 iounmap(cinfo->laguna_mmio);
1933 iounmap(info->screen_base);
1934 #if 0 /* if system didn't claim this region, we would... */
1935 release_mem_region(0xA0000, 65535);
1937 if (release_io_ports)
1938 release_region(0x3C0, 32);
1939 pci_release_regions(pdev);
1941 #endif /* CONFIG_PCI */
1944 static void cirrusfb_zorro_unmap(struct fb_info *info)
1946 struct cirrusfb_info *cinfo = info->par;
1947 struct zorro_dev *zdev = to_zorro_dev(info->device);
1949 if (info->fix.smem_start > 16 * MB_)
1950 iounmap(info->screen_base);
1951 if (info->fix.mmio_start > 16 * MB_)
1952 iounmap(cinfo->regbase);
1954 zorro_release_device(zdev);
1956 #endif /* CONFIG_ZORRO */
1958 /* function table of the above functions */
1959 static const struct fb_ops cirrusfb_ops = {
1960 .owner = THIS_MODULE,
1961 .fb_open = cirrusfb_open,
1962 .fb_release = cirrusfb_release,
1963 .fb_setcolreg = cirrusfb_setcolreg,
1964 .fb_check_var = cirrusfb_check_var,
1965 .fb_set_par = cirrusfb_set_par,
1966 .fb_pan_display = cirrusfb_pan_display,
1967 .fb_blank = cirrusfb_blank,
1968 .fb_fillrect = cirrusfb_fillrect,
1969 .fb_copyarea = cirrusfb_copyarea,
1970 .fb_sync = cirrusfb_sync,
1971 .fb_imageblit = cirrusfb_imageblit,
1974 static int cirrusfb_set_fbinfo(struct fb_info *info)
1976 struct cirrusfb_info *cinfo = info->par;
1977 struct fb_var_screeninfo *var = &info->var;
1979 info->pseudo_palette = cinfo->pseudo_palette;
1980 info->flags = FBINFO_DEFAULT
1981 | FBINFO_HWACCEL_XPAN
1982 | FBINFO_HWACCEL_YPAN
1983 | FBINFO_HWACCEL_FILLRECT
1984 | FBINFO_HWACCEL_IMAGEBLIT
1985 | FBINFO_HWACCEL_COPYAREA;
1986 if (noaccel || is_laguna(cinfo)) {
1987 info->flags |= FBINFO_HWACCEL_DISABLED;
1988 info->fix.accel = FB_ACCEL_NONE;
1990 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
1992 info->fbops = &cirrusfb_ops;
1994 if (cinfo->btype == BT_GD5480) {
1995 if (var->bits_per_pixel == 16)
1996 info->screen_base += 1 * MB_;
1997 if (var->bits_per_pixel == 32)
1998 info->screen_base += 2 * MB_;
2001 /* Fill fix common fields */
2002 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2003 sizeof(info->fix.id));
2005 /* monochrome: only 1 memory plane */
2006 /* 8 bit and above: Use whole memory area */
2007 info->fix.smem_len = info->screen_size;
2008 if (var->bits_per_pixel == 1)
2009 info->fix.smem_len /= 4;
2010 info->fix.type_aux = 0;
2011 info->fix.xpanstep = 1;
2012 info->fix.ypanstep = 1;
2013 info->fix.ywrapstep = 0;
2015 /* FIXME: map region at 0xB8000 if available, fill in here */
2016 info->fix.mmio_len = 0;
2018 fb_alloc_cmap(&info->cmap, 256, 0);
2023 static int cirrusfb_register(struct fb_info *info)
2025 struct cirrusfb_info *cinfo = info->par;
2029 assert(cinfo->btype != BT_NONE);
2031 /* set all the vital stuff */
2032 cirrusfb_set_fbinfo(info);
2034 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2036 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2038 dev_dbg(info->device, "wrong initial video mode\n");
2040 goto err_dealloc_cmap;
2043 info->var.activate = FB_ACTIVATE_NOW;
2045 err = cirrusfb_check_var(&info->var, info);
2047 /* should never happen */
2048 dev_dbg(info->device,
2049 "choking on default var... umm, no good.\n");
2050 goto err_dealloc_cmap;
2053 err = register_framebuffer(info);
2055 dev_err(info->device,
2056 "could not register fb device; err = %d!\n", err);
2057 goto err_dealloc_cmap;
2063 fb_dealloc_cmap(&info->cmap);
2067 static void cirrusfb_cleanup(struct fb_info *info)
2069 struct cirrusfb_info *cinfo = info->par;
2071 switch_monitor(cinfo, 0);
2072 unregister_framebuffer(info);
2073 fb_dealloc_cmap(&info->cmap);
2074 dev_dbg(info->device, "Framebuffer unregistered\n");
2076 framebuffer_release(info);
2080 static int cirrusfb_pci_register(struct pci_dev *pdev,
2081 const struct pci_device_id *ent)
2083 struct cirrusfb_info *cinfo;
2084 struct fb_info *info;
2085 unsigned long board_addr, board_size;
2088 ret = pci_enable_device(pdev);
2090 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2094 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2101 cinfo->btype = (enum cirrus_board) ent->driver_data;
2103 dev_dbg(info->device,
2104 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2105 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2106 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2107 (unsigned long long)pdev->resource[1].start);
2109 dev_dbg(info->device,
2110 "Attempt to get PCI info for Cirrus Graphics Card\n");
2111 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2112 /* FIXME: this forces VGA. alternatives? */
2113 cinfo->regbase = NULL;
2114 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2116 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2117 board_addr, info->fix.mmio_start);
2119 board_size = (cinfo->btype == BT_GD5480) ?
2120 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2122 ret = pci_request_regions(pdev, "cirrusfb");
2124 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2126 goto err_release_fb;
2128 #if 0 /* if the system didn't claim this region, we would... */
2129 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2130 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2133 goto err_release_regions;
2136 if (request_region(0x3C0, 32, "cirrusfb"))
2137 release_io_ports = 1;
2139 info->screen_base = ioremap(board_addr, board_size);
2140 if (!info->screen_base) {
2142 goto err_release_legacy;
2145 info->fix.smem_start = board_addr;
2146 info->screen_size = board_size;
2147 cinfo->unmap = cirrusfb_pci_unmap;
2149 dev_info(info->device,
2150 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2151 info->screen_size >> 10, board_addr);
2152 pci_set_drvdata(pdev, info);
2154 ret = cirrusfb_register(info);
2158 iounmap(info->screen_base);
2160 if (release_io_ports)
2161 release_region(0x3C0, 32);
2163 release_mem_region(0xA0000, 65535);
2164 err_release_regions:
2166 pci_release_regions(pdev);
2168 if (cinfo->laguna_mmio != NULL)
2169 iounmap(cinfo->laguna_mmio);
2170 framebuffer_release(info);
2175 static void cirrusfb_pci_unregister(struct pci_dev *pdev)
2177 struct fb_info *info = pci_get_drvdata(pdev);
2179 cirrusfb_cleanup(info);
2182 static struct pci_driver cirrusfb_pci_driver = {
2184 .id_table = cirrusfb_pci_table,
2185 .probe = cirrusfb_pci_register,
2186 .remove = cirrusfb_pci_unregister,
2189 .suspend = cirrusfb_pci_suspend,
2190 .resume = cirrusfb_pci_resume,
2194 #endif /* CONFIG_PCI */
2197 static int cirrusfb_zorro_register(struct zorro_dev *z,
2198 const struct zorro_device_id *ent)
2200 struct fb_info *info;
2202 const struct zorrocl *zcl;
2203 enum cirrus_board btype;
2204 unsigned long regbase, ramsize, rambase;
2205 struct cirrusfb_info *cinfo;
2207 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2211 zcl = (const struct zorrocl *)ent->driver_data;
2213 regbase = zorro_resource_start(z) + zcl->regoffset;
2214 ramsize = zcl->ramsize;
2216 rambase = zorro_resource_start(z) + zcl->ramoffset;
2217 if (zorro_resource_len(z) == 64 * MB_) {
2218 /* Quirk for 64 MiB Picasso IV */
2219 rambase += zcl->ramoffset;
2222 struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL);
2223 if (!ram || !zorro_resource_len(ram)) {
2224 dev_err(info->device, "No video RAM found\n");
2226 goto err_release_fb;
2228 rambase = zorro_resource_start(ram);
2229 ramsize = zorro_resource_len(ram);
2231 (ram = zorro_find_device(zcl->ramid2, NULL))) {
2232 if (zorro_resource_start(ram) != rambase + ramsize) {
2233 dev_warn(info->device,
2234 "Skipping non-contiguous RAM at %pR\n",
2237 ramsize += zorro_resource_len(ram);
2242 dev_info(info->device,
2243 "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n",
2244 cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
2247 if (!zorro_request_device(z, "cirrusfb")) {
2248 dev_err(info->device, "Cannot reserve %pR\n", &z->resource);
2250 goto err_release_fb;
2254 cinfo->btype = btype;
2256 info->fix.mmio_start = regbase;
2257 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2258 : ZTWO_VADDR(regbase);
2259 if (!cinfo->regbase) {
2260 dev_err(info->device, "Cannot map registers\n");
2262 goto err_release_dev;
2265 info->fix.smem_start = rambase;
2266 info->screen_size = ramsize;
2267 info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize)
2268 : ZTWO_VADDR(rambase);
2269 if (!info->screen_base) {
2270 dev_err(info->device, "Cannot map video RAM\n");
2275 cinfo->unmap = cirrusfb_zorro_unmap;
2277 dev_info(info->device,
2278 "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n",
2279 ramsize / MB_, rambase);
2281 /* MCLK select etc. */
2282 if (cirrusfb_board_info[btype].init_sr1f)
2283 vga_wseq(cinfo->regbase, CL_SEQR1F,
2284 cirrusfb_board_info[btype].sr1f);
2286 error = cirrusfb_register(info);
2288 dev_err(info->device, "Failed to register device, error %d\n",
2293 zorro_set_drvdata(z, info);
2297 if (rambase > 16 * MB_)
2298 iounmap(info->screen_base);
2301 if (regbase > 16 * MB_)
2302 iounmap(cinfo->regbase);
2304 zorro_release_device(z);
2306 framebuffer_release(info);
2310 void cirrusfb_zorro_unregister(struct zorro_dev *z)
2312 struct fb_info *info = zorro_get_drvdata(z);
2314 cirrusfb_cleanup(info);
2315 zorro_set_drvdata(z, NULL);
2318 static struct zorro_driver cirrusfb_zorro_driver = {
2320 .id_table = cirrusfb_zorro_table,
2321 .probe = cirrusfb_zorro_register,
2322 .remove = cirrusfb_zorro_unregister,
2324 #endif /* CONFIG_ZORRO */
2327 static int __init cirrusfb_setup(char *options)
2331 if (!options || !*options)
2334 while ((this_opt = strsep(&options, ",")) != NULL) {
2338 if (!strcmp(this_opt, "noaccel"))
2340 else if (!strncmp(this_opt, "mode:", 5))
2341 mode_option = this_opt + 5;
2343 mode_option = this_opt;
2353 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2354 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2355 MODULE_LICENSE("GPL");
2357 static int __init cirrusfb_init(void)
2362 char *option = NULL;
2364 if (fb_get_options("cirrusfb", &option))
2366 cirrusfb_setup(option);
2370 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2373 error |= pci_register_driver(&cirrusfb_pci_driver);
2378 static void __exit cirrusfb_exit(void)
2381 pci_unregister_driver(&cirrusfb_pci_driver);
2384 zorro_unregister_driver(&cirrusfb_zorro_driver);
2388 module_init(cirrusfb_init);
2390 module_param(mode_option, charp, 0);
2391 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2392 module_param(noaccel, bool, 0);
2393 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2396 module_exit(cirrusfb_exit);
2399 /**********************************************************************/
2400 /* about the following functions - I have used the same names for the */
2401 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2402 /* they just made sense for this purpose. Apart from that, I wrote */
2403 /* these functions myself. */
2404 /**********************************************************************/
2406 /*** WGen() - write into one of the external/general registers ***/
2407 static void WGen(const struct cirrusfb_info *cinfo,
2408 int regnum, unsigned char val)
2410 unsigned long regofs = 0;
2412 if (cinfo->btype == BT_PICASSO) {
2413 /* Picasso II specific hack */
2414 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2415 regnum == CL_VSSM2) */
2416 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2420 vga_w(cinfo->regbase, regofs + regnum, val);
2423 /*** RGen() - read out one of the external/general registers ***/
2424 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2426 unsigned long regofs = 0;
2428 if (cinfo->btype == BT_PICASSO) {
2429 /* Picasso II specific hack */
2430 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2431 regnum == CL_VSSM2) */
2432 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2436 return vga_r(cinfo->regbase, regofs + regnum);
2439 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2440 static void AttrOn(const struct cirrusfb_info *cinfo)
2442 assert(cinfo != NULL);
2444 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2445 /* if we're just in "write value" mode, write back the */
2446 /* same value as before to not modify anything */
2447 vga_w(cinfo->regbase, VGA_ATT_IW,
2448 vga_r(cinfo->regbase, VGA_ATT_R));
2450 /* turn on video bit */
2451 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2452 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2454 /* dummy write on Reg0 to be on "write index" mode next time */
2455 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2458 /*** WHDR() - write into the Hidden DAC register ***/
2459 /* as the HDR is the only extension register that requires special treatment
2460 * (the other extension registers are accessible just like the "ordinary"
2461 * registers of their functional group) here is a specialized routine for
2464 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2466 if (is_laguna(cinfo))
2468 if (cinfo->btype == BT_PICASSO) {
2469 /* Klaus' hint for correct access to HDR on some boards */
2470 /* first write 0 to pixel mask (3c6) */
2471 WGen(cinfo, VGA_PEL_MSK, 0x00);
2473 /* next read dummy from pixel address (3c8) */
2474 RGen(cinfo, VGA_PEL_IW);
2477 /* now do the usual stuff to access the HDR */
2479 RGen(cinfo, VGA_PEL_MSK);
2481 RGen(cinfo, VGA_PEL_MSK);
2483 RGen(cinfo, VGA_PEL_MSK);
2485 RGen(cinfo, VGA_PEL_MSK);
2488 WGen(cinfo, VGA_PEL_MSK, val);
2491 if (cinfo->btype == BT_PICASSO) {
2492 /* now first reset HDR access counter */
2493 RGen(cinfo, VGA_PEL_IW);
2496 /* and at the end, restore the mask value */
2497 /* ## is this mask always 0xff? */
2498 WGen(cinfo, VGA_PEL_MSK, 0xff);
2503 /*** WSFR() - write to the "special function register" (SFR) ***/
2504 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2507 assert(cinfo->regbase != NULL);
2509 z_writeb(val, cinfo->regbase + 0x8000);
2513 /* The Picasso has a second register for switching the monitor bit */
2514 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2517 /* writing an arbitrary value to this one causes the monitor switcher */
2518 /* to flip to Amiga display */
2519 assert(cinfo->regbase != NULL);
2521 z_writeb(val, cinfo->regbase + 0x9000);
2525 /*** WClut - set CLUT entry (range: 0..63) ***/
2526 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2527 unsigned char green, unsigned char blue)
2529 unsigned int data = VGA_PEL_D;
2531 /* address write mode register is not translated.. */
2532 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2534 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2535 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2536 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2537 /* but DAC data register IS, at least for Picasso II */
2538 if (cinfo->btype == BT_PICASSO)
2540 vga_w(cinfo->regbase, data, red);
2541 vga_w(cinfo->regbase, data, green);
2542 vga_w(cinfo->regbase, data, blue);
2544 vga_w(cinfo->regbase, data, blue);
2545 vga_w(cinfo->regbase, data, green);
2546 vga_w(cinfo->regbase, data, red);
2551 /*** RClut - read CLUT entry (range 0..63) ***/
2552 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2553 unsigned char *green, unsigned char *blue)
2555 unsigned int data = VGA_PEL_D;
2557 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2559 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2560 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2561 if (cinfo->btype == BT_PICASSO)
2563 *red = vga_r(cinfo->regbase, data);
2564 *green = vga_r(cinfo->regbase, data);
2565 *blue = vga_r(cinfo->regbase, data);
2567 *blue = vga_r(cinfo->regbase, data);
2568 *green = vga_r(cinfo->regbase, data);
2569 *red = vga_r(cinfo->regbase, data);
2574 /*******************************************************************
2577 Wait for the BitBLT engine to complete a possible earlier job
2578 *********************************************************************/
2580 /* FIXME: use interrupts instead */
2581 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2583 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2587 /*******************************************************************
2590 perform accelerated "scrolling"
2591 ********************************************************************/
2593 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2594 u_short nwidth, u_short nheight,
2595 u_long nsrc, u_long ndest,
2596 u_short bltmode, u_short line_length)
2599 /* pitch: set to line_length */
2600 /* dest pitch low */
2601 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2603 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2604 /* source pitch low */
2605 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2606 /* source pitch hi */
2607 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2609 /* BLT width: actual number of pixels - 1 */
2611 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2613 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2615 /* BLT height: actual number of lines -1 */
2616 /* BLT height low */
2617 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2619 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2621 /* BLT destination */
2623 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2625 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2627 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2631 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2633 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2635 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2638 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2640 /* BLT ROP: SrcCopy */
2641 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2643 /* and finally: GO! */
2644 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2647 /*******************************************************************
2650 perform accelerated "scrolling"
2651 ********************************************************************/
2653 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2654 u_short curx, u_short cury,
2655 u_short destx, u_short desty,
2656 u_short width, u_short height,
2657 u_short line_length)
2659 u_short nwidth = width - 1;
2660 u_short nheight = height - 1;
2665 /* if source adr < dest addr, do the Blt backwards */
2666 if (cury <= desty) {
2667 if (cury == desty) {
2668 /* if src and dest are on the same line, check x */
2674 /* standard case: forward blitting */
2675 nsrc = (cury * line_length) + curx;
2676 ndest = (desty * line_length) + destx;
2678 /* this means start addresses are at the end,
2679 * counting backwards
2681 nsrc += nheight * line_length + nwidth;
2682 ndest += nheight * line_length + nwidth;
2685 cirrusfb_WaitBLT(regbase);
2687 cirrusfb_set_blitter(regbase, nwidth, nheight,
2688 nsrc, ndest, bltmode, line_length);
2691 /*******************************************************************
2694 perform accelerated rectangle fill
2695 ********************************************************************/
2697 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2698 u_short x, u_short y, u_short width, u_short height,
2699 u32 fg_color, u32 bg_color, u_short line_length,
2702 u_long ndest = (y * line_length) + x;
2705 cirrusfb_WaitBLT(regbase);
2707 /* This is a ColorExpand Blt, using the */
2708 /* same color for foreground and background */
2709 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2710 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2713 if (bits_per_pixel >= 16) {
2714 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2715 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2718 if (bits_per_pixel >= 24) {
2719 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2720 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2723 if (bits_per_pixel == 32) {
2724 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2725 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2728 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2729 0, ndest, op | blitmode, line_length);
2732 /**************************************************************************
2733 * bestclock() - determine closest possible clock lower(?) than the
2734 * desired pixel clock
2735 **************************************************************************/
2736 static void bestclock(long freq, int *nom, int *den, int *div)
2741 assert(nom != NULL);
2742 assert(den != NULL);
2743 assert(div != NULL);
2754 for (n = 32; n < 128; n++) {
2757 d = (14318 * n) / freq;
2758 if ((d >= 7) && (d <= 63)) {
2765 h = ((14318 * n) / temp) >> s;
2766 h = h > freq ? h - freq : freq - h;
2775 if ((d >= 7) && (d <= 63)) {
2780 h = ((14318 * n) / d) >> s;
2781 h = h > freq ? h - freq : freq - h;
2792 /* -------------------------------------------------------------------------
2794 * debugging functions
2796 * -------------------------------------------------------------------------
2799 #ifdef CIRRUSFB_DEBUG
2802 * cirrusfb_dbg_print_regs
2803 * @regbase: If using newmmio, the newmmio base address, otherwise %NULL
2804 * @reg_class: type of registers to read: %CRT, or %SEQ
2807 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2808 * old-style I/O ports are queried for information, otherwise MMIO is
2809 * used at the given @base address to query the information.
2812 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2814 enum cirrusfb_dbg_reg_class reg_class, ...)
2817 unsigned char val = 0;
2821 va_start(list, reg_class);
2823 name = va_arg(list, char *);
2824 while (name != NULL) {
2825 reg = va_arg(list, int);
2827 switch (reg_class) {
2829 val = vga_rcrt(regbase, (unsigned char) reg);
2832 val = vga_rseq(regbase, (unsigned char) reg);
2835 /* should never occur */
2840 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2842 name = va_arg(list, char *);
2849 * cirrusfb_dbg_reg_dump
2850 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2853 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2854 * old-style I/O ports are queried for information, otherwise MMIO is
2855 * used at the given @base address to query the information.
2858 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2860 dev_dbg(info->device, "VGA CRTC register dump:\n");
2862 cirrusfb_dbg_print_regs(info, regbase, CRT,
2912 dev_dbg(info->device, "\n");
2914 dev_dbg(info->device, "VGA SEQ register dump:\n");
2916 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2945 dev_dbg(info->device, "\n");
2948 #endif /* CIRRUSFB_DEBUG */