drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16
  17 #include <video/exynos_dp.h>
  18
  19 #include "exynos_dp_core.h"
  20 #include "exynos_dp_reg.h"
  21
  22 #define COMMON_INT_MASK_1       0
  23 #define COMMON_INT_MASK_2       0
  24 #define COMMON_INT_MASK_3       0
  25 #define COMMON_INT_MASK_4       (HOTPLUG_CHG | HPD_LOST | PLUG)
  26 #define INT_STA_MASK            INT_HPD
  27
  28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  29 {
  30         u32 reg;
  31
  32         if (enable) {
  33                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  34                 reg |= HDCP_VIDEO_MUTE;
  35                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  36         } else {
  37                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  38                 reg &= ~HDCP_VIDEO_MUTE;
  39                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  40         }
  41 }
  42
  43 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  44 {
  45         u32 reg;
  46
  47         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  48         reg &= ~VIDEO_EN;
  49         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  50 }
  51
  52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  53 {
  54         u32 reg;
  55
  56         if (enable)
  57                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  58                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  59         else
  60                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  61                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  62
  63         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  64 }
  65
  66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  67 {
  68         u32 reg;
  69
  70         reg = TX_TERMINAL_CTRL_50_OHM;
  71         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  72
  73         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  74         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  75
  76         reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
  77         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  78
  79         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
  80                 TX_CUR1_2X | TX_CUR_16_MA;
  81         writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  82
  83         reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
  84                 CH1_AMP_400_MV | CH0_AMP_400_MV;
  85         writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  86 }
  87
  88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  89 {
  90         /* Set interrupt pin assertion polarity as high */
  91         writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
  92
  93         /* Clear pending regisers */
  94         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  95         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  96         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  97         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
  98         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
  99
 100         /* 0:mask,1: unmask */
 101         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 102         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 103         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 104         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 105         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 106 }
 107
 108 void exynos_dp_reset(struct exynos_dp_device *dp)
 109 {
 110         u32 reg;
 111
 112         exynos_dp_stop_video(dp);
 113         exynos_dp_enable_video_mute(dp, 0);
 114
 115         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 116                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 117                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 118         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 119
 120         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 121                 SERDES_FIFO_FUNC_EN_N |
 122                 LS_CLK_DOMAIN_FUNC_EN_N;
 123         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 124
 125         usleep_range(20, 30);
 126
 127         exynos_dp_lane_swap(dp, 0);
 128
 129         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 130         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 131         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 132         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 133
 134         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 135         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 136
 137         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 138         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 139
 140         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 141
 142         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 143
 144         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 145         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 146
 147         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 148         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 149
 150         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 151 }
 152
 153 void exynos_dp_swreset(struct exynos_dp_device *dp)
 154 {
 155         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
 156 }
 157
 158 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
 159 {
 160         u32 reg;
 161
 162         /* 0: mask, 1: unmask */
 163         reg = COMMON_INT_MASK_1;
 164         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 165
 166         reg = COMMON_INT_MASK_2;
 167         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 168
 169         reg = COMMON_INT_MASK_3;
 170         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 171
 172         reg = COMMON_INT_MASK_4;
 173         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 174
 175         reg = INT_STA_MASK;
 176         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 177 }
 178
 179 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 180 {
 181         u32 reg;
 182
 183         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 184         if (reg & PLL_LOCK)
 185                 return PLL_LOCKED;
 186         else
 187                 return PLL_UNLOCKED;
 188 }
 189
 190 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 191 {
 192         u32 reg;
 193
 194         if (enable) {
 195                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 196                 reg |= DP_PLL_PD;
 197                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 198         } else {
 199                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 200                 reg &= ~DP_PLL_PD;
 201                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 202         }
 203 }
 204
 205 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 206                                 enum analog_power_block block,
 207                                 bool enable)
 208 {
 209         u32 reg;
 210
 211         switch (block) {
 212         case AUX_BLOCK:
 213                 if (enable) {
 214                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 215                         reg |= AUX_PD;
 216                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 217                 } else {
 218                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 219                         reg &= ~AUX_PD;
 220                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 221                 }
 222                 break;
 223         case CH0_BLOCK:
 224                 if (enable) {
 225                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 226                         reg |= CH0_PD;
 227                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 228                 } else {
 229                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 230                         reg &= ~CH0_PD;
 231                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 232                 }
 233                 break;
 234         case CH1_BLOCK:
 235                 if (enable) {
 236                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 237                         reg |= CH1_PD;
 238                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 239                 } else {
 240                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 241                         reg &= ~CH1_PD;
 242                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 243                 }
 244                 break;
 245         case CH2_BLOCK:
 246                 if (enable) {
 247                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 248                         reg |= CH2_PD;
 249                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 250                 } else {
 251                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 252                         reg &= ~CH2_PD;
 253                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 254                 }
 255                 break;
 256         case CH3_BLOCK:
 257                 if (enable) {
 258                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 259                         reg |= CH3_PD;
 260                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 261                 } else {
 262                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 263                         reg &= ~CH3_PD;
 264                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 265                 }
 266                 break;
 267         case ANALOG_TOTAL:
 268                 if (enable) {
 269                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 270                         reg |= DP_PHY_PD;
 271                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 272                 } else {
 273                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 274                         reg &= ~DP_PHY_PD;
 275                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 276                 }
 277                 break;
 278         case POWER_ALL:
 279                 if (enable) {
 280                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 281                                 CH1_PD | CH0_PD;
 282                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 283                 } else {
 284                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 285                 }
 286                 break;
 287         default:
 288                 break;
 289         }
 290 }
 291
 292 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 293 {
 294         u32 reg;
 295         int timeout_loop = 0;
 296
 297         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 298
 299         reg = PLL_LOCK_CHG;
 300         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 301
 302         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 303         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 304         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 305
 306         /* Power up PLL */
 307         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 308                 exynos_dp_set_pll_power_down(dp, 0);
 309
 310                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 311                         timeout_loop++;
 312                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 313                                 dev_err(dp->dev, "failed to get pll lock status\n");
 314                                 return;
 315                         }
 316                         usleep_range(10, 20);
 317                 }
 318         }
 319
 320         /* Enable Serdes FIFO function and Link symbol clock domain module */
 321         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 322         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 323                 | AUX_FUNC_EN_N);
 324         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 325 }
 326
 327 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
 328 {
 329         u32 reg;
 330
 331         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 332         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 333
 334         reg = INT_HPD;
 335         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 336 }
 337
 338 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 339 {
 340         u32 reg;
 341
 342         exynos_dp_clear_hotplug_interrupts(dp);
 343
 344         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 345         reg &= ~(F_HPD | HPD_CTRL);
 346         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 347 }
 348
 349 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
 350 {
 351         u32 reg;
 352
 353         /* Parse hotplug interrupt status register */
 354         reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 355
 356         if (reg & PLUG)
 357                 return DP_IRQ_TYPE_HP_CABLE_IN;
 358
 359         if (reg & HPD_LOST)
 360                 return DP_IRQ_TYPE_HP_CABLE_OUT;
 361
 362         if (reg & HOTPLUG_CHG)
 363                 return DP_IRQ_TYPE_HP_CHANGE;
 364
 365         return DP_IRQ_TYPE_UNKNOWN;
 366 }
 367
 368 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 369 {
 370         u32 reg;
 371
 372         /* Disable AUX channel module */
 373         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 374         reg |= AUX_FUNC_EN_N;
 375         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 376 }
 377
 378 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 379 {
 380         u32 reg;
 381
 382         /* Clear inerrupts related to AUX channel */
 383         reg = RPLY_RECEIV | AUX_ERR;
 384         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 385
 386         exynos_dp_reset_aux(dp);
 387
 388         /* Disable AUX transaction H/W retry */
 389         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 390                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 391         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 392
 393         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 394         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 395         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 396
 397         /* Enable AUX channel module */
 398         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 399         reg &= ~AUX_FUNC_EN_N;
 400         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 401 }
 402
 403 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 404 {
 405         u32 reg;
 406
 407         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 408         if (reg & HPD_STATUS)
 409                 return 0;
 410
 411         return -EINVAL;
 412 }
 413
 414 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 415 {
 416         u32 reg;
 417
 418         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 419         reg &= ~SW_FUNC_EN_N;
 420         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 421 }
 422
 423 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 424 {
 425         int reg;
 426         int retval = 0;
 427         int timeout_loop = 0;
 428
 429         /* Enable AUX CH operation */
 430         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 431         reg |= AUX_EN;
 432         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 433
 434         /* Is AUX CH command reply received? */
 435         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 436         while (!(reg & RPLY_RECEIV)) {
 437                 timeout_loop++;
 438                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 439                         dev_err(dp->dev, "AUX CH command reply failed!\n");
 440                         return -ETIMEDOUT;
 441                 }
 442                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 443                 usleep_range(10, 11);
 444         }
 445
 446         /* Clear interrupt source for AUX CH command reply */
 447         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 448
 449         /* Clear interrupt source for AUX CH access error */
 450         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 451         if (reg & AUX_ERR) {
 452                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 453                 return -EREMOTEIO;
 454         }
 455
 456         /* Check AUX CH error access status */
 457         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 458         if ((reg & AUX_STATUS_MASK) != 0) {
 459                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 460                         reg & AUX_STATUS_MASK);
 461                 return -EREMOTEIO;
 462         }
 463
 464         return retval;
 465 }
 466
 467 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 468                                 unsigned int reg_addr,
 469                                 unsigned char data)
 470 {
 471         u32 reg;
 472         int i;
 473         int retval;
 474
 475         for (i = 0; i < 3; i++) {
 476                 /* Clear AUX CH data buffer */
 477                 reg = BUF_CLR;
 478                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 479
 480                 /* Select DPCD device address */
 481                 reg = AUX_ADDR_7_0(reg_addr);
 482                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 483                 reg = AUX_ADDR_15_8(reg_addr);
 484                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 485                 reg = AUX_ADDR_19_16(reg_addr);
 486                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 487
 488                 /* Write data buffer */
 489                 reg = (unsigned int)data;
 490                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 491
 492                 /*
 493                  * Set DisplayPort transaction and write 1 byte
 494                  * If bit 3 is 1, DisplayPort transaction.
 495                  * If Bit 3 is 0, I2C transaction.
 496                  */
 497                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 498                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 499
 500                 /* Start AUX transaction */
 501                 retval = exynos_dp_start_aux_transaction(dp);
 502                 if (retval == 0)
 503                         break;
 504                 else
 505                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 506                                 __func__);
 507         }
 508
 509         return retval;
 510 }
 511
 512 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 513                                 unsigned int reg_addr,
 514                                 unsigned char *data)
 515 {
 516         u32 reg;
 517         int i;
 518         int retval;
 519
 520         for (i = 0; i < 3; i++) {
 521                 /* Clear AUX CH data buffer */
 522                 reg = BUF_CLR;
 523                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 524
 525                 /* Select DPCD device address */
 526                 reg = AUX_ADDR_7_0(reg_addr);
 527                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 528                 reg = AUX_ADDR_15_8(reg_addr);
 529                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 530                 reg = AUX_ADDR_19_16(reg_addr);
 531                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 532
 533                 /*
 534                  * Set DisplayPort transaction and read 1 byte
 535                  * If bit 3 is 1, DisplayPort transaction.
 536                  * If Bit 3 is 0, I2C transaction.
 537                  */
 538                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 539                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 540
 541                 /* Start AUX transaction */
 542                 retval = exynos_dp_start_aux_transaction(dp);
 543                 if (retval == 0)
 544                         break;
 545                 else
 546                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 547                                 __func__);
 548         }
 549
 550         /* Read data buffer */
 551         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 552         *data = (unsigned char)(reg & 0xff);
 553
 554         return retval;
 555 }
 556
 557 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 558                                 unsigned int reg_addr,
 559                                 unsigned int count,
 560                                 unsigned char data[])
 561 {
 562         u32 reg;
 563         unsigned int start_offset;
 564         unsigned int cur_data_count;
 565         unsigned int cur_data_idx;
 566         int i;
 567         int retval = 0;
 568
 569         /* Clear AUX CH data buffer */
 570         reg = BUF_CLR;
 571         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 572
 573         start_offset = 0;
 574         while (start_offset < count) {
 575                 /* Buffer size of AUX CH is 16 * 4bytes */
 576                 if ((count - start_offset) > 16)
 577                         cur_data_count = 16;
 578                 else
 579                         cur_data_count = count - start_offset;
 580
 581                 for (i = 0; i < 3; i++) {
 582                         /* Select DPCD device address */
 583                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 584                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 585                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 586                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 587                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 588                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 589
 590                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 591                              cur_data_idx++) {
 592                                 reg = data[start_offset + cur_data_idx];
 593                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 594                                                           + 4 * cur_data_idx);
 595                         }
 596
 597                         /*
 598                          * Set DisplayPort transaction and write
 599                          * If bit 3 is 1, DisplayPort transaction.
 600                          * If Bit 3 is 0, I2C transaction.
 601                          */
 602                         reg = AUX_LENGTH(cur_data_count) |
 603                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 604                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 605
 606                         /* Start AUX transaction */
 607                         retval = exynos_dp_start_aux_transaction(dp);
 608                         if (retval == 0)
 609                                 break;
 610                         else
 611                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 612                                         __func__);
 613                 }
 614
 615                 start_offset += cur_data_count;
 616         }
 617
 618         return retval;
 619 }
 620
 621 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 622                                 unsigned int reg_addr,
 623                                 unsigned int count,
 624                                 unsigned char data[])
 625 {
 626         u32 reg;
 627         unsigned int start_offset;
 628         unsigned int cur_data_count;
 629         unsigned int cur_data_idx;
 630         int i;
 631         int retval = 0;
 632
 633         /* Clear AUX CH data buffer */
 634         reg = BUF_CLR;
 635         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 636
 637         start_offset = 0;
 638         while (start_offset < count) {
 639                 /* Buffer size of AUX CH is 16 * 4bytes */
 640                 if ((count - start_offset) > 16)
 641                         cur_data_count = 16;
 642                 else
 643                         cur_data_count = count - start_offset;
 644
 645                 /* AUX CH Request Transaction process */
 646                 for (i = 0; i < 3; i++) {
 647                         /* Select DPCD device address */
 648                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 649                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 650                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 651                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 652                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 653                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 654
 655                         /*
 656                          * Set DisplayPort transaction and read
 657                          * If bit 3 is 1, DisplayPort transaction.
 658                          * If Bit 3 is 0, I2C transaction.
 659                          */
 660                         reg = AUX_LENGTH(cur_data_count) |
 661                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 662                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 663
 664                         /* Start AUX transaction */
 665                         retval = exynos_dp_start_aux_transaction(dp);
 666                         if (retval == 0)
 667                                 break;
 668                         else
 669                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 670                                         __func__);
 671                 }
 672
 673                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 674                     cur_data_idx++) {
 675                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 676                                                  + 4 * cur_data_idx);
 677                         data[start_offset + cur_data_idx] =
 678                                 (unsigned char)reg;
 679                 }
 680
 681                 start_offset += cur_data_count;
 682         }
 683
 684         return retval;
 685 }
 686
 687 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 688                                 unsigned int device_addr,
 689                                 unsigned int reg_addr)
 690 {
 691         u32 reg;
 692         int retval;
 693
 694         /* Set EDID device address */
 695         reg = device_addr;
 696         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 697         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 698         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 699
 700         /* Set offset from base address of EDID device */
 701         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 702
 703         /*
 704          * Set I2C transaction and write address
 705          * If bit 3 is 1, DisplayPort transaction.
 706          * If Bit 3 is 0, I2C transaction.
 707          */
 708         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 709                 AUX_TX_COMM_WRITE;
 710         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 711
 712         /* Start AUX transaction */
 713         retval = exynos_dp_start_aux_transaction(dp);
 714         if (retval != 0)
 715                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 716
 717         return retval;
 718 }
 719
 720 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 721                                 unsigned int device_addr,
 722                                 unsigned int reg_addr,
 723                                 unsigned int *data)
 724 {
 725         u32 reg;
 726         int i;
 727         int retval;
 728
 729         for (i = 0; i < 3; i++) {
 730                 /* Clear AUX CH data buffer */
 731                 reg = BUF_CLR;
 732                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 733
 734                 /* Select EDID device */
 735                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 736                 if (retval != 0)
 737                         continue;
 738
 739                 /*
 740                  * Set I2C transaction and read data
 741                  * If bit 3 is 1, DisplayPort transaction.
 742                  * If Bit 3 is 0, I2C transaction.
 743                  */
 744                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 745                         AUX_TX_COMM_READ;
 746                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 747
 748                 /* Start AUX transaction */
 749                 retval = exynos_dp_start_aux_transaction(dp);
 750                 if (retval == 0)
 751                         break;
 752                 else
 753                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 754                                 __func__);
 755         }
 756
 757         /* Read data */
 758         if (retval == 0)
 759                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 760
 761         return retval;
 762 }
 763
 764 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 765                                 unsigned int device_addr,
 766                                 unsigned int reg_addr,
 767                                 unsigned int count,
 768                                 unsigned char edid[])
 769 {
 770         u32 reg;
 771         unsigned int i, j;
 772         unsigned int cur_data_idx;
 773         unsigned int defer = 0;
 774         int retval = 0;
 775
 776         for (i = 0; i < count; i += 16) {
 777                 for (j = 0; j < 3; j++) {
 778                         /* Clear AUX CH data buffer */
 779                         reg = BUF_CLR;
 780                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 781
 782                         /* Set normal AUX CH command */
 783                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 784                         reg &= ~ADDR_ONLY;
 785                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 786
 787                         /*
 788                          * If Rx sends defer, Tx sends only reads
 789                          * request without sending address
 790                          */
 791                         if (!defer)
 792                                 retval = exynos_dp_select_i2c_device(dp,
 793                                                 device_addr, reg_addr + i);
 794                         else
 795                                 defer = 0;
 796
 797                         if (retval == 0) {
 798                                 /*
 799                                  * Set I2C transaction and write data
 800                                  * If bit 3 is 1, DisplayPort transaction.
 801                                  * If Bit 3 is 0, I2C transaction.
 802                                  */
 803                                 reg = AUX_LENGTH(16) |
 804                                         AUX_TX_COMM_I2C_TRANSACTION |
 805                                         AUX_TX_COMM_READ;
 806                                 writel(reg, dp->reg_base +
 807                                         EXYNOS_DP_AUX_CH_CTL_1);
 808
 809                                 /* Start AUX transaction */
 810                                 retval = exynos_dp_start_aux_transaction(dp);
 811                                 if (retval == 0)
 812                                         break;
 813                                 else
 814                                         dev_dbg(dp->dev,
 815                                                 "%s: Aux Transaction fail!\n",
 816                                                 __func__);
 817                         }
 818                         /* Check if Rx sends defer */
 819                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 820                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 821                                 reg == AUX_RX_COMM_I2C_DEFER) {
 822                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 823                                 defer = 1;
 824                         }
 825                 }
 826
 827                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 828                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 829                                                  + 4 * cur_data_idx);
 830                         edid[i + cur_data_idx] = (unsigned char)reg;
 831                 }
 832         }
 833
 834         return retval;
 835 }
 836
 837 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 838 {
 839         u32 reg;
 840
 841         reg = bwtype;
 842         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 843                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 844 }
 845
 846 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 847 {
 848         u32 reg;
 849
 850         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 851         *bwtype = reg;
 852 }
 853
 854 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 855 {
 856         u32 reg;
 857
 858         reg = count;
 859         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 860 }
 861
 862 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 863 {
 864         u32 reg;
 865
 866         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 867         *count = reg;
 868 }
 869
 870 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 871 {
 872         u32 reg;
 873
 874         if (enable) {
 875                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 876                 reg |= ENHANCED;
 877                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 878         } else {
 879                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 880                 reg &= ~ENHANCED;
 881                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 882         }
 883 }
 884
 885 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 886                                  enum pattern_set pattern)
 887 {
 888         u32 reg;
 889
 890         switch (pattern) {
 891         case PRBS7:
 892                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 893                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 894                 break;
 895         case D10_2:
 896                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 897                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 898                 break;
 899         case TRAINING_PTN1:
 900                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 901                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 902                 break;
 903         case TRAINING_PTN2:
 904                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 905                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 906                 break;
 907         case DP_NONE:
 908                 reg = SCRAMBLING_ENABLE |
 909                         LINK_QUAL_PATTERN_SET_DISABLE |
 910                         SW_TRAINING_PATTERN_SET_NORMAL;
 911                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 912                 break;
 913         default:
 914                 break;
 915         }
 916 }
 917
 918 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 919 {
 920         u32 reg;
 921
 922         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 923         reg &= ~PRE_EMPHASIS_SET_MASK;
 924         reg |= level << PRE_EMPHASIS_SET_SHIFT;
 925         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 926 }
 927
 928 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 929 {
 930         u32 reg;
 931
 932         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 933         reg &= ~PRE_EMPHASIS_SET_MASK;
 934         reg |= level << PRE_EMPHASIS_SET_SHIFT;
 935         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 936 }
 937
 938 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 939 {
 940         u32 reg;
 941
 942         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 943         reg &= ~PRE_EMPHASIS_SET_MASK;
 944         reg |= level << PRE_EMPHASIS_SET_SHIFT;
 945         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 946 }
 947
 948 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 949 {
 950         u32 reg;
 951
 952         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 953         reg &= ~PRE_EMPHASIS_SET_MASK;
 954         reg |= level << PRE_EMPHASIS_SET_SHIFT;
 955         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 956 }
 957
 958 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 959                                         u32 training_lane)
 960 {
 961         u32 reg;
 962
 963         reg = training_lane;
 964         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 965 }
 966
 967 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 968                                         u32 training_lane)
 969 {
 970         u32 reg;
 971
 972         reg = training_lane;
 973         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 974 }
 975
 976 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 977                                         u32 training_lane)
 978 {
 979         u32 reg;
 980
 981         reg = training_lane;
 982         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 983 }
 984
 985 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 986                                         u32 training_lane)
 987 {
 988         u32 reg;
 989
 990         reg = training_lane;
 991         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 992 }
 993
 994 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 995 {
 996         u32 reg;
 997
 998         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 999         return reg;
1000 }
1001
1002 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
1003 {
1004         u32 reg;
1005
1006         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
1007         return reg;
1008 }
1009
1010 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
1011 {
1012         u32 reg;
1013
1014         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
1015         return reg;
1016 }
1017
1018 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
1019 {
1020         u32 reg;
1021
1022         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
1023         return reg;
1024 }
1025
1026 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
1027 {
1028         u32 reg;
1029
1030         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
1031         reg |= MACRO_RST;
1032         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1033
1034         /* 10 us is the minimum reset time. */
1035         usleep_range(10, 20);
1036
1037         reg &= ~MACRO_RST;
1038         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1039 }
1040
1041 void exynos_dp_init_video(struct exynos_dp_device *dp)
1042 {
1043         u32 reg;
1044
1045         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1046         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1047
1048         reg = 0x0;
1049         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1050
1051         reg = CHA_CRI(4) | CHA_CTRL;
1052         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1053
1054         reg = 0x0;
1055         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1056
1057         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1058         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1059 }
1060
1061 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
1062 {
1063         u32 reg;
1064
1065         /* Configure the input color depth, color space, dynamic range */
1066         reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1067                 (dp->video_info->color_depth << IN_BPC_SHIFT) |
1068                 (dp->video_info->color_space << IN_COLOR_F_SHIFT);
1069         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1070
1071         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1072         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1073         reg &= ~IN_YC_COEFFI_MASK;
1074         if (dp->video_info->ycbcr_coeff)
1075                 reg |= IN_YC_COEFFI_ITU709;
1076         else
1077                 reg |= IN_YC_COEFFI_ITU601;
1078         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1079 }
1080
1081 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1082 {
1083         u32 reg;
1084
1085         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1086         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1087
1088         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1089
1090         if (!(reg & DET_STA)) {
1091                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1092                 return -EINVAL;
1093         }
1094
1095         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1096         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1097
1098         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1099         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1100
1101         if (reg & CHA_STA) {
1102                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1103                 return -EINVAL;
1104         }
1105
1106         return 0;
1107 }
1108
1109 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1110                 enum clock_recovery_m_value_type type,
1111                 u32 m_value,
1112                 u32 n_value)
1113 {
1114         u32 reg;
1115
1116         if (type == REGISTER_M) {
1117                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1118                 reg |= FIX_M_VID;
1119                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1120                 reg = m_value & 0xff;
1121                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1122                 reg = (m_value >> 8) & 0xff;
1123                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1124                 reg = (m_value >> 16) & 0xff;
1125                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1126
1127                 reg = n_value & 0xff;
1128                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1129                 reg = (n_value >> 8) & 0xff;
1130                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1131                 reg = (n_value >> 16) & 0xff;
1132                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1133         } else  {
1134                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1135                 reg &= ~FIX_M_VID;
1136                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1137
1138                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1139                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1140                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1141         }
1142 }
1143
1144 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1145 {
1146         u32 reg;
1147
1148         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1149                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1150                 reg &= ~FORMAT_SEL;
1151                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1152         } else {
1153                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1154                 reg |= FORMAT_SEL;
1155                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1156         }
1157 }
1158
1159 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1160 {
1161         u32 reg;
1162
1163         if (enable) {
1164                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1165                 reg &= ~VIDEO_MODE_MASK;
1166                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1167                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1168         } else {
1169                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1170                 reg &= ~VIDEO_MODE_MASK;
1171                 reg |= VIDEO_MODE_SLAVE_MODE;
1172                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1173         }
1174 }
1175
1176 void exynos_dp_start_video(struct exynos_dp_device *dp)
1177 {
1178         u32 reg;
1179
1180         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1181         reg |= VIDEO_EN;
1182         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1183 }
1184
1185 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1186 {
1187         u32 reg;
1188
1189         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1190         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1191
1192         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1193         if (!(reg & STRM_VALID)) {
1194                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1195                 return -EINVAL;
1196         }
1197
1198         return 0;
1199 }
1200
1201 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
1202 {
1203         u32 reg;
1204
1205         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1206         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1207         reg |= MASTER_VID_FUNC_EN_N;
1208         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1209
1210         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1211         reg &= ~INTERACE_SCAN_CFG;
1212         reg |= (dp->video_info->interlaced << 2);
1213         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1214
1215         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1216         reg &= ~VSYNC_POLARITY_CFG;
1217         reg |= (dp->video_info->v_sync_polarity << 1);
1218         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1219
1220         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1221         reg &= ~HSYNC_POLARITY_CFG;
1222         reg |= (dp->video_info->h_sync_polarity << 0);
1223         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1224
1225         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1226         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1227 }
1228
1229 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1230 {
1231         u32 reg;
1232
1233         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1234         reg &= ~SCRAMBLING_DISABLE;
1235         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1236 }
1237
1238 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1239 {
1240         u32 reg;
1241
1242         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1243         reg |= SCRAMBLING_DISABLE;
1244         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1245 }