drivers/video/exynos/exynos_dp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  *
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <common.h>
  11 #include <display.h>
  12 #include <fdtdec.h>
  13 #include <log.h>
  14 #include <asm/global_data.h>
  15 #include <linux/delay.h>
  16 #include <linux/libfdt.h>
  17 #include <malloc.h>
  18 #include <video_bridge.h>
  19 #include <linux/compat.h>
  20 #include <linux/err.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/dp_info.h>
  24 #include <asm/arch/dp.h>
  25 #include <asm/arch/pinmux.h>
  26 #include <asm/arch/power.h>
  27
  28 #include "exynos_dp_lowlevel.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
  33 {
  34         disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
  35                 disp_info->h_back_porch + disp_info->h_front_porch;
  36         disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
  37                 disp_info->v_back_porch + disp_info->v_front_porch;
  38
  39         return;
  40 }
  41
  42 static int exynos_dp_init_dp(struct exynos_dp *regs)
  43 {
  44         int ret;
  45         exynos_dp_reset(regs);
  46
  47         /* SW defined function Normal operation */
  48         exynos_dp_enable_sw_func(regs, DP_ENABLE);
  49
  50         ret = exynos_dp_init_analog_func(regs);
  51         if (ret != EXYNOS_DP_SUCCESS)
  52                 return ret;
  53
  54         exynos_dp_init_hpd(regs);
  55         exynos_dp_init_aux(regs);
  56
  57         return ret;
  58 }
  59
  60 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  61 {
  62         int i;
  63         unsigned char sum = 0;
  64
  65         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  66                 sum = sum + edid_data[i];
  67
  68         return sum;
  69 }
  70
  71 static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
  72 {
  73         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  74         unsigned int extend_block = 0;
  75         unsigned char sum;
  76         unsigned char test_vector;
  77         int retval;
  78
  79         /*
  80          * EDID device address is 0x50.
  81          * However, if necessary, you must have set upper address
  82          * into E-EDID in I2C device, 0x30.
  83          */
  84
  85         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  86         exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
  87                                      EDID_EXTENSION_FLAG, &extend_block);
  88
  89         if (extend_block > 0) {
  90                 printf("DP EDID data includes a single extension!\n");
  91
  92                 /* Read EDID data */
  93                 retval = exynos_dp_read_bytes_from_i2c(regs,
  94                                                 I2C_EDID_DEVICE_ADDR,
  95                                                 EDID_HEADER_PATTERN,
  96                                                 EDID_BLOCK_LENGTH,
  97                                                 &edid[EDID_HEADER_PATTERN]);
  98                 if (retval != 0) {
  99                         printf("DP EDID Read failed!\n");
 100                         return -1;
 101                 }
 102                 sum = exynos_dp_calc_edid_check_sum(edid);
 103                 if (sum != 0) {
 104                         printf("DP EDID bad checksum!\n");
 105                         return -1;
 106                 }
 107
 108                 /* Read additional EDID data */
 109                 retval = exynos_dp_read_bytes_from_i2c(regs,
 110                                 I2C_EDID_DEVICE_ADDR,
 111                                 EDID_BLOCK_LENGTH,
 112                                 EDID_BLOCK_LENGTH,
 113                                 &edid[EDID_BLOCK_LENGTH]);
 114                 if (retval != 0) {
 115                         printf("DP EDID Read failed!\n");
 116                         return -1;
 117                 }
 118                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 119                 if (sum != 0) {
 120                         printf("DP EDID bad checksum!\n");
 121                         return -1;
 122                 }
 123
 124                 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 125                                               &test_vector);
 126                 if (test_vector & DPCD_TEST_EDID_READ) {
 127                         exynos_dp_write_byte_to_dpcd(regs,
 128                                 DPCD_TEST_EDID_CHECKSUM,
 129                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 130                         exynos_dp_write_byte_to_dpcd(regs,
 131                                 DPCD_TEST_RESPONSE,
 132                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 133                 }
 134         } else {
 135                 debug("DP EDID data does not include any extensions.\n");
 136
 137                 /* Read EDID data */
 138                 retval = exynos_dp_read_bytes_from_i2c(regs,
 139                                 I2C_EDID_DEVICE_ADDR,
 140                                 EDID_HEADER_PATTERN,
 141                                 EDID_BLOCK_LENGTH,
 142                                 &edid[EDID_HEADER_PATTERN]);
 143
 144                 if (retval != 0) {
 145                         printf("DP EDID Read failed!\n");
 146                         return -1;
 147                 }
 148                 sum = exynos_dp_calc_edid_check_sum(edid);
 149                 if (sum != 0) {
 150                         printf("DP EDID bad checksum!\n");
 151                         return -1;
 152                 }
 153
 154                 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 155                         &test_vector);
 156                 if (test_vector & DPCD_TEST_EDID_READ) {
 157                         exynos_dp_write_byte_to_dpcd(regs,
 158                                 DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 159                         exynos_dp_write_byte_to_dpcd(regs,
 160                                 DPCD_TEST_RESPONSE,
 161                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 162                 }
 163         }
 164
 165         debug("DP EDID Read success!\n");
 166
 167         return 0;
 168 }
 169
 170 static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
 171                                           struct exynos_dp_priv *priv)
 172 {
 173         unsigned char buf[12];
 174         unsigned int ret;
 175         unsigned char temp;
 176         unsigned char retry_cnt;
 177         unsigned char dpcd_rev[16];
 178         unsigned char lane_bw[16];
 179         unsigned char lane_cnt[16];
 180
 181         memset(dpcd_rev, 0, 16);
 182         memset(lane_bw, 0, 16);
 183         memset(lane_cnt, 0, 16);
 184         memset(buf, 0, 12);
 185
 186         retry_cnt = 5;
 187         while (retry_cnt) {
 188                 /* Read DPCD 0x0000-0x000b */
 189                 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
 190                                                      buf);
 191                 if (ret != EXYNOS_DP_SUCCESS) {
 192                         if (retry_cnt == 0) {
 193                                 printf("DP read_byte_from_dpcd() failed\n");
 194                                 return ret;
 195                         }
 196                         retry_cnt--;
 197                 } else
 198                         break;
 199         }
 200
 201         /* */
 202         temp = buf[DPCD_DPCD_REV];
 203         if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
 204                 priv->dpcd_rev = temp;
 205         else {
 206                 printf("DP Wrong DPCD Rev : %x\n", temp);
 207                 return -ENODEV;
 208         }
 209
 210         temp = buf[DPCD_MAX_LINK_RATE];
 211         if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
 212                 priv->lane_bw = temp;
 213         else {
 214                 printf("DP Wrong MAX LINK RATE : %x\n", temp);
 215                 return -EINVAL;
 216         }
 217
 218         /* Refer VESA Display Port Standard Ver1.1a Page 120 */
 219         if (priv->dpcd_rev == DP_DPCD_REV_11) {
 220                 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 221                 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
 222                         priv->dpcd_efc = 1;
 223                 else
 224                         priv->dpcd_efc = 0;
 225         } else {
 226                 temp = buf[DPCD_MAX_LANE_COUNT];
 227                 priv->dpcd_efc = 0;
 228         }
 229
 230         if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
 231                         temp == DP_LANE_CNT_4) {
 232                 priv->lane_cnt = temp;
 233         } else {
 234                 printf("DP Wrong MAX LANE COUNT : %x\n", temp);
 235                 return -EINVAL;
 236         }
 237
 238         ret = exynos_dp_read_edid(regs);
 239         if (ret != EXYNOS_DP_SUCCESS) {
 240                 printf("DP exynos_dp_read_edid() failed\n");
 241                 return -EINVAL;
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void exynos_dp_init_training(struct exynos_dp *regs)
 248 {
 249         /*
 250          * MACRO_RST must be applied after the PLL_LOCK to avoid
 251          * the DP inter pair skew issue for at least 10 us
 252          */
 253         exynos_dp_reset_macro(regs);
 254
 255         /* All DP analog module power up */
 256         exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
 257 }
 258
 259 static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
 260                                          struct exynos_dp_priv *priv)
 261 {
 262         unsigned char buf[5];
 263         unsigned int ret = 0;
 264
 265         debug("DP: %s was called\n", __func__);
 266
 267         priv->lt_info.lt_status = DP_LT_CR;
 268         priv->lt_info.ep_loop = 0;
 269         priv->lt_info.cr_loop[0] = 0;
 270         priv->lt_info.cr_loop[1] = 0;
 271         priv->lt_info.cr_loop[2] = 0;
 272         priv->lt_info.cr_loop[3] = 0;
 273
 274                 /* Set sink to D0 (Sink Not Ready) mode. */
 275         ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
 276                                            DPCD_SET_POWER_STATE_D0);
 277         if (ret != EXYNOS_DP_SUCCESS) {
 278                 printf("DP write_dpcd_byte failed\n");
 279                 return ret;
 280         }
 281
 282         /* Set link rate and count as you want to establish */
 283         exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
 284         exynos_dp_set_lane_count(regs, priv->lane_cnt);
 285
 286         /* Setup RX configuration */
 287         buf[0] = priv->lane_bw;
 288         buf[1] = priv->lane_cnt;
 289
 290         ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
 291         if (ret != EXYNOS_DP_SUCCESS) {
 292                 printf("DP write_dpcd_byte failed\n");
 293                 return ret;
 294         }
 295
 296         exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
 297                         priv->lane_cnt);
 298
 299         /* Set training pattern 1 */
 300         exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
 301
 302         /* Set RX training pattern */
 303         buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
 304
 305         buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 306                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 307         buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 308                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 309         buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 310                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 311         buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 312                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 313
 314         ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 315                                             5, buf);
 316         if (ret != EXYNOS_DP_SUCCESS) {
 317                 printf("DP write_dpcd_byte failed\n");
 318                 return ret;
 319         }
 320
 321         return ret;
 322 }
 323
 324 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
 325 {
 326         unsigned int ret;
 327
 328         exynos_dp_set_training_pattern(regs, DP_NONE);
 329
 330         ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 331                                            DPCD_TRAINING_PATTERN_DISABLED);
 332         if (ret != EXYNOS_DP_SUCCESS) {
 333                 printf("DP request_link_training_req failed\n");
 334                 return -EAGAIN;
 335         }
 336
 337         return ret;
 338 }
 339
 340 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 341                 struct exynos_dp *regs, unsigned char enable)
 342 {
 343         unsigned char data;
 344         unsigned int ret;
 345
 346         ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
 347                                             &data);
 348         if (ret != EXYNOS_DP_SUCCESS) {
 349                 printf("DP read_from_dpcd failed\n");
 350                 return -EAGAIN;
 351         }
 352
 353         if (enable)
 354                 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
 355         else
 356                 data = DPCD_LN_COUNT_SET(data);
 357
 358         ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
 359         if (ret != EXYNOS_DP_SUCCESS) {
 360                         printf("DP write_to_dpcd failed\n");
 361                         return -EAGAIN;
 362
 363         }
 364
 365         return ret;
 366 }
 367
 368 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
 369                                                 unsigned char enhance_mode)
 370 {
 371         unsigned int ret;
 372
 373         ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
 374         if (ret != EXYNOS_DP_SUCCESS) {
 375                 printf("DP rx_enhance_mode failed\n");
 376                 return -EAGAIN;
 377         }
 378
 379         exynos_dp_enable_enhanced_mode(regs, enhance_mode);
 380
 381         return ret;
 382 }
 383
 384 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
 385                                          struct exynos_dp_priv *priv,
 386                                          unsigned char *status)
 387 {
 388         unsigned int ret, i;
 389         unsigned char buf[2];
 390         unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
 391         unsigned char shift_val[DP_LANE_CNT_4] = {0,};
 392
 393         shift_val[0] = 0;
 394         shift_val[1] = 4;
 395         shift_val[2] = 0;
 396         shift_val[3] = 4;
 397
 398         ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
 399                                              buf);
 400         if (ret != EXYNOS_DP_SUCCESS) {
 401                 printf("DP read lane status failed\n");
 402                 return ret;
 403         }
 404
 405         for (i = 0; i < priv->lane_cnt; i++) {
 406                 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
 407                 if (lane_stat[0] != lane_stat[i]) {
 408                         printf("Wrong lane status\n");
 409                         return -EINVAL;
 410                 }
 411         }
 412
 413         *status = lane_stat[0];
 414
 415         return ret;
 416 }
 417
 418 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
 419                 unsigned char lane_num, unsigned char *sw, unsigned char *em)
 420 {
 421         unsigned int ret;
 422         unsigned char buf;
 423         unsigned int dpcd_addr;
 424         unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
 425
 426         /* lane_num value is used as array index, so this range 0 ~ 3 */
 427         dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 428
 429         ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
 430         if (ret != EXYNOS_DP_SUCCESS) {
 431                 printf("DP read adjust request failed\n");
 432                 return -EAGAIN;
 433         }
 434
 435         *sw = ((buf >> shift_val[lane_num]) & 0x03);
 436         *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
 437
 438         return ret;
 439 }
 440
 441 static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
 442                                         struct exynos_dp_priv *priv)
 443 {
 444         int ret;
 445
 446         ret = exynos_dp_training_pattern_dis(regs);
 447         if (ret != EXYNOS_DP_SUCCESS) {
 448                 printf("DP training_pattern_disable() failed\n");
 449                 priv->lt_info.lt_status = DP_LT_FAIL;
 450         }
 451
 452         ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 453         if (ret != EXYNOS_DP_SUCCESS) {
 454                 printf("DP set_enhanced_mode() failed\n");
 455                 priv->lt_info.lt_status = DP_LT_FAIL;
 456         }
 457
 458         return ret;
 459 }
 460
 461 static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
 462                                       struct exynos_dp_priv *priv)
 463 {
 464         int ret;
 465
 466         if (priv->lane_bw == DP_LANE_BW_2_70) {
 467                 priv->lane_bw = DP_LANE_BW_1_62;
 468                 printf("DP Change lane bw to 1.62Gbps\n");
 469                 priv->lt_info.lt_status = DP_LT_START;
 470                 ret = EXYNOS_DP_SUCCESS;
 471         } else {
 472                 ret = exynos_dp_training_pattern_dis(regs);
 473                 if (ret != EXYNOS_DP_SUCCESS)
 474                         printf("DP training_patter_disable() failed\n");
 475
 476                 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 477                 if (ret != EXYNOS_DP_SUCCESS)
 478                         printf("DP set_enhanced_mode() failed\n");
 479
 480                 priv->lt_info.lt_status = DP_LT_FAIL;
 481         }
 482
 483         return ret;
 484 }
 485
 486 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
 487                                         struct exynos_dp_priv *priv)
 488 {
 489         unsigned int ret;
 490         unsigned char lane_stat;
 491         unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
 492         unsigned int i;
 493         unsigned char adj_req_sw;
 494         unsigned char adj_req_em;
 495         unsigned char buf[5];
 496
 497         debug("DP: %s was called\n", __func__);
 498         mdelay(1);
 499
 500         ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 501         if (ret != EXYNOS_DP_SUCCESS) {
 502                         printf("DP read lane status failed\n");
 503                         priv->lt_info.lt_status = DP_LT_FAIL;
 504                         return ret;
 505         }
 506
 507         if (lane_stat & DP_LANE_STAT_CR_DONE) {
 508                 debug("DP clock Recovery training succeed\n");
 509                 exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
 510
 511                 for (i = 0; i < priv->lane_cnt; i++) {
 512                         ret = exynos_dp_read_dpcd_adj_req(regs, i,
 513                                                 &adj_req_sw, &adj_req_em);
 514                         if (ret != EXYNOS_DP_SUCCESS) {
 515                                 priv->lt_info.lt_status = DP_LT_FAIL;
 516                                 return ret;
 517                         }
 518
 519                         lt_ctl_val[i] = 0;
 520                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 521
 522                         if ((adj_req_sw == VOLTAGE_LEVEL_3)
 523                                 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 524                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 525                                         MAX_PRE_EMPHASIS_REACH_3;
 526                         }
 527                         exynos_dp_set_lanex_pre_emphasis(regs,
 528                                                          lt_ctl_val[i], i);
 529                 }
 530
 531                 buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
 532                 buf[1] = lt_ctl_val[0];
 533                 buf[2] = lt_ctl_val[1];
 534                 buf[3] = lt_ctl_val[2];
 535                 buf[4] = lt_ctl_val[3];
 536
 537                 ret = exynos_dp_write_bytes_to_dpcd(regs,
 538                                 DPCD_TRAINING_PATTERN_SET, 5, buf);
 539                 if (ret != EXYNOS_DP_SUCCESS) {
 540                         printf("DP write training pattern1 failed\n");
 541                         priv->lt_info.lt_status = DP_LT_FAIL;
 542                         return ret;
 543                 } else
 544                         priv->lt_info.lt_status = DP_LT_ET;
 545         } else {
 546                 for (i = 0; i < priv->lane_cnt; i++) {
 547                         lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
 548                                                 regs, i);
 549                                 ret = exynos_dp_read_dpcd_adj_req(regs, i,
 550                                                 &adj_req_sw, &adj_req_em);
 551                         if (ret != EXYNOS_DP_SUCCESS) {
 552                                 printf("DP read adj req failed\n");
 553                                 priv->lt_info.lt_status = DP_LT_FAIL;
 554                                 return ret;
 555                         }
 556
 557                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 558                                         (adj_req_em == PRE_EMPHASIS_LEVEL_3))
 559                                 ret = exynos_dp_reduce_link_rate(regs,
 560                                                                  priv);
 561
 562                         if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 563                                                 adj_req_sw) &&
 564                                 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
 565                                                 adj_req_em)) {
 566                                 priv->lt_info.cr_loop[i]++;
 567                                 if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
 568                                         ret = exynos_dp_reduce_link_rate(
 569                                                         regs, priv);
 570                         }
 571
 572                         lt_ctl_val[i] = 0;
 573                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 574
 575                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 576                                         (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 577                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 578                                         MAX_PRE_EMPHASIS_REACH_3;
 579                         }
 580                         exynos_dp_set_lanex_pre_emphasis(regs,
 581                                                          lt_ctl_val[i], i);
 582                 }
 583
 584                 ret = exynos_dp_write_bytes_to_dpcd(regs,
 585                                 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 586                 if (ret != EXYNOS_DP_SUCCESS) {
 587                         printf("DP write training pattern2 failed\n");
 588                         priv->lt_info.lt_status = DP_LT_FAIL;
 589                         return ret;
 590                 }
 591         }
 592
 593         return ret;
 594 }
 595
 596 static unsigned int exynos_dp_process_equalizer_training(
 597                 struct exynos_dp *regs, struct exynos_dp_priv *priv)
 598 {
 599         unsigned int ret;
 600         unsigned char lane_stat, adj_req_sw, adj_req_em, i;
 601         unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
 602         unsigned char interlane_aligned = 0;
 603         unsigned char f_bw;
 604         unsigned char f_lane_cnt;
 605         unsigned char sink_stat;
 606
 607         mdelay(1);
 608
 609         ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 610         if (ret != EXYNOS_DP_SUCCESS) {
 611                 printf("DP read lane status failed\n");
 612                 priv->lt_info.lt_status = DP_LT_FAIL;
 613                 return ret;
 614         }
 615
 616         debug("DP lane stat : %x\n", lane_stat);
 617
 618         if (lane_stat & DP_LANE_STAT_CR_DONE) {
 619                 ret = exynos_dp_read_byte_from_dpcd(regs,
 620                                                     DPCD_LN_ALIGN_UPDATED,
 621                                                     &sink_stat);
 622                 if (ret != EXYNOS_DP_SUCCESS) {
 623                         priv->lt_info.lt_status = DP_LT_FAIL;
 624
 625                         return ret;
 626                 }
 627
 628                 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 629
 630                 for (i = 0; i < priv->lane_cnt; i++) {
 631                         ret = exynos_dp_read_dpcd_adj_req(regs, i,
 632                                         &adj_req_sw, &adj_req_em);
 633                         if (ret != EXYNOS_DP_SUCCESS) {
 634                                 printf("DP read adj req 1 failed\n");
 635                                 priv->lt_info.lt_status = DP_LT_FAIL;
 636
 637                                 return ret;
 638                         }
 639
 640                         lt_ctl_val[i] = 0;
 641                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 642
 643                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 644                                 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 645                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
 646                                 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
 647                         }
 648                 }
 649
 650                 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
 651                         (lane_stat&DP_LANE_STAT_SYM_LOCK))
 652                         && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 653                         debug("DP Equalizer training succeed\n");
 654
 655                         f_bw = exynos_dp_get_link_bandwidth(regs);
 656                         f_lane_cnt = exynos_dp_get_lane_count(regs);
 657
 658                         debug("DP final BandWidth : %x\n", f_bw);
 659                         debug("DP final Lane Count : %x\n", f_lane_cnt);
 660
 661                         priv->lt_info.lt_status = DP_LT_FINISHED;
 662
 663                         exynos_dp_equalizer_err_link(regs, priv);
 664
 665                 } else {
 666                         priv->lt_info.ep_loop++;
 667
 668                         if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
 669                                 if (priv->lane_bw == DP_LANE_BW_2_70) {
 670                                         ret = exynos_dp_reduce_link_rate(
 671                                                         regs, priv);
 672                                 } else {
 673                                         priv->lt_info.lt_status =
 674                                                                 DP_LT_FAIL;
 675                                         exynos_dp_equalizer_err_link(regs,
 676                                                                      priv);
 677                                 }
 678                         } else {
 679                                 for (i = 0; i < priv->lane_cnt; i++)
 680                                         exynos_dp_set_lanex_pre_emphasis(
 681                                                 regs, lt_ctl_val[i], i);
 682
 683                                 ret = exynos_dp_write_bytes_to_dpcd(regs,
 684                                                 DPCD_TRAINING_LANE0_SET,
 685                                                 4, lt_ctl_val);
 686                                 if (ret != EXYNOS_DP_SUCCESS) {
 687                                         printf("DP set lt pattern failed\n");
 688                                         priv->lt_info.lt_status =
 689                                                                 DP_LT_FAIL;
 690                                         exynos_dp_equalizer_err_link(regs,
 691                                                                      priv);
 692                                 }
 693                         }
 694                 }
 695         } else if (priv->lane_bw == DP_LANE_BW_2_70) {
 696                 ret = exynos_dp_reduce_link_rate(regs, priv);
 697         } else {
 698                 priv->lt_info.lt_status = DP_LT_FAIL;
 699                 exynos_dp_equalizer_err_link(regs, priv);
 700         }
 701
 702         return ret;
 703 }
 704
 705 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
 706                                                struct exynos_dp_priv *priv)
 707 {
 708         unsigned int ret = 0;
 709         int training_finished;
 710
 711         /* Turn off unnecessary lane */
 712         if (priv->lane_cnt == 1)
 713                 exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
 714
 715         training_finished = 0;
 716
 717         priv->lt_info.lt_status = DP_LT_START;
 718
 719         /* Process here */
 720         while (!training_finished) {
 721                 switch (priv->lt_info.lt_status) {
 722                 case DP_LT_START:
 723                         ret = exynos_dp_link_start(regs, priv);
 724                         if (ret != EXYNOS_DP_SUCCESS) {
 725                                 printf("DP LT:link start failed\n");
 726                                 return ret;
 727                         }
 728                         break;
 729                 case DP_LT_CR:
 730                         ret = exynos_dp_process_clock_recovery(regs,
 731                                                                priv);
 732                         if (ret != EXYNOS_DP_SUCCESS) {
 733                                 printf("DP LT:clock recovery failed\n");
 734                                 return ret;
 735                         }
 736                         break;
 737                 case DP_LT_ET:
 738                         ret = exynos_dp_process_equalizer_training(regs,
 739                                                                    priv);
 740                         if (ret != EXYNOS_DP_SUCCESS) {
 741                                 printf("DP LT:equalizer training failed\n");
 742                                 return ret;
 743                         }
 744                         break;
 745                 case DP_LT_FINISHED:
 746                         training_finished = 1;
 747                         break;
 748                 case DP_LT_FAIL:
 749                         return -1;
 750                 }
 751         }
 752
 753         return ret;
 754 }
 755
 756 static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs,
 757                                              struct exynos_dp_priv *priv)
 758 {
 759         unsigned int ret;
 760
 761         exynos_dp_init_training(regs);
 762
 763         ret = exynos_dp_sw_link_training(regs, priv);
 764         if (ret != EXYNOS_DP_SUCCESS)
 765                 printf("DP dp_sw_link_training() failed\n");
 766
 767         return ret;
 768 }
 769
 770 static void exynos_dp_enable_scramble(struct exynos_dp *regs,
 771                                       unsigned int enable)
 772 {
 773         unsigned char data;
 774
 775         if (enable) {
 776                 exynos_dp_enable_scrambling(regs, DP_ENABLE);
 777
 778                 exynos_dp_read_byte_from_dpcd(regs,
 779                                               DPCD_TRAINING_PATTERN_SET, &data);
 780                 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 781                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 782         } else {
 783                 exynos_dp_enable_scrambling(regs, DP_DISABLE);
 784                 exynos_dp_read_byte_from_dpcd(regs,
 785                                               DPCD_TRAINING_PATTERN_SET, &data);
 786                 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 787                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 788         }
 789 }
 790
 791 static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
 792                                            struct exynos_dp_priv *priv)
 793 {
 794         unsigned int ret = 0;
 795         unsigned int retry_cnt;
 796
 797         mdelay(1);
 798
 799         if (priv->video_info.master_mode) {
 800                 printf("DP does not support master mode\n");
 801                 return -ENODEV;
 802         } else {
 803                 /* debug slave */
 804                 exynos_dp_config_video_slave_mode(regs,
 805                                                   &priv->video_info);
 806         }
 807
 808         exynos_dp_set_video_color_format(regs, &priv->video_info);
 809
 810         if (priv->video_info.bist_mode) {
 811                 if (exynos_dp_config_video_bist(regs, priv) != 0)
 812                         return -1;
 813         }
 814
 815         ret = exynos_dp_get_pll_lock_status(regs);
 816         if (ret != PLL_LOCKED) {
 817                 printf("DP PLL is not locked yet\n");
 818                 return -EIO;
 819         }
 820
 821         if (priv->video_info.master_mode == 0) {
 822                 retry_cnt = 10;
 823                 while (retry_cnt) {
 824                         ret = exynos_dp_is_slave_video_stream_clock_on(regs);
 825                         if (ret != EXYNOS_DP_SUCCESS) {
 826                                 if (retry_cnt == 0) {
 827                                         printf("DP stream_clock_on failed\n");
 828                                         return ret;
 829                                 }
 830                                 retry_cnt--;
 831                                 mdelay(1);
 832                         } else
 833                                 break;
 834                 }
 835         }
 836
 837         /* Set to use the register calculated M/N video */
 838         exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0);
 839
 840         /* For video bist, Video timing must be generated by register */
 841         exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE);
 842
 843         /* Enable video bist */
 844         if (priv->video_info.bist_pattern != COLOR_RAMP &&
 845                 priv->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
 846                 priv->video_info.bist_pattern != COLOR_SQUARE)
 847                 exynos_dp_enable_video_bist(regs,
 848                                             priv->video_info.bist_mode);
 849         else
 850                 exynos_dp_enable_video_bist(regs, DP_DISABLE);
 851
 852         /* Disable video mute */
 853         exynos_dp_enable_video_mute(regs, DP_DISABLE);
 854
 855         /* Configure video Master or Slave mode */
 856         exynos_dp_enable_video_master(regs,
 857                                       priv->video_info.master_mode);
 858
 859         /* Enable video */
 860         exynos_dp_start_video(regs);
 861
 862         if (priv->video_info.master_mode == 0) {
 863                 retry_cnt = 100;
 864                 while (retry_cnt) {
 865                         ret = exynos_dp_is_video_stream_on(regs);
 866                         if (ret != EXYNOS_DP_SUCCESS) {
 867                                 if (retry_cnt == 0) {
 868                                         printf("DP Timeout of video stream\n");
 869                                         return ret;
 870                                 }
 871                                 retry_cnt--;
 872                                 mdelay(5);
 873                         } else
 874                                 break;
 875                 }
 876         }
 877
 878         return ret;
 879 }
 880
 881 static int exynos_dp_of_to_plat(struct udevice *dev)
 882 {
 883         struct exynos_dp_priv *priv = dev_get_priv(dev);
 884         const void *blob = gd->fdt_blob;
 885         unsigned int node = dev_of_offset(dev);
 886         fdt_addr_t addr;
 887
 888         addr = dev_read_addr(dev);
 889         if (addr == FDT_ADDR_T_NONE) {
 890                 debug("Can't get the DP base address\n");
 891                 return -EINVAL;
 892         }
 893         priv->regs = (struct exynos_dp *)addr;
 894         priv->disp_info.h_res = fdtdec_get_int(blob, node,
 895                                                         "samsung,h-res", 0);
 896         priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
 897                                                 "samsung,h-sync-width", 0);
 898         priv->disp_info.h_back_porch = fdtdec_get_int(blob, node,
 899                                                 "samsung,h-back-porch", 0);
 900         priv->disp_info.h_front_porch = fdtdec_get_int(blob, node,
 901                                                 "samsung,h-front-porch", 0);
 902         priv->disp_info.v_res = fdtdec_get_int(blob, node,
 903                                                 "samsung,v-res", 0);
 904         priv->disp_info.v_sync_width = fdtdec_get_int(blob, node,
 905                                                 "samsung,v-sync-width", 0);
 906         priv->disp_info.v_back_porch = fdtdec_get_int(blob, node,
 907                                                 "samsung,v-back-porch", 0);
 908         priv->disp_info.v_front_porch = fdtdec_get_int(blob, node,
 909                                                 "samsung,v-front-porch", 0);
 910         priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
 911                                                 "samsung,v-sync-rate", 0);
 912
 913         priv->lt_info.lt_status = fdtdec_get_int(blob, node,
 914                                                 "samsung,lt-status", 0);
 915
 916         priv->video_info.master_mode = fdtdec_get_int(blob, node,
 917                                                 "samsung,master-mode", 0);
 918         priv->video_info.bist_mode = fdtdec_get_int(blob, node,
 919                                                 "samsung,bist-mode", 0);
 920         priv->video_info.bist_pattern = fdtdec_get_int(blob, node,
 921                                                 "samsung,bist-pattern", 0);
 922         priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
 923                                                 "samsung,h-sync-polarity", 0);
 924         priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
 925                                                 "samsung,v-sync-polarity", 0);
 926         priv->video_info.interlaced = fdtdec_get_int(blob, node,
 927                                                 "samsung,interlaced", 0);
 928         priv->video_info.color_space = fdtdec_get_int(blob, node,
 929                                                 "samsung,color-space", 0);
 930         priv->video_info.dynamic_range = fdtdec_get_int(blob, node,
 931                                                 "samsung,dynamic-range", 0);
 932         priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
 933                                                 "samsung,ycbcr-coeff", 0);
 934         priv->video_info.color_depth = fdtdec_get_int(blob, node,
 935                                                 "samsung,color-depth", 0);
 936         return 0;
 937 }
 938
 939 static int exynos_dp_bridge_init(struct udevice *dev)
 940 {
 941         const int max_tries = 10;
 942         int num_tries;
 943         int ret;
 944
 945         debug("%s\n", __func__);
 946         ret = video_bridge_attach(dev);
 947         if (ret) {
 948                 debug("video bridge init failed: %d\n", ret);
 949                 return ret;
 950         }
 951
 952         /*
 953          * We need to wait for 90ms after bringing up the bridge since there
 954          * is a phantom "high" on the HPD chip during its bootup.  The phantom
 955          * high comes within 7ms of de-asserting PD and persists for at least
 956          * 15ms.  The real high comes roughly 50ms after PD is de-asserted. The
 957          * phantom high makes it hard for us to know when the NXP chip is up.
 958          */
 959         mdelay(90);
 960
 961         for (num_tries = 0; num_tries < max_tries; num_tries++) {
 962                 /* Check HPD. If it's high, or we don't have it, all is well */
 963                 ret = video_bridge_check_attached(dev);
 964                 if (!ret || ret == -ENOENT)
 965                         return 0;
 966
 967                 debug("%s: eDP bridge failed to come up; try %d of %d\n",
 968                       __func__, num_tries, max_tries);
 969         }
 970
 971         /* Immediately go into bridge reset if the hp line is not high */
 972         return -EIO;
 973 }
 974
 975 static int exynos_dp_bridge_setup(const void *blob)
 976 {
 977         const int max_tries = 2;
 978         int num_tries;
 979         struct udevice *dev;
 980         int ret;
 981
 982         /* Configure I2C registers for Parade bridge */
 983         ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
 984         if (ret) {
 985                 debug("video bridge init failed: %d\n", ret);
 986                 return ret;
 987         }
 988
 989         if (strncmp(dev->driver->name, "parade", 6)) {
 990                 /* Mux HPHPD to the special hotplug detect mode */
 991                 exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
 992         }
 993
 994         for (num_tries = 0; num_tries < max_tries; num_tries++) {
 995                 ret = exynos_dp_bridge_init(dev);
 996                 if (!ret)
 997                         return 0;
 998                 if (num_tries == max_tries - 1)
 999                         break;
1000
1001                 /*
1002                 * If we're here, the bridge chip failed to initialise.
1003                 * Power down the bridge in an attempt to reset.
1004                 */
1005                 video_bridge_set_active(dev, false);
1006
1007                 /*
1008                 * Arbitrarily wait 300ms here with DP_N low.  Don't know for
1009                 * sure how long we should wait, but we're being paranoid.
1010                 */
1011                 mdelay(300);
1012         }
1013
1014         return ret;
1015 }
1016 int exynos_dp_enable(struct udevice *dev, int panel_bpp,
1017                      const struct display_timing *timing)
1018 {
1019         struct exynos_dp_priv *priv = dev_get_priv(dev);
1020         struct exynos_dp *regs = priv->regs;
1021         unsigned int ret;
1022
1023         debug("%s: start\n", __func__);
1024         exynos_dp_disp_info(&priv->disp_info);
1025
1026         ret = exynos_dp_bridge_setup(gd->fdt_blob);
1027         if (ret && ret != -ENODEV)
1028                 printf("LCD bridge failed to enable: %d\n", ret);
1029
1030         exynos_dp_phy_ctrl(1);
1031
1032         ret = exynos_dp_init_dp(regs);
1033         if (ret != EXYNOS_DP_SUCCESS) {
1034                 printf("DP exynos_dp_init_dp() failed\n");
1035                 return ret;
1036         }
1037
1038         ret = exynos_dp_handle_edid(regs, priv);
1039         if (ret != EXYNOS_DP_SUCCESS) {
1040                 printf("EDP handle_edid fail\n");
1041                 return ret;
1042         }
1043
1044         ret = exynos_dp_set_link_train(regs, priv);
1045         if (ret != EXYNOS_DP_SUCCESS) {
1046                 printf("DP link training fail\n");
1047                 return ret;
1048         }
1049
1050         exynos_dp_enable_scramble(regs, DP_ENABLE);
1051         exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE);
1052         exynos_dp_enable_enhanced_mode(regs, DP_ENABLE);
1053
1054         exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
1055         exynos_dp_set_lane_count(regs, priv->lane_cnt);
1056
1057         exynos_dp_init_video(regs);
1058         ret = exynos_dp_config_video(regs, priv);
1059         if (ret != EXYNOS_DP_SUCCESS) {
1060                 printf("Exynos DP init failed\n");
1061                 return ret;
1062         }
1063
1064         debug("Exynos DP init done\n");
1065
1066         return ret;
1067 }
1068
1069
1070 static const struct dm_display_ops exynos_dp_ops = {
1071         .enable = exynos_dp_enable,
1072 };
1073
1074 static const struct udevice_id exynos_dp_ids[] = {
1075         { .compatible = "samsung,exynos5-dp" },
1076         { }
1077 };
1078
1079 U_BOOT_DRIVER(exynos_dp) = {
1080         .name   = "exynos_dp",
1081         .id     = UCLASS_DISPLAY,
1082         .of_match = exynos_dp_ids,
1083         .ops    = &exynos_dp_ops,
1084         .of_to_plat     = exynos_dp_of_to_plat,
1085         .priv_auto      = sizeof(struct exynos_dp_priv),
1086 };