drivers/video/exynos/exynos_dp.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: Donghwa Lee <dh09.lee@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <linux/compat.h>
  13 #include <linux/err.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/dp_info.h>
  17 #include <asm/arch/dp.h>
  18 #include <fdtdec.h>
  19 #include <libfdt.h>
  20
  21 #include "exynos_dp_lowlevel.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 void __exynos_set_dp_phy(unsigned int onoff)
  26 {
  27 }
  28 void exynos_set_dp_phy(unsigned int onoff)
  29         __attribute__((weak, alias("__exynos_set_dp_phy")));
  30
  31 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
  32 {
  33         disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
  34                 disp_info->h_back_porch + disp_info->h_front_porch;
  35         disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
  36                 disp_info->v_back_porch + disp_info->v_front_porch;
  37
  38         return;
  39 }
  40
  41 static int exynos_dp_init_dp(struct exynos_dp *dp_regs)
  42 {
  43         int ret;
  44         exynos_dp_reset(dp_regs);
  45
  46         /* SW defined function Normal operation */
  47         exynos_dp_enable_sw_func(dp_regs, DP_ENABLE);
  48
  49         ret = exynos_dp_init_analog_func(dp_regs);
  50         if (ret != EXYNOS_DP_SUCCESS)
  51                 return ret;
  52
  53         exynos_dp_init_hpd(dp_regs);
  54         exynos_dp_init_aux(dp_regs);
  55
  56         return ret;
  57 }
  58
  59 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  60 {
  61         int i;
  62         unsigned char sum = 0;
  63
  64         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  65                 sum = sum + edid_data[i];
  66
  67         return sum;
  68 }
  69
  70 static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
  71 {
  72         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  73         unsigned int extend_block = 0;
  74         unsigned char sum;
  75         unsigned char test_vector;
  76         int retval;
  77
  78         /*
  79          * EDID device address is 0x50.
  80          * However, if necessary, you must have set upper address
  81          * into E-EDID in I2C device, 0x30.
  82          */
  83
  84         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  85         exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR,
  86                                      EDID_EXTENSION_FLAG, &extend_block);
  87
  88         if (extend_block > 0) {
  89                 printf("DP EDID data includes a single extension!\n");
  90
  91                 /* Read EDID data */
  92                 retval = exynos_dp_read_bytes_from_i2c(dp_regs,
  93                                                 I2C_EDID_DEVICE_ADDR,
  94                                                 EDID_HEADER_PATTERN,
  95                                                 EDID_BLOCK_LENGTH,
  96                                                 &edid[EDID_HEADER_PATTERN]);
  97                 if (retval != 0) {
  98                         printf("DP EDID Read failed!\n");
  99                         return -1;
 100                 }
 101                 sum = exynos_dp_calc_edid_check_sum(edid);
 102                 if (sum != 0) {
 103                         printf("DP EDID bad checksum!\n");
 104                         return -1;
 105                 }
 106
 107                 /* Read additional EDID data */
 108                 retval = exynos_dp_read_bytes_from_i2c(dp_regs,
 109                                 I2C_EDID_DEVICE_ADDR,
 110                                 EDID_BLOCK_LENGTH,
 111                                 EDID_BLOCK_LENGTH,
 112                                 &edid[EDID_BLOCK_LENGTH]);
 113                 if (retval != 0) {
 114                         printf("DP EDID Read failed!\n");
 115                         return -1;
 116                 }
 117                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 118                 if (sum != 0) {
 119                         printf("DP EDID bad checksum!\n");
 120                         return -1;
 121                 }
 122
 123                 exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
 124                                               &test_vector);
 125                 if (test_vector & DPCD_TEST_EDID_READ) {
 126                         exynos_dp_write_byte_to_dpcd(dp_regs,
 127                                 DPCD_TEST_EDID_CHECKSUM,
 128                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 129                         exynos_dp_write_byte_to_dpcd(dp_regs,
 130                                 DPCD_TEST_RESPONSE,
 131                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 132                 }
 133         } else {
 134                 debug("DP EDID data does not include any extensions.\n");
 135
 136                 /* Read EDID data */
 137                 retval = exynos_dp_read_bytes_from_i2c(dp_regs,
 138                                 I2C_EDID_DEVICE_ADDR,
 139                                 EDID_HEADER_PATTERN,
 140                                 EDID_BLOCK_LENGTH,
 141                                 &edid[EDID_HEADER_PATTERN]);
 142
 143                 if (retval != 0) {
 144                         printf("DP EDID Read failed!\n");
 145                         return -1;
 146                 }
 147                 sum = exynos_dp_calc_edid_check_sum(edid);
 148                 if (sum != 0) {
 149                         printf("DP EDID bad checksum!\n");
 150                         return -1;
 151                 }
 152
 153                 exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
 154                         &test_vector);
 155                 if (test_vector & DPCD_TEST_EDID_READ) {
 156                         exynos_dp_write_byte_to_dpcd(dp_regs,
 157                                 DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 158                         exynos_dp_write_byte_to_dpcd(dp_regs,
 159                                 DPCD_TEST_RESPONSE,
 160                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 161                 }
 162         }
 163
 164         debug("DP EDID Read success!\n");
 165
 166         return 0;
 167 }
 168
 169 static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 170                                           struct edp_device_info *edp_info)
 171 {
 172         unsigned char buf[12];
 173         unsigned int ret;
 174         unsigned char temp;
 175         unsigned char retry_cnt;
 176         unsigned char dpcd_rev[16];
 177         unsigned char lane_bw[16];
 178         unsigned char lane_cnt[16];
 179
 180         memset(dpcd_rev, 0, 16);
 181         memset(lane_bw, 0, 16);
 182         memset(lane_cnt, 0, 16);
 183         memset(buf, 0, 12);
 184
 185         retry_cnt = 5;
 186         while (retry_cnt) {
 187                 /* Read DPCD 0x0000-0x000b */
 188                 ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12,
 189                                                      buf);
 190                 if (ret != EXYNOS_DP_SUCCESS) {
 191                         if (retry_cnt == 0) {
 192                                 printf("DP read_byte_from_dpcd() failed\n");
 193                                 return ret;
 194                         }
 195                         retry_cnt--;
 196                 } else
 197                         break;
 198         }
 199
 200         /* */
 201         temp = buf[DPCD_DPCD_REV];
 202         if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
 203                 edp_info->dpcd_rev = temp;
 204         else {
 205                 printf("DP Wrong DPCD Rev : %x\n", temp);
 206                 return -ENODEV;
 207         }
 208
 209         temp = buf[DPCD_MAX_LINK_RATE];
 210         if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
 211                 edp_info->lane_bw = temp;
 212         else {
 213                 printf("DP Wrong MAX LINK RATE : %x\n", temp);
 214                 return -EINVAL;
 215         }
 216
 217         /* Refer VESA Display Port Standard Ver1.1a Page 120 */
 218         if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
 219                 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 220                 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
 221                         edp_info->dpcd_efc = 1;
 222                 else
 223                         edp_info->dpcd_efc = 0;
 224         } else {
 225                 temp = buf[DPCD_MAX_LANE_COUNT];
 226                 edp_info->dpcd_efc = 0;
 227         }
 228
 229         if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
 230                         temp == DP_LANE_CNT_4) {
 231                 edp_info->lane_cnt = temp;
 232         } else {
 233                 printf("DP Wrong MAX LANE COUNT : %x\n", temp);
 234                 return -EINVAL;
 235         }
 236
 237         ret = exynos_dp_read_edid(dp_regs);
 238         if (ret != EXYNOS_DP_SUCCESS) {
 239                 printf("DP exynos_dp_read_edid() failed\n");
 240                 return -EINVAL;
 241         }
 242
 243         return ret;
 244 }
 245
 246 static void exynos_dp_init_training(struct exynos_dp *dp_regs)
 247 {
 248         /*
 249          * MACRO_RST must be applied after the PLL_LOCK to avoid
 250          * the DP inter pair skew issue for at least 10 us
 251          */
 252         exynos_dp_reset_macro(dp_regs);
 253
 254         /* All DP analog module power up */
 255         exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0);
 256 }
 257
 258 static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 259                                          struct edp_device_info *edp_info)
 260 {
 261         unsigned char buf[5];
 262         unsigned int ret = 0;
 263
 264         debug("DP: %s was called\n", __func__);
 265
 266         edp_info->lt_info.lt_status = DP_LT_CR;
 267         edp_info->lt_info.ep_loop = 0;
 268         edp_info->lt_info.cr_loop[0] = 0;
 269         edp_info->lt_info.cr_loop[1] = 0;
 270         edp_info->lt_info.cr_loop[2] = 0;
 271         edp_info->lt_info.cr_loop[3] = 0;
 272
 273                 /* Set sink to D0 (Sink Not Ready) mode. */
 274         ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE,
 275                                            DPCD_SET_POWER_STATE_D0);
 276         if (ret != EXYNOS_DP_SUCCESS) {
 277                 printf("DP write_dpcd_byte failed\n");
 278                 return ret;
 279         }
 280
 281         /* Set link rate and count as you want to establish */
 282         exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
 283         exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 284
 285         /* Setup RX configuration */
 286         buf[0] = edp_info->lane_bw;
 287         buf[1] = edp_info->lane_cnt;
 288
 289         ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf);
 290         if (ret != EXYNOS_DP_SUCCESS) {
 291                 printf("DP write_dpcd_byte failed\n");
 292                 return ret;
 293         }
 294
 295         exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0,
 296                         edp_info->lane_cnt);
 297
 298         /* Set training pattern 1 */
 299         exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1);
 300
 301         /* Set RX training pattern */
 302         buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
 303
 304         buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 305                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 306         buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 307                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 308         buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 309                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 310         buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 311                 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 312
 313         ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 314                                             5, buf);
 315         if (ret != EXYNOS_DP_SUCCESS) {
 316                 printf("DP write_dpcd_byte failed\n");
 317                 return ret;
 318         }
 319
 320         return ret;
 321 }
 322
 323 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
 324 {
 325         unsigned int ret = EXYNOS_DP_SUCCESS;
 326
 327         exynos_dp_set_training_pattern(dp_regs, DP_NONE);
 328
 329         ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 330                                            DPCD_TRAINING_PATTERN_DISABLED);
 331         if (ret != EXYNOS_DP_SUCCESS) {
 332                 printf("DP request_link_training_req failed\n");
 333                 return -EAGAIN;
 334         }
 335
 336         return ret;
 337 }
 338
 339 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 340                 struct exynos_dp *dp_regs, unsigned char enable)
 341 {
 342         unsigned char data;
 343         unsigned int ret = EXYNOS_DP_SUCCESS;
 344
 345         ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET,
 346                                             &data);
 347         if (ret != EXYNOS_DP_SUCCESS) {
 348                 printf("DP read_from_dpcd failed\n");
 349                 return -EAGAIN;
 350         }
 351
 352         if (enable)
 353                 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
 354         else
 355                 data = DPCD_LN_COUNT_SET(data);
 356
 357         ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data);
 358         if (ret != EXYNOS_DP_SUCCESS) {
 359                         printf("DP write_to_dpcd failed\n");
 360                         return -EAGAIN;
 361
 362         }
 363
 364         return ret;
 365 }
 366
 367 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
 368                                                 unsigned char enhance_mode)
 369 {
 370         unsigned int ret = EXYNOS_DP_SUCCESS;
 371
 372         ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode);
 373         if (ret != EXYNOS_DP_SUCCESS) {
 374                 printf("DP rx_enhance_mode failed\n");
 375                 return -EAGAIN;
 376         }
 377
 378         exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode);
 379
 380         return ret;
 381 }
 382
 383 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
 384                                          struct edp_device_info *edp_info,
 385                                          unsigned char *status)
 386 {
 387         unsigned int ret, i;
 388         unsigned char buf[2];
 389         unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
 390         unsigned char shift_val[DP_LANE_CNT_4] = {0,};
 391
 392         shift_val[0] = 0;
 393         shift_val[1] = 4;
 394         shift_val[2] = 0;
 395         shift_val[3] = 4;
 396
 397         ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2,
 398                                              buf);
 399         if (ret != EXYNOS_DP_SUCCESS) {
 400                 printf("DP read lane status failed\n");
 401                 return ret;
 402         }
 403
 404         for (i = 0; i < edp_info->lane_cnt; i++) {
 405                 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
 406                 if (lane_stat[0] != lane_stat[i]) {
 407                         printf("Wrong lane status\n");
 408                         return -EINVAL;
 409                 }
 410         }
 411
 412         *status = lane_stat[0];
 413
 414         return ret;
 415 }
 416
 417 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 418                 unsigned char lane_num, unsigned char *sw, unsigned char *em)
 419 {
 420         unsigned int ret = EXYNOS_DP_SUCCESS;
 421         unsigned char buf;
 422         unsigned int dpcd_addr;
 423         unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
 424
 425         /* lane_num value is used as array index, so this range 0 ~ 3 */
 426         dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 427
 428         ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf);
 429         if (ret != EXYNOS_DP_SUCCESS) {
 430                 printf("DP read adjust request failed\n");
 431                 return -EAGAIN;
 432         }
 433
 434         *sw = ((buf >> shift_val[lane_num]) & 0x03);
 435         *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
 436
 437         return ret;
 438 }
 439
 440 static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
 441                                         struct edp_device_info *edp_info)
 442 {
 443         int ret;
 444
 445         ret = exynos_dp_training_pattern_dis(dp_regs);
 446         if (ret != EXYNOS_DP_SUCCESS) {
 447                 printf("DP training_pattern_disable() failed\n");
 448                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 449         }
 450
 451         ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 452         if (ret != EXYNOS_DP_SUCCESS) {
 453                 printf("DP set_enhanced_mode() failed\n");
 454                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 455         }
 456
 457         return ret;
 458 }
 459
 460 static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
 461                                       struct edp_device_info *edp_info)
 462 {
 463         int ret;
 464
 465         if (edp_info->lane_bw == DP_LANE_BW_2_70) {
 466                 edp_info->lane_bw = DP_LANE_BW_1_62;
 467                 printf("DP Change lane bw to 1.62Gbps\n");
 468                 edp_info->lt_info.lt_status = DP_LT_START;
 469                 ret = EXYNOS_DP_SUCCESS;
 470         } else {
 471                 ret = exynos_dp_training_pattern_dis(dp_regs);
 472                 if (ret != EXYNOS_DP_SUCCESS)
 473                         printf("DP training_patter_disable() failed\n");
 474
 475                 ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 476                 if (ret != EXYNOS_DP_SUCCESS)
 477                         printf("DP set_enhanced_mode() failed\n");
 478
 479                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 480         }
 481
 482         return ret;
 483 }
 484
 485 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 486                                         struct edp_device_info *edp_info)
 487 {
 488         unsigned int ret = EXYNOS_DP_SUCCESS;
 489         unsigned char lane_stat;
 490         unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
 491         unsigned int i;
 492         unsigned char adj_req_sw;
 493         unsigned char adj_req_em;
 494         unsigned char buf[5];
 495
 496         debug("DP: %s was called\n", __func__);
 497         mdelay(1);
 498
 499         ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 500         if (ret != EXYNOS_DP_SUCCESS) {
 501                         printf("DP read lane status failed\n");
 502                         edp_info->lt_info.lt_status = DP_LT_FAIL;
 503                         return ret;
 504         }
 505
 506         if (lane_stat & DP_LANE_STAT_CR_DONE) {
 507                 debug("DP clock Recovery training succeed\n");
 508                 exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2);
 509
 510                 for (i = 0; i < edp_info->lane_cnt; i++) {
 511                         ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 512                                                 &adj_req_sw, &adj_req_em);
 513                         if (ret != EXYNOS_DP_SUCCESS) {
 514                                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 515                                 return ret;
 516                         }
 517
 518                         lt_ctl_val[i] = 0;
 519                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 520
 521                         if ((adj_req_sw == VOLTAGE_LEVEL_3)
 522                                 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 523                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 524                                         MAX_PRE_EMPHASIS_REACH_3;
 525                         }
 526                         exynos_dp_set_lanex_pre_emphasis(dp_regs,
 527                                                          lt_ctl_val[i], i);
 528                 }
 529
 530                 buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
 531                 buf[1] = lt_ctl_val[0];
 532                 buf[2] = lt_ctl_val[1];
 533                 buf[3] = lt_ctl_val[2];
 534                 buf[4] = lt_ctl_val[3];
 535
 536                 ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 537                                 DPCD_TRAINING_PATTERN_SET, 5, buf);
 538                 if (ret != EXYNOS_DP_SUCCESS) {
 539                         printf("DP write training pattern1 failed\n");
 540                         edp_info->lt_info.lt_status = DP_LT_FAIL;
 541                         return ret;
 542                 } else
 543                         edp_info->lt_info.lt_status = DP_LT_ET;
 544         } else {
 545                 for (i = 0; i < edp_info->lane_cnt; i++) {
 546                         lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
 547                                                 dp_regs, i);
 548                                 ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 549                                                 &adj_req_sw, &adj_req_em);
 550                         if (ret != EXYNOS_DP_SUCCESS) {
 551                                 printf("DP read adj req failed\n");
 552                                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 553                                 return ret;
 554                         }
 555
 556                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 557                                         (adj_req_em == PRE_EMPHASIS_LEVEL_3))
 558                                 ret = exynos_dp_reduce_link_rate(dp_regs,
 559                                                                  edp_info);
 560
 561                         if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 562                                                 adj_req_sw) &&
 563                                 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
 564                                                 adj_req_em)) {
 565                                 edp_info->lt_info.cr_loop[i]++;
 566                                 if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
 567                                         ret = exynos_dp_reduce_link_rate(
 568                                                         dp_regs, edp_info);
 569                         }
 570
 571                         lt_ctl_val[i] = 0;
 572                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 573
 574                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 575                                         (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 576                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 577                                         MAX_PRE_EMPHASIS_REACH_3;
 578                         }
 579                         exynos_dp_set_lanex_pre_emphasis(dp_regs,
 580                                                          lt_ctl_val[i], i);
 581                 }
 582
 583                 ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 584                                 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 585                 if (ret != EXYNOS_DP_SUCCESS) {
 586                         printf("DP write training pattern2 failed\n");
 587                         edp_info->lt_info.lt_status = DP_LT_FAIL;
 588                         return ret;
 589                 }
 590         }
 591
 592         return ret;
 593 }
 594
 595 static unsigned int exynos_dp_process_equalizer_training(
 596                 struct exynos_dp *dp_regs, struct edp_device_info *edp_info)
 597 {
 598         unsigned int ret = EXYNOS_DP_SUCCESS;
 599         unsigned char lane_stat, adj_req_sw, adj_req_em, i;
 600         unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
 601         unsigned char interlane_aligned = 0;
 602         unsigned char f_bw;
 603         unsigned char f_lane_cnt;
 604         unsigned char sink_stat;
 605
 606         mdelay(1);
 607
 608         ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 609         if (ret != EXYNOS_DP_SUCCESS) {
 610                 printf("DP read lane status failed\n");
 611                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 612                 return ret;
 613         }
 614
 615         debug("DP lane stat : %x\n", lane_stat);
 616
 617         if (lane_stat & DP_LANE_STAT_CR_DONE) {
 618                 ret = exynos_dp_read_byte_from_dpcd(dp_regs,
 619                                                     DPCD_LN_ALIGN_UPDATED,
 620                                                     &sink_stat);
 621                 if (ret != EXYNOS_DP_SUCCESS) {
 622                         edp_info->lt_info.lt_status = DP_LT_FAIL;
 623
 624                         return ret;
 625                 }
 626
 627                 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 628
 629                 for (i = 0; i < edp_info->lane_cnt; i++) {
 630                         ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 631                                         &adj_req_sw, &adj_req_em);
 632                         if (ret != EXYNOS_DP_SUCCESS) {
 633                                 printf("DP read adj req 1 failed\n");
 634                                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 635
 636                                 return ret;
 637                         }
 638
 639                         lt_ctl_val[i] = 0;
 640                         lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
 641
 642                         if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 643                                 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
 644                                 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
 645                                 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
 646                         }
 647                 }
 648
 649                 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
 650                         (lane_stat&DP_LANE_STAT_SYM_LOCK))
 651                         && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 652                         debug("DP Equalizer training succeed\n");
 653
 654                         f_bw = exynos_dp_get_link_bandwidth(dp_regs);
 655                         f_lane_cnt = exynos_dp_get_lane_count(dp_regs);
 656
 657                         debug("DP final BandWidth : %x\n", f_bw);
 658                         debug("DP final Lane Count : %x\n", f_lane_cnt);
 659
 660                         edp_info->lt_info.lt_status = DP_LT_FINISHED;
 661
 662                         exynos_dp_equalizer_err_link(dp_regs, edp_info);
 663
 664                 } else {
 665                         edp_info->lt_info.ep_loop++;
 666
 667                         if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
 668                                 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
 669                                         ret = exynos_dp_reduce_link_rate(
 670                                                         dp_regs, edp_info);
 671                                 } else {
 672                                         edp_info->lt_info.lt_status =
 673                                                                 DP_LT_FAIL;
 674                                         exynos_dp_equalizer_err_link(dp_regs,
 675                                                                      edp_info);
 676                                 }
 677                         } else {
 678                                 for (i = 0; i < edp_info->lane_cnt; i++)
 679                                         exynos_dp_set_lanex_pre_emphasis(
 680                                                 dp_regs, lt_ctl_val[i], i);
 681
 682                                 ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 683                                                 DPCD_TRAINING_LANE0_SET,
 684                                                 4, lt_ctl_val);
 685                                 if (ret != EXYNOS_DP_SUCCESS) {
 686                                         printf("DP set lt pattern failed\n");
 687                                         edp_info->lt_info.lt_status =
 688                                                                 DP_LT_FAIL;
 689                                         exynos_dp_equalizer_err_link(dp_regs,
 690                                                                      edp_info);
 691                                 }
 692                         }
 693                 }
 694         } else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
 695                 ret = exynos_dp_reduce_link_rate(dp_regs, edp_info);
 696         } else {
 697                 edp_info->lt_info.lt_status = DP_LT_FAIL;
 698                 exynos_dp_equalizer_err_link(dp_regs, edp_info);
 699         }
 700
 701         return ret;
 702 }
 703
 704 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
 705                                                struct edp_device_info *edp_info)
 706 {
 707         unsigned int ret = 0;
 708         int training_finished;
 709
 710         /* Turn off unnecessary lane */
 711         if (edp_info->lane_cnt == 1)
 712                 exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1);
 713
 714         training_finished = 0;
 715
 716         edp_info->lt_info.lt_status = DP_LT_START;
 717
 718         /* Process here */
 719         while (!training_finished) {
 720                 switch (edp_info->lt_info.lt_status) {
 721                 case DP_LT_START:
 722                         ret = exynos_dp_link_start(dp_regs, edp_info);
 723                         if (ret != EXYNOS_DP_SUCCESS) {
 724                                 printf("DP LT:link start failed\n");
 725                                 return ret;
 726                         }
 727                         break;
 728                 case DP_LT_CR:
 729                         ret = exynos_dp_process_clock_recovery(dp_regs,
 730                                                                edp_info);
 731                         if (ret != EXYNOS_DP_SUCCESS) {
 732                                 printf("DP LT:clock recovery failed\n");
 733                                 return ret;
 734                         }
 735                         break;
 736                 case DP_LT_ET:
 737                         ret = exynos_dp_process_equalizer_training(dp_regs,
 738                                                                    edp_info);
 739                         if (ret != EXYNOS_DP_SUCCESS) {
 740                                 printf("DP LT:equalizer training failed\n");
 741                                 return ret;
 742                         }
 743                         break;
 744                 case DP_LT_FINISHED:
 745                         training_finished = 1;
 746                         break;
 747                 case DP_LT_FAIL:
 748                         return -1;
 749                 }
 750         }
 751
 752         return ret;
 753 }
 754
 755 static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
 756                                              struct edp_device_info *edp_info)
 757 {
 758         unsigned int ret;
 759
 760         exynos_dp_init_training(dp_regs);
 761
 762         ret = exynos_dp_sw_link_training(dp_regs, edp_info);
 763         if (ret != EXYNOS_DP_SUCCESS)
 764                 printf("DP dp_sw_link_training() failed\n");
 765
 766         return ret;
 767 }
 768
 769 static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
 770                                       unsigned int enable)
 771 {
 772         unsigned char data;
 773
 774         if (enable) {
 775                 exynos_dp_enable_scrambling(dp_regs, DP_ENABLE);
 776
 777                 exynos_dp_read_byte_from_dpcd(dp_regs,
 778                                               DPCD_TRAINING_PATTERN_SET, &data);
 779                 exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 780                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 781         } else {
 782                 exynos_dp_enable_scrambling(dp_regs, DP_DISABLE);
 783                 exynos_dp_read_byte_from_dpcd(dp_regs,
 784                                               DPCD_TRAINING_PATTERN_SET, &data);
 785                 exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 786                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 787         }
 788 }
 789
 790 static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
 791                                            struct edp_device_info *edp_info)
 792 {
 793         unsigned int ret = 0;
 794         unsigned int retry_cnt;
 795
 796         mdelay(1);
 797
 798         if (edp_info->video_info.master_mode) {
 799                 printf("DP does not support master mode\n");
 800                 return -ENODEV;
 801         } else {
 802                 /* debug slave */
 803                 exynos_dp_config_video_slave_mode(dp_regs,
 804                                                   &edp_info->video_info);
 805         }
 806
 807         exynos_dp_set_video_color_format(dp_regs, &edp_info->video_info);
 808
 809         if (edp_info->video_info.bist_mode) {
 810                 if (exynos_dp_config_video_bist(dp_regs, edp_info) != 0)
 811                         return -1;
 812         }
 813
 814         ret = exynos_dp_get_pll_lock_status(dp_regs);
 815         if (ret != PLL_LOCKED) {
 816                 printf("DP PLL is not locked yet\n");
 817                 return -EIO;
 818         }
 819
 820         if (edp_info->video_info.master_mode == 0) {
 821                 retry_cnt = 10;
 822                 while (retry_cnt) {
 823                         ret = exynos_dp_is_slave_video_stream_clock_on(dp_regs);
 824                         if (ret != EXYNOS_DP_SUCCESS) {
 825                                 if (retry_cnt == 0) {
 826                                         printf("DP stream_clock_on failed\n");
 827                                         return ret;
 828                                 }
 829                                 retry_cnt--;
 830                                 mdelay(1);
 831                         } else
 832                                 break;
 833                 }
 834         }
 835
 836         /* Set to use the register calculated M/N video */
 837         exynos_dp_set_video_cr_mn(dp_regs, CALCULATED_M, 0, 0);
 838
 839         /* For video bist, Video timing must be generated by register */
 840         exynos_dp_set_video_timing_mode(dp_regs, VIDEO_TIMING_FROM_CAPTURE);
 841
 842         /* Enable video bist */
 843         if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
 844                 edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
 845                 edp_info->video_info.bist_pattern != COLOR_SQUARE)
 846                 exynos_dp_enable_video_bist(dp_regs,
 847                                             edp_info->video_info.bist_mode);
 848         else
 849                 exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 850
 851         /* Disable video mute */
 852         exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 853
 854         /* Configure video Master or Slave mode */
 855         exynos_dp_enable_video_master(dp_regs,
 856                                       edp_info->video_info.master_mode);
 857
 858         /* Enable video */
 859         exynos_dp_start_video(dp_regs);
 860
 861         if (edp_info->video_info.master_mode == 0) {
 862                 retry_cnt = 100;
 863                 while (retry_cnt) {
 864                         ret = exynos_dp_is_video_stream_on(dp_regs);
 865                         if (ret != EXYNOS_DP_SUCCESS) {
 866                                 if (retry_cnt == 0) {
 867                                         printf("DP Timeout of video stream\n");
 868                                         return ret;
 869                                 }
 870                                 retry_cnt--;
 871                                 mdelay(5);
 872                         } else
 873                                 break;
 874                 }
 875         }
 876
 877         return ret;
 878 }
 879
 880 int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
 881 {
 882         unsigned int node = fdtdec_next_compatible(blob, 0,
 883                                                 COMPAT_SAMSUNG_EXYNOS5_DP);
 884         if (node <= 0) {
 885                 debug("exynos_dp: Can't get device node for dp\n");
 886                 return -ENODEV;
 887         }
 888
 889         edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
 890                                                         "samsung,h-res", 0);
 891         edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
 892                                                 "samsung,h-sync-width", 0);
 893         edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
 894                                                 "samsung,h-back-porch", 0);
 895         edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
 896                                                 "samsung,h-front-porch", 0);
 897         edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
 898                                                 "samsung,v-res", 0);
 899         edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
 900                                                 "samsung,v-sync-width", 0);
 901         edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
 902                                                 "samsung,v-back-porch", 0);
 903         edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
 904                                                 "samsung,v-front-porch", 0);
 905         edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
 906                                                 "samsung,v-sync-rate", 0);
 907
 908         edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
 909                                                 "samsung,lt-status", 0);
 910
 911         edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
 912                                                 "samsung,master-mode", 0);
 913         edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
 914                                                 "samsung,bist-mode", 0);
 915         edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
 916                                                 "samsung,bist-pattern", 0);
 917         edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
 918                                                 "samsung,h-sync-polarity", 0);
 919         edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
 920                                                 "samsung,v-sync-polarity", 0);
 921         edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
 922                                                 "samsung,interlaced", 0);
 923         edp_info->video_info.color_space = fdtdec_get_int(blob, node,
 924                                                 "samsung,color-space", 0);
 925         edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
 926                                                 "samsung,dynamic-range", 0);
 927         edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
 928                                                 "samsung,ycbcr-coeff", 0);
 929         edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
 930                                                 "samsung,color-depth", 0);
 931         return 0;
 932 }
 933
 934 unsigned int exynos_init_dp(void)
 935 {
 936         unsigned int ret;
 937         struct edp_device_info *edp_info;
 938         struct exynos_dp *dp_regs;
 939         int node;
 940
 941         edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
 942         if (!edp_info) {
 943                 debug("failed to allocate edp device object.\n");
 944                 return -EFAULT;
 945         }
 946
 947         if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
 948                 debug("unable to parse DP DT node\n");
 949
 950         node = fdtdec_next_compatible(gd->fdt_blob, 0,
 951                                       COMPAT_SAMSUNG_EXYNOS5_DP);
 952         if (node <= 0)
 953                 debug("exynos_dp: Can't get device node for dp\n");
 954
 955         dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
 956                                                       "reg");
 957         if (dp_regs == NULL)
 958                 debug("Can't get the DP base address\n");
 959
 960         exynos_dp_disp_info(&edp_info->disp_info);
 961
 962         exynos_set_dp_phy(1);
 963
 964         ret = exynos_dp_init_dp(dp_regs);
 965         if (ret != EXYNOS_DP_SUCCESS) {
 966                 printf("DP exynos_dp_init_dp() failed\n");
 967                 return ret;
 968         }
 969
 970         ret = exynos_dp_handle_edid(dp_regs, edp_info);
 971         if (ret != EXYNOS_DP_SUCCESS) {
 972                 printf("EDP handle_edid fail\n");
 973                 return ret;
 974         }
 975
 976         ret = exynos_dp_set_link_train(dp_regs, edp_info);
 977         if (ret != EXYNOS_DP_SUCCESS) {
 978                 printf("DP link training fail\n");
 979                 return ret;
 980         }
 981
 982         exynos_dp_enable_scramble(dp_regs, DP_ENABLE);
 983         exynos_dp_enable_rx_to_enhanced_mode(dp_regs, DP_ENABLE);
 984         exynos_dp_enable_enhanced_mode(dp_regs, DP_ENABLE);
 985
 986         exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
 987         exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 988
 989         exynos_dp_init_video(dp_regs);
 990         ret = exynos_dp_config_video(dp_regs, edp_info);
 991         if (ret != EXYNOS_DP_SUCCESS) {
 992                 printf("Exynos DP init failed\n");
 993                 return ret;
 994         }
 995
 996         debug("Exynos DP init done\n");
 997
 998         return ret;
 999 }