1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
11 * Based on the LCD driver for TI Avalanche processors written by
12 * Ajay Singh and Shalom Hai.
29 enum raster_load_mode {
34 struct display_panel {
35 enum panel_type panel_type; /* QVGA */
38 enum panel_shade panel_shade;
42 const char name[25]; /* Full name <vendor>_<model> */
44 unsigned short height;
45 int hfp; /* Horizontal front porch */
46 int hbp; /* Horizontal back porch */
47 int hsw; /* Horizontal Sync Pulse Width */
48 int vfp; /* Vertical front porch */
49 int vbp; /* Vertical back porch */
50 int vsw; /* Vertical Sync Pulse Width */
51 unsigned int pxl_clk; /* Pixel clock */
52 unsigned char invert_pxl_clk; /* Invert Pixel clock */
55 struct da8xx_lcdc_platform_data {
56 const char manu_name[10];
57 void *controller_data;
59 void (*panel_power_ctrl)(int);
62 struct lcd_ctrl_config {
63 const struct display_panel *p_disp_panel;
65 /* AC Bias Pin Frequency */
68 /* AC Bias Pin Transitions per Interrupt */
77 /* FIFO DMA Request Delay */
80 /* TFT Alternative Signal Mapping (Only for active) */
81 unsigned char tft_alt_mode;
83 /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
84 unsigned char stn_565_mode;
86 /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
87 unsigned char mono_8bit_mode;
89 /* Invert line clock */
90 unsigned char invert_line_clock;
92 /* Invert frame clock */
93 unsigned char invert_frm_clock;
95 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
96 unsigned char sync_edge;
98 /* Horizontal and Vertical Sync: Control: 0=ignore */
99 unsigned char sync_ctrl;
101 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
102 unsigned char raster_order;
105 struct lcd_sync_arg {
111 void da8xx_video_init(const struct da8xx_panel *panel,
112 const struct lcd_ctrl_config *lcd_cfg,
115 #endif /* ifndef DA8XX_FB_H */