1 // SPDX-License-Identifier: GPL-2.0+
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
11 * Based on the LCD driver for TI Avalanche processors written by
12 * Ajay Singh and Shalom Hai.
20 #include <linux/delay.h>
21 #include <linux/list.h>
24 #include <linux/errno.h>
26 #include <asm/arch/hardware.h>
28 #include "videomodes.h"
31 #if !defined(DA8XX_LCD_CNTL_BASE)
32 #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
35 #define DRIVER_NAME "da8xx_lcdc"
37 #define LCD_VERSION_1 1
38 #define LCD_VERSION_2 2
40 /* LCD Status Register */
41 #define LCD_END_OF_FRAME1 (1 << 9)
42 #define LCD_END_OF_FRAME0 (1 << 8)
43 #define LCD_PL_LOAD_DONE (1 << 6)
44 #define LCD_FIFO_UNDERFLOW (1 << 5)
45 #define LCD_SYNC_LOST (1 << 2)
47 /* LCD DMA Control Register */
48 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
49 #define LCD_DMA_BURST_1 0x0
50 #define LCD_DMA_BURST_2 0x1
51 #define LCD_DMA_BURST_4 0x2
52 #define LCD_DMA_BURST_8 0x3
53 #define LCD_DMA_BURST_16 0x4
54 #define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
55 #define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
56 #define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
57 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
59 #define LCD_V2_TFT_24BPP_MODE (1 << 25)
60 #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
62 /* LCD Control Register */
63 #define LCD_CLK_DIVISOR(x) ((x) << 8)
64 #define LCD_RASTER_MODE 0x01
66 /* LCD Raster Control Register */
67 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
68 #define PALETTE_AND_DATA 0x00
69 #define PALETTE_ONLY 0x01
70 #define DATA_ONLY 0x02
72 #define LCD_MONO_8BIT_MODE (1 << 9)
73 #define LCD_RASTER_ORDER (1 << 8)
74 #define LCD_TFT_MODE (1 << 7)
75 #define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
76 #define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
77 #define LCD_V1_PL_INT_ENA (1 << 4)
78 #define LCD_V2_PL_INT_ENA (1 << 6)
79 #define LCD_MONOCHROME_MODE (1 << 1)
80 #define LCD_RASTER_ENABLE (1 << 0)
81 #define LCD_TFT_ALT_ENABLE (1 << 23)
82 #define LCD_STN_565_ENABLE (1 << 24)
83 #define LCD_V2_DMA_CLK_EN (1 << 2)
84 #define LCD_V2_LIDD_CLK_EN (1 << 1)
85 #define LCD_V2_CORE_CLK_EN (1 << 0)
86 #define LCD_V2_LPP_B10 26
87 #define LCD_V2_TFT_24BPP_MODE (1 << 25)
88 #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
90 /* LCD Raster Timing 2 Register */
91 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
92 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
93 #define LCD_SYNC_CTRL (1 << 25)
94 #define LCD_SYNC_EDGE (1 << 24)
95 #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
96 #define LCD_INVERT_LINE_CLOCK (1 << 21)
97 #define LCD_INVERT_FRAME_CLOCK (1 << 20)
99 /* Clock registers available only on Version 2 */
100 #define LCD_CLK_MAIN_RESET (1 << 3)
102 struct da8xx_lcd_regs {
120 u32 dma_frm_buf_base_addr_0;
121 u32 dma_frm_buf_ceiling_addr_0;
122 u32 dma_frm_buf_base_addr_1;
123 u32 dma_frm_buf_ceiling_addr_1;
130 /* Clock registers available only on Version 2 */
135 #define LCD_NUM_BUFFERS 1
137 #define WSI_TIMEOUT 50
138 #define PALETTE_SIZE 256
139 #define LEFT_MARGIN 64
140 #define RIGHT_MARGIN 64
141 #define UPPER_MARGIN 32
142 #define LOWER_MARGIN 32
143 #define WAIT_FOR_FRAME_DONE true
144 #define NO_WAIT_FOR_FRAME_DONE false
146 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
148 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
150 DECLARE_GLOBAL_DATA_PTR;
153 static GraphicDevice gpanel;
154 static const struct da8xx_panel *lcd_panel;
155 static struct fb_info *da8xx_fb_info;
156 static int bits_x_pixel;
157 static unsigned int lcd_revision;
158 const struct lcd_ctrl_config *da8xx_lcd_cfg;
160 static inline unsigned int lcdc_read(u32 *addr)
162 return (unsigned int)readl(addr);
165 static inline void lcdc_write(unsigned int val, u32 *addr)
170 struct da8xx_fb_par {
172 unsigned char *v_palette_base;
173 dma_addr_t vram_phys;
174 unsigned long vram_size;
176 unsigned int dma_start;
177 unsigned int dma_end;
178 struct clk *lcdc_clk;
180 unsigned short pseudo_palette[16];
181 unsigned int palette_sz;
182 unsigned int pxl_clk;
189 /* Variable Screen Information */
190 static struct fb_var_screeninfo da8xx_fb_var = {
198 .pixclock = 46666, /* 46us - AUO display */
200 .left_margin = LEFT_MARGIN,
201 .right_margin = RIGHT_MARGIN,
202 .upper_margin = UPPER_MARGIN,
203 .lower_margin = LOWER_MARGIN,
205 .vmode = FB_VMODE_NONINTERLACED
208 static struct fb_fix_screeninfo da8xx_fb_fix = {
209 .id = "DA8xx FB Drv",
210 .type = FB_TYPE_PACKED_PIXELS,
212 .visual = FB_VISUAL_PSEUDOCOLOR,
216 .accel = FB_ACCEL_NONE
219 /* Enable the Raster Engine of the LCD Controller */
220 static inline void lcd_enable_raster(void)
224 /* Put LCDC in reset for several cycles */
225 if (lcd_revision == LCD_VERSION_2)
226 lcdc_write(LCD_CLK_MAIN_RESET,
227 &da8xx_fb_reg_base->clk_reset);
230 /* Bring LCDC out of reset */
231 if (lcd_revision == LCD_VERSION_2)
233 &da8xx_fb_reg_base->clk_reset);
237 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
238 if (!(reg & LCD_RASTER_ENABLE))
239 lcdc_write(reg | LCD_RASTER_ENABLE,
240 &da8xx_fb_reg_base->raster_ctrl);
243 /* Disable the Raster Engine of the LCD Controller */
244 static inline void lcd_disable_raster(bool wait_for_frame_done)
251 if (wait_for_frame_done)
254 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
255 if (reg & LCD_RASTER_ENABLE)
256 lcdc_write(reg & ~LCD_RASTER_ENABLE,
257 &da8xx_fb_reg_base->raster_ctrl);
259 /* Wait for the current frame to complete */
261 if (lcd_revision == LCD_VERSION_1)
262 stat = lcdc_read(&da8xx_fb_reg_base->stat);
264 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
267 } while (!(stat & 0x01) && (i++ < loop_cnt));
269 if (lcd_revision == LCD_VERSION_1)
270 lcdc_write(stat, &da8xx_fb_reg_base->stat);
272 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
274 if ((loop_cnt != 0) && (i >= loop_cnt)) {
275 printf("LCD Controller timed out\n");
280 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
288 /* init reg to clear PLM (loading mode) fields */
289 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
290 reg_ras &= ~(3 << 20);
292 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
294 if (load_mode == LOAD_DATA) {
295 start = par->dma_start;
298 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
299 if (lcd_revision == LCD_VERSION_1) {
300 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
302 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
303 LCD_V2_END_OF_FRAME0_INT_ENA |
304 LCD_V2_END_OF_FRAME1_INT_ENA |
305 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
306 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
309 #if (LCD_NUM_BUFFERS == 2)
310 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
311 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
312 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
313 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
314 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
316 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
317 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
318 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
319 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
320 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
323 } else if (load_mode == LOAD_PALETTE) {
324 start = par->p_palette_base;
325 end = start + par->palette_sz - 1;
327 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
328 if (lcd_revision == LCD_VERSION_1) {
329 reg_ras |= LCD_V1_PL_INT_ENA;
331 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
333 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
336 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
337 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
340 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
341 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
344 * The Raster enable bit must be set after all other control fields are
350 /* Configure the Burst Size of DMA */
351 static int lcd_cfg_dma(int burst_size)
355 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
356 switch (burst_size) {
358 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
361 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
364 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
367 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
370 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
375 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
380 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
384 /* Set the AC Bias Period and Number of Transitions per Interrupt */
385 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
386 reg |= LCD_AC_BIAS_FREQUENCY(period) |
387 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
388 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
391 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
396 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
397 reg |= ((back_porch & 0xff) << 24)
398 | ((front_porch & 0xff) << 16)
399 | ((pulse_width & 0x3f) << 10);
400 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
403 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
408 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
409 reg |= ((back_porch & 0xff) << 24)
410 | ((front_porch & 0xff) << 16)
411 | ((pulse_width & 0x3f) << 10);
412 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
415 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
420 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
422 LCD_MONOCHROME_MODE);
424 switch (cfg->p_disp_panel->panel_shade) {
426 reg |= LCD_MONOCHROME_MODE;
427 if (cfg->mono_8bit_mode)
428 reg |= LCD_MONO_8BIT_MODE;
432 if (cfg->tft_alt_mode)
433 reg |= LCD_TFT_ALT_ENABLE;
437 if (cfg->stn_565_mode)
438 reg |= LCD_STN_565_ENABLE;
445 /* enable additional interrupts here */
446 if (lcd_revision == LCD_VERSION_1) {
447 reg |= LCD_V1_UNDERFLOW_INT_ENA;
449 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
450 LCD_V2_UNDERFLOW_INT_ENA;
451 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
454 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
456 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
459 reg |= LCD_SYNC_CTRL;
461 reg &= ~LCD_SYNC_CTRL;
464 reg |= LCD_SYNC_EDGE;
466 reg &= ~LCD_SYNC_EDGE;
468 if (cfg->invert_line_clock)
469 reg |= LCD_INVERT_LINE_CLOCK;
471 reg &= ~LCD_INVERT_LINE_CLOCK;
473 if (cfg->invert_frm_clock)
474 reg |= LCD_INVERT_FRAME_CLOCK;
476 reg &= ~LCD_INVERT_FRAME_CLOCK;
478 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
483 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
484 u32 bpp, u32 raster_order)
488 /* Set the Panel Width */
489 /* Pixels per line = (PPL + 1)*16 */
490 if (lcd_revision == LCD_VERSION_1) {
492 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
498 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
503 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
505 if (lcd_revision == LCD_VERSION_1) {
506 reg |= ((width >> 4) - 1) << 4;
508 width = (width >> 4) - 1;
509 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
511 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
513 /* Set the Panel Height */
514 /* Set bits 9:0 of Lines Per Pixel */
515 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
516 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
517 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
519 /* Set bit 10 of Lines Per Pixel */
520 if (lcd_revision == LCD_VERSION_2) {
521 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
522 reg |= ((height - 1) & 0x400) << 16;
523 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
526 /* Set the Raster Order of the Frame Buffer */
527 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
529 reg |= LCD_RASTER_ORDER;
532 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
534 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
535 | LCD_V2_TFT_24BPP_UNPACK);
537 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
546 par->palette_sz = 16 * 2;
550 par->palette_sz = 256 * 2;
560 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
561 unsigned blue, unsigned transp,
562 struct fb_info *info)
564 struct da8xx_fb_par *par = info->par;
565 unsigned short *palette = (unsigned short *) par->v_palette_base;
572 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
575 if (info->var.bits_per_pixel == 8) {
580 pal = (red & 0x0f00);
581 pal |= (green & 0x00f0);
582 pal |= (blue & 0x000f);
584 if (palette[regno] != pal) {
586 palette[regno] = pal;
588 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
589 red >>= (16 - info->var.red.length);
590 red <<= info->var.red.offset;
592 green >>= (16 - info->var.green.length);
593 green <<= info->var.green.offset;
595 blue >>= (16 - info->var.blue.length);
596 blue <<= info->var.blue.offset;
598 par->pseudo_palette[regno] = red | green | blue;
600 if (palette[0] != 0x4000) {
604 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
605 ((info->var.bits_per_pixel == 24) && regno < 24)) {
606 red >>= (24 - info->var.red.length);
607 red <<= info->var.red.offset;
609 green >>= (24 - info->var.green.length);
610 green <<= info->var.green.offset;
612 blue >>= (24 - info->var.blue.length);
613 blue <<= info->var.blue.offset;
615 par->pseudo_palette[regno] = red | green | blue;
617 if (palette[0] != 0x4000) {
623 /* Update the palette in the h/w as needed. */
625 lcd_blit(LOAD_PALETTE, par);
630 static void lcd_reset(struct da8xx_fb_par *par)
632 /* Disable the Raster if previously Enabled */
633 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
635 /* DMA has to be disabled */
636 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
637 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
639 if (lcd_revision == LCD_VERSION_2) {
640 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
641 /* Write 1 to reset */
642 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
643 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
647 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
649 unsigned int lcd_clk, div;
651 /* Get clock from sysclk2 */
652 lcd_clk = clk_get(2);
654 div = lcd_clk / par->pxl_clk;
655 debug("LCD Clock: %d Divider: %d PixClk: %d\n",
656 lcd_clk, div, par->pxl_clk);
658 /* Configure the LCD clock divisor. */
659 lcdc_write(LCD_CLK_DIVISOR(div) |
660 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
662 if (lcd_revision == LCD_VERSION_2)
663 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
665 &da8xx_fb_reg_base->clk_ena);
668 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
669 const struct da8xx_panel *panel)
676 /* Calculate the divider */
677 lcd_calc_clk_divider(par);
679 if (panel->invert_pxl_clk)
680 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
681 LCD_INVERT_PIXEL_CLOCK),
682 &da8xx_fb_reg_base->raster_timing_2);
684 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
685 ~LCD_INVERT_PIXEL_CLOCK),
686 &da8xx_fb_reg_base->raster_timing_2);
688 /* Configure the DMA burst size. */
689 ret = lcd_cfg_dma(cfg->dma_burst_sz);
693 /* Configure the AC bias properties. */
694 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
696 /* Configure the vertical and horizontal sync properties. */
697 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
698 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
700 /* Configure for display */
701 ret = lcd_cfg_display(cfg);
705 if ((QVGA != cfg->p_disp_panel->panel_type) &&
706 (WVGA != cfg->p_disp_panel->panel_type))
709 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
710 cfg->bpp >= cfg->p_disp_panel->min_bpp)
713 bpp = cfg->p_disp_panel->max_bpp;
716 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
717 (unsigned int)panel->height, bpp,
723 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
724 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
729 static void lcdc_dma_start(void)
731 struct da8xx_fb_par *par = da8xx_fb_info->par;
732 lcdc_write(par->dma_start,
733 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
734 lcdc_write(par->dma_end,
735 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
737 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
739 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
742 static u32 lcdc_irq_handler_rev01(void)
744 struct da8xx_fb_par *par = da8xx_fb_info->par;
745 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
748 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
749 debug("LCD_SYNC_LOST\n");
750 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
751 lcdc_write(stat, &da8xx_fb_reg_base->stat);
753 return LCD_SYNC_LOST;
754 } else if (stat & LCD_PL_LOAD_DONE) {
755 debug("LCD_PL_LOAD_DONE\n");
757 * Must disable raster before changing state of any control bit.
758 * And also must be disabled before clearing the PL loading
759 * interrupt via the following write to the status register. If
760 * this is done after then one gets multiple PL done interrupts.
762 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
764 lcdc_write(stat, &da8xx_fb_reg_base->stat);
766 /* Disable PL completion interrupt */
767 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
768 reg_ras &= ~LCD_V1_PL_INT_ENA;
769 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
771 /* Setup and start data loading mode */
772 lcd_blit(LOAD_DATA, par);
773 return LCD_PL_LOAD_DONE;
775 lcdc_write(stat, &da8xx_fb_reg_base->stat);
777 if (stat & LCD_END_OF_FRAME0)
778 debug("LCD_END_OF_FRAME0\n");
780 lcdc_write(par->dma_start,
781 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
782 lcdc_write(par->dma_end,
783 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
785 return LCD_END_OF_FRAME0;
790 static u32 lcdc_irq_handler_rev02(void)
792 struct da8xx_fb_par *par = da8xx_fb_info->par;
793 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
796 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
797 debug("LCD_SYNC_LOST\n");
798 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
799 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
801 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
802 return LCD_SYNC_LOST;
803 } else if (stat & LCD_PL_LOAD_DONE) {
804 debug("LCD_PL_LOAD_DONE\n");
806 * Must disable raster before changing state of any control bit.
807 * And also must be disabled before clearing the PL loading
808 * interrupt via the following write to the status register. If
809 * this is done after then one gets multiple PL done interrupts.
811 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
813 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
815 /* Disable PL completion interrupt */
816 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
818 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
820 /* Setup and start data loading mode */
821 lcd_blit(LOAD_DATA, par);
822 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
823 return LCD_PL_LOAD_DONE;
825 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
827 if (stat & LCD_END_OF_FRAME0)
828 debug("LCD_END_OF_FRAME0\n");
830 lcdc_write(par->dma_start,
831 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
832 lcdc_write(par->dma_end,
833 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
835 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
836 return LCD_END_OF_FRAME0;
838 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
842 static u32 lcdc_irq_handler(void)
844 if (lcd_revision == LCD_VERSION_1)
845 return lcdc_irq_handler_rev01();
847 return lcdc_irq_handler_rev02();
850 static u32 wait_for_event(u32 event)
856 ret = lcdc_irq_handler();
859 } while (!(ret & event) && timeout);
861 if (!(ret & event)) {
862 printf("%s: event %d not hit\n", __func__, event);
870 void *video_hw_init(void)
872 struct da8xx_fb_par *par;
878 printf("Display not initialized\n");
881 gpanel.winSizeX = lcd_panel->width;
882 gpanel.winSizeY = lcd_panel->height;
883 gpanel.plnSizeX = lcd_panel->width;
884 gpanel.plnSizeY = lcd_panel->height;
886 switch (bits_x_pixel) {
888 gpanel.gdfBytesPP = 4;
889 gpanel.gdfIndex = GDF_32BIT_X888RGB;
892 gpanel.gdfBytesPP = 4;
893 gpanel.gdfIndex = GDF_32BIT_X888RGB;
896 gpanel.gdfBytesPP = 2;
897 gpanel.gdfIndex = GDF_16BIT_565RGB;
900 gpanel.gdfBytesPP = 1;
901 gpanel.gdfIndex = GDF__8BIT_INDEX;
905 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
907 /* Determine LCD IP Version */
908 rev = lcdc_read(&da8xx_fb_reg_base->revid);
911 lcd_revision = LCD_VERSION_1;
915 lcd_revision = LCD_VERSION_2;
918 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
920 lcd_revision = LCD_VERSION_1;
924 debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
929 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
930 da8xx_fb_info = malloc_cache_aligned(size);
931 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
933 if (!da8xx_fb_info) {
934 printf("Memory allocation failed for fb_info\n");
937 memset(da8xx_fb_info, 0, size);
938 p = (char *)da8xx_fb_info;
939 da8xx_fb_info->par = p + sizeof(struct fb_info);
940 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
942 par = da8xx_fb_info->par;
943 par->pxl_clk = lcd_panel->pxl_clk;
945 if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
946 printf("lcd_init failed\n");
950 /* allocate frame buffer */
951 par->vram_size = lcd_panel->width * lcd_panel->height *
953 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
955 par->vram_virt = malloc_cache_aligned(par->vram_size);
957 par->vram_phys = (dma_addr_t) par->vram_virt;
958 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
959 (unsigned int)par->vram_size,
960 (unsigned int)par->vram_virt);
961 if (!par->vram_virt) {
962 printf("GLCD: malloc for frame buffer failed\n");
965 gd->fb_base = (int)par->vram_virt;
967 gpanel.frameAdrs = (unsigned int)par->vram_virt;
968 da8xx_fb_info->screen_base = (char *) par->vram_virt;
969 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
970 da8xx_fb_fix.smem_len = par->vram_size;
971 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
973 par->dma_start = par->vram_phys;
974 par->dma_end = par->dma_start + lcd_panel->height *
975 da8xx_fb_fix.line_length - 1;
977 /* allocate palette buffer */
978 par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
979 if (!par->v_palette_base) {
980 printf("GLCD: malloc for palette buffer failed\n");
981 goto err_release_fb_mem;
983 memset(par->v_palette_base, 0, PALETTE_SIZE);
984 par->p_palette_base = (unsigned int)par->v_palette_base;
987 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
989 da8xx_fb_var.xres = lcd_panel->width;
990 da8xx_fb_var.xres_virtual = lcd_panel->width;
992 da8xx_fb_var.yres = lcd_panel->height;
993 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
995 da8xx_fb_var.grayscale =
996 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
997 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
999 da8xx_fb_var.hsync_len = lcd_panel->hsw;
1000 da8xx_fb_var.vsync_len = lcd_panel->vsw;
1002 /* Initialize fbinfo */
1003 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1004 da8xx_fb_info->fix = da8xx_fb_fix;
1005 da8xx_fb_info->var = da8xx_fb_var;
1006 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1007 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1008 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1010 /* Clear interrupt */
1011 memset((void *)par->vram_virt, 0, par->vram_size);
1012 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1013 if (lcd_revision == LCD_VERSION_1)
1014 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1016 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
1017 debug("Palette at 0x%x size %d\n", par->p_palette_base,
1021 /* Load a default palette */
1022 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1024 /* Check that the palette is loaded */
1025 wait_for_event(LCD_PL_LOAD_DONE);
1027 /* Wait until DMA is working */
1028 wait_for_event(LCD_END_OF_FRAME0);
1030 return (void *)&gpanel;
1033 free(par->vram_virt);
1036 free(da8xx_fb_info);
1041 void da8xx_video_init(const struct da8xx_panel *panel,
1042 const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
1045 da8xx_lcd_cfg = lcd_cfg;
1046 bits_x_pixel = bits_pixel;