drivers/video/broadwell_igd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * From coreboot src/soc/intel/broadwell/igd.c
   4  *
   5  * Copyright (C) 2016 Google, Inc
   6  */
   7
   8 #include <common.h>
   9 #include <bios_emul.h>
  10 #include <dm.h>
  11 #include <vbe.h>
  12 #include <video.h>
  13 #include <asm/cpu.h>
  14 #include <asm/intel_regs.h>
  15 #include <asm/io.h>
  16 #include <asm/mtrr.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/iomap.h>
  19 #include <asm/arch/pch.h>
  20 #include "i915_reg.h"
  21
  22 struct broadwell_igd_priv {
  23         u8 *regs;
  24 };
  25
  26 struct broadwell_igd_plat {
  27         u32 dp_hotplug[3];
  28
  29         int port_select;
  30         int power_up_delay;
  31         int power_backlight_on_delay;
  32         int power_down_delay;
  33         int power_backlight_off_delay;
  34         int power_cycle_delay;
  35         int cpu_backlight;
  36         int pch_backlight;
  37         int cdclk;
  38         int pre_graphics_delay;
  39 };
  40
  41 #define GT_RETRY                1000
  42 #define GT_CDCLK_337            0
  43 #define GT_CDCLK_450            1
  44 #define GT_CDCLK_540            2
  45 #define GT_CDCLK_675            3
  46
  47 u32 board_map_oprom_vendev(u32 vendev)
  48 {
  49         return SA_IGD_OPROM_VENDEV;
  50 }
  51
  52 static int poll32(u8 *addr, uint mask, uint value)
  53 {
  54         ulong start;
  55
  56         start = get_timer(0);
  57         debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  58         while ((readl(addr) & mask) != value) {
  59                 if (get_timer(start) > GT_RETRY) {
  60                         debug("poll32: timeout: %x\n", readl(addr));
  61                         return -ETIMEDOUT;
  62                 }
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int haswell_early_init(struct udevice *dev)
  69 {
  70         struct broadwell_igd_priv *priv = dev_get_priv(dev);
  71         u8 *regs = priv->regs;
  72         int ret;
  73
  74         /* Enable Force Wake */
  75         writel(0x00000020, regs + 0xa180);
  76         writel(0x00010001, regs + 0xa188);
  77         ret = poll32(regs + 0x130044, 1, 1);
  78         if (ret)
  79                 goto err;
  80
  81         /* Enable Counters */
  82         setbits_le32(regs + 0xa248, 0x00000016);
  83
  84         /* GFXPAUSE settings */
  85         writel(0x00070020, regs + 0xa000);
  86
  87         /* ECO Settings */
  88         clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  89
  90         /* Enable DOP Clock Gating */
  91         writel(0x000003fd, regs + 0x9424);
  92
  93         /* Enable Unit Level Clock Gating */
  94         writel(0x00000080, regs + 0x9400);
  95         writel(0x40401000, regs + 0x9404);
  96         writel(0x00000000, regs + 0x9408);
  97         writel(0x02000001, regs + 0x940c);
  98
  99         /*
 100          * RC6 Settings
 101          */
 102
 103         /* Wake Rate Limits */
 104         setbits_le32(regs + 0xa090, 0x00000000);
 105         setbits_le32(regs + 0xa098, 0x03e80000);
 106         setbits_le32(regs + 0xa09c, 0x00280000);
 107         setbits_le32(regs + 0xa0a8, 0x0001e848);
 108         setbits_le32(regs + 0xa0ac, 0x00000019);
 109
 110         /* Render/Video/Blitter Idle Max Count */
 111         writel(0x0000000a, regs + 0x02054);
 112         writel(0x0000000a, regs + 0x12054);
 113         writel(0x0000000a, regs + 0x22054);
 114         writel(0x0000000a, regs + 0x1a054);
 115
 116         /* RC Sleep / RCx Thresholds */
 117         setbits_le32(regs + 0xa0b0, 0x00000000);
 118         setbits_le32(regs + 0xa0b4, 0x000003e8);
 119         setbits_le32(regs + 0xa0b8, 0x0000c350);
 120
 121         /* RP Settings */
 122         setbits_le32(regs + 0xa010, 0x000f4240);
 123         setbits_le32(regs + 0xa014, 0x12060000);
 124         setbits_le32(regs + 0xa02c, 0x0000e808);
 125         setbits_le32(regs + 0xa030, 0x0003bd08);
 126         setbits_le32(regs + 0xa068, 0x000101d0);
 127         setbits_le32(regs + 0xa06c, 0x00055730);
 128         setbits_le32(regs + 0xa070, 0x0000000a);
 129
 130         /* RP Control */
 131         writel(0x00000b92, regs + 0xa024);
 132
 133         /* HW RC6 Control */
 134         writel(0x88040000, regs + 0xa090);
 135
 136         /* Video Frequency Request */
 137         writel(0x08000000, regs + 0xa00c);
 138
 139         /* Set RC6 VIDs */
 140         ret = poll32(regs + 0x138124, (1 << 31), 0);
 141         if (ret)
 142                 goto err;
 143         writel(0, regs + 0x138128);
 144         writel(0x80000004, regs + 0x138124);
 145         ret = poll32(regs + 0x138124, (1 << 31), 0);
 146         if (ret)
 147                 goto err;
 148
 149         /* Enable PM Interrupts */
 150         writel(0x03000076, regs + 0x4402c);
 151
 152         /* Enable RC6 in idle */
 153         writel(0x00040000, regs + 0xa094);
 154
 155         return 0;
 156 err:
 157         debug("%s: ret=%d\n", __func__, ret);
 158         return ret;
 159 };
 160
 161 static int haswell_late_init(struct udevice *dev)
 162 {
 163         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 164         u8 *regs = priv->regs;
 165         int ret;
 166
 167         /* Lock settings */
 168         setbits_le32(regs + 0x0a248, (1 << 31));
 169         setbits_le32(regs + 0x0a004, (1 << 4));
 170         setbits_le32(regs + 0x0a080, (1 << 2));
 171         setbits_le32(regs + 0x0a180, (1 << 31));
 172
 173         /* Disable Force Wake */
 174         writel(0x00010000, regs + 0xa188);
 175         ret = poll32(regs + 0x130044, 1, 0);
 176         if (ret)
 177                 goto err;
 178         writel(0x00000001, regs + 0xa188);
 179
 180         /* Enable power well for DP and Audio */
 181         setbits_le32(regs + 0x45400, (1 << 31));
 182         ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
 183         if (ret)
 184                 goto err;
 185
 186         return 0;
 187 err:
 188         debug("%s: ret=%d\n", __func__, ret);
 189         return ret;
 190 };
 191
 192 static int broadwell_early_init(struct udevice *dev)
 193 {
 194         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 195         u8 *regs = priv->regs;
 196         int ret;
 197
 198         /* Enable Force Wake */
 199         writel(0x00010001, regs + 0xa188);
 200         ret = poll32(regs + 0x130044, 1, 1);
 201         if (ret)
 202                 goto err;
 203
 204         /* Enable push bus metric control and shift */
 205         writel(0x00000004, regs + 0xa248);
 206         writel(0x000000ff, regs + 0xa250);
 207         writel(0x00000010, regs + 0xa25c);
 208
 209         /* GFXPAUSE settings (set based on stepping) */
 210
 211         /* ECO Settings */
 212         writel(0x45200000, regs + 0xa180);
 213
 214         /* Enable DOP Clock Gating */
 215         writel(0x000000fd, regs + 0x9424);
 216
 217         /* Enable Unit Level Clock Gating */
 218         writel(0x00000000, regs + 0x9400);
 219         writel(0x40401000, regs + 0x9404);
 220         writel(0x00000000, regs + 0x9408);
 221         writel(0x02000001, regs + 0x940c);
 222         writel(0x0000000a, regs + 0x1a054);
 223
 224         /* Video Frequency Request */
 225         writel(0x08000000, regs + 0xa00c);
 226
 227         writel(0x00000009, regs + 0x138158);
 228         writel(0x0000000d, regs + 0x13815c);
 229
 230         /*
 231          * RC6 Settings
 232          */
 233
 234         /* Wake Rate Limits */
 235         clrsetbits_le32(regs + 0x0a090, ~0, 0);
 236         setbits_le32(regs + 0x0a098, 0x03e80000);
 237         setbits_le32(regs + 0x0a09c, 0x00280000);
 238         setbits_le32(regs + 0x0a0a8, 0x0001e848);
 239         setbits_le32(regs + 0x0a0ac, 0x00000019);
 240
 241         /* Render/Video/Blitter Idle Max Count */
 242         writel(0x0000000a, regs + 0x02054);
 243         writel(0x0000000a, regs + 0x12054);
 244         writel(0x0000000a, regs + 0x22054);
 245
 246         /* RC Sleep / RCx Thresholds */
 247         setbits_le32(regs + 0x0a0b0, 0x00000000);
 248         setbits_le32(regs + 0x0a0b8, 0x00000271);
 249
 250         /* RP Settings */
 251         setbits_le32(regs + 0x0a010, 0x000f4240);
 252         setbits_le32(regs + 0x0a014, 0x12060000);
 253         setbits_le32(regs + 0x0a02c, 0x0000e808);
 254         setbits_le32(regs + 0x0a030, 0x0003bd08);
 255         setbits_le32(regs + 0x0a068, 0x000101d0);
 256         setbits_le32(regs + 0x0a06c, 0x00055730);
 257         setbits_le32(regs + 0x0a070, 0x0000000a);
 258         setbits_le32(regs + 0x0a168, 0x00000006);
 259
 260         /* RP Control */
 261         writel(0x00000b92, regs + 0xa024);
 262
 263         /* HW RC6 Control */
 264         writel(0x90040000, regs + 0xa090);
 265
 266         /* Set RC6 VIDs */
 267         ret = poll32(regs + 0x138124, (1 << 31), 0);
 268         if (ret)
 269                 goto err;
 270         writel(0, regs + 0x138128);
 271         writel(0x80000004, regs + 0x138124);
 272         ret = poll32(regs + 0x138124, (1 << 31), 0);
 273         if (ret)
 274                 goto err;
 275
 276         /* Enable PM Interrupts */
 277         writel(0x03000076, regs + 0x4402c);
 278
 279         /* Enable RC6 in idle */
 280         writel(0x00040000, regs + 0xa094);
 281
 282         return 0;
 283 err:
 284         debug("%s: ret=%d\n", __func__, ret);
 285         return ret;
 286 }
 287
 288 static int broadwell_late_init(struct udevice *dev)
 289 {
 290         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 291         u8 *regs = priv->regs;
 292         int ret;
 293
 294         /* Lock settings */
 295         setbits_le32(regs + 0x0a248, 1 << 31);
 296         setbits_le32(regs + 0x0a000, 1 << 18);
 297         setbits_le32(regs + 0x0a180, 1 << 31);
 298
 299         /* Disable Force Wake */
 300         writel(0x00010000, regs + 0xa188);
 301         ret = poll32(regs + 0x130044, 1, 0);
 302         if (ret)
 303                 goto err;
 304
 305         /* Enable power well for DP and Audio */
 306         setbits_le32(regs + 0x45400, 1 << 31);
 307         ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
 308         if (ret)
 309                 goto err;
 310
 311         return 0;
 312 err:
 313         debug("%s: ret=%d\n", __func__, ret);
 314         return ret;
 315 };
 316
 317
 318 static unsigned long gtt_read(struct broadwell_igd_priv *priv,
 319                               unsigned long reg)
 320 {
 321         return readl(priv->regs + reg);
 322 }
 323
 324 static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
 325                       unsigned long data)
 326 {
 327         writel(data, priv->regs + reg);
 328 }
 329
 330 static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
 331                                   u32 bic, u32 or)
 332 {
 333         clrsetbits_le32(priv->regs + reg, bic, or);
 334 }
 335
 336 static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
 337                     u32 value)
 338 {
 339         unsigned try = GT_RETRY;
 340         u32 data;
 341
 342         while (try--) {
 343                 data = gtt_read(priv, reg);
 344                 if ((data & mask) == value)
 345                         return 0;
 346                 udelay(10);
 347         }
 348
 349         debug("GT init timeout\n");
 350         return -ETIMEDOUT;
 351 }
 352
 353 static void igd_setup_panel(struct udevice *dev)
 354 {
 355         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 356         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 357         u32 reg32;
 358
 359         /* Setup Digital Port Hotplug */
 360         reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
 361         reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
 362         reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
 363         gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
 364
 365         /* Setup Panel Power On Delays */
 366         reg32 = (plat->port_select & 0x3) << 30;
 367         reg32 |= (plat->power_up_delay & 0x1fff) << 16;
 368         reg32 |= (plat->power_backlight_on_delay & 0x1fff);
 369         gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
 370
 371         /* Setup Panel Power Off Delays */
 372         reg32 = (plat->power_down_delay & 0x1fff) << 16;
 373         reg32 |= (plat->power_backlight_off_delay & 0x1fff);
 374         gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
 375
 376         /* Setup Panel Power Cycle Delay */
 377         if (plat->power_cycle_delay) {
 378                 reg32 = gtt_read(priv, PCH_PP_DIVISOR);
 379                 reg32 &= ~0xff;
 380                 reg32 |= plat->power_cycle_delay & 0xff;
 381                 gtt_write(priv, PCH_PP_DIVISOR, reg32);
 382         }
 383
 384         /* Enable Backlight if needed */
 385         if (plat->cpu_backlight) {
 386                 gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
 387                 gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
 388         }
 389         if (plat->pch_backlight) {
 390                 gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
 391                 gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
 392         }
 393 }
 394
 395 static int igd_cdclk_init_haswell(struct udevice *dev)
 396 {
 397         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 398         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 399         int cdclk = plat->cdclk;
 400         u16 devid;
 401         int gpu_is_ulx = 0;
 402         u32 dpdiv, lpcll;
 403         int ret;
 404
 405         dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
 406
 407         /* Check for ULX GT1 or GT2 */
 408         if (devid == 0x0a0e || devid == 0x0a1e)
 409                 gpu_is_ulx = 1;
 410
 411         /* 675MHz is not supported on haswell */
 412         if (cdclk == GT_CDCLK_675)
 413                 cdclk = GT_CDCLK_337;
 414
 415         /* If CD clock is fixed or ULT then set to 450MHz */
 416         if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
 417                 cdclk = GT_CDCLK_450;
 418
 419         /* 540MHz is not supported on ULX */
 420         if (gpu_is_ulx && cdclk == GT_CDCLK_540)
 421                 cdclk = GT_CDCLK_337;
 422
 423         /* 337.5MHz is not supported on non-ULT/ULX */
 424         if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
 425                 cdclk = GT_CDCLK_450;
 426
 427         /* Set variables based on CD Clock setting */
 428         switch (cdclk) {
 429         case GT_CDCLK_337:
 430                 dpdiv = 169;
 431                 lpcll = (1 << 26);
 432                 break;
 433         case GT_CDCLK_450:
 434                 dpdiv = 225;
 435                 lpcll = 0;
 436                 break;
 437         case GT_CDCLK_540:
 438                 dpdiv = 270;
 439                 lpcll = (1 << 26);
 440                 break;
 441         default:
 442                 ret = -EDOM;
 443                 goto err;
 444         }
 445
 446         /* Set LPCLL_CTL CD Clock Frequency Select */
 447         gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
 448
 449         /* ULX: Inform power controller of selected frequency */
 450         if (gpu_is_ulx) {
 451                 if (cdclk == GT_CDCLK_450)
 452                         gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
 453                 else
 454                         gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
 455                 gtt_write(priv, 0x13812c, 0x00000000);
 456                 gtt_write(priv, 0x138124, 0x80000017);
 457         }
 458
 459         /* Set CPU DP AUX 2X bit clock dividers */
 460         gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
 461         gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
 462
 463         return 0;
 464 err:
 465         debug("%s: ret=%d\n", __func__, ret);
 466         return ret;
 467 }
 468
 469 static int igd_cdclk_init_broadwell(struct udevice *dev)
 470 {
 471         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 472         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 473         int cdclk = plat->cdclk;
 474         u32 dpdiv, lpcll, pwctl, cdset;
 475         int ret;
 476
 477         /* Inform power controller of upcoming frequency change */
 478         gtt_write(priv, 0x138128, 0);
 479         gtt_write(priv, 0x13812c, 0);
 480         gtt_write(priv, 0x138124, 0x80000018);
 481
 482         /* Poll GT driver mailbox for run/busy clear */
 483         if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
 484                 cdclk = GT_CDCLK_450;
 485
 486         if (gtt_read(priv, 0x42014) & 0x1000000) {
 487                 /* If CD clock is fixed then set to 450MHz */
 488                 cdclk = GT_CDCLK_450;
 489         } else {
 490                 /* Program CD clock to highest supported freq */
 491                 if (cpu_is_ult())
 492                         cdclk = GT_CDCLK_540;
 493                 else
 494                         cdclk = GT_CDCLK_675;
 495         }
 496
 497         /* CD clock frequency 675MHz not supported on ULT */
 498         if (cpu_is_ult() && cdclk == GT_CDCLK_675)
 499                 cdclk = GT_CDCLK_540;
 500
 501         /* Set variables based on CD Clock setting */
 502         switch (cdclk) {
 503         case GT_CDCLK_337:
 504                 cdset = 337;
 505                 lpcll = (1 << 27);
 506                 pwctl = 2;
 507                 dpdiv = 169;
 508                 break;
 509         case GT_CDCLK_450:
 510                 cdset = 449;
 511                 lpcll = 0;
 512                 pwctl = 0;
 513                 dpdiv = 225;
 514                 break;
 515         case GT_CDCLK_540:
 516                 cdset = 539;
 517                 lpcll = (1 << 26);
 518                 pwctl = 1;
 519                 dpdiv = 270;
 520                 break;
 521         case GT_CDCLK_675:
 522                 cdset = 674;
 523                 lpcll = (1 << 26) | (1 << 27);
 524                 pwctl = 3;
 525                 dpdiv = 338;
 526                 break;
 527         default:
 528                 ret = -EDOM;
 529                 goto err;
 530         }
 531         debug("%s: frequency = %d\n", __func__, cdclk);
 532
 533         /* Set LPCLL_CTL CD Clock Frequency Select */
 534         gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
 535
 536         /* Inform power controller of selected frequency */
 537         gtt_write(priv, 0x138128, pwctl);
 538         gtt_write(priv, 0x13812c, 0);
 539         gtt_write(priv, 0x138124, 0x80000017);
 540
 541         /* Program CD Clock Frequency */
 542         gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
 543
 544         /* Set CPU DP AUX 2X bit clock dividers */
 545         gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
 546         gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
 547
 548         return 0;
 549 err:
 550         debug("%s: ret=%d\n", __func__, ret);
 551         return ret;
 552 }
 553
 554 u8 systemagent_revision(struct udevice *bus)
 555 {
 556         ulong val;
 557
 558         pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
 559                             PCI_SIZE_32);
 560
 561         return val;
 562 }
 563
 564 static int igd_pre_init(struct udevice *dev, bool is_broadwell)
 565 {
 566         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 567         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 568         u32 rp1_gfx_freq;
 569         int ret;
 570
 571         mdelay(plat->pre_graphics_delay);
 572
 573         /* Early init steps */
 574         if (is_broadwell) {
 575                 ret = broadwell_early_init(dev);
 576                 if (ret)
 577                         goto err;
 578
 579                 /* Set GFXPAUSE based on stepping */
 580                 if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
 581                     systemagent_revision(pci_get_controller(dev)) <= 9) {
 582                         gtt_write(priv, 0xa000, 0x300ff);
 583                 } else {
 584                         gtt_write(priv, 0xa000, 0x30020);
 585                 }
 586         } else {
 587                 ret = haswell_early_init(dev);
 588                 if (ret)
 589                         goto err;
 590         }
 591
 592         /* Set RP1 graphics frequency */
 593         rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
 594         gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
 595
 596         /* Post VBIOS panel setup */
 597         igd_setup_panel(dev);
 598
 599         return 0;
 600 err:
 601         debug("%s: ret=%d\n", __func__, ret);
 602         return ret;
 603 }
 604
 605 static int igd_post_init(struct udevice *dev, bool is_broadwell)
 606 {
 607         int ret;
 608
 609         /* Late init steps */
 610         if (is_broadwell) {
 611                 ret = igd_cdclk_init_broadwell(dev);
 612                 if (ret)
 613                         return ret;
 614                 ret = broadwell_late_init(dev);
 615                 if (ret)
 616                         return ret;
 617         } else {
 618                 igd_cdclk_init_haswell(dev);
 619                 ret = haswell_late_init(dev);
 620                 if (ret)
 621                         return ret;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int broadwell_igd_int15_handler(void)
 628 {
 629         int res = 0;
 630
 631         debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
 632
 633         switch (M.x86.R_AX) {
 634         case 0x5f35:
 635                 /*
 636                  * Boot Display Device Hook:
 637                  *  bit 0 = CRT
 638                  *  bit 1 = TV (eDP)
 639                  *  bit 2 = EFP
 640                  *  bit 3 = LFP
 641                  *  bit 4 = CRT2
 642                  *  bit 5 = TV2 (eDP)
 643                  *  bit 6 = EFP2
 644                  *  bit 7 = LFP2
 645                  */
 646                 M.x86.R_AX = 0x005f;
 647                 M.x86.R_CX = 0x0000; /* Use video bios default */
 648                 res = 1;
 649                 break;
 650         default:
 651                 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
 652                 break;
 653         }
 654
 655         return res;
 656 }
 657
 658 static int broadwell_igd_probe(struct udevice *dev)
 659 {
 660         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 661         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 662         bool is_broadwell;
 663         int ret;
 664
 665         if (!ll_boot_init()) {
 666                 /*
 667                  * If we are running from EFI or coreboot, this driver can't
 668                  * work.
 669                  */
 670                 printf("Not available (previous bootloader prevents it)\n");
 671                 return -EPERM;
 672         }
 673         is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
 674         bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
 675         debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
 676         ret = igd_pre_init(dev, is_broadwell);
 677         if (!ret) {
 678                 ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
 679                 if (ret)
 680                         debug("failed to run video BIOS: %d\n", ret);
 681         }
 682         if (!ret)
 683                 ret = igd_post_init(dev, is_broadwell);
 684         bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
 685         if (ret)
 686                 return ret;
 687
 688         /* Use write-combining for the graphics memory, 256MB */
 689         ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
 690         if (!ret)
 691                 ret = mtrr_commit(true);
 692         if (ret && ret != -ENOSYS) {
 693                 printf("Failed to add MTRR: Display will be slow (err %d)\n",
 694                        ret);
 695         }
 696
 697         debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
 698               plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
 699
 700         return 0;
 701 }
 702
 703 static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
 704 {
 705         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 706         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 707         int node = dev_of_offset(dev);
 708         const void *blob = gd->fdt_blob;
 709
 710         if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
 711                                  plat->dp_hotplug,
 712                                  ARRAY_SIZE(plat->dp_hotplug)))
 713                 return -EINVAL;
 714         plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
 715         plat->power_cycle_delay = fdtdec_get_int(blob, node,
 716                         "intel,power-cycle-delay", 0);
 717         plat->power_up_delay = fdtdec_get_int(blob, node,
 718                         "intel,power-up-delay", 0);
 719         plat->power_down_delay = fdtdec_get_int(blob, node,
 720                         "intel,power-down-delay", 0);
 721         plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
 722                         "intel,power-backlight-on-delay", 0);
 723         plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
 724                         "intel,power-backlight-off-delay", 0);
 725         plat->cpu_backlight = fdtdec_get_int(blob, node,
 726                         "intel,cpu-backlight", 0);
 727         plat->pch_backlight = fdtdec_get_int(blob, node,
 728                         "intel,pch-backlight", 0);
 729         plat->pre_graphics_delay = fdtdec_get_int(blob, node,
 730                         "intel,pre-graphics-delay", 0);
 731         priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
 732         debug("%s: regs at %p\n", __func__, priv->regs);
 733         debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
 734               plat->dp_hotplug[2]);
 735         debug("port_select = %d\n", plat->port_select);
 736         debug("power_up_delay = %d\n", plat->power_up_delay);
 737         debug("power_backlight_on_delay = %d\n",
 738               plat->power_backlight_on_delay);
 739         debug("power_down_delay = %d\n", plat->power_down_delay);
 740         debug("power_backlight_off_delay = %d\n",
 741               plat->power_backlight_off_delay);
 742         debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
 743         debug("cpu_backlight = %x\n", plat->cpu_backlight);
 744         debug("pch_backlight = %x\n", plat->pch_backlight);
 745         debug("cdclk = %d\n", plat->cdclk);
 746         debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
 747
 748         return 0;
 749 }
 750
 751 static const struct video_ops broadwell_igd_ops = {
 752 };
 753
 754 static const struct udevice_id broadwell_igd_ids[] = {
 755         { .compatible = "intel,broadwell-igd" },
 756         { }
 757 };
 758
 759 U_BOOT_DRIVER(broadwell_igd) = {
 760         .name   = "broadwell_igd",
 761         .id     = UCLASS_VIDEO,
 762         .of_match = broadwell_igd_ids,
 763         .ops    = &broadwell_igd_ops,
 764         .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
 765         .probe  = broadwell_igd_probe,
 766         .priv_auto_alloc_size   = sizeof(struct broadwell_igd_priv),
 767         .platdata_auto_alloc_size       = sizeof(struct broadwell_igd_plat),
 768 };