drivers/video/atmel_lcdfb.c

   1 /*
   2  * Driver for AT91/AT32 LCD Controller
   3  *
   4  * Copyright (C) 2007 Atmel Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/gpio.h>
  12 #include <asm/arch/clk.h>
  13 #include <lcd.h>
  14 #include <atmel_lcdc.h>
  15
  16 /* configurable parameters */
  17 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  18 #define ATMEL_LCDC_DMA_BURST_LEN        8
  19 #ifndef ATMEL_LCDC_GUARD_TIME
  20 #define ATMEL_LCDC_GUARD_TIME           1
  21 #endif
  22
  23 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
  24 #define ATMEL_LCDC_FIFO_SIZE            2048
  25 #else
  26 #define ATMEL_LCDC_FIFO_SIZE            512
  27 #endif
  28
  29 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  30 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  31
  32 ushort *configuration_get_cmap(void)
  33 {
  34         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  35 }
  36
  37 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  38 void fb_put_word(uchar **fb, uchar **from)
  39 {
  40         *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  41         *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  42         *from += 2;
  43 }
  44 #endif
  45
  46 #ifdef CONFIG_LCD_LOGO
  47 #include <bmp_logo.h>
  48 void lcd_logo_set_cmap(void)
  49 {
  50         int i;
  51         uint lut_entry;
  52         ushort colreg;
  53         uint *cmap = (uint *)configuration_get_cmap();
  54
  55         for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  56                 colreg = bmp_logo_palette[i];
  57 #ifdef CONFIG_ATMEL_LCD_BGR555
  58                 lut_entry = ((colreg & 0x000F) << 11) |
  59                                 ((colreg & 0x00F0) <<  2) |
  60                                 ((colreg & 0x0F00) >>  7);
  61 #else
  62                 lut_entry = ((colreg & 0x000F) << 1) |
  63                                 ((colreg & 0x00F0) << 3) |
  64                                 ((colreg & 0x0F00) << 4);
  65 #endif
  66                 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  67                 cmap++;
  68         }
  69 }
  70 #endif
  71
  72 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  73 {
  74 #if defined(CONFIG_ATMEL_LCD_BGR555)
  75         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  76                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  77 #else
  78         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  79                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  80 #endif
  81 }
  82
  83 void lcd_ctrl_init(void *lcdbase)
  84 {
  85         unsigned long value;
  86
  87         /* Turn off the LCD controller and the DMA controller */
  88         lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
  89                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  90
  91         /* Wait for the LCDC core to become idle */
  92         while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  93                 udelay(10);
  94
  95         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
  96
  97         /* Reset LCDC DMA */
  98         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  99
 100         /* ...set frame size and burst length = 8 words (?) */
 101         value = (panel_info.vl_col * panel_info.vl_row *
 102                  NBITS(panel_info.vl_bpix)) / 32;
 103         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 104         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
 105
 106         /* Set pixel clock */
 107         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
 108         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
 109                 value++;
 110         value = (value / 2) - 1;
 111
 112         if (!value) {
 113                 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 114         } else
 115                 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
 116                             value << ATMEL_LCDC_CLKVAL_OFFSET);
 117
 118         /* Initialize control register 2 */
 119 #ifdef CONFIG_AVR32
 120         value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 121 #else
 122         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 123 #endif
 124         if (panel_info.vl_tft)
 125                 value |= ATMEL_LCDC_DISTYPE_TFT;
 126
 127         value |= panel_info.vl_sync;
 128         value |= (panel_info.vl_bpix << 5);
 129         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
 130
 131         /* Vertical timing */
 132         value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
 133         value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
 134         value |= panel_info.vl_lower_margin;
 135         lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
 136
 137         /* Horizontal timing */
 138         value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
 139         value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
 140         value |= (panel_info.vl_left_margin - 1);
 141         lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
 142
 143         /* Display size */
 144         value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 145         value |= panel_info.vl_row - 1;
 146         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
 147
 148         /* FIFO Threshold: Use formula from data sheet */
 149         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 150         lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
 151
 152         /* Toggle LCD_MODE every frame */
 153         lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
 154
 155         /* Disable all interrupts */
 156         lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
 157
 158         /* Set contrast */
 159         value = ATMEL_LCDC_PS_DIV8 |
 160                 ATMEL_LCDC_ENA_PWMENABLE;
 161         if (!panel_info.vl_cont_pol_low)
 162                 value |= ATMEL_LCDC_POL_POSITIVE;
 163         lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
 164         lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 165
 166         /* Set framebuffer DMA base address and pixel offset */
 167         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
 168
 169         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 170         lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
 171                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 172 }
 173
 174 ulong calc_fbsize(void)
 175 {
 176         return ((panel_info.vl_col * panel_info.vl_row *
 177                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 178 }