1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AT91/AT32 LCD Controller
5 * Copyright (C) 2007 Atmel Corporation
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
19 #include <bmp_layout.h>
20 #include <atmel_lcdc.h>
21 #include <linux/delay.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_DM_VIDEO
27 /* Maximum LCD size we support */
30 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
34 struct atmel_fb_priv {
35 struct display_timing timing;
38 /* configurable parameters */
39 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
40 #define ATMEL_LCDC_DMA_BURST_LEN 8
41 #ifndef ATMEL_LCDC_GUARD_TIME
42 #define ATMEL_LCDC_GUARD_TIME 1
45 #if defined(CONFIG_AT91SAM9263)
46 #define ATMEL_LCDC_FIFO_SIZE 2048
48 #define ATMEL_LCDC_FIFO_SIZE 512
51 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
52 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
54 #ifndef CONFIG_DM_VIDEO
55 ushort *configuration_get_cmap(void)
57 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
60 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
61 void fb_put_word(uchar **fb, uchar **from)
63 *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
64 *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
69 #ifdef CONFIG_LCD_LOGO
71 void lcd_logo_set_cmap(void)
76 uint *cmap = (uint *)configuration_get_cmap();
78 for (i = 0; i < BMP_LOGO_COLORS; ++i) {
79 colreg = bmp_logo_palette[i];
80 #ifdef CONFIG_ATMEL_LCD_BGR555
81 lut_entry = ((colreg & 0x000F) << 11) |
82 ((colreg & 0x00F0) << 2) |
83 ((colreg & 0x0F00) >> 7);
85 lut_entry = ((colreg & 0x000F) << 1) |
86 ((colreg & 0x00F0) << 3) |
87 ((colreg & 0x0F00) << 4);
89 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
95 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
97 #if defined(CONFIG_ATMEL_LCD_BGR555)
98 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
99 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
101 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
102 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
106 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
110 for (i = 0; i < colors; ++i) {
111 struct bmp_color_table_entry cte = bmp->color_table[i];
112 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
117 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
118 bool tft, bool cont_pol_low, ulong lcdbase)
121 void *reg = (void *)addr;
123 /* Turn off the LCD controller and the DMA controller */
124 lcdc_writel(reg, ATMEL_LCDC_PWRCON,
125 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
127 /* Wait for the LCDC core to become idle */
128 while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
131 lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
134 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
136 /* ...set frame size and burst length = 8 words (?) */
137 value = (timing->hactive.typ * timing->vactive.typ *
139 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
140 lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
142 /* Set pixel clock */
143 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
144 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
146 value = (value / 2) - 1;
149 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
151 lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
152 value << ATMEL_LCDC_CLKVAL_OFFSET);
154 /* Initialize control register 2 */
155 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
157 value |= ATMEL_LCDC_DISTYPE_TFT;
159 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
160 value |= ATMEL_LCDC_INVLINE_INVERTED;
161 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
162 value |= ATMEL_LCDC_INVFRAME_INVERTED;
164 lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
166 /* Vertical timing */
167 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
168 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
169 value |= timing->vfront_porch.typ;
170 /* Magic! (Datasheet says "Bit 31 must be written to 1") */
172 lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
174 /* Horizontal timing */
175 value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
176 value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
177 value |= (timing->hback_porch.typ - 1);
178 lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
181 value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
182 value |= timing->vactive.typ - 1;
183 lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
185 /* FIFO Threshold: Use formula from data sheet */
186 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
187 lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
189 /* Toggle LCD_MODE every frame */
190 lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
192 /* Disable all interrupts */
193 lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
196 value = ATMEL_LCDC_PS_DIV8 |
197 ATMEL_LCDC_ENA_PWMENABLE;
199 value |= ATMEL_LCDC_POL_POSITIVE;
200 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
201 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
203 /* Set framebuffer DMA base address and pixel offset */
204 lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
206 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
207 lcdc_writel(reg, ATMEL_LCDC_PWRCON,
208 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
211 #ifndef CONFIG_DM_VIDEO
212 void lcd_ctrl_init(void *lcdbase)
214 struct display_timing timing;
217 if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
218 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
219 if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
220 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
221 timing.pixelclock.typ = panel_info.vl_clk;
223 timing.hactive.typ = panel_info.vl_col;
224 timing.hfront_porch.typ = panel_info.vl_right_margin;
225 timing.hback_porch.typ = panel_info.vl_left_margin;
226 timing.hsync_len.typ = panel_info.vl_hsync_len;
228 timing.vactive.typ = panel_info.vl_row;
229 timing.vfront_porch.typ = panel_info.vl_clk;
230 timing.vback_porch.typ = panel_info.vl_clk;
231 timing.vsync_len.typ = panel_info.vl_clk;
233 atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
234 panel_info.vl_tft, panel_info.vl_cont_pol_low,
238 ulong calc_fbsize(void)
240 return ((panel_info.vl_col * panel_info.vl_row *
241 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
245 #ifdef CONFIG_DM_VIDEO
246 static int atmel_fb_lcd_probe(struct udevice *dev)
248 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
249 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
250 struct atmel_fb_priv *priv = dev_get_priv(dev);
251 struct display_timing *timing = &priv->timing;
254 * For now some values are hard-coded. We could use the device tree
255 * bindings in simple-framebuffer.txt to specify the format/bpp and
256 * some Atmel-specific binding for tft and cont_pol_low.
258 atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
260 uc_priv->xsize = timing->hactive.typ;
261 uc_priv->ysize = timing->vactive.typ;
262 uc_priv->bpix = VIDEO_BPP16;
263 video_set_flush_dcache(dev, true);
264 debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
265 uc_plat->size, uc_priv->xsize, uc_priv->ysize);
270 static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
272 struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
273 struct atmel_fb_priv *priv = dev_get_priv(dev);
274 struct display_timing *timing = &priv->timing;
275 const void *blob = gd->fdt_blob;
277 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
278 plat->timing_index, timing)) {
279 debug("%s: Failed to decode display timing\n", __func__);
286 static int atmel_fb_lcd_bind(struct udevice *dev)
288 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
290 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
291 (1 << VIDEO_BPP16) / 8;
292 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
297 static const struct udevice_id atmel_fb_lcd_ids[] = {
298 { .compatible = "atmel,at91sam9g45-lcdc" },
302 U_BOOT_DRIVER(atmel_fb) = {
305 .of_match = atmel_fb_lcd_ids,
306 .bind = atmel_fb_lcd_bind,
307 .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
308 .probe = atmel_fb_lcd_probe,
309 .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
310 .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),