drivers/video/atmel_lcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 LCD Controller
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_lcd.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <log.h>
  13 #include <part.h>
  14 #include <video.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/clk.h>
  19 #include <lcd.h>
  20 #include <bmp_layout.h>
  21 #include <atmel_lcdc.h>
  22 #include <linux/delay.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #ifdef CONFIG_DM_VIDEO
  27 enum {
  28         /* Maximum LCD size we support */
  29         LCD_MAX_WIDTH           = 1366,
  30         LCD_MAX_HEIGHT          = 768,
  31         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  32 };
  33 #endif
  34
  35 struct atmel_fb_priv {
  36         struct display_timing timing;
  37 };
  38
  39 /* configurable parameters */
  40 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  41 #define ATMEL_LCDC_DMA_BURST_LEN        8
  42 #ifndef ATMEL_LCDC_GUARD_TIME
  43 #define ATMEL_LCDC_GUARD_TIME           1
  44 #endif
  45
  46 #if defined(CONFIG_AT91SAM9263)
  47 #define ATMEL_LCDC_FIFO_SIZE            2048
  48 #else
  49 #define ATMEL_LCDC_FIFO_SIZE            512
  50 #endif
  51
  52 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  53 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  54
  55 #ifndef CONFIG_DM_VIDEO
  56 ushort *configuration_get_cmap(void)
  57 {
  58         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  59 }
  60
  61 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  62 void fb_put_word(uchar **fb, uchar **from)
  63 {
  64         *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  65         *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  66         *from += 2;
  67 }
  68 #endif
  69
  70 #ifdef CONFIG_LCD_LOGO
  71 #include <bmp_logo.h>
  72 void lcd_logo_set_cmap(void)
  73 {
  74         int i;
  75         uint lut_entry;
  76         ushort colreg;
  77         uint *cmap = (uint *)configuration_get_cmap();
  78
  79         for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  80                 colreg = bmp_logo_palette[i];
  81 #ifdef CONFIG_ATMEL_LCD_BGR555
  82                 lut_entry = ((colreg & 0x000F) << 11) |
  83                                 ((colreg & 0x00F0) <<  2) |
  84                                 ((colreg & 0x0F00) >>  7);
  85 #else
  86                 lut_entry = ((colreg & 0x000F) << 1) |
  87                                 ((colreg & 0x00F0) << 3) |
  88                                 ((colreg & 0x0F00) << 4);
  89 #endif
  90                 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  91                 cmap++;
  92         }
  93 }
  94 #endif
  95
  96 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  97 {
  98 #if defined(CONFIG_ATMEL_LCD_BGR555)
  99         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
 100                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
 101 #else
 102         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
 103                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
 104 #endif
 105 }
 106
 107 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 108 {
 109         int i;
 110
 111         for (i = 0; i < colors; ++i) {
 112                 struct bmp_color_table_entry cte = bmp->color_table[i];
 113                 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
 114         }
 115 }
 116 #endif
 117
 118 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 119                           bool tft, bool cont_pol_low, ulong lcdbase)
 120 {
 121         unsigned long value;
 122         void *reg = (void *)addr;
 123
 124         /* Turn off the LCD controller and the DMA controller */
 125         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 126                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 127
 128         /* Wait for the LCDC core to become idle */
 129         while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 130                 udelay(10);
 131
 132         lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 133
 134         /* Reset LCDC DMA */
 135         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 136
 137         /* ...set frame size and burst length = 8 words (?) */
 138         value = (timing->hactive.typ * timing->vactive.typ *
 139                  (1 << bpix)) / 32;
 140         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 141         lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 142
 143         /* Set pixel clock */
 144         value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
 145         if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 146                 value++;
 147         value = (value / 2) - 1;
 148
 149         if (!value) {
 150                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 151         } else
 152                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 153                             value << ATMEL_LCDC_CLKVAL_OFFSET);
 154
 155         /* Initialize control register 2 */
 156         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 157         if (tft)
 158                 value |= ATMEL_LCDC_DISTYPE_TFT;
 159
 160         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 161                 value |= ATMEL_LCDC_INVLINE_INVERTED;
 162         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 163                 value |= ATMEL_LCDC_INVFRAME_INVERTED;
 164         value |= bpix << 5;
 165         lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 166
 167         /* Vertical timing */
 168         value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
 169         value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
 170         value |= timing->vfront_porch.typ;
 171         /* Magic! (Datasheet says "Bit 31 must be written to 1") */
 172         value |= 1U << 31;
 173         lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 174
 175         /* Horizontal timing */
 176         value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
 177         value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
 178         value |= (timing->hback_porch.typ - 1);
 179         lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 180
 181         /* Display size */
 182         value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 183         value |= timing->vactive.typ - 1;
 184         lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 185
 186         /* FIFO Threshold: Use formula from data sheet */
 187         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 188         lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 189
 190         /* Toggle LCD_MODE every frame */
 191         lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 192
 193         /* Disable all interrupts */
 194         lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 195
 196         /* Set contrast */
 197         value = ATMEL_LCDC_PS_DIV8 |
 198                 ATMEL_LCDC_ENA_PWMENABLE;
 199         if (!cont_pol_low)
 200                 value |= ATMEL_LCDC_POL_POSITIVE;
 201         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
 202         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 203
 204         /* Set framebuffer DMA base address and pixel offset */
 205         lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 206
 207         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 208         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 209                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 210 }
 211
 212 #ifndef CONFIG_DM_VIDEO
 213 void lcd_ctrl_init(void *lcdbase)
 214 {
 215         struct display_timing timing;
 216
 217         timing.flags = 0;
 218         if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
 219                 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
 220         if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
 221                 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
 222         timing.pixelclock.typ = panel_info.vl_clk;
 223
 224         timing.hactive.typ = panel_info.vl_col;
 225         timing.hfront_porch.typ = panel_info.vl_right_margin;
 226         timing.hback_porch.typ = panel_info.vl_left_margin;
 227         timing.hsync_len.typ = panel_info.vl_hsync_len;
 228
 229         timing.vactive.typ = panel_info.vl_row;
 230         timing.vfront_porch.typ = panel_info.vl_clk;
 231         timing.vback_porch.typ = panel_info.vl_clk;
 232         timing.vsync_len.typ = panel_info.vl_clk;
 233
 234         atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
 235                       panel_info.vl_tft, panel_info.vl_cont_pol_low,
 236                       (ulong)lcdbase);
 237 }
 238
 239 ulong calc_fbsize(void)
 240 {
 241         return ((panel_info.vl_col * panel_info.vl_row *
 242                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_DM_VIDEO
 247 static int atmel_fb_lcd_probe(struct udevice *dev)
 248 {
 249         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 250         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 251         struct atmel_fb_priv *priv = dev_get_priv(dev);
 252         struct display_timing *timing = &priv->timing;
 253
 254         /*
 255          * For now some values are hard-coded. We could use the device tree
 256          * bindings in simple-framebuffer.txt to specify the format/bpp and
 257          * some Atmel-specific binding for tft and cont_pol_low.
 258          */
 259         atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
 260                       uc_plat->base);
 261         uc_priv->xsize = timing->hactive.typ;
 262         uc_priv->ysize = timing->vactive.typ;
 263         uc_priv->bpix = VIDEO_BPP16;
 264         video_set_flush_dcache(dev, true);
 265         debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
 266               uc_plat->size, uc_priv->xsize, uc_priv->ysize);
 267
 268         return 0;
 269 }
 270
 271 static int atmel_fb_of_to_plat(struct udevice *dev)
 272 {
 273         struct atmel_lcd_plat *plat = dev_get_plat(dev);
 274         struct atmel_fb_priv *priv = dev_get_priv(dev);
 275         struct display_timing *timing = &priv->timing;
 276         const void *blob = gd->fdt_blob;
 277
 278         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 279                                          plat->timing_index, timing)) {
 280                 debug("%s: Failed to decode display timing\n", __func__);
 281                 return -EINVAL;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int atmel_fb_lcd_bind(struct udevice *dev)
 288 {
 289         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 290
 291         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 292                         (1 << VIDEO_BPP16) / 8;
 293         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 294
 295         return 0;
 296 }
 297
 298 static const struct udevice_id atmel_fb_lcd_ids[] = {
 299         { .compatible = "atmel,at91sam9g45-lcdc" },
 300         { }
 301 };
 302
 303 U_BOOT_DRIVER(atmel_fb) = {
 304         .name   = "atmel_fb",
 305         .id     = UCLASS_VIDEO,
 306         .of_match = atmel_fb_lcd_ids,
 307         .bind   = atmel_fb_lcd_bind,
 308         .of_to_plat     = atmel_fb_of_to_plat,
 309         .probe  = atmel_fb_lcd_probe,
 310         .plat_auto      = sizeof(struct atmel_lcd_plat),
 311         .priv_auto      = sizeof(struct atmel_fb_priv),
 312 };
 313 #endif