drivers/video/atmel_lcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 LCD Controller
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_lcd.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <video.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/clk.h>
  16 #include <lcd.h>
  17 #include <bmp_layout.h>
  18 #include <atmel_lcdc.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifdef CONFIG_DM_VIDEO
  23 enum {
  24         /* Maximum LCD size we support */
  25         LCD_MAX_WIDTH           = 1366,
  26         LCD_MAX_HEIGHT          = 768,
  27         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  28 };
  29 #endif
  30
  31 struct atmel_fb_priv {
  32         struct display_timing timing;
  33 };
  34
  35 /* configurable parameters */
  36 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  37 #define ATMEL_LCDC_DMA_BURST_LEN        8
  38 #ifndef ATMEL_LCDC_GUARD_TIME
  39 #define ATMEL_LCDC_GUARD_TIME           1
  40 #endif
  41
  42 #if defined(CONFIG_AT91SAM9263)
  43 #define ATMEL_LCDC_FIFO_SIZE            2048
  44 #else
  45 #define ATMEL_LCDC_FIFO_SIZE            512
  46 #endif
  47
  48 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  49 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  50
  51 #ifndef CONFIG_DM_VIDEO
  52 ushort *configuration_get_cmap(void)
  53 {
  54         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  55 }
  56
  57 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  58 void fb_put_word(uchar **fb, uchar **from)
  59 {
  60         *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  61         *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  62         *from += 2;
  63 }
  64 #endif
  65
  66 #ifdef CONFIG_LCD_LOGO
  67 #include <bmp_logo.h>
  68 void lcd_logo_set_cmap(void)
  69 {
  70         int i;
  71         uint lut_entry;
  72         ushort colreg;
  73         uint *cmap = (uint *)configuration_get_cmap();
  74
  75         for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  76                 colreg = bmp_logo_palette[i];
  77 #ifdef CONFIG_ATMEL_LCD_BGR555
  78                 lut_entry = ((colreg & 0x000F) << 11) |
  79                                 ((colreg & 0x00F0) <<  2) |
  80                                 ((colreg & 0x0F00) >>  7);
  81 #else
  82                 lut_entry = ((colreg & 0x000F) << 1) |
  83                                 ((colreg & 0x00F0) << 3) |
  84                                 ((colreg & 0x0F00) << 4);
  85 #endif
  86                 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  87                 cmap++;
  88         }
  89 }
  90 #endif
  91
  92 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  93 {
  94 #if defined(CONFIG_ATMEL_LCD_BGR555)
  95         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  96                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  97 #else
  98         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  99                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
 100 #endif
 101 }
 102
 103 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 104 {
 105         int i;
 106
 107         for (i = 0; i < colors; ++i) {
 108                 struct bmp_color_table_entry cte = bmp->color_table[i];
 109                 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
 110         }
 111 }
 112 #endif
 113
 114 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 115                           bool tft, bool cont_pol_low, ulong lcdbase)
 116 {
 117         unsigned long value;
 118         void *reg = (void *)addr;
 119
 120         /* Turn off the LCD controller and the DMA controller */
 121         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 122                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 123
 124         /* Wait for the LCDC core to become idle */
 125         while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 126                 udelay(10);
 127
 128         lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 129
 130         /* Reset LCDC DMA */
 131         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 132
 133         /* ...set frame size and burst length = 8 words (?) */
 134         value = (timing->hactive.typ * timing->vactive.typ *
 135                  (1 << bpix)) / 32;
 136         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 137         lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 138
 139         /* Set pixel clock */
 140         value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
 141         if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 142                 value++;
 143         value = (value / 2) - 1;
 144
 145         if (!value) {
 146                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 147         } else
 148                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 149                             value << ATMEL_LCDC_CLKVAL_OFFSET);
 150
 151         /* Initialize control register 2 */
 152         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 153         if (tft)
 154                 value |= ATMEL_LCDC_DISTYPE_TFT;
 155
 156         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 157                 value |= ATMEL_LCDC_INVLINE_INVERTED;
 158         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 159                 value |= ATMEL_LCDC_INVFRAME_INVERTED;
 160         value |= bpix << 5;
 161         lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 162
 163         /* Vertical timing */
 164         value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
 165         value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
 166         value |= timing->vfront_porch.typ;
 167         /* Magic! (Datasheet says "Bit 31 must be written to 1") */
 168         value |= 1U << 31;
 169         lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 170
 171         /* Horizontal timing */
 172         value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
 173         value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
 174         value |= (timing->hback_porch.typ - 1);
 175         lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 176
 177         /* Display size */
 178         value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 179         value |= timing->vactive.typ - 1;
 180         lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 181
 182         /* FIFO Threshold: Use formula from data sheet */
 183         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 184         lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 185
 186         /* Toggle LCD_MODE every frame */
 187         lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 188
 189         /* Disable all interrupts */
 190         lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 191
 192         /* Set contrast */
 193         value = ATMEL_LCDC_PS_DIV8 |
 194                 ATMEL_LCDC_ENA_PWMENABLE;
 195         if (!cont_pol_low)
 196                 value |= ATMEL_LCDC_POL_POSITIVE;
 197         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
 198         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 199
 200         /* Set framebuffer DMA base address and pixel offset */
 201         lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 202
 203         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 204         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 205                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 206 }
 207
 208 #ifndef CONFIG_DM_VIDEO
 209 void lcd_ctrl_init(void *lcdbase)
 210 {
 211         struct display_timing timing;
 212
 213         timing.flags = 0;
 214         if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
 215                 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
 216         if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
 217                 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
 218         timing.pixelclock.typ = panel_info.vl_clk;
 219
 220         timing.hactive.typ = panel_info.vl_col;
 221         timing.hfront_porch.typ = panel_info.vl_right_margin;
 222         timing.hback_porch.typ = panel_info.vl_left_margin;
 223         timing.hsync_len.typ = panel_info.vl_hsync_len;
 224
 225         timing.vactive.typ = panel_info.vl_row;
 226         timing.vfront_porch.typ = panel_info.vl_clk;
 227         timing.vback_porch.typ = panel_info.vl_clk;
 228         timing.vsync_len.typ = panel_info.vl_clk;
 229
 230         atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
 231                       panel_info.vl_tft, panel_info.vl_cont_pol_low,
 232                       (ulong)lcdbase);
 233 }
 234
 235 ulong calc_fbsize(void)
 236 {
 237         return ((panel_info.vl_col * panel_info.vl_row *
 238                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 239 }
 240 #endif
 241
 242 #ifdef CONFIG_DM_VIDEO
 243 static int atmel_fb_lcd_probe(struct udevice *dev)
 244 {
 245         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 246         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 247         struct atmel_fb_priv *priv = dev_get_priv(dev);
 248         struct display_timing *timing = &priv->timing;
 249
 250         /*
 251          * For now some values are hard-coded. We could use the device tree
 252          * bindings in simple-framebuffer.txt to specify the format/bpp and
 253          * some Atmel-specific binding for tft and cont_pol_low.
 254          */
 255         atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
 256                       uc_plat->base);
 257         uc_priv->xsize = timing->hactive.typ;
 258         uc_priv->ysize = timing->vactive.typ;
 259         uc_priv->bpix = VIDEO_BPP16;
 260         video_set_flush_dcache(dev, true);
 261         debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
 262               uc_plat->size, uc_priv->xsize, uc_priv->ysize);
 263
 264         return 0;
 265 }
 266
 267 static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
 268 {
 269         struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
 270         struct atmel_fb_priv *priv = dev_get_priv(dev);
 271         struct display_timing *timing = &priv->timing;
 272         const void *blob = gd->fdt_blob;
 273
 274         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 275                                          plat->timing_index, timing)) {
 276                 debug("%s: Failed to decode display timing\n", __func__);
 277                 return -EINVAL;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int atmel_fb_lcd_bind(struct udevice *dev)
 284 {
 285         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 286
 287         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 288                         (1 << VIDEO_BPP16) / 8;
 289         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 290
 291         return 0;
 292 }
 293
 294 static const struct udevice_id atmel_fb_lcd_ids[] = {
 295         { .compatible = "atmel,at91sam9g45-lcdc" },
 296         { }
 297 };
 298
 299 U_BOOT_DRIVER(atmel_fb) = {
 300         .name   = "atmel_fb",
 301         .id     = UCLASS_VIDEO,
 302         .of_match = atmel_fb_lcd_ids,
 303         .bind   = atmel_fb_lcd_bind,
 304         .ofdata_to_platdata     = atmel_fb_ofdata_to_platdata,
 305         .probe  = atmel_fb_lcd_probe,
 306         .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
 307         .priv_auto_alloc_size   = sizeof(struct atmel_fb_priv),
 308 };
 309 #endif