drivers/video/atmel_lcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 LCD Controller
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_lcd.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <log.h>
  13 #include <part.h>
  14 #include <video.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/clk.h>
  19 #include <lcd.h>
  20 #include <bmp_layout.h>
  21 #include <atmel_lcdc.h>
  22 #include <linux/delay.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #ifdef CONFIG_DM_VIDEO
  27 enum {
  28         /* Maximum LCD size we support */
  29         LCD_MAX_WIDTH           = 1366,
  30         LCD_MAX_HEIGHT          = 768,
  31         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  32 };
  33 #endif
  34
  35 struct atmel_fb_priv {
  36         struct display_timing timing;
  37 };
  38
  39 /* configurable parameters */
  40 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  41 #define ATMEL_LCDC_DMA_BURST_LEN        8
  42 #ifndef ATMEL_LCDC_GUARD_TIME
  43 #define ATMEL_LCDC_GUARD_TIME           1
  44 #endif
  45
  46 #if defined(CONFIG_AT91SAM9263)
  47 #define ATMEL_LCDC_FIFO_SIZE            2048
  48 #else
  49 #define ATMEL_LCDC_FIFO_SIZE            512
  50 #endif
  51
  52 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  53 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  54
  55 #ifndef CONFIG_DM_VIDEO
  56 ushort *configuration_get_cmap(void)
  57 {
  58         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  59 }
  60
  61 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  62 void fb_put_word(uchar **fb, uchar **from)
  63 {
  64         *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  65         *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  66         *from += 2;
  67 }
  68 #endif
  69
  70 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  71 {
  72 #if defined(CONFIG_ATMEL_LCD_BGR555)
  73         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  74                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  75 #else
  76         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  77                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  78 #endif
  79 }
  80
  81 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
  82 {
  83         int i;
  84
  85         for (i = 0; i < colors; ++i) {
  86                 struct bmp_color_table_entry cte = bmp->color_table[i];
  87                 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
  88         }
  89 }
  90 #endif
  91
  92 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
  93                           bool tft, bool cont_pol_low, ulong lcdbase)
  94 {
  95         unsigned long value;
  96         void *reg = (void *)addr;
  97
  98         /* Turn off the LCD controller and the DMA controller */
  99         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 100                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 101
 102         /* Wait for the LCDC core to become idle */
 103         while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 104                 udelay(10);
 105
 106         lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 107
 108         /* Reset LCDC DMA */
 109         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 110
 111         /* ...set frame size and burst length = 8 words (?) */
 112         value = (timing->hactive.typ * timing->vactive.typ *
 113                  (1 << bpix)) / 32;
 114         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 115         lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 116
 117         /* Set pixel clock */
 118         value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
 119         if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 120                 value++;
 121         value = (value / 2) - 1;
 122
 123         if (!value) {
 124                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 125         } else
 126                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 127                             value << ATMEL_LCDC_CLKVAL_OFFSET);
 128
 129         /* Initialize control register 2 */
 130         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 131         if (tft)
 132                 value |= ATMEL_LCDC_DISTYPE_TFT;
 133
 134         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 135                 value |= ATMEL_LCDC_INVLINE_INVERTED;
 136         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 137                 value |= ATMEL_LCDC_INVFRAME_INVERTED;
 138         value |= bpix << 5;
 139         lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 140
 141         /* Vertical timing */
 142         value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
 143         value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
 144         value |= timing->vfront_porch.typ;
 145         /* Magic! (Datasheet says "Bit 31 must be written to 1") */
 146         value |= 1U << 31;
 147         lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 148
 149         /* Horizontal timing */
 150         value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
 151         value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
 152         value |= (timing->hback_porch.typ - 1);
 153         lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 154
 155         /* Display size */
 156         value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 157         value |= timing->vactive.typ - 1;
 158         lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 159
 160         /* FIFO Threshold: Use formula from data sheet */
 161         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 162         lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 163
 164         /* Toggle LCD_MODE every frame */
 165         lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 166
 167         /* Disable all interrupts */
 168         lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 169
 170         /* Set contrast */
 171         value = ATMEL_LCDC_PS_DIV8 |
 172                 ATMEL_LCDC_ENA_PWMENABLE;
 173         if (!cont_pol_low)
 174                 value |= ATMEL_LCDC_POL_POSITIVE;
 175         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
 176         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 177
 178         /* Set framebuffer DMA base address and pixel offset */
 179         lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 180
 181         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 182         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 183                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 184 }
 185
 186 #ifndef CONFIG_DM_VIDEO
 187 void lcd_ctrl_init(void *lcdbase)
 188 {
 189         struct display_timing timing;
 190
 191         timing.flags = 0;
 192         if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
 193                 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
 194         if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
 195                 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
 196         timing.pixelclock.typ = panel_info.vl_clk;
 197
 198         timing.hactive.typ = panel_info.vl_col;
 199         timing.hfront_porch.typ = panel_info.vl_right_margin;
 200         timing.hback_porch.typ = panel_info.vl_left_margin;
 201         timing.hsync_len.typ = panel_info.vl_hsync_len;
 202
 203         timing.vactive.typ = panel_info.vl_row;
 204         timing.vfront_porch.typ = panel_info.vl_clk;
 205         timing.vback_porch.typ = panel_info.vl_clk;
 206         timing.vsync_len.typ = panel_info.vl_clk;
 207
 208         atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
 209                       panel_info.vl_tft, panel_info.vl_cont_pol_low,
 210                       (ulong)lcdbase);
 211 }
 212
 213 ulong calc_fbsize(void)
 214 {
 215         return ((panel_info.vl_col * panel_info.vl_row *
 216                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 217 }
 218 #endif
 219
 220 #ifdef CONFIG_DM_VIDEO
 221 static int atmel_fb_lcd_probe(struct udevice *dev)
 222 {
 223         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 224         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 225         struct atmel_fb_priv *priv = dev_get_priv(dev);
 226         struct display_timing *timing = &priv->timing;
 227
 228         /*
 229          * For now some values are hard-coded. We could use the device tree
 230          * bindings in simple-framebuffer.txt to specify the format/bpp and
 231          * some Atmel-specific binding for tft and cont_pol_low.
 232          */
 233         atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
 234                       uc_plat->base);
 235         uc_priv->xsize = timing->hactive.typ;
 236         uc_priv->ysize = timing->vactive.typ;
 237         uc_priv->bpix = VIDEO_BPP16;
 238         video_set_flush_dcache(dev, true);
 239         debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
 240               uc_plat->size, uc_priv->xsize, uc_priv->ysize);
 241
 242         return 0;
 243 }
 244
 245 static int atmel_fb_of_to_plat(struct udevice *dev)
 246 {
 247         struct atmel_lcd_plat *plat = dev_get_plat(dev);
 248         struct atmel_fb_priv *priv = dev_get_priv(dev);
 249         struct display_timing *timing = &priv->timing;
 250         const void *blob = gd->fdt_blob;
 251
 252         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 253                                          plat->timing_index, timing)) {
 254                 debug("%s: Failed to decode display timing\n", __func__);
 255                 return -EINVAL;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int atmel_fb_lcd_bind(struct udevice *dev)
 262 {
 263         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 264
 265         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 266                         (1 << VIDEO_BPP16) / 8;
 267         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 268
 269         return 0;
 270 }
 271
 272 static const struct udevice_id atmel_fb_lcd_ids[] = {
 273         { .compatible = "atmel,at91sam9g45-lcdc" },
 274         { }
 275 };
 276
 277 U_BOOT_DRIVER(atmel_fb) = {
 278         .name   = "atmel_fb",
 279         .id     = UCLASS_VIDEO,
 280         .of_match = atmel_fb_lcd_ids,
 281         .bind   = atmel_fb_lcd_bind,
 282         .of_to_plat     = atmel_fb_of_to_plat,
 283         .probe  = atmel_fb_lcd_probe,
 284         .plat_auto      = sizeof(struct atmel_lcd_plat),
 285         .priv_auto      = sizeof(struct atmel_fb_priv),
 286 };
 287 #endif