drivers/video/atmel_hlcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   4  *
   5  * Copyright (C) 2012 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <part.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/clk.h>
  17 #include <clk.h>
  18 #include <dm.h>
  19 #include <fdtdec.h>
  20 #include <lcd.h>
  21 #include <video.h>
  22 #include <wait_bit.h>
  23 #include <atmel_hlcdc.h>
  24 #include <linux/bug.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifndef CONFIG_DM_VIDEO
  29
  30 /* configurable parameters */
  31 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  32 #define ATMEL_LCDC_DMA_BURST_LEN        8
  33 #ifndef ATMEL_LCDC_GUARD_TIME
  34 #define ATMEL_LCDC_GUARD_TIME           1
  35 #endif
  36
  37 #define ATMEL_LCDC_FIFO_SIZE            512
  38
  39 /*
  40  * the CLUT register map as following
  41  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  42  */
  43 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  44 {
  45         writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  46                ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  47                | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  48                | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  49 }
  50
  51 void lcd_ctrl_init(void *lcdbase)
  52 {
  53         unsigned long value;
  54         struct lcd_dma_desc *desc;
  55         struct atmel_hlcd_regs *regs;
  56         int ret;
  57
  58         if (!has_lcdc())
  59                 return;     /* No lcdc */
  60
  61         regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  62
  63         /* Disable DISP signal */
  64         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  65         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  66                                 false, 1000, false);
  67         if (ret)
  68                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  69         /* Disable synchronization */
  70         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  71         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  72                                 false, 1000, false);
  73         if (ret)
  74                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  75         /* Disable pixel clock */
  76         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  77         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  78                                 false, 1000, false);
  79         if (ret)
  80                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  81         /* Disable PWM */
  82         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  83         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  84                                 false, 1000, false);
  85         if (ret)
  86                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  87
  88         /* Set pixel clock */
  89         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  90         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  91                 value++;
  92
  93         if (value < 1) {
  94                 /* Using system clock as pixel clock */
  95                 writel(LCDC_LCDCFG0_CLKDIV(0)
  96                         | LCDC_LCDCFG0_CGDISHCR
  97                         | LCDC_LCDCFG0_CGDISHEO
  98                         | LCDC_LCDCFG0_CGDISOVR1
  99                         | LCDC_LCDCFG0_CGDISBASE
 100                         | panel_info.vl_clk_pol
 101                         | LCDC_LCDCFG0_CLKSEL,
 102                         &regs->lcdc_lcdcfg0);
 103
 104         } else {
 105                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 106                         | LCDC_LCDCFG0_CGDISHCR
 107                         | LCDC_LCDCFG0_CGDISHEO
 108                         | LCDC_LCDCFG0_CGDISOVR1
 109                         | LCDC_LCDCFG0_CGDISBASE
 110                         | panel_info.vl_clk_pol,
 111                         &regs->lcdc_lcdcfg0);
 112         }
 113
 114         /* Initialize control register 5 */
 115         value = 0;
 116
 117         value |= panel_info.vl_sync;
 118
 119 #ifndef LCD_OUTPUT_BPP
 120         /* Output is 24bpp */
 121         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 122 #else
 123         switch (LCD_OUTPUT_BPP) {
 124         case 12:
 125                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 126                 break;
 127         case 16:
 128                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 129                 break;
 130         case 18:
 131                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 132                 break;
 133         case 24:
 134                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 135                 break;
 136         default:
 137                 BUG();
 138                 break;
 139         }
 140 #endif
 141
 142         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 143         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 144         writel(value, &regs->lcdc_lcdcfg5);
 145
 146         /* Vertical & Horizontal Timing */
 147         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 148         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 149         writel(value, &regs->lcdc_lcdcfg1);
 150
 151         value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
 152         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 153         writel(value, &regs->lcdc_lcdcfg2);
 154
 155         value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
 156         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 157         writel(value, &regs->lcdc_lcdcfg3);
 158
 159         /* Display size */
 160         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 161         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 162         writel(value, &regs->lcdc_lcdcfg4);
 163
 164         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 165                &regs->lcdc_basecfg0);
 166
 167         switch (NBITS(panel_info.vl_bpix)) {
 168         case 16:
 169                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 170                        &regs->lcdc_basecfg1);
 171                 break;
 172         case 32:
 173                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 174                        &regs->lcdc_basecfg1);
 175                 break;
 176         default:
 177                 BUG();
 178                 break;
 179         }
 180
 181         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 182         writel(0, &regs->lcdc_basecfg3);
 183         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 184
 185         /* Disable all interrupts */
 186         writel(~0UL, &regs->lcdc_lcdidr);
 187         writel(~0UL, &regs->lcdc_baseidr);
 188
 189         /* Setup the DMA descriptor, this descriptor will loop to itself */
 190         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 191
 192         desc->address = (u32)lcdbase;
 193         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 194         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 195                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 196         desc->next = (u32)desc;
 197
 198         /* Flush the DMA descriptor if we enabled dcache */
 199         flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
 200
 201         writel(desc->address, &regs->lcdc_baseaddr);
 202         writel(desc->control, &regs->lcdc_basectrl);
 203         writel(desc->next, &regs->lcdc_basenext);
 204         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 205                &regs->lcdc_basecher);
 206
 207         /* Enable LCD */
 208         value = readl(&regs->lcdc_lcden);
 209         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 210         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 211                                 true, 1000, false);
 212         if (ret)
 213                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 214         value = readl(&regs->lcdc_lcden);
 215         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 216         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 217                                 true, 1000, false);
 218         if (ret)
 219                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 220         value = readl(&regs->lcdc_lcden);
 221         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 222         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 223                                 true, 1000, false);
 224         if (ret)
 225                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 226         value = readl(&regs->lcdc_lcden);
 227         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 228         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 229                                 true, 1000, false);
 230         if (ret)
 231                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 232
 233         /* Enable flushing if we enabled dcache */
 234         lcd_set_flush_dcache(1);
 235 }
 236
 237 #else
 238
 239 enum {
 240         LCD_MAX_WIDTH           = 1024,
 241         LCD_MAX_HEIGHT          = 768,
 242         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
 243 };
 244
 245 struct atmel_hlcdc_priv {
 246         struct atmel_hlcd_regs *regs;
 247         struct display_timing timing;
 248         unsigned int vl_bpix;
 249         unsigned int output_mode;
 250         unsigned int guard_time;
 251         ulong clk_rate;
 252 };
 253
 254 static int at91_hlcdc_enable_clk(struct udevice *dev)
 255 {
 256         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 257         struct clk clk;
 258         ulong clk_rate;
 259         int ret;
 260
 261         ret = clk_get_by_index(dev, 0, &clk);
 262         if (ret)
 263                 return -EINVAL;
 264
 265         ret = clk_enable(&clk);
 266         if (ret)
 267                 return ret;
 268
 269         clk_rate = clk_get_rate(&clk);
 270         if (!clk_rate) {
 271                 clk_disable(&clk);
 272                 return -ENODEV;
 273         }
 274
 275         priv->clk_rate = clk_rate;
 276
 277         clk_free(&clk);
 278
 279         return 0;
 280 }
 281
 282 static void atmel_hlcdc_init(struct udevice *dev)
 283 {
 284         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 285         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 286         struct atmel_hlcd_regs *regs = priv->regs;
 287         struct display_timing *timing = &priv->timing;
 288         struct lcd_dma_desc *desc;
 289         unsigned long value, vl_clk_pol;
 290         int ret;
 291
 292         /* Disable DISP signal */
 293         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
 294         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 295                                 false, 1000, false);
 296         if (ret)
 297                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 298         /* Disable synchronization */
 299         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
 300         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 301                                 false, 1000, false);
 302         if (ret)
 303                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 304         /* Disable pixel clock */
 305         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
 306         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 307                                 false, 1000, false);
 308         if (ret)
 309                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 310         /* Disable PWM */
 311         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
 312         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 313                                 false, 1000, false);
 314         if (ret)
 315                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 316
 317         /* Set pixel clock */
 318         value = priv->clk_rate / timing->pixelclock.typ;
 319         if (priv->clk_rate % timing->pixelclock.typ)
 320                 value++;
 321
 322         vl_clk_pol = 0;
 323         if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 324                 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
 325
 326         if (value < 1) {
 327                 /* Using system clock as pixel clock */
 328                 writel(LCDC_LCDCFG0_CLKDIV(0)
 329                         | LCDC_LCDCFG0_CGDISHCR
 330                         | LCDC_LCDCFG0_CGDISHEO
 331                         | LCDC_LCDCFG0_CGDISOVR1
 332                         | LCDC_LCDCFG0_CGDISBASE
 333                         | vl_clk_pol
 334                         | LCDC_LCDCFG0_CLKSEL,
 335                         &regs->lcdc_lcdcfg0);
 336
 337         } else {
 338                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 339                         | LCDC_LCDCFG0_CGDISHCR
 340                         | LCDC_LCDCFG0_CGDISHEO
 341                         | LCDC_LCDCFG0_CGDISOVR1
 342                         | LCDC_LCDCFG0_CGDISBASE
 343                         | vl_clk_pol,
 344                         &regs->lcdc_lcdcfg0);
 345         }
 346
 347         /* Initialize control register 5 */
 348         value = 0;
 349
 350         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 351                 value |= LCDC_LCDCFG5_HSPOL;
 352         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 353                 value |= LCDC_LCDCFG5_VSPOL;
 354
 355         switch (priv->output_mode) {
 356         case 12:
 357                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 358                 break;
 359         case 16:
 360                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 361                 break;
 362         case 18:
 363                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 364                 break;
 365         case 24:
 366                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 367                 break;
 368         default:
 369                 BUG();
 370                 break;
 371         }
 372
 373         value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
 374         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 375         writel(value, &regs->lcdc_lcdcfg5);
 376
 377         /* Vertical & Horizontal Timing */
 378         value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
 379         value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
 380         writel(value, &regs->lcdc_lcdcfg1);
 381
 382         value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
 383         value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
 384         writel(value, &regs->lcdc_lcdcfg2);
 385
 386         value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
 387         value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
 388         writel(value, &regs->lcdc_lcdcfg3);
 389
 390         /* Display size */
 391         value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
 392         value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
 393         writel(value, &regs->lcdc_lcdcfg4);
 394
 395         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 396                &regs->lcdc_basecfg0);
 397
 398         switch (VNBITS(priv->vl_bpix)) {
 399         case 16:
 400                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 401                        &regs->lcdc_basecfg1);
 402                 break;
 403         case 32:
 404                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 405                        &regs->lcdc_basecfg1);
 406                 break;
 407         default:
 408                 BUG();
 409                 break;
 410         }
 411
 412         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 413         writel(0, &regs->lcdc_basecfg3);
 414         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 415
 416         /* Disable all interrupts */
 417         writel(~0UL, &regs->lcdc_lcdidr);
 418         writel(~0UL, &regs->lcdc_baseidr);
 419
 420         /* Setup the DMA descriptor, this descriptor will loop to itself */
 421         desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
 422         if (!desc)
 423                 return;
 424
 425         desc->address = (u32)uc_plat->base;
 426
 427         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 428         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 429                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 430         desc->next = (u32)desc;
 431
 432         /* Flush the DMA descriptor if we enabled dcache */
 433         flush_dcache_range((u32)desc,
 434                            ALIGN(((u32)desc + sizeof(*desc)),
 435                            CONFIG_SYS_CACHELINE_SIZE));
 436
 437         writel(desc->address, &regs->lcdc_baseaddr);
 438         writel(desc->control, &regs->lcdc_basectrl);
 439         writel(desc->next, &regs->lcdc_basenext);
 440         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 441                &regs->lcdc_basecher);
 442
 443         /* Enable LCD */
 444         value = readl(&regs->lcdc_lcden);
 445         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 446         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 447                                 true, 1000, false);
 448         if (ret)
 449                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 450         value = readl(&regs->lcdc_lcden);
 451         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 452         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 453                                 true, 1000, false);
 454         if (ret)
 455                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 456         value = readl(&regs->lcdc_lcden);
 457         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 458         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 459                                 true, 1000, false);
 460         if (ret)
 461                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 462         value = readl(&regs->lcdc_lcden);
 463         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 464         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 465                                 true, 1000, false);
 466         if (ret)
 467                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 468 }
 469
 470 static int atmel_hlcdc_probe(struct udevice *dev)
 471 {
 472         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 473         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 474         int ret;
 475
 476         ret = at91_hlcdc_enable_clk(dev);
 477         if (ret)
 478                 return ret;
 479
 480         atmel_hlcdc_init(dev);
 481
 482         uc_priv->xsize = priv->timing.hactive.typ;
 483         uc_priv->ysize = priv->timing.vactive.typ;
 484         uc_priv->bpix = priv->vl_bpix;
 485
 486         /* Enable flushing if we enabled dcache */
 487         video_set_flush_dcache(dev, true);
 488
 489         return 0;
 490 }
 491
 492 static int atmel_hlcdc_of_to_plat(struct udevice *dev)
 493 {
 494         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 495         const void *blob = gd->fdt_blob;
 496         int node = dev_of_offset(dev);
 497
 498         priv->regs = dev_read_addr_ptr(dev);
 499         if (!priv->regs) {
 500                 debug("%s: No display controller address\n", __func__);
 501                 return -EINVAL;
 502         }
 503
 504         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 505                                          0, &priv->timing)) {
 506                 debug("%s: Failed to decode display timing\n", __func__);
 507                 return -EINVAL;
 508         }
 509
 510         if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
 511                 priv->timing.hactive.typ = LCD_MAX_WIDTH;
 512
 513         if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
 514                 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
 515
 516         priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
 517         if (!priv->vl_bpix) {
 518                 debug("%s: Failed to get bits per pixel\n", __func__);
 519                 return -EINVAL;
 520         }
 521
 522         priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
 523         priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
 524
 525         return 0;
 526 }
 527
 528 static int atmel_hlcdc_bind(struct udevice *dev)
 529 {
 530         struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 531
 532         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 533                                 (1 << LCD_MAX_LOG2_BPP) / 8;
 534
 535         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 536
 537         return 0;
 538 }
 539
 540 static const struct udevice_id atmel_hlcdc_ids[] = {
 541         { .compatible = "atmel,sama5d2-hlcdc" },
 542         { .compatible = "atmel,at91sam9x5-hlcdc" },
 543         { }
 544 };
 545
 546 U_BOOT_DRIVER(atmel_hlcdfb) = {
 547         .name   = "atmel_hlcdfb",
 548         .id     = UCLASS_VIDEO,
 549         .of_match = atmel_hlcdc_ids,
 550         .bind   = atmel_hlcdc_bind,
 551         .probe  = atmel_hlcdc_probe,
 552         .of_to_plat = atmel_hlcdc_of_to_plat,
 553         .priv_auto      = sizeof(struct atmel_hlcdc_priv),
 554 };
 555
 556 #endif