1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AT91/AT32 MULTI LAYER LCD Controller
5 * Copyright (C) 2012 Atmel Corporation
13 #include <asm/global_data.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
23 #include <atmel_hlcdc.h>
24 #include <linux/bug.h>
26 #if defined(CONFIG_LCD_LOGO)
30 DECLARE_GLOBAL_DATA_PTR;
32 #ifndef CONFIG_DM_VIDEO
34 /* configurable parameters */
35 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
36 #define ATMEL_LCDC_DMA_BURST_LEN 8
37 #ifndef ATMEL_LCDC_GUARD_TIME
38 #define ATMEL_LCDC_GUARD_TIME 1
41 #define ATMEL_LCDC_FIFO_SIZE 512
44 * the CLUT register map as following
45 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
47 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
49 writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
50 ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
51 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
52 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
55 ushort *configuration_get_cmap(void)
57 #if defined(CONFIG_LCD_LOGO)
58 return bmp_logo_palette;
64 void lcd_ctrl_init(void *lcdbase)
67 struct lcd_dma_desc *desc;
68 struct atmel_hlcd_regs *regs;
74 regs = (struct atmel_hlcd_regs *)panel_info.mmio;
76 /* Disable DISP signal */
77 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
78 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
81 printf("%s: %d: Timeout!\n", __func__, __LINE__);
82 /* Disable synchronization */
83 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
84 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
87 printf("%s: %d: Timeout!\n", __func__, __LINE__);
88 /* Disable pixel clock */
89 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
90 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
93 printf("%s: %d: Timeout!\n", __func__, __LINE__);
95 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
96 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
99 printf("%s: %d: Timeout!\n", __func__, __LINE__);
101 /* Set pixel clock */
102 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
103 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
107 /* Using system clock as pixel clock */
108 writel(LCDC_LCDCFG0_CLKDIV(0)
109 | LCDC_LCDCFG0_CGDISHCR
110 | LCDC_LCDCFG0_CGDISHEO
111 | LCDC_LCDCFG0_CGDISOVR1
112 | LCDC_LCDCFG0_CGDISBASE
113 | panel_info.vl_clk_pol
114 | LCDC_LCDCFG0_CLKSEL,
115 ®s->lcdc_lcdcfg0);
118 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
119 | LCDC_LCDCFG0_CGDISHCR
120 | LCDC_LCDCFG0_CGDISHEO
121 | LCDC_LCDCFG0_CGDISOVR1
122 | LCDC_LCDCFG0_CGDISBASE
123 | panel_info.vl_clk_pol,
124 ®s->lcdc_lcdcfg0);
127 /* Initialize control register 5 */
130 value |= panel_info.vl_sync;
132 #ifndef LCD_OUTPUT_BPP
133 /* Output is 24bpp */
134 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
136 switch (LCD_OUTPUT_BPP) {
138 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
141 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
144 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
147 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
155 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
156 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
157 writel(value, ®s->lcdc_lcdcfg5);
159 /* Vertical & Horizontal Timing */
160 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
161 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
162 writel(value, ®s->lcdc_lcdcfg1);
164 value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
165 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
166 writel(value, ®s->lcdc_lcdcfg2);
168 value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
169 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
170 writel(value, ®s->lcdc_lcdcfg3);
173 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
174 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
175 writel(value, ®s->lcdc_lcdcfg4);
177 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
178 ®s->lcdc_basecfg0);
180 switch (NBITS(panel_info.vl_bpix)) {
182 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
183 ®s->lcdc_basecfg1);
186 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
187 ®s->lcdc_basecfg1);
194 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
195 writel(0, ®s->lcdc_basecfg3);
196 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
198 /* Disable all interrupts */
199 writel(~0UL, ®s->lcdc_lcdidr);
200 writel(~0UL, ®s->lcdc_baseidr);
202 /* Setup the DMA descriptor, this descriptor will loop to itself */
203 desc = (struct lcd_dma_desc *)(lcdbase - 16);
205 desc->address = (u32)lcdbase;
206 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
207 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
208 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
209 desc->next = (u32)desc;
211 /* Flush the DMA descriptor if we enabled dcache */
212 flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
214 writel(desc->address, ®s->lcdc_baseaddr);
215 writel(desc->control, ®s->lcdc_basectrl);
216 writel(desc->next, ®s->lcdc_basenext);
217 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
218 ®s->lcdc_basecher);
221 value = readl(®s->lcdc_lcden);
222 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
223 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
226 printf("%s: %d: Timeout!\n", __func__, __LINE__);
227 value = readl(®s->lcdc_lcden);
228 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
229 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
232 printf("%s: %d: Timeout!\n", __func__, __LINE__);
233 value = readl(®s->lcdc_lcden);
234 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
235 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
238 printf("%s: %d: Timeout!\n", __func__, __LINE__);
239 value = readl(®s->lcdc_lcden);
240 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
241 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
244 printf("%s: %d: Timeout!\n", __func__, __LINE__);
246 /* Enable flushing if we enabled dcache */
247 lcd_set_flush_dcache(1);
253 LCD_MAX_WIDTH = 1024,
254 LCD_MAX_HEIGHT = 768,
255 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
258 struct atmel_hlcdc_priv {
259 struct atmel_hlcd_regs *regs;
260 struct display_timing timing;
261 unsigned int vl_bpix;
262 unsigned int output_mode;
263 unsigned int guard_time;
267 static int at91_hlcdc_enable_clk(struct udevice *dev)
269 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
274 ret = clk_get_by_index(dev, 0, &clk);
278 ret = clk_enable(&clk);
282 clk_rate = clk_get_rate(&clk);
288 priv->clk_rate = clk_rate;
295 static void atmel_hlcdc_init(struct udevice *dev)
297 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
298 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
299 struct atmel_hlcd_regs *regs = priv->regs;
300 struct display_timing *timing = &priv->timing;
301 struct lcd_dma_desc *desc;
302 unsigned long value, vl_clk_pol;
305 /* Disable DISP signal */
306 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
307 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
310 printf("%s: %d: Timeout!\n", __func__, __LINE__);
311 /* Disable synchronization */
312 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
313 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
316 printf("%s: %d: Timeout!\n", __func__, __LINE__);
317 /* Disable pixel clock */
318 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
319 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
322 printf("%s: %d: Timeout!\n", __func__, __LINE__);
324 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
325 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
328 printf("%s: %d: Timeout!\n", __func__, __LINE__);
330 /* Set pixel clock */
331 value = priv->clk_rate / timing->pixelclock.typ;
332 if (priv->clk_rate % timing->pixelclock.typ)
336 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
337 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
340 /* Using system clock as pixel clock */
341 writel(LCDC_LCDCFG0_CLKDIV(0)
342 | LCDC_LCDCFG0_CGDISHCR
343 | LCDC_LCDCFG0_CGDISHEO
344 | LCDC_LCDCFG0_CGDISOVR1
345 | LCDC_LCDCFG0_CGDISBASE
347 | LCDC_LCDCFG0_CLKSEL,
348 ®s->lcdc_lcdcfg0);
351 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
352 | LCDC_LCDCFG0_CGDISHCR
353 | LCDC_LCDCFG0_CGDISHEO
354 | LCDC_LCDCFG0_CGDISOVR1
355 | LCDC_LCDCFG0_CGDISBASE
357 ®s->lcdc_lcdcfg0);
360 /* Initialize control register 5 */
363 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
364 value |= LCDC_LCDCFG5_HSPOL;
365 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
366 value |= LCDC_LCDCFG5_VSPOL;
368 switch (priv->output_mode) {
370 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
373 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
376 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
379 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
386 value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
387 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
388 writel(value, ®s->lcdc_lcdcfg5);
390 /* Vertical & Horizontal Timing */
391 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
392 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
393 writel(value, ®s->lcdc_lcdcfg1);
395 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
396 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
397 writel(value, ®s->lcdc_lcdcfg2);
399 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
400 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
401 writel(value, ®s->lcdc_lcdcfg3);
404 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
405 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
406 writel(value, ®s->lcdc_lcdcfg4);
408 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
409 ®s->lcdc_basecfg0);
411 switch (VNBITS(priv->vl_bpix)) {
413 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
414 ®s->lcdc_basecfg1);
417 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
418 ®s->lcdc_basecfg1);
425 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
426 writel(0, ®s->lcdc_basecfg3);
427 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
429 /* Disable all interrupts */
430 writel(~0UL, ®s->lcdc_lcdidr);
431 writel(~0UL, ®s->lcdc_baseidr);
433 /* Setup the DMA descriptor, this descriptor will loop to itself */
434 desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
438 desc->address = (u32)uc_plat->base;
440 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
441 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
442 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
443 desc->next = (u32)desc;
445 /* Flush the DMA descriptor if we enabled dcache */
446 flush_dcache_range((u32)desc,
447 ALIGN(((u32)desc + sizeof(*desc)),
448 CONFIG_SYS_CACHELINE_SIZE));
450 writel(desc->address, ®s->lcdc_baseaddr);
451 writel(desc->control, ®s->lcdc_basectrl);
452 writel(desc->next, ®s->lcdc_basenext);
453 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
454 ®s->lcdc_basecher);
457 value = readl(®s->lcdc_lcden);
458 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
459 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
462 printf("%s: %d: Timeout!\n", __func__, __LINE__);
463 value = readl(®s->lcdc_lcden);
464 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
465 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
468 printf("%s: %d: Timeout!\n", __func__, __LINE__);
469 value = readl(®s->lcdc_lcden);
470 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
471 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
474 printf("%s: %d: Timeout!\n", __func__, __LINE__);
475 value = readl(®s->lcdc_lcden);
476 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
477 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
480 printf("%s: %d: Timeout!\n", __func__, __LINE__);
483 static int atmel_hlcdc_probe(struct udevice *dev)
485 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
486 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
489 ret = at91_hlcdc_enable_clk(dev);
493 atmel_hlcdc_init(dev);
495 uc_priv->xsize = priv->timing.hactive.typ;
496 uc_priv->ysize = priv->timing.vactive.typ;
497 uc_priv->bpix = priv->vl_bpix;
499 /* Enable flushing if we enabled dcache */
500 video_set_flush_dcache(dev, true);
505 static int atmel_hlcdc_of_to_plat(struct udevice *dev)
507 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
508 const void *blob = gd->fdt_blob;
509 int node = dev_of_offset(dev);
511 priv->regs = dev_read_addr_ptr(dev);
513 debug("%s: No display controller address\n", __func__);
517 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
519 debug("%s: Failed to decode display timing\n", __func__);
523 if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
524 priv->timing.hactive.typ = LCD_MAX_WIDTH;
526 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
527 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
529 priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
530 if (!priv->vl_bpix) {
531 debug("%s: Failed to get bits per pixel\n", __func__);
535 priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
536 priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
541 static int atmel_hlcdc_bind(struct udevice *dev)
543 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
545 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
546 (1 << LCD_MAX_LOG2_BPP) / 8;
548 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
553 static const struct udevice_id atmel_hlcdc_ids[] = {
554 { .compatible = "atmel,sama5d2-hlcdc" },
555 { .compatible = "atmel,at91sam9x5-hlcdc" },
559 U_BOOT_DRIVER(atmel_hlcdfb) = {
560 .name = "atmel_hlcdfb",
562 .of_match = atmel_hlcdc_ids,
563 .bind = atmel_hlcdc_bind,
564 .probe = atmel_hlcdc_probe,
565 .of_to_plat = atmel_hlcdc_of_to_plat,
566 .priv_auto = sizeof(struct atmel_hlcdc_priv),