1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AT91/AT32 MULTI LAYER LCD Controller
5 * Copyright (C) 2012 Atmel Corporation
13 #include <asm/global_data.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
23 #include <atmel_hlcdc.h>
24 #include <linux/bug.h>
26 DECLARE_GLOBAL_DATA_PTR;
31 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
34 struct atmel_hlcdc_priv {
35 struct atmel_hlcd_regs *regs;
36 struct display_timing timing;
38 unsigned int output_mode;
39 unsigned int guard_time;
43 static int at91_hlcdc_enable_clk(struct udevice *dev)
45 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
50 ret = clk_get_by_index(dev, 0, &clk);
54 ret = clk_enable(&clk);
58 clk_rate = clk_get_rate(&clk);
64 priv->clk_rate = clk_rate;
71 static void atmel_hlcdc_init(struct udevice *dev)
73 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
74 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
75 struct atmel_hlcd_regs *regs = priv->regs;
76 struct display_timing *timing = &priv->timing;
77 struct lcd_dma_desc *desc;
78 unsigned long value, vl_clk_pol;
81 /* Disable DISP signal */
82 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
83 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
86 printf("%s: %d: Timeout!\n", __func__, __LINE__);
87 /* Disable synchronization */
88 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
89 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
92 printf("%s: %d: Timeout!\n", __func__, __LINE__);
93 /* Disable pixel clock */
94 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
95 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
98 printf("%s: %d: Timeout!\n", __func__, __LINE__);
100 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
101 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
104 printf("%s: %d: Timeout!\n", __func__, __LINE__);
106 /* Set pixel clock */
107 value = priv->clk_rate / timing->pixelclock.typ;
108 if (priv->clk_rate % timing->pixelclock.typ)
112 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
113 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
116 /* Using system clock as pixel clock */
117 writel(LCDC_LCDCFG0_CLKDIV(0)
118 | LCDC_LCDCFG0_CGDISHCR
119 | LCDC_LCDCFG0_CGDISHEO
120 | LCDC_LCDCFG0_CGDISOVR1
121 | LCDC_LCDCFG0_CGDISBASE
123 | LCDC_LCDCFG0_CLKSEL,
124 ®s->lcdc_lcdcfg0);
127 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
128 | LCDC_LCDCFG0_CGDISHCR
129 | LCDC_LCDCFG0_CGDISHEO
130 | LCDC_LCDCFG0_CGDISOVR1
131 | LCDC_LCDCFG0_CGDISBASE
133 ®s->lcdc_lcdcfg0);
136 /* Initialize control register 5 */
139 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
140 value |= LCDC_LCDCFG5_HSPOL;
141 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
142 value |= LCDC_LCDCFG5_VSPOL;
144 switch (priv->output_mode) {
146 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
149 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
152 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
155 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
162 value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
163 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
164 writel(value, ®s->lcdc_lcdcfg5);
166 /* Vertical & Horizontal Timing */
167 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
168 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
169 writel(value, ®s->lcdc_lcdcfg1);
171 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
172 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
173 writel(value, ®s->lcdc_lcdcfg2);
175 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
176 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
177 writel(value, ®s->lcdc_lcdcfg3);
180 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
181 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
182 writel(value, ®s->lcdc_lcdcfg4);
184 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
185 ®s->lcdc_basecfg0);
187 switch (VNBITS(priv->vl_bpix)) {
189 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
190 ®s->lcdc_basecfg1);
193 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
194 ®s->lcdc_basecfg1);
201 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
202 writel(0, ®s->lcdc_basecfg3);
203 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
205 /* Disable all interrupts */
206 writel(~0UL, ®s->lcdc_lcdidr);
207 writel(~0UL, ®s->lcdc_baseidr);
209 /* Setup the DMA descriptor, this descriptor will loop to itself */
210 desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
214 desc->address = (u32)uc_plat->base;
216 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
217 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
218 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
219 desc->next = (u32)desc;
221 /* Flush the DMA descriptor if we enabled dcache */
222 flush_dcache_range((u32)desc,
223 ALIGN(((u32)desc + sizeof(*desc)),
224 CONFIG_SYS_CACHELINE_SIZE));
226 writel(desc->address, ®s->lcdc_baseaddr);
227 writel(desc->control, ®s->lcdc_basectrl);
228 writel(desc->next, ®s->lcdc_basenext);
229 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
230 ®s->lcdc_basecher);
233 value = readl(®s->lcdc_lcden);
234 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
235 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
238 printf("%s: %d: Timeout!\n", __func__, __LINE__);
239 value = readl(®s->lcdc_lcden);
240 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
241 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
244 printf("%s: %d: Timeout!\n", __func__, __LINE__);
245 value = readl(®s->lcdc_lcden);
246 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
247 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
250 printf("%s: %d: Timeout!\n", __func__, __LINE__);
251 value = readl(®s->lcdc_lcden);
252 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
253 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
256 printf("%s: %d: Timeout!\n", __func__, __LINE__);
259 static int atmel_hlcdc_probe(struct udevice *dev)
261 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
262 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
265 ret = at91_hlcdc_enable_clk(dev);
269 atmel_hlcdc_init(dev);
271 uc_priv->xsize = priv->timing.hactive.typ;
272 uc_priv->ysize = priv->timing.vactive.typ;
273 uc_priv->bpix = priv->vl_bpix;
275 /* Enable flushing if we enabled dcache */
276 video_set_flush_dcache(dev, true);
281 static int atmel_hlcdc_of_to_plat(struct udevice *dev)
283 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
284 const void *blob = gd->fdt_blob;
285 int node = dev_of_offset(dev);
287 priv->regs = dev_read_addr_ptr(dev);
289 debug("%s: No display controller address\n", __func__);
293 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
295 debug("%s: Failed to decode display timing\n", __func__);
299 if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
300 priv->timing.hactive.typ = LCD_MAX_WIDTH;
302 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
303 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
305 priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
306 if (!priv->vl_bpix) {
307 debug("%s: Failed to get bits per pixel\n", __func__);
311 priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
312 priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
317 static int atmel_hlcdc_bind(struct udevice *dev)
319 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
321 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
322 (1 << LCD_MAX_LOG2_BPP) / 8;
324 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
329 static const struct udevice_id atmel_hlcdc_ids[] = {
330 { .compatible = "atmel,sama5d2-hlcdc" },
331 { .compatible = "atmel,at91sam9x5-hlcdc" },
335 U_BOOT_DRIVER(atmel_hlcdfb) = {
336 .name = "atmel_hlcdfb",
338 .of_match = atmel_hlcdc_ids,
339 .bind = atmel_hlcdc_bind,
340 .probe = atmel_hlcdc_probe,
341 .of_to_plat = atmel_hlcdc_of_to_plat,
342 .priv_auto = sizeof(struct atmel_hlcdc_priv),