1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AT91/AT32 MULTI LAYER LCD Controller
5 * Copyright (C) 2012 Atmel Corporation
13 #include <asm/global_data.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
22 #include <atmel_hlcdc.h>
23 #include <linux/bug.h>
25 DECLARE_GLOBAL_DATA_PTR;
30 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
33 struct atmel_hlcdc_priv {
34 struct atmel_hlcd_regs *regs;
35 struct display_timing timing;
37 unsigned int output_mode;
38 unsigned int guard_time;
42 static int at91_hlcdc_enable_clk(struct udevice *dev)
44 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
49 ret = clk_get_by_index(dev, 0, &clk);
53 ret = clk_enable(&clk);
57 clk_rate = clk_get_rate(&clk);
63 priv->clk_rate = clk_rate;
70 static void atmel_hlcdc_init(struct udevice *dev)
72 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
73 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
74 struct atmel_hlcd_regs *regs = priv->regs;
75 struct display_timing *timing = &priv->timing;
76 struct lcd_dma_desc *desc;
77 unsigned long value, vl_clk_pol;
80 /* Disable DISP signal */
81 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
82 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
85 printf("%s: %d: Timeout!\n", __func__, __LINE__);
86 /* Disable synchronization */
87 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
88 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
91 printf("%s: %d: Timeout!\n", __func__, __LINE__);
92 /* Disable pixel clock */
93 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
94 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
97 printf("%s: %d: Timeout!\n", __func__, __LINE__);
99 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
100 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
103 printf("%s: %d: Timeout!\n", __func__, __LINE__);
105 /* Set pixel clock */
106 value = priv->clk_rate / timing->pixelclock.typ;
107 if (priv->clk_rate % timing->pixelclock.typ)
111 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
112 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
115 /* Using system clock as pixel clock */
116 writel(LCDC_LCDCFG0_CLKDIV(0)
117 | LCDC_LCDCFG0_CGDISHCR
118 | LCDC_LCDCFG0_CGDISHEO
119 | LCDC_LCDCFG0_CGDISOVR1
120 | LCDC_LCDCFG0_CGDISBASE
122 | LCDC_LCDCFG0_CLKSEL,
123 ®s->lcdc_lcdcfg0);
126 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
127 | LCDC_LCDCFG0_CGDISHCR
128 | LCDC_LCDCFG0_CGDISHEO
129 | LCDC_LCDCFG0_CGDISOVR1
130 | LCDC_LCDCFG0_CGDISBASE
132 ®s->lcdc_lcdcfg0);
135 /* Initialize control register 5 */
138 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
139 value |= LCDC_LCDCFG5_HSPOL;
140 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
141 value |= LCDC_LCDCFG5_VSPOL;
143 switch (priv->output_mode) {
145 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
148 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
151 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
154 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
161 value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
162 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
163 writel(value, ®s->lcdc_lcdcfg5);
165 /* Vertical & Horizontal Timing */
166 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
167 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
168 writel(value, ®s->lcdc_lcdcfg1);
170 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
171 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
172 writel(value, ®s->lcdc_lcdcfg2);
174 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
175 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
176 writel(value, ®s->lcdc_lcdcfg3);
179 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
180 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
181 writel(value, ®s->lcdc_lcdcfg4);
183 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
184 ®s->lcdc_basecfg0);
186 switch (VNBITS(priv->vl_bpix)) {
188 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
189 ®s->lcdc_basecfg1);
192 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
193 ®s->lcdc_basecfg1);
200 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
201 writel(0, ®s->lcdc_basecfg3);
202 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
204 /* Disable all interrupts */
205 writel(~0UL, ®s->lcdc_lcdidr);
206 writel(~0UL, ®s->lcdc_baseidr);
208 /* Setup the DMA descriptor, this descriptor will loop to itself */
209 desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
213 desc->address = (u32)uc_plat->base;
215 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
216 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
217 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
218 desc->next = (u32)desc;
220 /* Flush the DMA descriptor if we enabled dcache */
221 flush_dcache_range((u32)desc,
222 ALIGN(((u32)desc + sizeof(*desc)),
223 CONFIG_SYS_CACHELINE_SIZE));
225 writel(desc->address, ®s->lcdc_baseaddr);
226 writel(desc->control, ®s->lcdc_basectrl);
227 writel(desc->next, ®s->lcdc_basenext);
228 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
229 ®s->lcdc_basecher);
232 value = readl(®s->lcdc_lcden);
233 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
234 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
237 printf("%s: %d: Timeout!\n", __func__, __LINE__);
238 value = readl(®s->lcdc_lcden);
239 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
240 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
243 printf("%s: %d: Timeout!\n", __func__, __LINE__);
244 value = readl(®s->lcdc_lcden);
245 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
246 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
249 printf("%s: %d: Timeout!\n", __func__, __LINE__);
250 value = readl(®s->lcdc_lcden);
251 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
252 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
255 printf("%s: %d: Timeout!\n", __func__, __LINE__);
258 static int atmel_hlcdc_probe(struct udevice *dev)
260 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
261 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
264 ret = at91_hlcdc_enable_clk(dev);
268 atmel_hlcdc_init(dev);
270 uc_priv->xsize = priv->timing.hactive.typ;
271 uc_priv->ysize = priv->timing.vactive.typ;
272 uc_priv->bpix = priv->vl_bpix;
274 /* Enable flushing if we enabled dcache */
275 video_set_flush_dcache(dev, true);
280 static int atmel_hlcdc_of_to_plat(struct udevice *dev)
282 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
283 const void *blob = gd->fdt_blob;
284 int node = dev_of_offset(dev);
286 priv->regs = dev_read_addr_ptr(dev);
288 debug("%s: No display controller address\n", __func__);
292 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
294 debug("%s: Failed to decode display timing\n", __func__);
298 if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
299 priv->timing.hactive.typ = LCD_MAX_WIDTH;
301 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
302 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
304 priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
305 if (!priv->vl_bpix) {
306 debug("%s: Failed to get bits per pixel\n", __func__);
310 priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
311 priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
316 static int atmel_hlcdc_bind(struct udevice *dev)
318 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
320 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
321 (1 << LCD_MAX_LOG2_BPP) / 8;
323 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
328 static const struct udevice_id atmel_hlcdc_ids[] = {
329 { .compatible = "atmel,sama5d2-hlcdc" },
330 { .compatible = "atmel,at91sam9x5-hlcdc" },
334 U_BOOT_DRIVER(atmel_hlcdfb) = {
335 .name = "atmel_hlcdfb",
337 .of_match = atmel_hlcdc_ids,
338 .bind = atmel_hlcdc_bind,
339 .probe = atmel_hlcdc_probe,
340 .of_to_plat = atmel_hlcdc_of_to_plat,
341 .priv_auto = sizeof(struct atmel_hlcdc_priv),