Merge git://git.denx.de/u-boot-x86
[platform/kernel/u-boot.git] / drivers / video / anx9804.c
1 /*
2  * (C) 2015 Hans de Goede <hdegoede@redhat.com>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * Support for the ANX9804 bridge chip, which can take pixel data coming
9  * from a parallel LCD interface and translate it on the flight into a DP
10  * interface for driving eDP TFT displays.
11  */
12
13 #include <common.h>
14 #include <i2c.h>
15 #include "anx9804.h"
16
17 #define BIT(x) (1 << (x))
18
19 /* Registers at i2c address 0x38 */
20
21 #define ANX9804_HDCP_CONTROL_0_REG                              0x01
22
23 #define ANX9804_SYS_CTRL2_REG                                   0x81
24 #define ANX9804_SYS_CTRL2_CHA_STA                               0x04
25
26 #define ANX9804_SYS_CTRL3_REG                                   0x82
27 #define ANX9804_SYS_CTRL3_VALID_CTRL                            BIT(0)
28 #define ANX9804_SYS_CTRL3_F_VALID                               BIT(1)
29 #define ANX9804_SYS_CTRL3_HPD_CTRL                              BIT(4)
30 #define ANX9804_SYS_CTRL3_F_HPD                                 BIT(5)
31
32 #define ANX9804_LINK_BW_SET_REG                                 0xa0
33 #define ANX9804_LANE_COUNT_SET_REG                              0xa1
34 #define ANX9804_TRAINING_PTN_SET_REG                            0xa2
35 #define ANX9804_TRAINING_LANE0_SET_REG                          0xa3
36 #define ANX9804_TRAINING_LANE1_SET_REG                          0xa4
37 #define ANX9804_TRAINING_LANE2_SET_REG                          0xa5
38 #define ANX9804_TRAINING_LANE3_SET_REG                          0xa6
39
40 #define ANX9804_LINK_TRAINING_CTRL_REG                          0xa8
41 #define ANX9804_LINK_TRAINING_CTRL_EN                           BIT(0)
42
43 #define ANX9804_LINK_DEBUG_REG                                  0xb8
44 #define ANX9804_PLL_CTRL_REG                                    0xc7    
45 #define ANX9804_ANALOG_POWER_DOWN_REG                           0xc8
46
47 /* Registers at i2c address 0x39 */
48
49 #define ANX9804_DEV_IDH_REG                                     0x03
50
51 #define ANX9804_POWERD_CTRL_REG                                 0x05
52 #define ANX9804_POWERD_AUDIO                                    BIT(4)
53
54 #define ANX9804_RST_CTRL_REG                                    0x06
55
56 #define ANX9804_RST_CTRL2_REG                                   0x07
57 #define ANX9804_RST_CTRL2_AUX                                   BIT(2)
58 #define ANX9804_RST_CTRL2_AC_MODE                               BIT(6)
59
60 #define ANX9804_VID_CTRL1_REG                                   0x08
61 #define ANX9804_VID_CTRL1_VID_EN                                BIT(7)
62 #define ANX9804_VID_CTRL1_EDGE                                  BIT(0)
63
64 #define ANX9804_VID_CTRL2_REG                                   0x09
65 #define ANX9804_ANALOG_DEBUG_REG1                               0xdc
66 #define ANX9804_ANALOG_DEBUG_REG3                               0xde
67 #define ANX9804_PLL_FILTER_CTRL1                                0xdf
68 #define ANX9804_PLL_FILTER_CTRL3                                0xe1
69 #define ANX9804_PLL_FILTER_CTRL                                 0xe2
70 #define ANX9804_PLL_CTRL3                                       0xe6
71
72 /**
73  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
74  *
75  * This function will init an anx9804 parallel lcd to dp bridge chip
76  * using the passed in parameters.
77  *
78  * @i2c_bus:    Number of the i2c bus to which the anx9804 is connected.
79  * @lanes:      Number of displayport lanes to use
80  * @data_rate:  Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
81  * @bpp:        Bits per pixel, must be 18 or 24
82  */
83 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
84 {
85         unsigned int orig_i2c_bus = i2c_get_bus_num();
86         u8 c, colordepth;
87         int i;
88
89         i2c_set_bus_num(i2c_bus);
90
91         if (bpp == 18)
92                 colordepth = 0x00; /* 6 bit */
93         else
94                 colordepth = 0x10; /* 8 bit */
95
96         /* Reset */
97         i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
98         mdelay(100);
99         i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
100
101         /* Write 0 to the powerdown reg (powerup everything) */
102         i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
103
104         c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
105         if (c != 0x98) {
106                 printf("Error anx9804 chipid mismatch\n");
107                 i2c_set_bus_num(orig_i2c_bus);
108                 return;
109         }
110
111         for (i = 0; i < 100; i++) {
112                 c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
113                 i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
114                 c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
115                 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
116                         break;
117
118                 mdelay(5);
119         }
120         if (i == 100)
121                 printf("Error anx9804 clock is not stable\n");
122
123         i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
124         
125         /* Set a bunch of analog related register values */
126         i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); 
127         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); 
128         i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); 
129         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
130         i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
131         i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
132         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
133         i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
134         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
135
136         /* Force HPD */
137         i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
138                       ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
139
140         /* Power up and configure lanes */
141         i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
142         i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
143         i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
144         i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
145         i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
146
147         /* Reset AUX CH */
148         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
149                       ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
150         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
151                       ANX9804_RST_CTRL2_AC_MODE);
152
153         /* Powerdown audio and some other unused bits */
154         i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
155         i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
156         i2c_reg_write(0x38, 0xa7, 0x00);
157
158         /* Set data-rate / lanes */
159         i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
160         i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
161
162         /* Link training */     
163         i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
164                       ANX9804_LINK_TRAINING_CTRL_EN);
165         mdelay(5);
166         for (i = 0; i < 100; i++) {
167                 c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
168                 if ((c & 0x01) == 0)
169                         break;
170
171                 mdelay(5);
172         }
173         if(i == 100) {
174                 printf("Error anx9804 link training timeout\n");
175                 i2c_set_bus_num(orig_i2c_bus);
176                 return;
177         }
178
179         /* Enable */
180         i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
181                       ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
182         /* Force stream valid */
183         i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
184                       ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
185                       ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
186
187         i2c_set_bus_num(orig_i2c_bus);
188 }