drivers/video/anx9804.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) 2015 Hans de Goede <hdegoede@redhat.com>
   4  */
   5
   6 /*
   7  * Support for the ANX9804 bridge chip, which can take pixel data coming
   8  * from a parallel LCD interface and translate it on the flight into a DP
   9  * interface for driving eDP TFT displays.
  10  */
  11
  12 #include <common.h>
  13 #include <i2c.h>
  14 #include <linux/delay.h>
  15 #include "anx98xx-edp.h"
  16 #include "anx9804.h"
  17
  18 /**
  19  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  20  *
  21  * This function will init an anx9804 parallel lcd to dp bridge chip
  22  * using the passed in parameters.
  23  *
  24  * @i2c_bus:    Device of the i2c bus to which the anx9804 is connected.
  25  * @lanes:      Number of displayport lanes to use
  26  * @data_rate:  Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
  27  * @bpp:        Bits per pixel, must be 18 or 24
  28  */
  29 void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
  30 {
  31         struct udevice *chip0, *chip1;
  32         int c, colordepth, i, ret;
  33
  34         ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
  35         if (ret)
  36                 return;
  37
  38         ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
  39         if (ret)
  40                 return;
  41
  42         if (bpp == 18)
  43                 colordepth = 0x00; /* 6 bit */
  44         else
  45                 colordepth = 0x10; /* 8 bit */
  46
  47         /* Reset */
  48         dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
  49         mdelay(100);
  50         dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
  51
  52         /* Write 0 to the powerdown reg (powerup everything) */
  53         dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
  54
  55         c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
  56         if (c != 0x98) {
  57                 printf("Error anx9804 chipid mismatch\n");
  58                 return;
  59         }
  60
  61         for (i = 0; i < 100; i++) {
  62                 c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
  63                 dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
  64                 c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
  65                 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
  66                         break;
  67
  68                 mdelay(5);
  69         }
  70         if (i == 100)
  71                 printf("Error anx9804 clock is not stable\n");
  72
  73         dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
  74
  75         /* Set a bunch of analog related register values */
  76         dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
  77         dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
  78         dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
  79         dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
  80         dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
  81         dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
  82         dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
  83         dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
  84         dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
  85
  86         /* Force HPD */
  87         dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
  88                          ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
  89
  90         /* Power up and configure lanes */
  91         dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
  92         dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
  93         dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
  94         dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
  95         dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
  96
  97         /* Reset AUX CH */
  98         dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
  99                          ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
 100         dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
 101                          ANX9804_RST_CTRL2_AC_MODE);
 102
 103         /* Powerdown audio and some other unused bits */
 104         dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
 105         dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
 106         dm_i2c_reg_write(chip0, 0xa7, 0x00);
 107
 108         /* Set data-rate / lanes */
 109         dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
 110         dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
 111
 112         /* Link training */
 113         dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
 114                          ANX9804_LINK_TRAINING_CTRL_EN);
 115         mdelay(5);
 116         for (i = 0; i < 100; i++) {
 117                 c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
 118                 if ((c & 0x01) == 0)
 119                         break;
 120
 121                 mdelay(5);
 122         }
 123         if(i == 100) {
 124                 printf("Error anx9804 link training timeout\n");
 125                 return;
 126         }
 127
 128         /* Enable */
 129         dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
 130                          ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
 131         /* Force stream valid */
 132         dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
 133                          ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
 134                          ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
 135 }