1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
10 #define HSVS_CONTROL (0x01 << 25) /*
11 * 0 = lcd_lp and lcd_fp are driven on
12 * opposite edges of pixel clock than
14 * 1 = lcd_lp and lcd_fp are driven
15 * according to bit 24 Note that this
16 * bit MUST be set to '0' for Passive
17 * Matrix displays the edge timing is
20 #define HSVS_RISEFALL (0x01 << 24) /*
21 * 0 = lcd_lp and lcd_fp are driven on
22 * the rising edge of pixel clock (bit
23 * 25 must be set to 1)
24 * 1 = lcd_lp and lcd_fp are driven on
25 * the falling edge of pixel clock (bit
26 * 25 must be set to 1)
28 #define DE_INVERT (0x01 << 23) /*
29 * 0 = DE is low-active
30 * 1 = DE is high-active
32 #define PXCLK_INVERT (0x01 << 22) /*
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
36 #define HSYNC_INVERT (0x01 << 21) /*
37 * 0 = HSYNC is active high
38 * 1 = HSYNC is avtive low
40 #define VSYNC_INVERT (0x01 << 20) /*
41 * 0 = VSYNC is active high
42 * 1 = VSYNC is active low
45 struct am335x_lcdpanel {
46 unsigned int hactive; /* Horizontal active area */
47 unsigned int vactive; /* Vertical active area */
48 unsigned int bpp; /* bits per pixel */
49 unsigned int hfp; /* Horizontal front porch */
50 unsigned int hbp; /* Horizontal back porch */
51 unsigned int hsw; /* Horizontal Sync Pulse Width */
52 unsigned int vfp; /* Vertical front porch */
53 unsigned int vbp; /* Vertical back porch */
54 unsigned int vsw; /* Vertical Sync Pulse Width */
55 unsigned int pxl_clk; /* Pixel clock */
56 unsigned int pol; /* polarity of sync, clock signals */
57 unsigned int pup_delay; /*
58 * time in ms after power on to
59 * initialization of lcd-controller
62 unsigned int pon_delay; /*
63 * time in ms after initialization of
64 * lcd-controller (pic stabilization)
66 void (*panel_power_ctrl)(int); /* fp for power on/off display */
69 int am335xfb_init(struct am335x_lcdpanel *panel);
71 #endif /* AM335X_FB_H */