1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO PCI config space virtualization
5 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
6 * Author: Alex Williamson <alex.williamson@redhat.com>
8 * Derived from original vfio:
9 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
10 * Author: Tom Lyon, pugs@cisco.com
14 * This code handles reading and writing of PCI configuration registers.
15 * This is hairy because we want to allow a lot of flexibility to the
16 * user driver, but cannot trust it with all of the config fields.
17 * Tables determine which fields can be read and written, as well as
18 * which fields are 'virtualized' - special actions and translations to
19 * make it appear to the user that he has control, when in fact things
20 * must be negotiated with the underlying OS.
24 #include <linux/pci.h>
25 #include <linux/uaccess.h>
26 #include <linux/vfio.h>
27 #include <linux/slab.h>
29 #include <linux/vfio_pci_core.h>
31 /* Fake capability ID for standard config space */
32 #define PCI_CAP_ID_BASIC 0
34 #define is_bar(offset) \
35 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
36 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
39 * Lengths of PCI Config Capabilities
40 * 0: Removed from the user visible capability list
43 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
44 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
45 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
46 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
47 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
48 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
49 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
50 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
51 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
52 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
53 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
54 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
55 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
57 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
58 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
59 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
60 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
61 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
62 [PCI_CAP_ID_SATA] = 0xFF,
63 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
67 * Lengths of PCIe/PCI-X Extended Config Capabilities
68 * 0: Removed or masked from the user visible capability list
71 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
72 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
73 [PCI_EXT_CAP_ID_VC] = 0xFF,
74 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
75 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
76 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
77 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
78 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
79 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
80 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
81 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
83 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
84 [PCI_EXT_CAP_ID_ACS] = 0xFF,
85 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
86 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
87 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
88 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
89 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
90 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
91 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
92 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
93 [PCI_EXT_CAP_ID_DPA] = 0xFF,
94 [PCI_EXT_CAP_ID_TPH] = 0xFF,
95 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
96 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
102 * Read/Write Permission Bits - one bit for each bit in capability
103 * Any field can be read if it exists, but what is read depends on
104 * whether the field is 'virtualized', or just pass through to the
105 * hardware. Any virtualized field is also virtualized for writes.
106 * Writes are only permitted if they have a 1 bit here.
109 u8 *virt; /* read/write virtual data, not hw */
110 u8 *write; /* writeable bits */
111 int (*readfn)(struct vfio_pci_core_device *vdev, int pos, int count,
112 struct perm_bits *perm, int offset, __le32 *val);
113 int (*writefn)(struct vfio_pci_core_device *vdev, int pos, int count,
114 struct perm_bits *perm, int offset, __le32 val);
118 #define ALL_VIRT 0xFFFFFFFFU
120 #define ALL_WRITE 0xFFFFFFFFU
122 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
123 __le32 *val, int count)
132 ret = pci_user_read_config_byte(pdev, offset, &tmp);
139 ret = pci_user_read_config_word(pdev, offset, &tmp);
144 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
148 *val = cpu_to_le32(tmp_val);
153 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
154 __le32 val, int count)
157 u32 tmp_val = le32_to_cpu(val);
161 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
164 ret = pci_user_write_config_word(pdev, offset, tmp_val);
167 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
174 static int vfio_default_config_read(struct vfio_pci_core_device *vdev, int pos,
175 int count, struct perm_bits *perm,
176 int offset, __le32 *val)
180 memcpy(val, vdev->vconfig + pos, count);
182 memcpy(&virt, perm->virt + offset, count);
184 /* Any non-virtualized bits? */
185 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
186 struct pci_dev *pdev = vdev->pdev;
190 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
194 *val = (phys_val & ~virt) | (*val & virt);
200 static int vfio_default_config_write(struct vfio_pci_core_device *vdev, int pos,
201 int count, struct perm_bits *perm,
202 int offset, __le32 val)
204 __le32 virt = 0, write = 0;
206 memcpy(&write, perm->write + offset, count);
209 return count; /* drop, no writable bits */
211 memcpy(&virt, perm->virt + offset, count);
213 /* Virtualized and writable bits go to vconfig */
217 memcpy(&virt_val, vdev->vconfig + pos, count);
219 virt_val &= ~(write & virt);
220 virt_val |= (val & (write & virt));
222 memcpy(vdev->vconfig + pos, &virt_val, count);
225 /* Non-virtualized and writable bits go to hardware */
227 struct pci_dev *pdev = vdev->pdev;
231 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
235 phys_val &= ~(write & ~virt);
236 phys_val |= (val & (write & ~virt));
238 ret = vfio_user_config_write(pdev, pos, phys_val, count);
246 /* Allow direct read from hardware, except for capability next pointer */
247 static int vfio_direct_config_read(struct vfio_pci_core_device *vdev, int pos,
248 int count, struct perm_bits *perm,
249 int offset, __le32 *val)
253 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
257 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
259 memcpy(val, vdev->vconfig + pos, count);
260 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
261 if (offset == PCI_CAP_LIST_ID && count > 1)
262 memcpy(val, vdev->vconfig + pos,
263 min(PCI_CAP_FLAGS, count));
264 else if (offset == PCI_CAP_LIST_NEXT)
265 memcpy(val, vdev->vconfig + pos, 1);
271 /* Raw access skips any kind of virtualization */
272 static int vfio_raw_config_write(struct vfio_pci_core_device *vdev, int pos,
273 int count, struct perm_bits *perm,
274 int offset, __le32 val)
278 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
285 static int vfio_raw_config_read(struct vfio_pci_core_device *vdev, int pos,
286 int count, struct perm_bits *perm,
287 int offset, __le32 *val)
291 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
298 /* Virt access uses only virtualization */
299 static int vfio_virt_config_write(struct vfio_pci_core_device *vdev, int pos,
300 int count, struct perm_bits *perm,
301 int offset, __le32 val)
303 memcpy(vdev->vconfig + pos, &val, count);
307 static int vfio_virt_config_read(struct vfio_pci_core_device *vdev, int pos,
308 int count, struct perm_bits *perm,
309 int offset, __le32 *val)
311 memcpy(val, vdev->vconfig + pos, count);
315 /* Default capability regions to read-only, no-virtualization */
316 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
317 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
319 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
320 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
323 * Default unassigned regions to raw read-write access. Some devices
324 * require this to function as they hide registers between the gaps in
325 * config space (be2net). Like MMIO and I/O port registers, we have
326 * to trust the hardware isolation.
328 static struct perm_bits unassigned_perms = {
329 .readfn = vfio_raw_config_read,
330 .writefn = vfio_raw_config_write
333 static struct perm_bits virt_perms = {
334 .readfn = vfio_virt_config_read,
335 .writefn = vfio_virt_config_write
338 static void free_perm_bits(struct perm_bits *perm)
346 static int alloc_perm_bits(struct perm_bits *perm, int size)
349 * Round up all permission bits to the next dword, this lets us
350 * ignore whether a read/write exceeds the defined capability
351 * structure. We can do this because:
352 * - Standard config space is already dword aligned
353 * - Capabilities are all dword aligned (bits 0:1 of next reserved)
354 * - Express capabilities defined as dword aligned
356 size = round_up(size, 4);
360 * - All Readable, None Writeable, None Virtualized
362 perm->virt = kzalloc(size, GFP_KERNEL);
363 perm->write = kzalloc(size, GFP_KERNEL);
364 if (!perm->virt || !perm->write) {
365 free_perm_bits(perm);
369 perm->readfn = vfio_default_config_read;
370 perm->writefn = vfio_default_config_write;
376 * Helper functions for filling in permission tables
378 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
381 p->write[off] = write;
384 /* Handle endian-ness - pci and tables are little-endian */
385 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
387 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
388 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
391 /* Handle endian-ness - pci and tables are little-endian */
392 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
394 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
395 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
398 /* Caller should hold memory_lock semaphore */
399 bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev)
401 struct pci_dev *pdev = vdev->pdev;
402 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
405 * Memory region cannot be accessed if device power state is D3.
407 * SR-IOV VF memory enable is handled by the MSE bit in the
408 * PF SR-IOV capability, there's therefore no need to trigger
409 * faults based on the virtual value.
411 return pdev->current_state < PCI_D3hot &&
412 (pdev->no_command_memory || (cmd & PCI_COMMAND_MEMORY));
416 * Restore the *real* BARs after we detect a FLR or backdoor reset.
417 * (backdoor = some device specific technique that we didn't catch)
419 static void vfio_bar_restore(struct vfio_pci_core_device *vdev)
421 struct pci_dev *pdev = vdev->pdev;
422 u32 *rbar = vdev->rbar;
429 pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__);
431 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
432 pci_user_write_config_dword(pdev, i, *rbar);
434 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
437 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
438 cmd |= PCI_COMMAND_INTX_DISABLE;
439 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
443 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
445 unsigned long flags = pci_resource_flags(pdev, bar);
448 if (flags & IORESOURCE_IO)
449 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
451 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
453 if (flags & IORESOURCE_PREFETCH)
454 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
456 if (flags & IORESOURCE_MEM_64)
457 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
459 return cpu_to_le32(val);
463 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
464 * to reflect the hardware capabilities. This implements BAR sizing.
466 static void vfio_bar_fixup(struct vfio_pci_core_device *vdev)
468 struct pci_dev *pdev = vdev->pdev;
476 vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
478 for (i = 0; i < PCI_STD_NUM_BARS; i++, vbar++) {
479 int bar = i + PCI_STD_RESOURCES;
481 if (!pci_resource_start(pdev, bar)) {
482 *vbar = 0; /* Unmapped by host = unimplemented to user */
486 mask = ~(pci_resource_len(pdev, bar) - 1);
488 *vbar &= cpu_to_le32((u32)mask);
489 *vbar |= vfio_generate_bar_flags(pdev, bar);
491 if (*vbar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
493 *vbar &= cpu_to_le32((u32)(mask >> 32));
498 vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
501 * NB. REGION_INFO will have reported zero size if we weren't able
502 * to read the ROM, but we still return the actual BAR size here if
503 * it exists (or the shadow ROM space).
505 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
506 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
507 mask |= PCI_ROM_ADDRESS_ENABLE;
508 *vbar &= cpu_to_le32((u32)mask);
509 } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
510 IORESOURCE_ROM_SHADOW) {
511 mask = ~(0x20000 - 1);
512 mask |= PCI_ROM_ADDRESS_ENABLE;
513 *vbar &= cpu_to_le32((u32)mask);
517 vdev->bardirty = false;
520 static int vfio_basic_config_read(struct vfio_pci_core_device *vdev, int pos,
521 int count, struct perm_bits *perm,
522 int offset, __le32 *val)
524 if (is_bar(offset)) /* pos == offset for basic config */
525 vfio_bar_fixup(vdev);
527 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
529 /* Mask in virtual memory enable */
530 if (offset == PCI_COMMAND && vdev->pdev->no_command_memory) {
531 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
532 u32 tmp_val = le32_to_cpu(*val);
534 tmp_val |= cmd & PCI_COMMAND_MEMORY;
535 *val = cpu_to_le32(tmp_val);
541 /* Test whether BARs match the value we think they should contain */
542 static bool vfio_need_bar_restore(struct vfio_pci_core_device *vdev)
544 int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
547 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
549 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
550 if (ret || vdev->rbar[i] != bar)
558 static int vfio_basic_config_write(struct vfio_pci_core_device *vdev, int pos,
559 int count, struct perm_bits *perm,
560 int offset, __le32 val)
562 struct pci_dev *pdev = vdev->pdev;
567 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
569 if (offset == PCI_COMMAND) {
570 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
573 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
577 new_cmd = le32_to_cpu(val);
579 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
580 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
581 new_io = !!(new_cmd & PCI_COMMAND_IO);
583 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
584 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
585 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
588 vfio_pci_zap_and_down_write_memory_lock(vdev);
590 down_write(&vdev->memory_lock);
593 * If the user is writing mem/io enable (new_mem/io) and we
594 * think it's already enabled (virt_mem/io), but the hardware
595 * shows it disabled (phys_mem/io, then the device has
596 * undergone some kind of backdoor reset and needs to be
597 * restored before we allow it to enable the bars.
598 * SR-IOV devices will trigger this - for mem enable let's
599 * catch this now and for io enable it will be caught later
601 if ((new_mem && virt_mem && !phys_mem &&
602 !pdev->no_command_memory) ||
603 (new_io && virt_io && !phys_io) ||
604 vfio_need_bar_restore(vdev))
605 vfio_bar_restore(vdev);
608 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
610 if (offset == PCI_COMMAND)
611 up_write(&vdev->memory_lock);
616 * Save current memory/io enable bits in vconfig to allow for
617 * the test above next time.
619 if (offset == PCI_COMMAND) {
620 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
622 *virt_cmd &= cpu_to_le16(~mask);
623 *virt_cmd |= cpu_to_le16(new_cmd & mask);
625 up_write(&vdev->memory_lock);
628 /* Emulate INTx disable */
629 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
630 bool virt_intx_disable;
632 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
633 PCI_COMMAND_INTX_DISABLE);
635 if (virt_intx_disable && !vdev->virq_disabled) {
636 vdev->virq_disabled = true;
637 vfio_pci_intx_mask(vdev);
638 } else if (!virt_intx_disable && vdev->virq_disabled) {
639 vdev->virq_disabled = false;
640 vfio_pci_intx_unmask(vdev);
645 vdev->bardirty = true;
650 /* Permissions for the Basic PCI Header */
651 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
653 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
656 perm->readfn = vfio_basic_config_read;
657 perm->writefn = vfio_basic_config_write;
659 /* Virtualized for SR-IOV functions, which just have FFFF */
660 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
661 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
664 * Virtualize INTx disable, we use it internally for interrupt
665 * control and can emulate it for non-PCI 2.3 devices.
667 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
669 /* Virtualize capability list, we might want to skip/disable */
670 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
672 /* No harm to write */
673 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
674 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
675 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
677 /* Virtualize all bars, can't touch the real ones */
678 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
679 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
680 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
681 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
682 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
683 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
684 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
686 /* Allow us to adjust capability chain */
687 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
689 /* Sometimes used by sw, just virtualize */
690 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
692 /* Virtualize interrupt pin to allow hiding INTx */
693 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
699 * It takes all the required locks to protect the access of power related
700 * variables and then invokes vfio_pci_set_power_state().
702 static void vfio_lock_and_set_power_state(struct vfio_pci_core_device *vdev,
705 if (state >= PCI_D3hot)
706 vfio_pci_zap_and_down_write_memory_lock(vdev);
708 down_write(&vdev->memory_lock);
710 vfio_pci_set_power_state(vdev, state);
711 up_write(&vdev->memory_lock);
714 static int vfio_pm_config_write(struct vfio_pci_core_device *vdev, int pos,
715 int count, struct perm_bits *perm,
716 int offset, __le32 val)
718 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
722 if (offset == PCI_PM_CTRL) {
725 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
740 vfio_lock_and_set_power_state(vdev, state);
746 /* Permissions for the Power Management capability */
747 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
749 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
752 perm->writefn = vfio_pm_config_write;
755 * We always virtualize the next field so we can remove
756 * capabilities from the chain if we want to.
758 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
761 * The guests can't process PME events. If any PME event will be
762 * generated, then it will be mostly handled in the host and the
763 * host will clear the PME_STATUS. So virtualize PME_Support bits.
764 * The vconfig bits will be cleared during device capability
767 p_setw(perm, PCI_PM_PMC, PCI_PM_CAP_PME_MASK, NO_WRITE);
770 * Power management is defined *per function*, so we can let
771 * the user change power state, but we trap and initiate the
772 * change ourselves, so the state bits are read-only.
774 * The guest can't process PME from D3cold so virtualize PME_Status
775 * and PME_En bits. The vconfig bits will be cleared during device
776 * capability initialization.
778 p_setd(perm, PCI_PM_CTRL,
779 PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS,
780 ~(PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS |
781 PCI_PM_CTRL_STATE_MASK));
786 static int vfio_vpd_config_write(struct vfio_pci_core_device *vdev, int pos,
787 int count, struct perm_bits *perm,
788 int offset, __le32 val)
790 struct pci_dev *pdev = vdev->pdev;
791 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
792 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
797 * Write through to emulation. If the write includes the upper byte
798 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
801 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
802 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
803 offset + count <= PCI_VPD_ADDR + 1)
806 addr = le16_to_cpu(*paddr);
808 if (addr & PCI_VPD_ADDR_F) {
809 data = le32_to_cpu(*pdata);
810 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
814 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
816 *pdata = cpu_to_le32(data);
820 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
821 * signal completion. If an error occurs above, we assume that not
822 * toggling this bit will induce a driver timeout.
824 addr ^= PCI_VPD_ADDR_F;
825 *paddr = cpu_to_le16(addr);
830 /* Permissions for Vital Product Data capability */
831 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
833 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
836 perm->writefn = vfio_vpd_config_write;
839 * We always virtualize the next field so we can remove
840 * capabilities from the chain if we want to.
842 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
845 * Both the address and data registers are virtualized to
846 * enable access through the pci_vpd_read/write functions
848 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
849 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
854 /* Permissions for PCI-X capability */
855 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
857 /* Alloc 24, but only 8 are used in v0 */
858 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
861 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
863 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
864 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
868 static int vfio_exp_config_write(struct vfio_pci_core_device *vdev, int pos,
869 int count, struct perm_bits *perm,
870 int offset, __le32 val)
872 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
873 offset + PCI_EXP_DEVCTL);
874 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
876 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
881 * The FLR bit is virtualized, if set and the device supports PCIe
882 * FLR, issue a reset_function. Regardless, clear the bit, the spec
883 * requires it to be always read as zero. NB, reset_function might
884 * not use a PCIe FLR, we don't have that level of granularity.
886 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
890 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
892 ret = pci_user_read_config_dword(vdev->pdev,
893 pos - offset + PCI_EXP_DEVCAP,
896 if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) {
897 vfio_pci_zap_and_down_write_memory_lock(vdev);
898 pci_try_reset_function(vdev->pdev);
899 up_write(&vdev->memory_lock);
904 * MPS is virtualized to the user, writes do not change the physical
905 * register since determining a proper MPS value requires a system wide
906 * device view. The MRRS is largely independent of MPS, but since the
907 * user does not have that system-wide view, they might set a safe, but
908 * inefficiently low value. Here we allow writes through to hardware,
909 * but we set the floor to the physical device MPS setting, so that
910 * we can at least use full TLPs, as defined by the MPS value.
912 * NB, if any devices actually depend on an artificially low MRRS
913 * setting, this will need to be revisited, perhaps with a quirk
914 * though pcie_set_readrq().
916 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
918 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
919 readrq = max(readrq, pcie_get_mps(vdev->pdev));
921 pcie_set_readrq(vdev->pdev, readrq);
927 /* Permissions for PCI Express capability */
928 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
930 /* Alloc largest of possible sizes */
931 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
934 perm->writefn = vfio_exp_config_write;
936 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
939 * Allow writes to device control fields, except devctl_phantom,
940 * which could confuse IOMMU, MPS, which can break communication
941 * with other physical devices, and the ARI bit in devctl2, which
942 * is set at probe time. FLR and MRRS get virtualized via our
945 p_setw(perm, PCI_EXP_DEVCTL,
946 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
947 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
948 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
952 static int vfio_af_config_write(struct vfio_pci_core_device *vdev, int pos,
953 int count, struct perm_bits *perm,
954 int offset, __le32 val)
956 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
958 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
963 * The FLR bit is virtualized, if set and the device supports AF
964 * FLR, issue a reset_function. Regardless, clear the bit, the spec
965 * requires it to be always read as zero. NB, reset_function might
966 * not use an AF FLR, we don't have that level of granularity.
968 if (*ctrl & PCI_AF_CTRL_FLR) {
972 *ctrl &= ~PCI_AF_CTRL_FLR;
974 ret = pci_user_read_config_byte(vdev->pdev,
975 pos - offset + PCI_AF_CAP,
978 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) {
979 vfio_pci_zap_and_down_write_memory_lock(vdev);
980 pci_try_reset_function(vdev->pdev);
981 up_write(&vdev->memory_lock);
988 /* Permissions for Advanced Function capability */
989 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
991 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
994 perm->writefn = vfio_af_config_write;
996 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
997 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
1001 /* Permissions for Advanced Error Reporting extended capability */
1002 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
1006 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
1010 * Virtualize the first dword of all express capabilities
1011 * because it includes the next pointer. This lets us later
1012 * remove capabilities from the chain if we need to.
1014 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1016 /* Writable bits mask */
1017 mask = PCI_ERR_UNC_UND | /* Undefined */
1018 PCI_ERR_UNC_DLP | /* Data Link Protocol */
1019 PCI_ERR_UNC_SURPDN | /* Surprise Down */
1020 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
1021 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
1022 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
1023 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
1024 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
1025 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
1026 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
1027 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
1028 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
1029 PCI_ERR_UNC_ACSV | /* ACS Violation */
1030 PCI_ERR_UNC_INTN | /* internal error */
1031 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
1032 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
1033 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
1034 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
1035 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
1036 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
1038 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
1039 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
1040 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
1041 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
1042 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
1043 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
1044 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
1045 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
1046 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
1047 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
1049 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
1050 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
1051 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
1055 /* Permissions for Power Budgeting extended capability */
1056 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
1058 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
1061 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1063 /* Writing the data selector is OK, the info is still read-only */
1064 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
1069 * Initialize the shared permission tables
1071 void vfio_pci_uninit_perm_bits(void)
1073 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1075 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1076 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1077 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1078 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1079 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1081 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1082 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1085 int __init vfio_pci_init_perm_bits(void)
1089 /* Basic config space */
1090 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1093 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1094 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1095 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1096 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1097 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1098 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1100 /* Extended capabilities */
1101 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1102 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1103 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1106 vfio_pci_uninit_perm_bits();
1111 static int vfio_find_cap_start(struct vfio_pci_core_device *vdev, int pos)
1114 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1115 PCI_STD_HEADER_SIZEOF;
1116 cap = vdev->pci_config_map[pos];
1118 if (cap == PCI_CAP_ID_BASIC)
1121 /* XXX Can we have to abutting capabilities of the same type? */
1122 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1128 static int vfio_msi_config_read(struct vfio_pci_core_device *vdev, int pos,
1129 int count, struct perm_bits *perm,
1130 int offset, __le32 *val)
1132 /* Update max available queue size from msi_qmax */
1133 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1137 start = vfio_find_cap_start(vdev, pos);
1139 flags = (__le16 *)&vdev->vconfig[start];
1141 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1142 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1145 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1148 static int vfio_msi_config_write(struct vfio_pci_core_device *vdev, int pos,
1149 int count, struct perm_bits *perm,
1150 int offset, __le32 val)
1152 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1156 /* Fixup and write configured queue size and enable to hardware */
1157 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1162 start = vfio_find_cap_start(vdev, pos);
1164 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1166 flags = le16_to_cpu(*pflags);
1168 /* MSI is enabled via ioctl */
1170 flags &= ~PCI_MSI_FLAGS_ENABLE;
1172 /* Check queue size */
1173 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1174 flags &= ~PCI_MSI_FLAGS_QSIZE;
1175 flags |= vdev->msi_qmax << 4;
1178 /* Write back to virt and to hardware */
1179 *pflags = cpu_to_le16(flags);
1180 ret = pci_user_write_config_word(vdev->pdev,
1181 start + PCI_MSI_FLAGS,
1191 * MSI determination is per-device, so this routine gets used beyond
1192 * initialization time. Don't add __init
1194 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1196 if (alloc_perm_bits(perm, len))
1199 perm->readfn = vfio_msi_config_read;
1200 perm->writefn = vfio_msi_config_write;
1202 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1205 * The upper byte of the control register is reserved,
1206 * just setup the lower byte.
1208 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1209 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1210 if (flags & PCI_MSI_FLAGS_64BIT) {
1211 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1212 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1213 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1214 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1215 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1218 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1219 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1220 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1221 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1227 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1228 static int vfio_msi_cap_len(struct vfio_pci_core_device *vdev, u8 pos)
1230 struct pci_dev *pdev = vdev->pdev;
1234 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1236 return pcibios_err_to_errno(ret);
1238 len = 10; /* Minimum size */
1239 if (flags & PCI_MSI_FLAGS_64BIT)
1241 if (flags & PCI_MSI_FLAGS_MASKBIT)
1247 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1248 if (!vdev->msi_perm)
1251 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1253 kfree(vdev->msi_perm);
1260 /* Determine extended capability length for VC (2 & 9) and MFVC */
1261 static int vfio_vc_cap_len(struct vfio_pci_core_device *vdev, u16 pos)
1263 struct pci_dev *pdev = vdev->pdev;
1265 int ret, evcc, phases, vc_arb;
1266 int len = PCI_CAP_VC_BASE_SIZEOF;
1268 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1270 return pcibios_err_to_errno(ret);
1272 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1273 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1275 return pcibios_err_to_errno(ret);
1277 if (tmp & PCI_VC_CAP2_128_PHASE)
1279 else if (tmp & PCI_VC_CAP2_64_PHASE)
1281 else if (tmp & PCI_VC_CAP2_32_PHASE)
1286 vc_arb = phases * 4;
1289 * Port arbitration tables are root & switch only;
1290 * function arbitration tables are function 0 only.
1291 * In either case, we'll never let user write them so
1292 * we don't care how big they are
1294 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1296 len = round_up(len, 16);
1302 static int vfio_cap_len(struct vfio_pci_core_device *vdev, u8 cap, u8 pos)
1304 struct pci_dev *pdev = vdev->pdev;
1311 case PCI_CAP_ID_MSI:
1312 return vfio_msi_cap_len(vdev, pos);
1313 case PCI_CAP_ID_PCIX:
1314 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1316 return pcibios_err_to_errno(ret);
1318 if (PCI_X_CMD_VERSION(word)) {
1319 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1320 /* Test for extended capabilities */
1321 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1323 vdev->extended_caps = (dword != 0);
1325 return PCI_CAP_PCIX_SIZEOF_V2;
1327 return PCI_CAP_PCIX_SIZEOF_V0;
1328 case PCI_CAP_ID_VNDR:
1329 /* length follows next field */
1330 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1332 return pcibios_err_to_errno(ret);
1335 case PCI_CAP_ID_EXP:
1336 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1337 /* Test for extended capabilities */
1338 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1339 vdev->extended_caps = (dword != 0);
1342 /* length based on version and type */
1343 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
1344 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1345 return 0xc; /* "All Devices" only, no link */
1346 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1348 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1349 return 0x2c; /* No link */
1350 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1353 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1355 return pcibios_err_to_errno(ret);
1357 return (byte & HT_3BIT_CAP_MASK) ?
1358 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1359 case PCI_CAP_ID_SATA:
1360 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1362 return pcibios_err_to_errno(ret);
1364 byte &= PCI_SATA_REGS_MASK;
1365 if (byte == PCI_SATA_REGS_INLINE)
1366 return PCI_SATA_SIZEOF_LONG;
1368 return PCI_SATA_SIZEOF_SHORT;
1370 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n",
1371 __func__, cap, pos);
1377 static int vfio_ext_cap_len(struct vfio_pci_core_device *vdev, u16 ecap, u16 epos)
1379 struct pci_dev *pdev = vdev->pdev;
1385 case PCI_EXT_CAP_ID_VNDR:
1386 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1388 return pcibios_err_to_errno(ret);
1390 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1391 case PCI_EXT_CAP_ID_VC:
1392 case PCI_EXT_CAP_ID_VC9:
1393 case PCI_EXT_CAP_ID_MFVC:
1394 return vfio_vc_cap_len(vdev, epos);
1395 case PCI_EXT_CAP_ID_ACS:
1396 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1398 return pcibios_err_to_errno(ret);
1400 if (byte & PCI_ACS_EC) {
1403 ret = pci_read_config_byte(pdev,
1404 epos + PCI_ACS_EGRESS_BITS,
1407 return pcibios_err_to_errno(ret);
1409 bits = byte ? round_up(byte, 32) : 256;
1410 return 8 + (bits / 8);
1414 case PCI_EXT_CAP_ID_REBAR:
1415 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1417 return pcibios_err_to_errno(ret);
1419 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1420 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1422 return 4 + (byte * 8);
1423 case PCI_EXT_CAP_ID_DPA:
1424 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1426 return pcibios_err_to_errno(ret);
1428 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1429 return PCI_DPA_BASE_SIZEOF + byte + 1;
1430 case PCI_EXT_CAP_ID_TPH:
1431 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1433 return pcibios_err_to_errno(ret);
1435 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1438 sts = dword & PCI_TPH_CAP_ST_MASK;
1439 sts >>= PCI_TPH_CAP_ST_SHIFT;
1440 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1442 return PCI_TPH_BASE_SIZEOF;
1444 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n",
1445 __func__, ecap, epos);
1451 static void vfio_update_pm_vconfig_bytes(struct vfio_pci_core_device *vdev,
1454 __le16 *pmc = (__le16 *)&vdev->vconfig[offset + PCI_PM_PMC];
1455 __le16 *ctrl = (__le16 *)&vdev->vconfig[offset + PCI_PM_CTRL];
1457 /* Clear vconfig PME_Support, PME_Status, and PME_En bits */
1458 *pmc &= ~cpu_to_le16(PCI_PM_CAP_PME_MASK);
1459 *ctrl &= ~cpu_to_le16(PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS);
1462 static int vfio_fill_vconfig_bytes(struct vfio_pci_core_device *vdev,
1463 int offset, int size)
1465 struct pci_dev *pdev = vdev->pdev;
1469 * We try to read physical config space in the largest chunks
1470 * we can, assuming that all of the fields support dword access.
1471 * pci_save_state() makes this same assumption and seems to do ok.
1476 if (size >= 4 && !(offset % 4)) {
1477 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1480 ret = pci_read_config_dword(pdev, offset, &dword);
1483 *dwordp = cpu_to_le32(dword);
1485 } else if (size >= 2 && !(offset % 2)) {
1486 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1489 ret = pci_read_config_word(pdev, offset, &word);
1492 *wordp = cpu_to_le16(word);
1495 u8 *byte = &vdev->vconfig[offset];
1496 ret = pci_read_config_byte(pdev, offset, byte);
1509 static int vfio_cap_init(struct vfio_pci_core_device *vdev)
1511 struct pci_dev *pdev = vdev->pdev;
1512 u8 *map = vdev->pci_config_map;
1515 int loops, ret, caps = 0;
1517 /* Any capabilities? */
1518 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1522 if (!(status & PCI_STATUS_CAP_LIST))
1523 return 0; /* Done */
1525 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1529 /* Mark the previous position in case we want to skip a capability */
1530 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1532 /* We can bound our loop, capabilities are dword aligned */
1533 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1534 while (pos && loops--) {
1538 ret = pci_read_config_byte(pdev, pos, &cap);
1542 ret = pci_read_config_byte(pdev,
1543 pos + PCI_CAP_LIST_NEXT, &next);
1548 * ID 0 is a NULL capability, conflicting with our fake
1549 * PCI_CAP_ID_BASIC. As it has no content, consider it
1552 if (cap && cap <= PCI_CAP_ID_MAX) {
1553 len = pci_cap_length[cap];
1554 if (len == 0xFF) { /* Variable length */
1555 len = vfio_cap_len(vdev, cap, pos);
1562 pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__,
1569 /* Sanity check, do we overlap other capabilities? */
1570 for (i = 0; i < len; i++) {
1571 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1574 pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n",
1575 __func__, pos + i, map[pos + i], cap);
1578 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1580 memset(map + pos, cap, len);
1581 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1585 if (cap == PCI_CAP_ID_PM)
1586 vfio_update_pm_vconfig_bytes(vdev, pos);
1588 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1593 /* If we didn't fill any capabilities, clear the status flag */
1595 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1596 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1602 static int vfio_ecap_init(struct vfio_pci_core_device *vdev)
1604 struct pci_dev *pdev = vdev->pdev;
1605 u8 *map = vdev->pci_config_map;
1607 __le32 *prev = NULL;
1608 int loops, ret, ecaps = 0;
1610 if (!vdev->extended_caps)
1613 epos = PCI_CFG_SPACE_SIZE;
1615 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1617 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1621 bool hidden = false;
1623 ret = pci_read_config_dword(pdev, epos, &header);
1627 ecap = PCI_EXT_CAP_ID(header);
1629 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1630 len = pci_ext_cap_length[ecap];
1632 len = vfio_ext_cap_len(vdev, ecap, epos);
1639 pci_info(pdev, "%s: hiding ecap %#x@%#x\n",
1640 __func__, ecap, epos);
1642 /* If not the first in the chain, we can skip over it */
1644 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1645 *prev &= cpu_to_le32(~(0xffcU << 20));
1646 *prev |= cpu_to_le32(val << 20);
1651 * Otherwise, fill in a placeholder, the direct
1652 * readfn will virtualize this automatically
1654 len = PCI_CAP_SIZEOF;
1658 for (i = 0; i < len; i++) {
1659 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1662 pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n",
1663 __func__, epos + i, map[epos + i], ecap);
1667 * Even though ecap is 2 bytes, we're currently a long way
1668 * from exceeding 1 byte capabilities. If we ever make it
1669 * up to 0xFE we'll need to up this to a two-byte, byte map.
1671 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1673 memset(map + epos, ecap, len);
1674 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1679 * If we're just using this capability to anchor the list,
1680 * hide the real ID. Only count real ecaps. XXX PCI spec
1681 * indicates to use cap id = 0, version = 0, next = 0 if
1682 * ecaps are absent, hope users check all the way to next.
1685 *(__le32 *)&vdev->vconfig[epos] &=
1686 cpu_to_le32((0xffcU << 20));
1690 prev = (__le32 *)&vdev->vconfig[epos];
1691 epos = PCI_EXT_CAP_NEXT(header);
1695 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1701 * Nag about hardware bugs, hopefully to have vendors fix them, but at least
1702 * to collect a list of dependencies for the VF INTx pin quirk below.
1704 static const struct pci_device_id known_bogus_vf_intx_pin[] = {
1705 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
1710 * For each device we allocate a pci_config_map that indicates the
1711 * capability occupying each dword and thus the struct perm_bits we
1712 * use for read and write. We also allocate a virtualized config
1713 * space which tracks reads and writes to bits that we emulate for
1714 * the user. Initial values filled from device.
1716 * Using shared struct perm_bits between all vfio-pci devices saves
1717 * us from allocating cfg_size buffers for virt and write for every
1718 * device. We could remove vconfig and allocate individual buffers
1719 * for each area requiring emulated bits, but the array of pointers
1720 * would be comparable in size (at least for standard config space).
1722 int vfio_config_init(struct vfio_pci_core_device *vdev)
1724 struct pci_dev *pdev = vdev->pdev;
1729 * Config space, caps and ecaps are all dword aligned, so we could
1730 * use one byte per dword to record the type. However, there are
1731 * no requirements on the length of a capability, so the gap between
1732 * capabilities needs byte granularity.
1734 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1738 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1744 vdev->pci_config_map = map;
1745 vdev->vconfig = vconfig;
1747 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1748 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1749 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1751 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1755 vdev->bardirty = true;
1758 * XXX can we just pci_load_saved_state/pci_restore_state?
1759 * may need to rebuild vconfig after that
1762 /* For restore after reset */
1763 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1764 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1765 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1766 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1767 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1768 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1769 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1771 if (pdev->is_virtfn) {
1772 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1773 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1776 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
1777 * does not apply to VFs and VFs must implement this register
1778 * as read-only with value zero. Userspace is not readily able
1779 * to identify whether a device is a VF and thus that the pin
1780 * definition on the device is bogus should it violate this
1781 * requirement. We already virtualize the pin register for
1782 * other purposes, so we simply need to replace the bogus value
1783 * and consider VFs when we determine INTx IRQ count.
1785 if (vconfig[PCI_INTERRUPT_PIN] &&
1786 !pci_match_id(known_bogus_vf_intx_pin, pdev))
1788 "Hardware bug: VF reports bogus INTx pin %d\n",
1789 vconfig[PCI_INTERRUPT_PIN]);
1791 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
1793 if (pdev->no_command_memory) {
1795 * VFs and devices that set pdev->no_command_memory do not
1796 * implement the memory enable bit of the COMMAND register
1797 * therefore we'll not have it set in our initial copy of
1798 * config space after pci_enable_device(). For consistency
1799 * with PFs, set the virtual enable bit here.
1801 *(__le16 *)&vconfig[PCI_COMMAND] |=
1802 cpu_to_le16(PCI_COMMAND_MEMORY);
1805 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1806 vconfig[PCI_INTERRUPT_PIN] = 0;
1808 ret = vfio_cap_init(vdev);
1812 ret = vfio_ecap_init(vdev);
1820 vdev->pci_config_map = NULL;
1822 vdev->vconfig = NULL;
1823 return pcibios_err_to_errno(ret);
1826 void vfio_config_free(struct vfio_pci_core_device *vdev)
1828 kfree(vdev->vconfig);
1829 vdev->vconfig = NULL;
1830 kfree(vdev->pci_config_map);
1831 vdev->pci_config_map = NULL;
1832 if (vdev->msi_perm) {
1833 free_perm_bits(vdev->msi_perm);
1834 kfree(vdev->msi_perm);
1835 vdev->msi_perm = NULL;
1840 * Find the remaining number of bytes in a dword that match the given
1841 * position. Stop at either the end of the capability or the dword boundary.
1843 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_core_device *vdev,
1846 u8 cap = vdev->pci_config_map[pos];
1849 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1855 static ssize_t vfio_config_do_rw(struct vfio_pci_core_device *vdev, char __user *buf,
1856 size_t count, loff_t *ppos, bool iswrite)
1858 struct pci_dev *pdev = vdev->pdev;
1859 struct perm_bits *perm;
1861 int cap_start = 0, offset;
1865 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1866 *ppos + count > pdev->cfg_size)
1870 * Chop accesses into aligned chunks containing no more than a
1871 * single capability. Caller increments to the next chunk.
1873 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1874 if (count >= 4 && !(*ppos % 4))
1876 else if (count >= 2 && !(*ppos % 2))
1883 cap_id = vdev->pci_config_map[*ppos];
1885 if (cap_id == PCI_CAP_ID_INVALID) {
1886 perm = &unassigned_perms;
1888 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1892 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1893 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1895 perm = &ecap_perms[cap_id];
1896 cap_start = vfio_find_cap_start(vdev, *ppos);
1898 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1900 perm = &cap_perms[cap_id];
1902 if (cap_id == PCI_CAP_ID_MSI)
1903 perm = vdev->msi_perm;
1905 if (cap_id > PCI_CAP_ID_BASIC)
1906 cap_start = vfio_find_cap_start(vdev, *ppos);
1910 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1911 WARN_ON(cap_start > *ppos);
1913 offset = *ppos - cap_start;
1919 if (copy_from_user(&val, buf, count))
1922 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1925 ret = perm->readfn(vdev, *ppos, count,
1926 perm, offset, &val);
1931 if (copy_to_user(buf, &val, count))
1938 ssize_t vfio_pci_config_rw(struct vfio_pci_core_device *vdev, char __user *buf,
1939 size_t count, loff_t *ppos, bool iswrite)
1945 pos &= VFIO_PCI_OFFSET_MASK;
1948 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);