1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, HiSilicon Ltd.
6 #include <linux/device.h>
7 #include <linux/eventfd.h>
8 #include <linux/file.h>
9 #include <linux/hisi_acc_qm.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/vfio.h>
14 #include <linux/vfio_pci_core.h>
15 #include <linux/anon_inodes.h>
17 #include "hisi_acc_vfio_pci.h"
19 /* Return 0 on VM acc device ready, -ETIMEDOUT hardware timeout */
20 static int qm_wait_dev_not_ready(struct hisi_qm *qm)
24 return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE,
25 val, !(val & 0x1), MB_POLL_PERIOD_US,
30 * Each state Reg is checked 100 times,
31 * with a delay of 100 microseconds after each check
33 static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs)
38 state = readl(qm->io_base + regs);
39 while (state && check_times < ERROR_CHECK_TIMEOUT) {
40 udelay(CHECK_DELAY_TIME);
41 state = readl(qm->io_base + regs);
48 static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr,
53 if (nums < 1 || nums > QM_REGS_MAX_LEN)
56 for (i = 0; i < nums; i++) {
57 data[i] = readl(qm->io_base + reg_addr);
58 reg_addr += QM_REG_ADDR_OFFSET;
64 static int qm_write_regs(struct hisi_qm *qm, u32 reg,
69 if (nums < 1 || nums > QM_REGS_MAX_LEN)
72 for (i = 0; i < nums; i++)
73 writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET);
78 static int qm_get_vft(struct hisi_qm *qm, u32 *base)
84 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
88 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
89 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<
91 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
92 qp_num = (QM_SQC_VFT_NUM_MASK_V2 &
93 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
98 static int qm_get_sqc(struct hisi_qm *qm, u64 *addr)
102 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, 0, 0, 1);
106 *addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
107 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<
113 static int qm_get_cqc(struct hisi_qm *qm, u64 *addr)
117 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, 0, 0, 1);
121 *addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
122 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<
128 static int qm_get_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data)
130 struct device *dev = &qm->pdev->dev;
133 ret = qm_read_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1);
135 dev_err(dev, "failed to read QM_VF_AEQ_INT_MASK\n");
139 ret = qm_read_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1);
141 dev_err(dev, "failed to read QM_VF_EQ_INT_MASK\n");
145 ret = qm_read_regs(qm, QM_IFC_INT_SOURCE_V,
146 &vf_data->ifc_int_source, 1);
148 dev_err(dev, "failed to read QM_IFC_INT_SOURCE_V\n");
152 ret = qm_read_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1);
154 dev_err(dev, "failed to read QM_IFC_INT_MASK\n");
158 ret = qm_read_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1);
160 dev_err(dev, "failed to read QM_IFC_INT_SET_V\n");
164 ret = qm_read_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1);
166 dev_err(dev, "failed to read QM_PAGE_SIZE\n");
170 /* QM_EQC_DW has 7 regs */
171 ret = qm_read_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7);
173 dev_err(dev, "failed to read QM_EQC_DW\n");
177 /* QM_AEQC_DW has 7 regs */
178 ret = qm_read_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7);
180 dev_err(dev, "failed to read QM_AEQC_DW\n");
187 static int qm_set_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data)
189 struct device *dev = &qm->pdev->dev;
193 if (unlikely(hisi_qm_wait_mb_ready(qm))) {
194 dev_err(&qm->pdev->dev, "QM device is not ready to write\n");
198 ret = qm_write_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1);
200 dev_err(dev, "failed to write QM_VF_AEQ_INT_MASK\n");
204 ret = qm_write_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1);
206 dev_err(dev, "failed to write QM_VF_EQ_INT_MASK\n");
210 ret = qm_write_regs(qm, QM_IFC_INT_SOURCE_V,
211 &vf_data->ifc_int_source, 1);
213 dev_err(dev, "failed to write QM_IFC_INT_SOURCE_V\n");
217 ret = qm_write_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1);
219 dev_err(dev, "failed to write QM_IFC_INT_MASK\n");
223 ret = qm_write_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1);
225 dev_err(dev, "failed to write QM_IFC_INT_SET_V\n");
229 ret = qm_write_regs(qm, QM_QUE_ISO_CFG_V, &vf_data->que_iso_cfg, 1);
231 dev_err(dev, "failed to write QM_QUE_ISO_CFG_V\n");
235 ret = qm_write_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1);
237 dev_err(dev, "failed to write QM_PAGE_SIZE\n");
241 /* QM_EQC_DW has 7 regs */
242 ret = qm_write_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7);
244 dev_err(dev, "failed to write QM_EQC_DW\n");
248 /* QM_AEQC_DW has 7 regs */
249 ret = qm_write_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7);
251 dev_err(dev, "failed to write QM_AEQC_DW\n");
258 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd,
259 u16 index, u8 priority)
265 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
266 dbase = QM_DOORBELL_SQ_CQ_BASE_V2;
268 dbase = QM_DOORBELL_EQ_AEQ_BASE_V2;
270 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
271 ((u64)randata << QM_DB_RAND_SHIFT_V2) |
272 ((u64)index << QM_DB_INDEX_SHIFT_V2) |
273 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
275 writeq(doorbell, qm->io_base + dbase);
278 static int pf_qm_get_qp_num(struct hisi_qm *qm, int vf_id, u32 *rbase)
285 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
286 val & BIT(0), MB_POLL_PERIOD_US,
291 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
293 writel(0x0, qm->io_base + QM_VFT_CFG_TYPE);
294 writel(vf_id, qm->io_base + QM_VFT_CFG);
296 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
297 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
299 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
300 val & BIT(0), MB_POLL_PERIOD_US,
305 sqc_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |
306 ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) <<
308 *rbase = QM_SQC_VFT_BASE_MASK_V2 &
309 (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
310 qp_num = (QM_SQC_VFT_NUM_MASK_V2 &
311 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
316 static void qm_dev_cmd_init(struct hisi_qm *qm)
318 /* Clear VF communication status registers. */
319 writel(0x1, qm->io_base + QM_IFC_INT_SOURCE_V);
321 /* Enable pf and vf communication. */
322 writel(0x0, qm->io_base + QM_IFC_INT_MASK);
325 static int vf_qm_cache_wb(struct hisi_qm *qm)
329 writel(0x1, qm->io_base + QM_CACHE_WB_START);
330 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
331 val, val & BIT(0), MB_POLL_PERIOD_US,
332 MB_POLL_TIMEOUT_US)) {
333 dev_err(&qm->pdev->dev, "vf QM writeback sqc cache fail\n");
340 static void vf_qm_fun_reset(struct hisi_qm *qm)
344 for (i = 0; i < qm->qp_num; i++)
345 qm_db(qm, i, QM_DOORBELL_CMD_SQ, 0, 1);
348 static int vf_qm_func_stop(struct hisi_qm *qm)
350 return hisi_qm_mb(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0);
353 static int vf_qm_check_match(struct hisi_acc_vf_core_device *hisi_acc_vdev,
354 struct hisi_acc_vf_migration_file *migf)
356 struct acc_vf_data *vf_data = &migf->vf_data;
357 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
358 struct hisi_qm *pf_qm = hisi_acc_vdev->pf_qm;
359 struct device *dev = &vf_qm->pdev->dev;
363 if (migf->total_length < QM_MATCH_SIZE || hisi_acc_vdev->match_done)
366 if (vf_data->acc_magic != ACC_DEV_MAGIC) {
367 dev_err(dev, "failed to match ACC_DEV_MAGIC\n");
371 if (vf_data->dev_id != hisi_acc_vdev->vf_dev->device) {
372 dev_err(dev, "failed to match VF devices\n");
376 /* VF qp num check */
377 ret = qm_get_vft(vf_qm, &vf_qm->qp_base);
379 dev_err(dev, "failed to get vft qp nums\n");
383 if (ret != vf_data->qp_num) {
384 dev_err(dev, "failed to match VF qp num\n");
390 /* VF isolation state check */
391 ret = qm_read_regs(pf_qm, QM_QUE_ISO_CFG_V, &que_iso_state, 1);
393 dev_err(dev, "failed to read QM_QUE_ISO_CFG_V\n");
397 if (vf_data->que_iso_cfg != que_iso_state) {
398 dev_err(dev, "failed to match isolation state\n");
402 ret = qm_write_regs(vf_qm, QM_VF_STATE, &vf_data->vf_qm_state, 1);
404 dev_err(dev, "failed to write QM_VF_STATE\n");
408 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state;
409 hisi_acc_vdev->match_done = true;
413 static int vf_qm_get_match_data(struct hisi_acc_vf_core_device *hisi_acc_vdev,
414 struct acc_vf_data *vf_data)
416 struct hisi_qm *pf_qm = hisi_acc_vdev->pf_qm;
417 struct device *dev = &pf_qm->pdev->dev;
418 int vf_id = hisi_acc_vdev->vf_id;
421 vf_data->acc_magic = ACC_DEV_MAGIC;
423 vf_data->dev_id = hisi_acc_vdev->vf_dev->device;
425 /* VF qp num save from PF */
426 ret = pf_qm_get_qp_num(pf_qm, vf_id, &vf_data->qp_base);
428 dev_err(dev, "failed to get vft qp nums!\n");
432 vf_data->qp_num = ret;
434 /* VF isolation state save from PF */
435 ret = qm_read_regs(pf_qm, QM_QUE_ISO_CFG_V, &vf_data->que_iso_cfg, 1);
437 dev_err(dev, "failed to read QM_QUE_ISO_CFG_V!\n");
444 static int vf_qm_load_data(struct hisi_acc_vf_core_device *hisi_acc_vdev,
445 struct hisi_acc_vf_migration_file *migf)
447 struct hisi_qm *qm = &hisi_acc_vdev->vf_qm;
448 struct device *dev = &qm->pdev->dev;
449 struct acc_vf_data *vf_data = &migf->vf_data;
452 /* Return if only match data was transferred */
453 if (migf->total_length == QM_MATCH_SIZE)
456 if (migf->total_length < sizeof(struct acc_vf_data))
459 qm->eqe_dma = vf_data->eqe_dma;
460 qm->aeqe_dma = vf_data->aeqe_dma;
461 qm->sqc_dma = vf_data->sqc_dma;
462 qm->cqc_dma = vf_data->cqc_dma;
464 qm->qp_base = vf_data->qp_base;
465 qm->qp_num = vf_data->qp_num;
467 ret = qm_set_regs(qm, vf_data);
469 dev_err(dev, "set VF regs failed\n");
473 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
475 dev_err(dev, "set sqc failed\n");
479 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
481 dev_err(dev, "set cqc failed\n");
489 static int vf_qm_state_save(struct hisi_acc_vf_core_device *hisi_acc_vdev,
490 struct hisi_acc_vf_migration_file *migf)
492 struct acc_vf_data *vf_data = &migf->vf_data;
493 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
494 struct device *dev = &vf_qm->pdev->dev;
497 if (unlikely(qm_wait_dev_not_ready(vf_qm))) {
498 /* Update state and return with match data */
499 vf_data->vf_qm_state = QM_NOT_READY;
500 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state;
501 migf->total_length = QM_MATCH_SIZE;
505 vf_data->vf_qm_state = QM_READY;
506 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state;
508 ret = vf_qm_cache_wb(vf_qm);
510 dev_err(dev, "failed to writeback QM Cache!\n");
514 ret = qm_get_regs(vf_qm, vf_data);
518 /* Every reg is 32 bit, the dma address is 64 bit. */
519 vf_data->eqe_dma = vf_data->qm_eqc_dw[1];
520 vf_data->eqe_dma <<= QM_XQC_ADDR_OFFSET;
521 vf_data->eqe_dma |= vf_data->qm_eqc_dw[0];
522 vf_data->aeqe_dma = vf_data->qm_aeqc_dw[1];
523 vf_data->aeqe_dma <<= QM_XQC_ADDR_OFFSET;
524 vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[0];
526 /* Through SQC_BT/CQC_BT to get sqc and cqc address */
527 ret = qm_get_sqc(vf_qm, &vf_data->sqc_dma);
529 dev_err(dev, "failed to read SQC addr!\n");
533 ret = qm_get_cqc(vf_qm, &vf_data->cqc_dma);
535 dev_err(dev, "failed to read CQC addr!\n");
539 migf->total_length = sizeof(struct acc_vf_data);
543 static struct hisi_acc_vf_core_device *hisi_acc_drvdata(struct pci_dev *pdev)
545 struct vfio_pci_core_device *core_device = dev_get_drvdata(&pdev->dev);
547 return container_of(core_device, struct hisi_acc_vf_core_device,
551 /* Check the PF's RAS state and Function INT state */
553 hisi_acc_check_int_state(struct hisi_acc_vf_core_device *hisi_acc_vdev)
555 struct hisi_qm *vfqm = &hisi_acc_vdev->vf_qm;
556 struct hisi_qm *qm = hisi_acc_vdev->pf_qm;
557 struct pci_dev *vf_pdev = hisi_acc_vdev->vf_dev;
558 struct device *dev = &qm->pdev->dev;
561 /* Check RAS state */
562 state = qm_check_reg_state(qm, QM_ABNORMAL_INT_STATUS);
564 dev_err(dev, "failed to check QM RAS state!\n");
568 /* Check Function Communication state between PF and VF */
569 state = qm_check_reg_state(vfqm, QM_IFC_INT_STATUS);
571 dev_err(dev, "failed to check QM IFC INT state!\n");
574 state = qm_check_reg_state(vfqm, QM_IFC_INT_SET_V);
576 dev_err(dev, "failed to check QM IFC INT SET state!\n");
580 /* Check submodule task state */
581 switch (vf_pdev->device) {
582 case PCI_DEVICE_ID_HUAWEI_SEC_VF:
583 state = qm_check_reg_state(qm, SEC_CORE_INT_STATUS);
585 dev_err(dev, "failed to check QM SEC Core INT state!\n");
589 case PCI_DEVICE_ID_HUAWEI_HPRE_VF:
590 state = qm_check_reg_state(qm, HPRE_HAC_INT_STATUS);
592 dev_err(dev, "failed to check QM HPRE HAC INT state!\n");
596 case PCI_DEVICE_ID_HUAWEI_ZIP_VF:
597 state = qm_check_reg_state(qm, HZIP_CORE_INT_STATUS);
599 dev_err(dev, "failed to check QM ZIP Core INT state!\n");
604 dev_err(dev, "failed to detect acc module type!\n");
609 static void hisi_acc_vf_disable_fd(struct hisi_acc_vf_migration_file *migf)
611 mutex_lock(&migf->lock);
612 migf->disabled = true;
613 migf->total_length = 0;
614 migf->filp->f_pos = 0;
615 mutex_unlock(&migf->lock);
618 static void hisi_acc_vf_disable_fds(struct hisi_acc_vf_core_device *hisi_acc_vdev)
620 if (hisi_acc_vdev->resuming_migf) {
621 hisi_acc_vf_disable_fd(hisi_acc_vdev->resuming_migf);
622 fput(hisi_acc_vdev->resuming_migf->filp);
623 hisi_acc_vdev->resuming_migf = NULL;
626 if (hisi_acc_vdev->saving_migf) {
627 hisi_acc_vf_disable_fd(hisi_acc_vdev->saving_migf);
628 fput(hisi_acc_vdev->saving_migf->filp);
629 hisi_acc_vdev->saving_migf = NULL;
634 * This function is called in all state_mutex unlock cases to
635 * handle a 'deferred_reset' if exists.
638 hisi_acc_vf_state_mutex_unlock(struct hisi_acc_vf_core_device *hisi_acc_vdev)
641 spin_lock(&hisi_acc_vdev->reset_lock);
642 if (hisi_acc_vdev->deferred_reset) {
643 hisi_acc_vdev->deferred_reset = false;
644 spin_unlock(&hisi_acc_vdev->reset_lock);
645 hisi_acc_vdev->vf_qm_state = QM_NOT_READY;
646 hisi_acc_vdev->mig_state = VFIO_DEVICE_STATE_RUNNING;
647 hisi_acc_vf_disable_fds(hisi_acc_vdev);
650 mutex_unlock(&hisi_acc_vdev->state_mutex);
651 spin_unlock(&hisi_acc_vdev->reset_lock);
654 static void hisi_acc_vf_start_device(struct hisi_acc_vf_core_device *hisi_acc_vdev)
656 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
658 if (hisi_acc_vdev->vf_qm_state != QM_READY)
661 /* Make sure the device is enabled */
662 qm_dev_cmd_init(vf_qm);
664 vf_qm_fun_reset(vf_qm);
667 static int hisi_acc_vf_load_state(struct hisi_acc_vf_core_device *hisi_acc_vdev)
669 struct device *dev = &hisi_acc_vdev->vf_dev->dev;
670 struct hisi_acc_vf_migration_file *migf = hisi_acc_vdev->resuming_migf;
673 /* Recover data to VF */
674 ret = vf_qm_load_data(hisi_acc_vdev, migf);
676 dev_err(dev, "failed to recover the VF!\n");
683 static int hisi_acc_vf_release_file(struct inode *inode, struct file *filp)
685 struct hisi_acc_vf_migration_file *migf = filp->private_data;
687 hisi_acc_vf_disable_fd(migf);
688 mutex_destroy(&migf->lock);
693 static ssize_t hisi_acc_vf_resume_write(struct file *filp, const char __user *buf,
694 size_t len, loff_t *pos)
696 struct hisi_acc_vf_migration_file *migf = filp->private_data;
697 u8 *vf_data = (u8 *)&migf->vf_data;
698 loff_t requested_length;
707 check_add_overflow((loff_t)len, *pos, &requested_length))
710 if (requested_length > sizeof(struct acc_vf_data))
713 mutex_lock(&migf->lock);
714 if (migf->disabled) {
719 ret = copy_from_user(vf_data + *pos, buf, len);
726 migf->total_length += len;
728 ret = vf_qm_check_match(migf->hisi_acc_vdev, migf);
732 mutex_unlock(&migf->lock);
736 static const struct file_operations hisi_acc_vf_resume_fops = {
737 .owner = THIS_MODULE,
738 .write = hisi_acc_vf_resume_write,
739 .release = hisi_acc_vf_release_file,
743 static struct hisi_acc_vf_migration_file *
744 hisi_acc_vf_pci_resume(struct hisi_acc_vf_core_device *hisi_acc_vdev)
746 struct hisi_acc_vf_migration_file *migf;
748 migf = kzalloc(sizeof(*migf), GFP_KERNEL_ACCOUNT);
750 return ERR_PTR(-ENOMEM);
752 migf->filp = anon_inode_getfile("hisi_acc_vf_mig", &hisi_acc_vf_resume_fops, migf,
754 if (IS_ERR(migf->filp)) {
755 int err = PTR_ERR(migf->filp);
761 stream_open(migf->filp->f_inode, migf->filp);
762 mutex_init(&migf->lock);
763 migf->hisi_acc_vdev = hisi_acc_vdev;
767 static long hisi_acc_vf_precopy_ioctl(struct file *filp,
768 unsigned int cmd, unsigned long arg)
770 struct hisi_acc_vf_migration_file *migf = filp->private_data;
771 struct hisi_acc_vf_core_device *hisi_acc_vdev = migf->hisi_acc_vdev;
772 loff_t *pos = &filp->f_pos;
773 struct vfio_precopy_info info;
777 if (cmd != VFIO_MIG_GET_PRECOPY_INFO)
780 minsz = offsetofend(struct vfio_precopy_info, dirty_bytes);
782 if (copy_from_user(&info, (void __user *)arg, minsz))
784 if (info.argsz < minsz)
787 mutex_lock(&hisi_acc_vdev->state_mutex);
788 if (hisi_acc_vdev->mig_state != VFIO_DEVICE_STATE_PRE_COPY) {
789 mutex_unlock(&hisi_acc_vdev->state_mutex);
793 mutex_lock(&migf->lock);
795 if (migf->disabled) {
800 if (*pos > migf->total_length) {
805 info.dirty_bytes = 0;
806 info.initial_bytes = migf->total_length - *pos;
808 ret = copy_to_user((void __user *)arg, &info, minsz) ? -EFAULT : 0;
810 mutex_unlock(&migf->lock);
811 mutex_unlock(&hisi_acc_vdev->state_mutex);
815 static ssize_t hisi_acc_vf_save_read(struct file *filp, char __user *buf, size_t len,
818 struct hisi_acc_vf_migration_file *migf = filp->private_data;
826 mutex_lock(&migf->lock);
827 if (*pos > migf->total_length) {
832 if (migf->disabled) {
837 len = min_t(size_t, migf->total_length - *pos, len);
839 u8 *vf_data = (u8 *)&migf->vf_data;
841 ret = copy_to_user(buf, vf_data + *pos, len);
850 mutex_unlock(&migf->lock);
854 static const struct file_operations hisi_acc_vf_save_fops = {
855 .owner = THIS_MODULE,
856 .read = hisi_acc_vf_save_read,
857 .unlocked_ioctl = hisi_acc_vf_precopy_ioctl,
858 .compat_ioctl = compat_ptr_ioctl,
859 .release = hisi_acc_vf_release_file,
863 static struct hisi_acc_vf_migration_file *
864 hisi_acc_open_saving_migf(struct hisi_acc_vf_core_device *hisi_acc_vdev)
866 struct hisi_acc_vf_migration_file *migf;
869 migf = kzalloc(sizeof(*migf), GFP_KERNEL_ACCOUNT);
871 return ERR_PTR(-ENOMEM);
873 migf->filp = anon_inode_getfile("hisi_acc_vf_mig", &hisi_acc_vf_save_fops, migf,
875 if (IS_ERR(migf->filp)) {
876 int err = PTR_ERR(migf->filp);
882 stream_open(migf->filp->f_inode, migf->filp);
883 mutex_init(&migf->lock);
884 migf->hisi_acc_vdev = hisi_acc_vdev;
886 ret = vf_qm_get_match_data(hisi_acc_vdev, &migf->vf_data);
895 static struct hisi_acc_vf_migration_file *
896 hisi_acc_vf_pre_copy(struct hisi_acc_vf_core_device *hisi_acc_vdev)
898 struct hisi_acc_vf_migration_file *migf;
900 migf = hisi_acc_open_saving_migf(hisi_acc_vdev);
904 migf->total_length = QM_MATCH_SIZE;
908 static struct hisi_acc_vf_migration_file *
909 hisi_acc_vf_stop_copy(struct hisi_acc_vf_core_device *hisi_acc_vdev, bool open)
912 struct hisi_acc_vf_migration_file *migf = NULL;
916 * Userspace didn't use PRECOPY support. Hence saving_migf
919 migf = hisi_acc_open_saving_migf(hisi_acc_vdev);
923 migf = hisi_acc_vdev->saving_migf;
926 ret = vf_qm_state_save(hisi_acc_vdev, migf);
930 return open ? migf : NULL;
933 static int hisi_acc_vf_stop_device(struct hisi_acc_vf_core_device *hisi_acc_vdev)
935 struct device *dev = &hisi_acc_vdev->vf_dev->dev;
936 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
939 ret = vf_qm_func_stop(vf_qm);
941 dev_err(dev, "failed to stop QM VF function!\n");
945 ret = hisi_acc_check_int_state(hisi_acc_vdev);
947 dev_err(dev, "failed to check QM INT state!\n");
954 hisi_acc_vf_set_device_state(struct hisi_acc_vf_core_device *hisi_acc_vdev,
957 u32 cur = hisi_acc_vdev->mig_state;
960 if (cur == VFIO_DEVICE_STATE_RUNNING && new == VFIO_DEVICE_STATE_PRE_COPY) {
961 struct hisi_acc_vf_migration_file *migf;
963 migf = hisi_acc_vf_pre_copy(hisi_acc_vdev);
965 return ERR_CAST(migf);
966 get_file(migf->filp);
967 hisi_acc_vdev->saving_migf = migf;
971 if (cur == VFIO_DEVICE_STATE_PRE_COPY && new == VFIO_DEVICE_STATE_STOP_COPY) {
972 struct hisi_acc_vf_migration_file *migf;
974 ret = hisi_acc_vf_stop_device(hisi_acc_vdev);
978 migf = hisi_acc_vf_stop_copy(hisi_acc_vdev, false);
980 return ERR_CAST(migf);
985 if (cur == VFIO_DEVICE_STATE_RUNNING && new == VFIO_DEVICE_STATE_STOP) {
986 ret = hisi_acc_vf_stop_device(hisi_acc_vdev);
992 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_STOP_COPY) {
993 struct hisi_acc_vf_migration_file *migf;
995 migf = hisi_acc_vf_stop_copy(hisi_acc_vdev, true);
997 return ERR_CAST(migf);
998 get_file(migf->filp);
999 hisi_acc_vdev->saving_migf = migf;
1003 if ((cur == VFIO_DEVICE_STATE_STOP_COPY && new == VFIO_DEVICE_STATE_STOP)) {
1004 hisi_acc_vf_disable_fds(hisi_acc_vdev);
1008 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_RESUMING) {
1009 struct hisi_acc_vf_migration_file *migf;
1011 migf = hisi_acc_vf_pci_resume(hisi_acc_vdev);
1013 return ERR_CAST(migf);
1014 get_file(migf->filp);
1015 hisi_acc_vdev->resuming_migf = migf;
1019 if (cur == VFIO_DEVICE_STATE_RESUMING && new == VFIO_DEVICE_STATE_STOP) {
1020 ret = hisi_acc_vf_load_state(hisi_acc_vdev);
1022 return ERR_PTR(ret);
1023 hisi_acc_vf_disable_fds(hisi_acc_vdev);
1027 if (cur == VFIO_DEVICE_STATE_PRE_COPY && new == VFIO_DEVICE_STATE_RUNNING) {
1028 hisi_acc_vf_disable_fds(hisi_acc_vdev);
1032 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_RUNNING) {
1033 hisi_acc_vf_start_device(hisi_acc_vdev);
1038 * vfio_mig_get_next_state() does not use arcs other than the above
1041 return ERR_PTR(-EINVAL);
1044 static struct file *
1045 hisi_acc_vfio_pci_set_device_state(struct vfio_device *vdev,
1046 enum vfio_device_mig_state new_state)
1048 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(vdev,
1049 struct hisi_acc_vf_core_device, core_device.vdev);
1050 enum vfio_device_mig_state next_state;
1051 struct file *res = NULL;
1054 mutex_lock(&hisi_acc_vdev->state_mutex);
1055 while (new_state != hisi_acc_vdev->mig_state) {
1056 ret = vfio_mig_get_next_state(vdev,
1057 hisi_acc_vdev->mig_state,
1058 new_state, &next_state);
1060 res = ERR_PTR(-EINVAL);
1064 res = hisi_acc_vf_set_device_state(hisi_acc_vdev, next_state);
1067 hisi_acc_vdev->mig_state = next_state;
1068 if (WARN_ON(res && new_state != hisi_acc_vdev->mig_state)) {
1070 res = ERR_PTR(-EINVAL);
1074 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev);
1079 hisi_acc_vfio_pci_get_data_size(struct vfio_device *vdev,
1080 unsigned long *stop_copy_length)
1082 *stop_copy_length = sizeof(struct acc_vf_data);
1087 hisi_acc_vfio_pci_get_device_state(struct vfio_device *vdev,
1088 enum vfio_device_mig_state *curr_state)
1090 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(vdev,
1091 struct hisi_acc_vf_core_device, core_device.vdev);
1093 mutex_lock(&hisi_acc_vdev->state_mutex);
1094 *curr_state = hisi_acc_vdev->mig_state;
1095 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev);
1099 static void hisi_acc_vf_pci_aer_reset_done(struct pci_dev *pdev)
1101 struct hisi_acc_vf_core_device *hisi_acc_vdev = hisi_acc_drvdata(pdev);
1103 if (hisi_acc_vdev->core_device.vdev.migration_flags !=
1104 VFIO_MIGRATION_STOP_COPY)
1108 * As the higher VFIO layers are holding locks across reset and using
1109 * those same locks with the mm_lock we need to prevent ABBA deadlock
1110 * with the state_mutex and mm_lock.
1111 * In case the state_mutex was taken already we defer the cleanup work
1112 * to the unlock flow of the other running context.
1114 spin_lock(&hisi_acc_vdev->reset_lock);
1115 hisi_acc_vdev->deferred_reset = true;
1116 if (!mutex_trylock(&hisi_acc_vdev->state_mutex)) {
1117 spin_unlock(&hisi_acc_vdev->reset_lock);
1120 spin_unlock(&hisi_acc_vdev->reset_lock);
1121 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev);
1124 static int hisi_acc_vf_qm_init(struct hisi_acc_vf_core_device *hisi_acc_vdev)
1126 struct vfio_pci_core_device *vdev = &hisi_acc_vdev->core_device;
1127 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
1128 struct pci_dev *vf_dev = vdev->pdev;
1131 * ACC VF dev BAR2 region consists of both functional register space
1132 * and migration control register space. For migration to work, we
1133 * need access to both. Hence, we map the entire BAR2 region here.
1134 * But unnecessarily exposing the migration BAR region to the Guest
1135 * has the potential to prevent/corrupt the Guest migration. Hence,
1136 * we restrict access to the migration control space from
1137 * Guest(Please see mmap/ioctl/read/write override functions).
1139 * Please note that it is OK to expose the entire VF BAR if migration
1140 * is not supported or required as this cannot affect the ACC PF
1143 * Also the HiSilicon ACC VF devices supported by this driver on
1144 * HiSilicon hardware platforms are integrated end point devices
1145 * and the platform lacks the capability to perform any PCIe P2P
1146 * between these devices.
1150 ioremap(pci_resource_start(vf_dev, VFIO_PCI_BAR2_REGION_INDEX),
1151 pci_resource_len(vf_dev, VFIO_PCI_BAR2_REGION_INDEX));
1152 if (!vf_qm->io_base)
1155 vf_qm->fun_type = QM_HW_VF;
1156 vf_qm->pdev = vf_dev;
1157 mutex_init(&vf_qm->mailbox_lock);
1162 static struct hisi_qm *hisi_acc_get_pf_qm(struct pci_dev *pdev)
1164 struct hisi_qm *pf_qm;
1165 struct pci_driver *pf_driver;
1167 if (!pdev->is_virtfn)
1170 switch (pdev->device) {
1171 case PCI_DEVICE_ID_HUAWEI_SEC_VF:
1172 pf_driver = hisi_sec_get_pf_driver();
1174 case PCI_DEVICE_ID_HUAWEI_HPRE_VF:
1175 pf_driver = hisi_hpre_get_pf_driver();
1177 case PCI_DEVICE_ID_HUAWEI_ZIP_VF:
1178 pf_driver = hisi_zip_get_pf_driver();
1187 pf_qm = pci_iov_get_pf_drvdata(pdev, pf_driver);
1189 return !IS_ERR(pf_qm) ? pf_qm : NULL;
1192 static int hisi_acc_pci_rw_access_check(struct vfio_device *core_vdev,
1193 size_t count, loff_t *ppos,
1196 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
1197 struct vfio_pci_core_device *vdev =
1198 container_of(core_vdev, struct vfio_pci_core_device, vdev);
1200 if (index == VFIO_PCI_BAR2_REGION_INDEX) {
1201 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
1202 resource_size_t end = pci_resource_len(vdev->pdev, index) / 2;
1204 /* Check if access is for migration control region */
1208 *new_count = min(count, (size_t)(end - pos));
1214 static int hisi_acc_vfio_pci_mmap(struct vfio_device *core_vdev,
1215 struct vm_area_struct *vma)
1217 struct vfio_pci_core_device *vdev =
1218 container_of(core_vdev, struct vfio_pci_core_device, vdev);
1221 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT);
1222 if (index == VFIO_PCI_BAR2_REGION_INDEX) {
1223 u64 req_len, pgoff, req_start;
1224 resource_size_t end = pci_resource_len(vdev->pdev, index) / 2;
1226 req_len = vma->vm_end - vma->vm_start;
1227 pgoff = vma->vm_pgoff &
1228 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1);
1229 req_start = pgoff << PAGE_SHIFT;
1231 if (req_start + req_len > end)
1235 return vfio_pci_core_mmap(core_vdev, vma);
1238 static ssize_t hisi_acc_vfio_pci_write(struct vfio_device *core_vdev,
1239 const char __user *buf, size_t count,
1242 size_t new_count = count;
1245 ret = hisi_acc_pci_rw_access_check(core_vdev, count, ppos, &new_count);
1249 return vfio_pci_core_write(core_vdev, buf, new_count, ppos);
1252 static ssize_t hisi_acc_vfio_pci_read(struct vfio_device *core_vdev,
1253 char __user *buf, size_t count,
1256 size_t new_count = count;
1259 ret = hisi_acc_pci_rw_access_check(core_vdev, count, ppos, &new_count);
1263 return vfio_pci_core_read(core_vdev, buf, new_count, ppos);
1266 static long hisi_acc_vfio_pci_ioctl(struct vfio_device *core_vdev, unsigned int cmd,
1269 if (cmd == VFIO_DEVICE_GET_REGION_INFO) {
1270 struct vfio_pci_core_device *vdev =
1271 container_of(core_vdev, struct vfio_pci_core_device, vdev);
1272 struct pci_dev *pdev = vdev->pdev;
1273 struct vfio_region_info info;
1274 unsigned long minsz;
1276 minsz = offsetofend(struct vfio_region_info, offset);
1278 if (copy_from_user(&info, (void __user *)arg, minsz))
1281 if (info.argsz < minsz)
1284 if (info.index == VFIO_PCI_BAR2_REGION_INDEX) {
1285 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index);
1288 * ACC VF dev BAR2 region consists of both functional
1289 * register space and migration control register space.
1290 * Report only the functional region to Guest.
1292 info.size = pci_resource_len(pdev, info.index) / 2;
1294 info.flags = VFIO_REGION_INFO_FLAG_READ |
1295 VFIO_REGION_INFO_FLAG_WRITE |
1296 VFIO_REGION_INFO_FLAG_MMAP;
1298 return copy_to_user((void __user *)arg, &info, minsz) ?
1302 return vfio_pci_core_ioctl(core_vdev, cmd, arg);
1305 static int hisi_acc_vfio_pci_open_device(struct vfio_device *core_vdev)
1307 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev,
1308 struct hisi_acc_vf_core_device, core_device.vdev);
1309 struct vfio_pci_core_device *vdev = &hisi_acc_vdev->core_device;
1312 ret = vfio_pci_core_enable(vdev);
1316 if (core_vdev->mig_ops) {
1317 ret = hisi_acc_vf_qm_init(hisi_acc_vdev);
1319 vfio_pci_core_disable(vdev);
1322 hisi_acc_vdev->mig_state = VFIO_DEVICE_STATE_RUNNING;
1325 vfio_pci_core_finish_enable(vdev);
1329 static void hisi_acc_vfio_pci_close_device(struct vfio_device *core_vdev)
1331 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev,
1332 struct hisi_acc_vf_core_device, core_device.vdev);
1333 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm;
1335 iounmap(vf_qm->io_base);
1336 vfio_pci_core_close_device(core_vdev);
1339 static const struct vfio_migration_ops hisi_acc_vfio_pci_migrn_state_ops = {
1340 .migration_set_state = hisi_acc_vfio_pci_set_device_state,
1341 .migration_get_state = hisi_acc_vfio_pci_get_device_state,
1342 .migration_get_data_size = hisi_acc_vfio_pci_get_data_size,
1345 static int hisi_acc_vfio_pci_migrn_init_dev(struct vfio_device *core_vdev)
1347 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev,
1348 struct hisi_acc_vf_core_device, core_device.vdev);
1349 struct pci_dev *pdev = to_pci_dev(core_vdev->dev);
1350 struct hisi_qm *pf_qm = hisi_acc_get_pf_qm(pdev);
1352 hisi_acc_vdev->vf_id = pci_iov_vf_id(pdev) + 1;
1353 hisi_acc_vdev->pf_qm = pf_qm;
1354 hisi_acc_vdev->vf_dev = pdev;
1355 mutex_init(&hisi_acc_vdev->state_mutex);
1357 core_vdev->migration_flags = VFIO_MIGRATION_STOP_COPY | VFIO_MIGRATION_PRE_COPY;
1358 core_vdev->mig_ops = &hisi_acc_vfio_pci_migrn_state_ops;
1360 return vfio_pci_core_init_dev(core_vdev);
1363 static const struct vfio_device_ops hisi_acc_vfio_pci_migrn_ops = {
1364 .name = "hisi-acc-vfio-pci-migration",
1365 .init = hisi_acc_vfio_pci_migrn_init_dev,
1366 .release = vfio_pci_core_release_dev,
1367 .open_device = hisi_acc_vfio_pci_open_device,
1368 .close_device = hisi_acc_vfio_pci_close_device,
1369 .ioctl = hisi_acc_vfio_pci_ioctl,
1370 .device_feature = vfio_pci_core_ioctl_feature,
1371 .read = hisi_acc_vfio_pci_read,
1372 .write = hisi_acc_vfio_pci_write,
1373 .mmap = hisi_acc_vfio_pci_mmap,
1374 .request = vfio_pci_core_request,
1375 .match = vfio_pci_core_match,
1376 .bind_iommufd = vfio_iommufd_physical_bind,
1377 .unbind_iommufd = vfio_iommufd_physical_unbind,
1378 .attach_ioas = vfio_iommufd_physical_attach_ioas,
1379 .detach_ioas = vfio_iommufd_physical_detach_ioas,
1382 static const struct vfio_device_ops hisi_acc_vfio_pci_ops = {
1383 .name = "hisi-acc-vfio-pci",
1384 .init = vfio_pci_core_init_dev,
1385 .release = vfio_pci_core_release_dev,
1386 .open_device = hisi_acc_vfio_pci_open_device,
1387 .close_device = vfio_pci_core_close_device,
1388 .ioctl = vfio_pci_core_ioctl,
1389 .device_feature = vfio_pci_core_ioctl_feature,
1390 .read = vfio_pci_core_read,
1391 .write = vfio_pci_core_write,
1392 .mmap = vfio_pci_core_mmap,
1393 .request = vfio_pci_core_request,
1394 .match = vfio_pci_core_match,
1395 .bind_iommufd = vfio_iommufd_physical_bind,
1396 .unbind_iommufd = vfio_iommufd_physical_unbind,
1397 .attach_ioas = vfio_iommufd_physical_attach_ioas,
1398 .detach_ioas = vfio_iommufd_physical_detach_ioas,
1401 static int hisi_acc_vfio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1403 struct hisi_acc_vf_core_device *hisi_acc_vdev;
1404 const struct vfio_device_ops *ops = &hisi_acc_vfio_pci_ops;
1405 struct hisi_qm *pf_qm;
1409 pf_qm = hisi_acc_get_pf_qm(pdev);
1410 if (pf_qm && pf_qm->ver >= QM_HW_V3) {
1411 vf_id = pci_iov_vf_id(pdev);
1413 ops = &hisi_acc_vfio_pci_migrn_ops;
1415 pci_warn(pdev, "migration support failed, continue with generic interface\n");
1418 hisi_acc_vdev = vfio_alloc_device(hisi_acc_vf_core_device,
1419 core_device.vdev, &pdev->dev, ops);
1420 if (IS_ERR(hisi_acc_vdev))
1421 return PTR_ERR(hisi_acc_vdev);
1423 dev_set_drvdata(&pdev->dev, &hisi_acc_vdev->core_device);
1424 ret = vfio_pci_core_register_device(&hisi_acc_vdev->core_device);
1430 vfio_put_device(&hisi_acc_vdev->core_device.vdev);
1434 static void hisi_acc_vfio_pci_remove(struct pci_dev *pdev)
1436 struct hisi_acc_vf_core_device *hisi_acc_vdev = hisi_acc_drvdata(pdev);
1438 vfio_pci_core_unregister_device(&hisi_acc_vdev->core_device);
1439 vfio_put_device(&hisi_acc_vdev->core_device.vdev);
1442 static const struct pci_device_id hisi_acc_vfio_pci_table[] = {
1443 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) },
1444 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) },
1445 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) },
1449 MODULE_DEVICE_TABLE(pci, hisi_acc_vfio_pci_table);
1451 static const struct pci_error_handlers hisi_acc_vf_err_handlers = {
1452 .reset_done = hisi_acc_vf_pci_aer_reset_done,
1453 .error_detected = vfio_pci_core_aer_err_detected,
1456 static struct pci_driver hisi_acc_vfio_pci_driver = {
1457 .name = KBUILD_MODNAME,
1458 .id_table = hisi_acc_vfio_pci_table,
1459 .probe = hisi_acc_vfio_pci_probe,
1460 .remove = hisi_acc_vfio_pci_remove,
1461 .err_handler = &hisi_acc_vf_err_handlers,
1462 .driver_managed_dma = true,
1465 module_pci_driver(hisi_acc_vfio_pci_driver);
1467 MODULE_LICENSE("GPL v2");
1468 MODULE_AUTHOR("Liu Longfang <liulongfang@huawei.com>");
1469 MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
1470 MODULE_DESCRIPTION("HiSilicon VFIO PCI - VFIO PCI driver with live migration support for HiSilicon ACC device family");