drivers/usb_ohci.c

   1 /*
   2  * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
   3  *
   4  * Interrupt support is added. Now, it has been tested
   5  * on ULI1575 chip and works well with USB keyboard.
   6  *
   7  * (C) Copyright 2007
   8  * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
   9  *
  10  * (C) Copyright 2003
  11  * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  12  *
  13  * Note: Much of this code has been derived from Linux 2.4
  14  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  15  * (C) Copyright 2000-2002 David Brownell
  16  *
  17  * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  18  * ebenard@eukrea.com - based on s3c24x0's driver
  19  *
  20  * See file CREDITS for list of people who contributed to this
  21  * project.
  22  *
  23  * This program is free software; you can redistribute it and/or
  24  * modify it under the terms of the GNU General Public License as
  25  * published by the Free Software Foundation; either version 2 of
  26  * the License, or (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36  * MA 02111-1307 USA
  37  *
  38  */
  39 /*
  40  * IMPORTANT NOTES
  41  * 1 - Read doc/README.generic_usb_ohci
  42  * 2 - this driver is intended for use with USB Mass Storage Devices
  43  *     (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  44  * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  45  *     to activate workaround for bug #41 or this driver will NOT work!
  46  */
  47
  48 #include <common.h>
  49
  50 #ifdef CONFIG_USB_OHCI_NEW
  51
  52 #include <asm/byteorder.h>
  53
  54 #if defined(CONFIG_PCI_OHCI)
  55 # include <pci.h>
  56 #endif
  57
  58 #include <malloc.h>
  59 #include <usb.h>
  60 #include "usb_ohci.h"
  61
  62 #if defined(CONFIG_ARM920T) || \
  63     defined(CONFIG_S3C2400) || \
  64     defined(CONFIG_S3C2410) || \
  65     defined(CONFIG_440EP) || \
  66     defined(CONFIG_PCI_OHCI) || \
  67     defined(CONFIG_MPC5200)
  68 # define OHCI_USE_NPS           /* force NoPowerSwitching mode */
  69 #endif
  70
  71 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  72 #undef DEBUG
  73 #undef SHOW_INFO
  74 #undef OHCI_FILL_TRACE
  75
  76 /* For initializing controller (mask in an HCFS mode too) */
  77 #define OHCI_CONTROL_INIT \
  78         (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  79
  80 /*
  81  * e.g. PCI controllers need this
  82  */
  83 #ifdef CFG_OHCI_SWAP_REG_ACCESS
  84 # define readl(a) __swap_32(*((vu_long *)(a)))
  85 # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
  86 #else
  87 # define readl(a) (*((vu_long *)(a)))
  88 # define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  89 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
  90
  91 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  92
  93 #ifdef CONFIG_PCI_OHCI
  94 static struct pci_device_id ohci_pci_ids[] = {
  95         {0x10b9, 0x5237},       /* ULI1575 PCI OHCI module ids */
  96         /* Please add supported PCI OHCI controller ids here */
  97         {0, 0}
  98 };
  99 #endif
 100
 101 #ifdef DEBUG
 102 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
 103 #else
 104 #define dbg(format, arg...) do {} while(0)
 105 #endif /* DEBUG */
 106 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
 107 #undef SHOW_INFO
 108 #ifdef SHOW_INFO
 109 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
 110 #else
 111 #define info(format, arg...) do {} while(0)
 112 #endif
 113
 114 #ifdef CFG_OHCI_BE_CONTROLLER
 115 # define m16_swap(x) cpu_to_be16(x)
 116 # define m32_swap(x) cpu_to_be32(x)
 117 #else
 118 # define m16_swap(x) cpu_to_le16(x)
 119 # define m32_swap(x) cpu_to_le32(x)
 120 #endif /* CFG_OHCI_BE_CONTROLLER */
 121
 122 /* global ohci_t */
 123 static ohci_t gohci;
 124 /* this must be aligned to a 256 byte boundary */
 125 struct ohci_hcca ghcca[1];
 126 /* a pointer to the aligned storage */
 127 struct ohci_hcca *phcca;
 128 /* this allocates EDs for all possible endpoints */
 129 struct ohci_device ohci_dev;
 130 /* RHSC flag */
 131 int got_rhsc;
 132 /* device which was disconnected */
 133 struct usb_device *devgone;
 134
 135
 136
 137 /*-------------------------------------------------------------------------*/
 138
 139 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
 140  * The erratum (#4) description is incorrect.  AMD's workaround waits
 141  * till some bits (mostly reserved) are clear; ok for all revs.
 142  */
 143 #define OHCI_QUIRK_AMD756 0xabcd
 144 #define read_roothub(hc, register, mask) ({ \
 145         u32 temp = readl (&hc->regs->roothub.register); \
 146         if (hc->flags & OHCI_QUIRK_AMD756) \
 147                 while (temp & mask) \
 148                         temp = readl (&hc->regs->roothub.register); \
 149         temp; })
 150
 151 static u32 roothub_a (struct ohci *hc)
 152         { return read_roothub (hc, a, 0xfc0fe000); }
 153 static inline u32 roothub_b (struct ohci *hc)
 154         { return readl (&hc->regs->roothub.b); }
 155 static inline u32 roothub_status (struct ohci *hc)
 156         { return readl (&hc->regs->roothub.status); }
 157 static u32 roothub_portstatus (struct ohci *hc, int i)
 158         { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
 159
 160
 161 /* forward declaration */
 162 static int hc_interrupt (void);
 163 static void
 164 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
 165         int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
 166
 167 /*-------------------------------------------------------------------------*
 168  * URB support functions
 169  *-------------------------------------------------------------------------*/
 170
 171 /* free HCD-private data associated with this URB */
 172
 173 static void urb_free_priv (urb_priv_t * urb)
 174 {
 175         int             i;
 176         int             last;
 177         struct td       * td;
 178
 179         last = urb->length - 1;
 180         if (last >= 0) {
 181                 for (i = 0; i <= last; i++) {
 182                         td = urb->td[i];
 183                         if (td) {
 184                                 td->usb_dev = NULL;
 185                                 urb->td[i] = NULL;
 186                         }
 187                 }
 188         }
 189         free(urb);
 190 }
 191
 192 /*-------------------------------------------------------------------------*/
 193
 194 #ifdef DEBUG
 195 static int sohci_get_current_frame_number (struct usb_device * dev);
 196
 197 /* debug| print the main components of an URB
 198  * small: 0) header + data packets 1) just header */
 199
 200 static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
 201         unsigned long pipe, void * buffer,
 202         int transfer_len, struct devrequest * setup, char * str, int small)
 203 {
 204         dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
 205                         str,
 206                         sohci_get_current_frame_number (dev),
 207                         usb_pipedevice (pipe),
 208                         usb_pipeendpoint (pipe),
 209                         usb_pipeout (pipe)? 'O': 'I',
 210                         usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
 211                                 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
 212                         (purb ? purb->actual_length : 0),
 213                         transfer_len, dev->status);
 214 #ifdef  OHCI_VERBOSE_DEBUG
 215         if (!small) {
 216                 int i, len;
 217
 218                 if (usb_pipecontrol (pipe)) {
 219                         printf (__FILE__ ": cmd(8):");
 220                         for (i = 0; i < 8 ; i++)
 221                                 printf (" %02x", ((__u8 *) setup) [i]);
 222                         printf ("\n");
 223                 }
 224                 if (transfer_len > 0 && buffer) {
 225                         printf (__FILE__ ": data(%d/%d):",
 226                                 (purb ? purb->actual_length : 0),
 227                                 transfer_len);
 228                         len = usb_pipeout (pipe)?
 229                                         transfer_len:
 230                                         (purb ? purb->actual_length : 0);
 231                         for (i = 0; i < 16 && i < len; i++)
 232                                 printf (" %02x", ((__u8 *) buffer) [i]);
 233                         printf ("%s\n", i < len? "...": "");
 234                 }
 235         }
 236 #endif
 237 }
 238
 239 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
 240 void ep_print_int_eds (ohci_t *ohci, char * str) {
 241         int i, j;
 242          __u32 * ed_p;
 243         for (i= 0; i < 32; i++) {
 244                 j = 5;
 245                 ed_p = &(ohci->hcca->int_table [i]);
 246                 if (*ed_p == 0)
 247                     continue;
 248                 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
 249                 while (*ed_p != 0 && j--) {
 250                         ed_t *ed = (ed_t *)m32_swap(ed_p);
 251                         printf (" ed: %4x;", ed->hwINFO);
 252                         ed_p = &ed->hwNextED;
 253                 }
 254                 printf ("\n");
 255         }
 256 }
 257
 258 static void ohci_dump_intr_mask (char *label, __u32 mask)
 259 {
 260         dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
 261                 label,
 262                 mask,
 263                 (mask & OHCI_INTR_MIE) ? " MIE" : "",
 264                 (mask & OHCI_INTR_OC) ? " OC" : "",
 265                 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
 266                 (mask & OHCI_INTR_FNO) ? " FNO" : "",
 267                 (mask & OHCI_INTR_UE) ? " UE" : "",
 268                 (mask & OHCI_INTR_RD) ? " RD" : "",
 269                 (mask & OHCI_INTR_SF) ? " SF" : "",
 270                 (mask & OHCI_INTR_WDH) ? " WDH" : "",
 271                 (mask & OHCI_INTR_SO) ? " SO" : ""
 272                 );
 273 }
 274
 275 static void maybe_print_eds (char *label, __u32 value)
 276 {
 277         ed_t *edp = (ed_t *)value;
 278
 279         if (value) {
 280                 dbg ("%s %08x", label, value);
 281                 dbg ("%08x", edp->hwINFO);
 282                 dbg ("%08x", edp->hwTailP);
 283                 dbg ("%08x", edp->hwHeadP);
 284                 dbg ("%08x", edp->hwNextED);
 285         }
 286 }
 287
 288 static char * hcfs2string (int state)
 289 {
 290         switch (state) {
 291                 case OHCI_USB_RESET:    return "reset";
 292                 case OHCI_USB_RESUME:   return "resume";
 293                 case OHCI_USB_OPER:     return "operational";
 294                 case OHCI_USB_SUSPEND:  return "suspend";
 295         }
 296         return "?";
 297 }
 298
 299 /* dump control and status registers */
 300 static void ohci_dump_status (ohci_t *controller)
 301 {
 302         struct ohci_regs        *regs = controller->regs;
 303         __u32                   temp;
 304
 305         temp = readl (&regs->revision) & 0xff;
 306         if (temp != 0x10)
 307                 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
 308
 309         temp = readl (&regs->control);
 310         dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 311                 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
 312                 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
 313                 (temp & OHCI_CTRL_IR) ? " IR" : "",
 314                 hcfs2string (temp & OHCI_CTRL_HCFS),
 315                 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
 316                 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
 317                 (temp & OHCI_CTRL_IE) ? " IE" : "",
 318                 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
 319                 temp & OHCI_CTRL_CBSR
 320                 );
 321
 322         temp = readl (&regs->cmdstatus);
 323         dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 324                 (temp & OHCI_SOC) >> 16,
 325                 (temp & OHCI_OCR) ? " OCR" : "",
 326                 (temp & OHCI_BLF) ? " BLF" : "",
 327                 (temp & OHCI_CLF) ? " CLF" : "",
 328                 (temp & OHCI_HCR) ? " HCR" : ""
 329                 );
 330
 331         ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
 332         ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
 333
 334         maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
 335
 336         maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
 337         maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
 338
 339         maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
 340         maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
 341
 342         maybe_print_eds ("donehead", readl (&regs->donehead));
 343 }
 344
 345 static void ohci_dump_roothub (ohci_t *controller, int verbose)
 346 {
 347         __u32                   temp, ndp, i;
 348
 349         temp = roothub_a (controller);
 350         ndp = (temp & RH_A_NDP);
 351 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 352         ndp = (ndp == 2) ? 1:0;
 353 #endif
 354         if (verbose) {
 355                 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
 356                         ((temp & RH_A_POTPGT) >> 24) & 0xff,
 357                         (temp & RH_A_NOCP) ? " NOCP" : "",
 358                         (temp & RH_A_OCPM) ? " OCPM" : "",
 359                         (temp & RH_A_DT) ? " DT" : "",
 360                         (temp & RH_A_NPS) ? " NPS" : "",
 361                         (temp & RH_A_PSM) ? " PSM" : "",
 362                         ndp
 363                         );
 364                 temp = roothub_b (controller);
 365                 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
 366                         temp,
 367                         (temp & RH_B_PPCM) >> 16,
 368                         (temp & RH_B_DR)
 369                         );
 370                 temp = roothub_status (controller);
 371                 dbg ("roothub.status: %08x%s%s%s%s%s%s",
 372                         temp,
 373                         (temp & RH_HS_CRWE) ? " CRWE" : "",
 374                         (temp & RH_HS_OCIC) ? " OCIC" : "",
 375                         (temp & RH_HS_LPSC) ? " LPSC" : "",
 376                         (temp & RH_HS_DRWE) ? " DRWE" : "",
 377                         (temp & RH_HS_OCI) ? " OCI" : "",
 378                         (temp & RH_HS_LPS) ? " LPS" : ""
 379                         );
 380         }
 381
 382         for (i = 0; i < ndp; i++) {
 383                 temp = roothub_portstatus (controller, i);
 384                 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
 385                         i,
 386                         temp,
 387                         (temp & RH_PS_PRSC) ? " PRSC" : "",
 388                         (temp & RH_PS_OCIC) ? " OCIC" : "",
 389                         (temp & RH_PS_PSSC) ? " PSSC" : "",
 390                         (temp & RH_PS_PESC) ? " PESC" : "",
 391                         (temp & RH_PS_CSC) ? " CSC" : "",
 392
 393                         (temp & RH_PS_LSDA) ? " LSDA" : "",
 394                         (temp & RH_PS_PPS) ? " PPS" : "",
 395                         (temp & RH_PS_PRS) ? " PRS" : "",
 396                         (temp & RH_PS_POCI) ? " POCI" : "",
 397                         (temp & RH_PS_PSS) ? " PSS" : "",
 398
 399                         (temp & RH_PS_PES) ? " PES" : "",
 400                         (temp & RH_PS_CCS) ? " CCS" : ""
 401                         );
 402         }
 403 }
 404
 405 static void ohci_dump (ohci_t *controller, int verbose)
 406 {
 407         dbg ("OHCI controller usb-%s state", controller->slot_name);
 408
 409         /* dumps some of the state we know about */
 410         ohci_dump_status (controller);
 411         if (verbose)
 412                 ep_print_int_eds (controller, "hcca");
 413         dbg ("hcca frame #%04x", controller->hcca->frame_no);
 414         ohci_dump_roothub (controller, 1);
 415 }
 416
 417
 418 #endif /* DEBUG */
 419
 420 /*-------------------------------------------------------------------------*
 421  * Interface functions (URB)
 422  *-------------------------------------------------------------------------*/
 423
 424 /* get a transfer request */
 425
 426 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
 427 {
 428         ohci_t *ohci;
 429         ed_t * ed;
 430         urb_priv_t *purb_priv = urb;
 431         int i, size = 0;
 432         struct usb_device *dev = urb->dev;
 433         unsigned long pipe = urb->pipe;
 434         void *buffer = urb->transfer_buffer;
 435         int transfer_len = urb->transfer_buffer_length;
 436         int interval = urb->interval;
 437
 438         ohci = &gohci;
 439
 440         /* when controller's hung, permit only roothub cleanup attempts
 441          * such as powering down ports */
 442         if (ohci->disabled) {
 443                 err("sohci_submit_job: EPIPE");
 444                 return -1;
 445         }
 446
 447         /* we're about to begin a new transaction here so mark the URB unfinished */
 448         urb->finished = 0;
 449
 450         /* every endpoint has a ed, locate and fill it */
 451         if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
 452                 err("sohci_submit_job: ENOMEM");
 453                 return -1;
 454         }
 455
 456         /* for the private part of the URB we need the number of TDs (size) */
 457         switch (usb_pipetype (pipe)) {
 458                 case PIPE_BULK: /* one TD for every 4096 Byte */
 459                         size = (transfer_len - 1) / 4096 + 1;
 460                         break;
 461                 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
 462                         size = (transfer_len == 0)? 2:
 463                                                 (transfer_len - 1) / 4096 + 3;
 464                         break;
 465                 case PIPE_INTERRUPT: /* 1 TD */
 466                         size = 1;
 467                         break;
 468         }
 469
 470         ed->purb = urb;
 471
 472         if (size >= (N_URB_TD - 1)) {
 473                 err("need %d TDs, only have %d", size, N_URB_TD);
 474                 return -1;
 475         }
 476         purb_priv->pipe = pipe;
 477
 478         /* fill the private part of the URB */
 479         purb_priv->length = size;
 480         purb_priv->ed = ed;
 481         purb_priv->actual_length = 0;
 482
 483         /* allocate the TDs */
 484         /* note that td[0] was allocated in ep_add_ed */
 485         for (i = 0; i < size; i++) {
 486                 purb_priv->td[i] = td_alloc (dev);
 487                 if (!purb_priv->td[i]) {
 488                         purb_priv->length = i;
 489                         urb_free_priv (purb_priv);
 490                         err("sohci_submit_job: ENOMEM");
 491                         return -1;
 492                 }
 493         }
 494
 495         if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
 496                 urb_free_priv (purb_priv);
 497                 err("sohci_submit_job: EINVAL");
 498                 return -1;
 499         }
 500
 501         /* link the ed into a chain if is not already */
 502         if (ed->state != ED_OPER)
 503                 ep_link (ohci, ed);
 504
 505         /* fill the TDs and link it to the ed */
 506         td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
 507
 508         return 0;
 509 }
 510
 511 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
 512 {
 513         struct ohci_regs *regs = hc->regs;
 514
 515         switch (usb_pipetype (urb->pipe)) {
 516         case PIPE_INTERRUPT:
 517                 /* implicitly requeued */
 518                 if (urb->dev->irq_handle &&
 519                                 (urb->dev->irq_act_len = urb->actual_length)) {
 520                         writel (OHCI_INTR_WDH, &regs->intrenable);
 521                         readl (&regs->intrenable); /* PCI posting flush */
 522                         urb->dev->irq_handle(urb->dev);
 523                         writel (OHCI_INTR_WDH, &regs->intrdisable);
 524                         readl (&regs->intrdisable); /* PCI posting flush */
 525                 }
 526                 urb->actual_length = 0;
 527                 td_submit_job (
 528                                 urb->dev,
 529                                 urb->pipe,
 530                                 urb->transfer_buffer,
 531                                 urb->transfer_buffer_length,
 532                                 NULL,
 533                                 urb,
 534                                 urb->interval);
 535                 break;
 536         case PIPE_CONTROL:
 537         case PIPE_BULK:
 538                 break;
 539         default:
 540                 return 0;
 541         }
 542         return 1;
 543 }
 544
 545 /*-------------------------------------------------------------------------*/
 546
 547 #ifdef DEBUG
 548 /* tell us the current USB frame number */
 549
 550 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
 551 {
 552         ohci_t *ohci = &gohci;
 553
 554         return m16_swap (ohci->hcca->frame_no);
 555 }
 556 #endif
 557
 558 /*-------------------------------------------------------------------------*
 559  * ED handling functions
 560  *-------------------------------------------------------------------------*/
 561
 562 /* search for the right branch to insert an interrupt ed into the int tree
 563  * do some load ballancing;
 564  * returns the branch and
 565  * sets the interval to interval = 2^integer (ld (interval)) */
 566
 567 static int ep_int_ballance (ohci_t * ohci, int interval, int load)
 568 {
 569         int i, branch = 0;
 570
 571         /* search for the least loaded interrupt endpoint
 572          * branch of all 32 branches
 573          */
 574         for (i = 0; i < 32; i++)
 575                 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
 576                         branch = i;
 577
 578         branch = branch % interval;
 579         for (i = branch; i < 32; i += interval)
 580                 ohci->ohci_int_load [i] += load;
 581
 582         return branch;
 583 }
 584
 585 /*-------------------------------------------------------------------------*/
 586
 587 /*  2^int( ld (inter)) */
 588
 589 static int ep_2_n_interval (int inter)
 590 {
 591         int i;
 592         for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
 593         return 1 << i;
 594 }
 595
 596 /*-------------------------------------------------------------------------*/
 597
 598 /* the int tree is a binary tree
 599  * in order to process it sequentially the indexes of the branches have to be mapped
 600  * the mapping reverses the bits of a word of num_bits length */
 601
 602 static int ep_rev (int num_bits, int word)
 603 {
 604         int i, wout = 0;
 605
 606         for (i = 0; i < num_bits; i++)
 607                 wout |= (((word >> i) & 1) << (num_bits - i - 1));
 608         return wout;
 609 }
 610
 611 /*-------------------------------------------------------------------------*
 612  * ED handling functions
 613  *-------------------------------------------------------------------------*/
 614
 615 /* link an ed into one of the HC chains */
 616
 617 static int ep_link (ohci_t *ohci, ed_t *edi)
 618 {
 619         volatile ed_t *ed = edi;
 620         int int_branch;
 621         int i;
 622         int inter;
 623         int interval;
 624         int load;
 625         __u32 * ed_p;
 626
 627         ed->state = ED_OPER;
 628         ed->int_interval = 0;
 629
 630         switch (ed->type) {
 631         case PIPE_CONTROL:
 632                 ed->hwNextED = 0;
 633                 if (ohci->ed_controltail == NULL) {
 634                         writel (ed, &ohci->regs->ed_controlhead);
 635                 } else {
 636                         ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
 637                 }
 638                 ed->ed_prev = ohci->ed_controltail;
 639                 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 640                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 641                         ohci->hc_control |= OHCI_CTRL_CLE;
 642                         writel (ohci->hc_control, &ohci->regs->control);
 643                 }
 644                 ohci->ed_controltail = edi;
 645                 break;
 646
 647         case PIPE_BULK:
 648                 ed->hwNextED = 0;
 649                 if (ohci->ed_bulktail == NULL) {
 650                         writel (ed, &ohci->regs->ed_bulkhead);
 651                 } else {
 652                         ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
 653                 }
 654                 ed->ed_prev = ohci->ed_bulktail;
 655                 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 656                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 657                         ohci->hc_control |= OHCI_CTRL_BLE;
 658                         writel (ohci->hc_control, &ohci->regs->control);
 659                 }
 660                 ohci->ed_bulktail = edi;
 661                 break;
 662
 663         case PIPE_INTERRUPT:
 664                 load = ed->int_load;
 665                 interval = ep_2_n_interval (ed->int_period);
 666                 ed->int_interval = interval;
 667                 int_branch = ep_int_ballance (ohci, interval, load);
 668                 ed->int_branch = int_branch;
 669
 670                 for (i = 0; i < ep_rev (6, interval); i += inter) {
 671                         inter = 1;
 672                         for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
 673                                 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
 674                                 ed_p = &(((ed_t *)ed_p)->hwNextED))
 675                                         inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
 676                         ed->hwNextED = *ed_p;
 677                         *ed_p = m32_swap(ed);
 678                 }
 679                 break;
 680         }
 681         return 0;
 682 }
 683
 684 /*-------------------------------------------------------------------------*/
 685
 686 /* scan the periodic table to find and unlink this ED */
 687 static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
 688                 unsigned index, unsigned period)
 689 {
 690         for (; index < NUM_INTS; index += period) {
 691                 __u32   *ed_p = &ohci->hcca->int_table [index];
 692
 693                 /* ED might have been unlinked through another path */
 694                 while (*ed_p != 0) {
 695                         if (((struct ed *)m32_swap (ed_p)) == ed) {
 696                                 *ed_p = ed->hwNextED;
 697                                 break;
 698                         }
 699                         ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED);
 700                 }
 701         }
 702 }
 703
 704
 705 /* unlink an ed from one of the HC chains.
 706  * just the link to the ed is unlinked.
 707  * the link from the ed still points to another operational ed or 0
 708  * so the HC can eventually finish the processing of the unlinked ed */
 709
 710 static int ep_unlink (ohci_t *ohci, ed_t *edi)
 711 {
 712         volatile ed_t *ed = edi;
 713         int i;
 714
 715         ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
 716
 717         switch (ed->type) {
 718         case PIPE_CONTROL:
 719                 if (ed->ed_prev == NULL) {
 720                         if (!ed->hwNextED) {
 721                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 722                                 writel (ohci->hc_control, &ohci->regs->control);
 723                         }
 724                         writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
 725                 } else {
 726                         ed->ed_prev->hwNextED = ed->hwNextED;
 727                 }
 728                 if (ohci->ed_controltail == ed) {
 729                         ohci->ed_controltail = ed->ed_prev;
 730                 } else {
 731                         ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 732                 }
 733                 break;
 734
 735         case PIPE_BULK:
 736                 if (ed->ed_prev == NULL) {
 737                         if (!ed->hwNextED) {
 738                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 739                                 writel (ohci->hc_control, &ohci->regs->control);
 740                         }
 741                         writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
 742                 } else {
 743                         ed->ed_prev->hwNextED = ed->hwNextED;
 744                 }
 745                 if (ohci->ed_bulktail == ed) {
 746                         ohci->ed_bulktail = ed->ed_prev;
 747                 } else {
 748                         ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 749                 }
 750                 break;
 751
 752         case PIPE_INTERRUPT:
 753                 periodic_unlink (ohci, ed, 0, 1);
 754                 for (i = ed->int_branch; i < 32; i += ed->int_interval)
 755                     ohci->ohci_int_load[i] -= ed->int_load;
 756                 break;
 757         }
 758         ed->state = ED_UNLINK;
 759         return 0;
 760 }
 761
 762
 763 /*-------------------------------------------------------------------------*/
 764
 765 /* add/reinit an endpoint; this should be done once at the
 766  * usb_set_configuration command, but the USB stack is a little bit
 767  * stateless so we do it at every transaction if the state of the ed
 768  * is ED_NEW then a dummy td is added and the state is changed to
 769  * ED_UNLINK in all other cases the state is left unchanged the ed
 770  * info fields are setted anyway even though most of them should not
 771  * change
 772  */
 773 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
 774                 int interval, int load)
 775 {
 776         td_t *td;
 777         ed_t *ed_ret;
 778         volatile ed_t *ed;
 779
 780         ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
 781                         (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
 782
 783         if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
 784                 err("ep_add_ed: pending delete");
 785                 /* pending delete request */
 786                 return NULL;
 787         }
 788
 789         if (ed->state == ED_NEW) {
 790                 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
 791                 /* dummy td; end of td list for ed */
 792                 td = td_alloc (usb_dev);
 793                 ed->hwTailP = m32_swap ((unsigned long)td);
 794                 ed->hwHeadP = ed->hwTailP;
 795                 ed->state = ED_UNLINK;
 796                 ed->type = usb_pipetype (pipe);
 797                 ohci_dev.ed_cnt++;
 798         }
 799
 800         ed->hwINFO = m32_swap (usb_pipedevice (pipe)
 801                         | usb_pipeendpoint (pipe) << 7
 802                         | (usb_pipeisoc (pipe)? 0x8000: 0)
 803                         | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
 804                         | usb_pipeslow (pipe) << 13
 805                         | usb_maxpacket (usb_dev, pipe) << 16);
 806
 807         if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
 808                 ed->int_period = interval;
 809                 ed->int_load = load;
 810         }
 811
 812         return ed_ret;
 813 }
 814
 815 /*-------------------------------------------------------------------------*
 816  * TD handling functions
 817  *-------------------------------------------------------------------------*/
 818
 819 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 820
 821 static void td_fill (ohci_t *ohci, unsigned int info,
 822         void *data, int len,
 823         struct usb_device *dev, int index, urb_priv_t *urb_priv)
 824 {
 825         volatile td_t  *td, *td_pt;
 826 #ifdef OHCI_FILL_TRACE
 827         int i;
 828 #endif
 829
 830         if (index > urb_priv->length) {
 831                 err("index > length");
 832                 return;
 833         }
 834         /* use this td as the next dummy */
 835         td_pt = urb_priv->td [index];
 836         td_pt->hwNextTD = 0;
 837
 838         /* fill the old dummy TD */
 839         td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
 840
 841         td->ed = urb_priv->ed;
 842         td->next_dl_td = NULL;
 843         td->index = index;
 844         td->data = (__u32)data;
 845 #ifdef OHCI_FILL_TRACE
 846         if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
 847                 for (i = 0; i < len; i++)
 848                 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
 849                 printf("\n");
 850         }
 851 #endif
 852         if (!len)
 853                 data = 0;
 854
 855         td->hwINFO = m32_swap (info);
 856         td->hwCBP = m32_swap ((unsigned long)data);
 857         if (data)
 858                 td->hwBE = m32_swap ((unsigned long)(data + len - 1));
 859         else
 860                 td->hwBE = 0;
 861         td->hwNextTD = m32_swap ((unsigned long)td_pt);
 862
 863         /* append to queue */
 864         td->ed->hwTailP = td->hwNextTD;
 865 }
 866
 867 /*-------------------------------------------------------------------------*/
 868
 869 /* prepare all TDs of a transfer */
 870
 871 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
 872         int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
 873 {
 874         ohci_t *ohci = &gohci;
 875         int data_len = transfer_len;
 876         void *data;
 877         int cnt = 0;
 878         __u32 info = 0;
 879         unsigned int toggle = 0;
 880
 881         /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
 882         if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
 883                 toggle = TD_T_TOGGLE;
 884         } else {
 885                 toggle = TD_T_DATA0;
 886                 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
 887         }
 888         urb->td_cnt = 0;
 889         if (data_len)
 890                 data = buffer;
 891         else
 892                 data = 0;
 893
 894         switch (usb_pipetype (pipe)) {
 895         case PIPE_BULK:
 896                 info = usb_pipeout (pipe)?
 897                         TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
 898                 while(data_len > 4096) {
 899                         td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
 900                         data += 4096; data_len -= 4096; cnt++;
 901                 }
 902                 info = usb_pipeout (pipe)?
 903                         TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
 904                 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
 905                 cnt++;
 906
 907                 if (!ohci->sleeping)
 908                         writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
 909                 break;
 910
 911         case PIPE_CONTROL:
 912                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 913                 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
 914                 if (data_len > 0) {
 915                         info = usb_pipeout (pipe)?
 916                                 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
 917                         /* NOTE:  mishandles transfers >8K, some >4K */
 918                         td_fill (ohci, info, data, data_len, dev, cnt++, urb);
 919                 }
 920                 info = usb_pipeout (pipe)?
 921                         TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
 922                 td_fill (ohci, info, data, 0, dev, cnt++, urb);
 923                 if (!ohci->sleeping)
 924                         writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
 925                 break;
 926
 927         case PIPE_INTERRUPT:
 928                 info = usb_pipeout (urb->pipe)?
 929                         TD_CC | TD_DP_OUT | toggle:
 930                         TD_CC | TD_R | TD_DP_IN | toggle;
 931                 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
 932                 break;
 933         }
 934         if (urb->length != cnt)
 935                 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
 936 }
 937
 938 /*-------------------------------------------------------------------------*
 939  * Done List handling functions
 940  *-------------------------------------------------------------------------*/
 941
 942
 943 /* calculate the transfer length and update the urb */
 944
 945 static void dl_transfer_length(td_t * td)
 946 {
 947         __u32 tdINFO, tdBE, tdCBP;
 948         urb_priv_t *lurb_priv = td->ed->purb;
 949
 950         tdINFO = m32_swap (td->hwINFO);
 951         tdBE   = m32_swap (td->hwBE);
 952         tdCBP  = m32_swap (td->hwCBP);
 953
 954
 955         if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
 956             ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
 957                 if (tdBE != 0) {
 958                         if (td->hwCBP == 0)
 959                                 lurb_priv->actual_length += tdBE - td->data + 1;
 960                         else
 961                                 lurb_priv->actual_length += tdCBP - td->data;
 962                 }
 963         }
 964 }
 965
 966 /*-------------------------------------------------------------------------*/
 967
 968 /* replies to the request have to be on a FIFO basis so
 969  * we reverse the reversed done-list */
 970
 971 static td_t * dl_reverse_done_list (ohci_t *ohci)
 972 {
 973         __u32 td_list_hc;
 974         td_t *td_rev = NULL;
 975         td_t *td_list = NULL;
 976         urb_priv_t *lurb_priv = NULL;
 977
 978         td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
 979         ohci->hcca->done_head = 0;
 980
 981         while (td_list_hc) {
 982                 td_list = (td_t *)td_list_hc;
 983
 984                 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
 985                         lurb_priv = td_list->ed->purb;
 986                         dbg(" USB-error/status: %x : %p",
 987                                         TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
 988                         if (td_list->ed->hwHeadP & m32_swap (0x1)) {
 989                                 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
 990                                         td_list->ed->hwHeadP =
 991                                                 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
 992                                                                         (td_list->ed->hwHeadP & m32_swap (0x2));
 993                                         lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
 994                                 } else
 995                                         td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
 996                         }
 997 #ifdef CONFIG_MPC5200
 998                         td_list->hwNextTD = 0;
 999 #endif
1000                 }
1001
1002                 td_list->next_dl_td = td_rev;
1003                 td_rev = td_list;
1004                 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
1005         }
1006         return td_list;
1007 }
1008
1009 /*-------------------------------------------------------------------------*/
1010
1011 /* td done list */
1012 static int dl_done_list (ohci_t *ohci, td_t *td_list)
1013 {
1014         td_t *td_list_next = NULL;
1015         ed_t *ed;
1016         int cc = 0;
1017         int stat = 0;
1018         /* urb_t *urb; */
1019         urb_priv_t *lurb_priv;
1020         __u32 tdINFO, edHeadP, edTailP;
1021
1022         while (td_list) {
1023                 td_list_next = td_list->next_dl_td;
1024
1025                 tdINFO = m32_swap (td_list->hwINFO);
1026
1027                 ed = td_list->ed;
1028                 lurb_priv = ed->purb;
1029
1030                 dl_transfer_length(td_list);
1031
1032                 /* error code of transfer */
1033                 cc = TD_CC_GET (tdINFO);
1034                 if (cc != 0) {
1035                         dbg("ConditionCode %#x", cc);
1036                         stat = cc_to_error[cc];
1037                 }
1038
1039                 /* see if this done list makes for all TD's of current URB,
1040                  * and mark the URB finished if so */
1041                 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
1042 #if 1
1043                         if ((ed->state & (ED_OPER | ED_UNLINK)) &&
1044                             (lurb_priv->state != URB_DEL))
1045 #else
1046                         if ((ed->state & (ED_OPER | ED_UNLINK)))
1047 #endif
1048                                 lurb_priv->finished = sohci_return_job(ohci,
1049                                                 lurb_priv);
1050                         else
1051                                 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
1052                 } else
1053                         dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
1054                                 lurb_priv->length);
1055                 if (ed->state != ED_NEW &&
1056                           (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
1057                         edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
1058                         edTailP = m32_swap (ed->hwTailP);
1059
1060                         /* unlink eds if they are not busy */
1061                         if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1062                                 ep_unlink (ohci, ed);
1063                 }
1064
1065                 td_list = td_list_next;
1066         }
1067         return stat;
1068 }
1069
1070 /*-------------------------------------------------------------------------*
1071  * Virtual Root Hub
1072  *-------------------------------------------------------------------------*/
1073
1074 /* Device descriptor */
1075 static __u8 root_hub_dev_des[] =
1076 {
1077         0x12,       /*  __u8  bLength; */
1078         0x01,       /*  __u8  bDescriptorType; Device */
1079         0x10,       /*  __u16 bcdUSB; v1.1 */
1080         0x01,
1081         0x09,       /*  __u8  bDeviceClass; HUB_CLASSCODE */
1082         0x00,       /*  __u8  bDeviceSubClass; */
1083         0x00,       /*  __u8  bDeviceProtocol; */
1084         0x08,       /*  __u8  bMaxPacketSize0; 8 Bytes */
1085         0x00,       /*  __u16 idVendor; */
1086         0x00,
1087         0x00,       /*  __u16 idProduct; */
1088         0x00,
1089         0x00,       /*  __u16 bcdDevice; */
1090         0x00,
1091         0x00,       /*  __u8  iManufacturer; */
1092         0x01,       /*  __u8  iProduct; */
1093         0x00,       /*  __u8  iSerialNumber; */
1094         0x01        /*  __u8  bNumConfigurations; */
1095 };
1096
1097
1098 /* Configuration descriptor */
1099 static __u8 root_hub_config_des[] =
1100 {
1101         0x09,       /*  __u8  bLength; */
1102         0x02,       /*  __u8  bDescriptorType; Configuration */
1103         0x19,       /*  __u16 wTotalLength; */
1104         0x00,
1105         0x01,       /*  __u8  bNumInterfaces; */
1106         0x01,       /*  __u8  bConfigurationValue; */
1107         0x00,       /*  __u8  iConfiguration; */
1108         0x40,       /*  __u8  bmAttributes;
1109                  Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1110         0x00,       /*  __u8  MaxPower; */
1111
1112         /* interface */
1113         0x09,       /*  __u8  if_bLength; */
1114         0x04,       /*  __u8  if_bDescriptorType; Interface */
1115         0x00,       /*  __u8  if_bInterfaceNumber; */
1116         0x00,       /*  __u8  if_bAlternateSetting; */
1117         0x01,       /*  __u8  if_bNumEndpoints; */
1118         0x09,       /*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
1119         0x00,       /*  __u8  if_bInterfaceSubClass; */
1120         0x00,       /*  __u8  if_bInterfaceProtocol; */
1121         0x00,       /*  __u8  if_iInterface; */
1122
1123         /* endpoint */
1124         0x07,       /*  __u8  ep_bLength; */
1125         0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
1126         0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
1127         0x03,       /*  __u8  ep_bmAttributes; Interrupt */
1128         0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1129         0x00,
1130         0xff        /*  __u8  ep_bInterval; 255 ms */
1131 };
1132
1133 static unsigned char root_hub_str_index0[] =
1134 {
1135         0x04,                   /*  __u8  bLength; */
1136         0x03,                   /*  __u8  bDescriptorType; String-descriptor */
1137         0x09,                   /*  __u8  lang ID */
1138         0x04,                   /*  __u8  lang ID */
1139 };
1140
1141 static unsigned char root_hub_str_index1[] =
1142 {
1143         28,                     /*  __u8  bLength; */
1144         0x03,                   /*  __u8  bDescriptorType; String-descriptor */
1145         'O',                    /*  __u8  Unicode */
1146         0,                              /*  __u8  Unicode */
1147         'H',                    /*  __u8  Unicode */
1148         0,                              /*  __u8  Unicode */
1149         'C',                    /*  __u8  Unicode */
1150         0,                              /*  __u8  Unicode */
1151         'I',                    /*  __u8  Unicode */
1152         0,                              /*  __u8  Unicode */
1153         ' ',                    /*  __u8  Unicode */
1154         0,                              /*  __u8  Unicode */
1155         'R',                    /*  __u8  Unicode */
1156         0,                              /*  __u8  Unicode */
1157         'o',                    /*  __u8  Unicode */
1158         0,                              /*  __u8  Unicode */
1159         'o',                    /*  __u8  Unicode */
1160         0,                              /*  __u8  Unicode */
1161         't',                    /*  __u8  Unicode */
1162         0,                              /*  __u8  Unicode */
1163         ' ',                    /*  __u8  Unicode */
1164         0,                              /*  __u8  Unicode */
1165         'H',                    /*  __u8  Unicode */
1166         0,                              /*  __u8  Unicode */
1167         'u',                    /*  __u8  Unicode */
1168         0,                              /*  __u8  Unicode */
1169         'b',                    /*  __u8  Unicode */
1170         0,                              /*  __u8  Unicode */
1171 };
1172
1173 /* Hub class-specific descriptor is constructed dynamically */
1174
1175
1176 /*-------------------------------------------------------------------------*/
1177
1178 #define OK(x)                   len = (x); break
1179 #ifdef DEBUG
1180 #define WR_RH_STAT(x)           {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
1181 #define WR_RH_PORTSTAT(x)       {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
1182 #else
1183 #define WR_RH_STAT(x)           writel((x), &gohci.regs->roothub.status)
1184 #define WR_RH_PORTSTAT(x)       writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
1185 #endif
1186 #define RD_RH_STAT              roothub_status(&gohci)
1187 #define RD_RH_PORTSTAT          roothub_portstatus(&gohci,wIndex-1)
1188
1189 /* request to virtual root hub */
1190
1191 int rh_check_port_status(ohci_t *controller)
1192 {
1193         __u32 temp, ndp, i;
1194         int res;
1195
1196         res = -1;
1197         temp = roothub_a (controller);
1198         ndp = (temp & RH_A_NDP);
1199 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1200         ndp = (ndp == 2) ? 1:0;
1201 #endif
1202         for (i = 0; i < ndp; i++) {
1203                 temp = roothub_portstatus (controller, i);
1204                 /* check for a device disconnect */
1205                 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1206                         (RH_PS_PESC | RH_PS_CSC)) &&
1207                         ((temp & RH_PS_CCS) == 0)) {
1208                         res = i;
1209                         break;
1210                 }
1211         }
1212         return res;
1213 }
1214
1215 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1216                 void *buffer, int transfer_len, struct devrequest *cmd)
1217 {
1218         void * data = buffer;
1219         int leni = transfer_len;
1220         int len = 0;
1221         int stat = 0;
1222         __u32 datab[4];
1223         __u8 *data_buf = (__u8 *)datab;
1224         __u16 bmRType_bReq;
1225         __u16 wValue;
1226         __u16 wIndex;
1227         __u16 wLength;
1228
1229 #ifdef DEBUG
1230 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1231 #else
1232         wait_ms(1);
1233 #endif
1234         if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1235                 info("Root-Hub submit IRQ: NOT implemented");
1236                 return 0;
1237         }
1238
1239         bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
1240         wValue        = cpu_to_le16 (cmd->value);
1241         wIndex        = cpu_to_le16 (cmd->index);
1242         wLength       = cpu_to_le16 (cmd->length);
1243
1244         info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1245                 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1246
1247         switch (bmRType_bReq) {
1248         /* Request Destination:
1249            without flags: Device,
1250            RH_INTERFACE: interface,
1251            RH_ENDPOINT: endpoint,
1252            RH_CLASS means HUB here,
1253            RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
1254         */
1255
1256         case RH_GET_STATUS:
1257                         *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
1258         case RH_GET_STATUS | RH_INTERFACE:
1259                         *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1260         case RH_GET_STATUS | RH_ENDPOINT:
1261                         *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1262         case RH_GET_STATUS | RH_CLASS:
1263                         *(__u32 *) data_buf = cpu_to_le32 (
1264                                 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1265                         OK (4);
1266         case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1267                         *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
1268
1269         case RH_CLEAR_FEATURE | RH_ENDPOINT:
1270                 switch (wValue) {
1271                         case (RH_ENDPOINT_STALL): OK (0);
1272                 }
1273                 break;
1274
1275         case RH_CLEAR_FEATURE | RH_CLASS:
1276                 switch (wValue) {
1277                         case RH_C_HUB_LOCAL_POWER:
1278                                 OK(0);
1279                         case (RH_C_HUB_OVER_CURRENT):
1280                                         WR_RH_STAT(RH_HS_OCIC); OK (0);
1281                 }
1282                 break;
1283
1284         case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1285                 switch (wValue) {
1286                         case (RH_PORT_ENABLE):
1287                                         WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1288                         case (RH_PORT_SUSPEND):
1289                                         WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1290                         case (RH_PORT_POWER):
1291                                         WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1292                         case (RH_C_PORT_CONNECTION):
1293                                         WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1294                         case (RH_C_PORT_ENABLE):
1295                                         WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1296                         case (RH_C_PORT_SUSPEND):
1297                                         WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1298                         case (RH_C_PORT_OVER_CURRENT):
1299                                         WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1300                         case (RH_C_PORT_RESET):
1301                                         WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1302                 }
1303                 break;
1304
1305         case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1306                 switch (wValue) {
1307                         case (RH_PORT_SUSPEND):
1308                                         WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1309                         case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1310                                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1311                                             WR_RH_PORTSTAT (RH_PS_PRS);
1312                                         OK (0);
1313                         case (RH_PORT_POWER):
1314                                         WR_RH_PORTSTAT (RH_PS_PPS );
1315                                         wait_ms(100);
1316                                         OK (0);
1317                         case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1318                                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1319                                             WR_RH_PORTSTAT (RH_PS_PES );
1320                                         OK (0);
1321                 }
1322                 break;
1323
1324         case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1325
1326         case RH_GET_DESCRIPTOR:
1327                 switch ((wValue & 0xff00) >> 8) {
1328                         case (0x01): /* device descriptor */
1329                                 len = min_t(unsigned int,
1330                                           leni,
1331                                           min_t(unsigned int,
1332                                               sizeof (root_hub_dev_des),
1333                                               wLength));
1334                                 data_buf = root_hub_dev_des; OK(len);
1335                         case (0x02): /* configuration descriptor */
1336                                 len = min_t(unsigned int,
1337                                           leni,
1338                                           min_t(unsigned int,
1339                                               sizeof (root_hub_config_des),
1340                                               wLength));
1341                                 data_buf = root_hub_config_des; OK(len);
1342                         case (0x03): /* string descriptors */
1343                                 if(wValue==0x0300) {
1344                                         len = min_t(unsigned int,
1345                                                   leni,
1346                                                   min_t(unsigned int,
1347                                                       sizeof (root_hub_str_index0),
1348                                                       wLength));
1349                                         data_buf = root_hub_str_index0;
1350                                         OK(len);
1351                                 }
1352                                 if(wValue==0x0301) {
1353                                         len = min_t(unsigned int,
1354                                                   leni,
1355                                                   min_t(unsigned int,
1356                                                       sizeof (root_hub_str_index1),
1357                                                       wLength));
1358                                         data_buf = root_hub_str_index1;
1359                                         OK(len);
1360                         }
1361                         default:
1362                                 stat = USB_ST_STALLED;
1363                 }
1364                 break;
1365
1366         case RH_GET_DESCRIPTOR | RH_CLASS:
1367         {
1368                 __u32 temp = roothub_a (&gohci);
1369
1370                 data_buf [0] = 9;               /* min length; */
1371                 data_buf [1] = 0x29;
1372                 data_buf [2] = temp & RH_A_NDP;
1373 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1374                 data_buf [2] = (data_buf [2] == 2) ? 1:0;
1375 #endif
1376                 data_buf [3] = 0;
1377                 if (temp & RH_A_PSM)    /* per-port power switching? */
1378                         data_buf [3] |= 0x1;
1379                 if (temp & RH_A_NOCP)   /* no overcurrent reporting? */
1380                         data_buf [3] |= 0x10;
1381                 else if (temp & RH_A_OCPM)      /* per-port overcurrent reporting? */
1382                         data_buf [3] |= 0x8;
1383
1384                 /* corresponds to data_buf[4-7] */
1385                 datab [1] = 0;
1386                 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1387                 temp = roothub_b (&gohci);
1388                 data_buf [7] = temp & RH_B_DR;
1389                 if (data_buf [2] < 7) {
1390                         data_buf [8] = 0xff;
1391                 } else {
1392                         data_buf [0] += 2;
1393                         data_buf [8] = (temp & RH_B_DR) >> 8;
1394                         data_buf [10] = data_buf [9] = 0xff;
1395                 }
1396
1397                 len = min_t(unsigned int, leni,
1398                             min_t(unsigned int, data_buf [0], wLength));
1399                 OK (len);
1400         }
1401
1402         case RH_GET_CONFIGURATION:      *(__u8 *) data_buf = 0x01; OK (1);
1403
1404         case RH_SET_CONFIGURATION:      WR_RH_STAT (0x10000); OK (0);
1405
1406         default:
1407                 dbg ("unsupported root hub command");
1408                 stat = USB_ST_STALLED;
1409         }
1410
1411 #ifdef  DEBUG
1412         ohci_dump_roothub (&gohci, 1);
1413 #else
1414         wait_ms(1);
1415 #endif
1416
1417         len = min_t(int, len, leni);
1418         if (data != data_buf)
1419             memcpy (data, data_buf, len);
1420         dev->act_len = len;
1421         dev->status = stat;
1422
1423 #ifdef DEBUG
1424         pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1425 #else
1426         wait_ms(1);
1427 #endif
1428
1429         return stat;
1430 }
1431
1432 /*-------------------------------------------------------------------------*/
1433
1434 /* common code for handling submit messages - used for all but root hub */
1435 /* accesses. */
1436 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1437                 int transfer_len, struct devrequest *setup, int interval)
1438 {
1439         int stat = 0;
1440         int maxsize = usb_maxpacket(dev, pipe);
1441         int timeout;
1442         urb_priv_t *urb;
1443
1444         urb = malloc(sizeof(urb_priv_t));
1445         memset(urb, 0, sizeof(urb_priv_t));
1446
1447         urb->dev = dev;
1448         urb->pipe = pipe;
1449         urb->transfer_buffer = buffer;
1450         urb->transfer_buffer_length = transfer_len;
1451         urb->interval = interval;
1452
1453         /* device pulled? Shortcut the action. */
1454         if (devgone == dev) {
1455                 dev->status = USB_ST_CRC_ERR;
1456                 return 0;
1457         }
1458
1459 #ifdef DEBUG
1460         urb->actual_length = 0;
1461         pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1462 #else
1463         wait_ms(1);
1464 #endif
1465         if (!maxsize) {
1466                 err("submit_common_message: pipesize for pipe %lx is zero",
1467                         pipe);
1468                 return -1;
1469         }
1470
1471         if (sohci_submit_job(urb, setup) < 0) {
1472                 err("sohci_submit_job failed");
1473                 return -1;
1474         }
1475
1476 #if 0
1477         wait_ms(10);
1478         /* ohci_dump_status(&gohci); */
1479 #endif
1480
1481         /* allow more time for a BULK device to react - some are slow */
1482 #define BULK_TO  5000   /* timeout in milliseconds */
1483         if (usb_pipetype (pipe) == PIPE_BULK)
1484                 timeout = BULK_TO;
1485         else
1486                 timeout = 100;
1487
1488         /* wait for it to complete */
1489         for (;;) {
1490                 /* check whether the controller is done */
1491                 stat = hc_interrupt();
1492                 if (stat < 0) {
1493                         stat = USB_ST_CRC_ERR;
1494                         break;
1495                 }
1496
1497                 /* NOTE: since we are not interrupt driven in U-Boot and always
1498                  * handle only one URB at a time, we cannot assume the
1499                  * transaction finished on the first successful return from
1500                  * hc_interrupt().. unless the flag for current URB is set,
1501                  * meaning that all TD's to/from device got actually
1502                  * transferred and processed. If the current URB is not
1503                  * finished we need to re-iterate this loop so as
1504                  * hc_interrupt() gets called again as there needs to be some
1505                  * more TD's to process still */
1506                 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1507                         /* 0xff is returned for an SF-interrupt */
1508                         break;
1509                 }
1510
1511                 if (--timeout) {
1512                         wait_ms(1);
1513                         if (!urb->finished)
1514                                 dbg("\%");
1515
1516                 } else {
1517                         err("CTL:TIMEOUT ");
1518                         dbg("submit_common_msg: TO status %x\n", stat);
1519                         urb->finished = 1;
1520                         stat = USB_ST_CRC_ERR;
1521                         break;
1522                 }
1523         }
1524
1525         dev->status = stat;
1526         dev->act_len = transfer_len;
1527
1528 #ifdef DEBUG
1529         pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1530 #else
1531         wait_ms(1);
1532 #endif
1533
1534         /* free TDs in urb_priv */
1535         if (usb_pipetype (pipe) != PIPE_INTERRUPT)
1536                 urb_free_priv (urb);
1537         return 0;
1538 }
1539
1540 /* submit routines called from usb.c */
1541 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1542                 int transfer_len)
1543 {
1544         info("submit_bulk_msg");
1545         return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1546 }
1547
1548 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1549                 int transfer_len, struct devrequest *setup)
1550 {
1551         int maxsize = usb_maxpacket(dev, pipe);
1552
1553         info("submit_control_msg");
1554 #ifdef DEBUG
1555         pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1556 #else
1557         wait_ms(1);
1558 #endif
1559         if (!maxsize) {
1560                 err("submit_control_message: pipesize for pipe %lx is zero",
1561                         pipe);
1562                 return -1;
1563         }
1564         if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1565                 gohci.rh.dev = dev;
1566                 /* root hub - redirect */
1567                 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1568                         setup);
1569         }
1570
1571         return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1572 }
1573
1574 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1575                 int transfer_len, int interval)
1576 {
1577         info("submit_int_msg");
1578         return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
1579                         interval);
1580 }
1581
1582 /*-------------------------------------------------------------------------*
1583  * HC functions
1584  *-------------------------------------------------------------------------*/
1585
1586 /* reset the HC and BUS */
1587
1588 static int hc_reset (ohci_t *ohci)
1589 {
1590         int timeout = 30;
1591         int smm_timeout = 50; /* 0,5 sec */
1592
1593         dbg("%s\n", __FUNCTION__);
1594
1595         if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1596                 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1597                 info("USB HC TakeOver from SMM");
1598                 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1599                         wait_ms (10);
1600                         if (--smm_timeout == 0) {
1601                                 err("USB HC TakeOver failed!");
1602                                 return -1;
1603                         }
1604                 }
1605         }
1606
1607         /* Disable HC interrupts */
1608         writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1609
1610         dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1611                 ohci->slot_name,
1612                 readl(&ohci->regs->control));
1613
1614         /* Reset USB (needed by some controllers) */
1615         ohci->hc_control = 0;
1616         writel (ohci->hc_control, &ohci->regs->control);
1617
1618         /* HC Reset requires max 10 us delay */
1619         writel (OHCI_HCR,  &ohci->regs->cmdstatus);
1620         while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1621                 if (--timeout == 0) {
1622                         err("USB HC reset timed out!");
1623                         return -1;
1624                 }
1625                 udelay (1);
1626         }
1627         return 0;
1628 }
1629
1630 /*-------------------------------------------------------------------------*/
1631
1632 /* Start an OHCI controller, set the BUS operational
1633  * enable interrupts
1634  * connect the virtual root hub */
1635
1636 static int hc_start (ohci_t * ohci)
1637 {
1638         __u32 mask;
1639         unsigned int fminterval;
1640
1641         ohci->disabled = 1;
1642
1643         /* Tell the controller where the control and bulk lists are
1644          * The lists are empty now. */
1645
1646         writel (0, &ohci->regs->ed_controlhead);
1647         writel (0, &ohci->regs->ed_bulkhead);
1648
1649         writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1650
1651         fminterval = 0x2edf;
1652         writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1653         fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1654         writel (fminterval, &ohci->regs->fminterval);
1655         writel (0x628, &ohci->regs->lsthresh);
1656
1657         /* start controller operations */
1658         ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1659         ohci->disabled = 0;
1660         writel (ohci->hc_control, &ohci->regs->control);
1661
1662         /* disable all interrupts */
1663         mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1664                         OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1665                         OHCI_INTR_OC | OHCI_INTR_MIE);
1666         writel (mask, &ohci->regs->intrdisable);
1667         /* clear all interrupts */
1668         mask &= ~OHCI_INTR_MIE;
1669         writel (mask, &ohci->regs->intrstatus);
1670         /* Choose the interrupts we care about now  - but w/o MIE */
1671         mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1672         writel (mask, &ohci->regs->intrenable);
1673
1674 #ifdef  OHCI_USE_NPS
1675         /* required for AMD-756 and some Mac platforms */
1676         writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1677                 &ohci->regs->roothub.a);
1678         writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1679 #endif  /* OHCI_USE_NPS */
1680
1681 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1682         /* POTPGT delay is bits 24-31, in 2 ms units. */
1683         mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1684
1685         /* connect the virtual root hub */
1686         ohci->rh.devnum = 0;
1687
1688         return 0;
1689 }
1690
1691 /*-------------------------------------------------------------------------*/
1692
1693 /* Poll USB interrupt. */
1694 void usb_event_poll(void)
1695 {
1696         hc_interrupt();
1697 }
1698
1699 /* an interrupt happens */
1700
1701 static int hc_interrupt (void)
1702 {
1703         ohci_t *ohci = &gohci;
1704         struct ohci_regs *regs = ohci->regs;
1705         int ints;
1706         int stat = -1;
1707
1708         if ((ohci->hcca->done_head != 0) &&
1709             !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1710                 ints =  OHCI_INTR_WDH;
1711         } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1712                 ohci->disabled++;
1713                 err ("%s device removed!", ohci->slot_name);
1714                 return -1;
1715         } else if ((ints &= readl (&regs->intrenable)) == 0) {
1716                 dbg("hc_interrupt: returning..\n");
1717                 return 0xff;
1718         }
1719
1720         /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1721
1722         if (ints & OHCI_INTR_RHSC) {
1723                 got_rhsc = 1;
1724                 stat = 0xff;
1725         }
1726
1727         if (ints & OHCI_INTR_UE) {
1728                 ohci->disabled++;
1729                 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1730                         ohci->slot_name);
1731                 /* e.g. due to PCI Master/Target Abort */
1732
1733 #ifdef  DEBUG
1734                 ohci_dump (ohci, 1);
1735 #else
1736         wait_ms(1);
1737 #endif
1738                 /* FIXME: be optimistic, hope that bug won't repeat often. */
1739                 /* Make some non-interrupt context restart the controller. */
1740                 /* Count and limit the retries though; either hardware or */
1741                 /* software errors can go forever... */
1742                 hc_reset (ohci);
1743                 return -1;
1744         }
1745
1746         if (ints & OHCI_INTR_WDH) {
1747                 wait_ms(1);
1748                 writel (OHCI_INTR_WDH, &regs->intrdisable);
1749                 (void)readl (&regs->intrdisable); /* flush */
1750                 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1751                 writel (OHCI_INTR_WDH, &regs->intrenable);
1752                 (void)readl (&regs->intrdisable); /* flush */
1753         }
1754
1755         if (ints & OHCI_INTR_SO) {
1756                 dbg("USB Schedule overrun\n");
1757                 writel (OHCI_INTR_SO, &regs->intrenable);
1758                 stat = -1;
1759         }
1760
1761         /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
1762         if (ints & OHCI_INTR_SF) {
1763                 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1764                 wait_ms(1);
1765                 writel (OHCI_INTR_SF, &regs->intrdisable);
1766                 if (ohci->ed_rm_list[frame] != NULL)
1767                         writel (OHCI_INTR_SF, &regs->intrenable);
1768                 stat = 0xff;
1769         }
1770
1771         writel (ints, &regs->intrstatus);
1772         return stat;
1773 }
1774
1775 /*-------------------------------------------------------------------------*/
1776
1777 /*-------------------------------------------------------------------------*/
1778
1779 /* De-allocate all resources.. */
1780
1781 static void hc_release_ohci (ohci_t *ohci)
1782 {
1783         dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1784
1785         if (!ohci->disabled)
1786                 hc_reset (ohci);
1787 }
1788
1789 /*-------------------------------------------------------------------------*/
1790
1791 /*
1792  * low level initalisation routine, called from usb.c
1793  */
1794 static char ohci_inited = 0;
1795
1796 int usb_lowlevel_init(void)
1797 {
1798 #ifdef CONFIG_PCI_OHCI
1799         pci_dev_t pdev;
1800 #endif
1801
1802 #ifdef CFG_USB_OHCI_CPU_INIT
1803         /* cpu dependant init */
1804         if(usb_cpu_init())
1805                 return -1;
1806 #endif
1807
1808 #ifdef CFG_USB_OHCI_BOARD_INIT
1809         /*  board dependant init */
1810         if(usb_board_init())
1811                 return -1;
1812 #endif
1813         memset (&gohci, 0, sizeof (ohci_t));
1814
1815         /* align the storage */
1816         if ((__u32)&ghcca[0] & 0xff) {
1817                 err("HCCA not aligned!!");
1818                 return -1;
1819         }
1820         phcca = &ghcca[0];
1821         info("aligned ghcca %p", phcca);
1822         memset(&ohci_dev, 0, sizeof(struct ohci_device));
1823         if ((__u32)&ohci_dev.ed[0] & 0x7) {
1824                 err("EDs not aligned!!");
1825                 return -1;
1826         }
1827         memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1828         if ((__u32)gtd & 0x7) {
1829                 err("TDs not aligned!!");
1830                 return -1;
1831         }
1832         ptd = gtd;
1833         gohci.hcca = phcca;
1834         memset (phcca, 0, sizeof (struct ohci_hcca));
1835
1836         gohci.disabled = 1;
1837         gohci.sleeping = 0;
1838         gohci.irq = -1;
1839 #ifdef CONFIG_PCI_OHCI
1840         pdev = pci_find_devices(ohci_pci_ids, 0);
1841
1842         if (pdev != -1) {
1843                 u16 vid, did;
1844                 u32 base;
1845                 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1846                 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1847                 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1848                                 vid, did, (pdev >> 16) & 0xff,
1849                                 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1850                 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1851                 printf("OHCI regs address 0x%08x\n", base);
1852                 gohci.regs = (struct ohci_regs *)base;
1853         } else
1854                 return -1;
1855 #else
1856         gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
1857 #endif
1858
1859         gohci.flags = 0;
1860         gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
1861
1862         if (hc_reset (&gohci) < 0) {
1863                 hc_release_ohci (&gohci);
1864                 err ("can't reset usb-%s", gohci.slot_name);
1865 #ifdef CFG_USB_OHCI_BOARD_INIT
1866                 /* board dependant cleanup */
1867                 usb_board_init_fail();
1868 #endif
1869
1870 #ifdef CFG_USB_OHCI_CPU_INIT
1871                 /* cpu dependant cleanup */
1872                 usb_cpu_init_fail();
1873 #endif
1874                 return -1;
1875         }
1876
1877         /* FIXME this is a second HC reset; why?? */
1878         /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1879            wait_ms(10); */
1880         if (hc_start (&gohci) < 0) {
1881                 err ("can't start usb-%s", gohci.slot_name);
1882                 hc_release_ohci (&gohci);
1883                 /* Initialization failed */
1884 #ifdef CFG_USB_OHCI_BOARD_INIT
1885                 /* board dependant cleanup */
1886                 usb_board_stop();
1887 #endif
1888
1889 #ifdef CFG_USB_OHCI_CPU_INIT
1890                 /* cpu dependant cleanup */
1891                 usb_cpu_stop();
1892 #endif
1893                 return -1;
1894         }
1895
1896 #ifdef  DEBUG
1897         ohci_dump (&gohci, 1);
1898 #else
1899         wait_ms(1);
1900 #endif
1901         ohci_inited = 1;
1902         return 0;
1903 }
1904
1905 int usb_lowlevel_stop(void)
1906 {
1907         /* this gets called really early - before the controller has */
1908         /* even been initialized! */
1909         if (!ohci_inited)
1910                 return 0;
1911         /* TODO release any interrupts, etc. */
1912         /* call hc_release_ohci() here ? */
1913         hc_reset (&gohci);
1914
1915 #ifdef CFG_USB_OHCI_BOARD_INIT
1916         /* board dependant cleanup */
1917         if(usb_board_stop())
1918                 return -1;
1919 #endif
1920
1921 #ifdef CFG_USB_OHCI_CPU_INIT
1922         /* cpu dependant cleanup */
1923         if(usb_cpu_stop())
1924                 return -1;
1925 #endif
1926
1927         return 0;
1928 }
1929 #endif /* CONFIG_USB_OHCI_NEW */