2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2 of
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
25 #define DeviceRequest \
26 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
28 #define DeviceOutRequest \
29 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
31 #define InterfaceRequest \
32 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
34 #define EndpointRequest \
35 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
37 #define EndpointOutRequest \
38 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
45 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
46 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
47 uint32_t cr_hcsparams;
48 uint32_t cr_hccparams;
49 uint8_t cr_hcsp_portrt[8];
54 #define CMD_ASE (1 << 5)
56 #define STD_ASS (1 << 15)
59 uint32_t or_ctrldssegment;
60 uint32_t or_periodiclistbase;
61 uint32_t or_asynclistaddr;
62 uint32_t _reserved_[9];
63 uint32_t or_configflag;
64 uint32_t or_portsc[2];
68 /* Interface descriptor */
69 struct usb_linux_interface_descriptor {
70 unsigned char bLength;
71 unsigned char bDescriptorType;
72 unsigned char bInterfaceNumber;
73 unsigned char bAlternateSetting;
74 unsigned char bNumEndpoints;
75 unsigned char bInterfaceClass;
76 unsigned char bInterfaceSubClass;
77 unsigned char bInterfaceProtocol;
78 unsigned char iInterface;
79 } __attribute__ ((packed));
81 /* Configuration descriptor information.. */
82 struct usb_linux_config_descriptor {
83 unsigned char bLength;
84 unsigned char bDescriptorType;
85 unsigned short wTotalLength;
86 unsigned char bNumInterfaces;
87 unsigned char bConfigurationValue;
88 unsigned char iConfiguration;
89 unsigned char bmAttributes;
90 unsigned char MaxPower;
91 } __attribute__ ((packed));
93 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
94 #define ehci_readl(x) (x)
95 #define ehci_writel(a, b) (a) = (b)
97 #define ehci_readl(x) cpu_to_le32((x))
98 #define ehci_writel(a, b) (a) = cpu_to_le32((b))
101 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
102 #define hc32_to_cpu(x) be32_to_cpu((x))
103 #define cpu_to_hc32(x) cpu_to_be32((x))
105 #define hc32_to_cpu(x) le32_to_cpu((x))
106 #define cpu_to_hc32(x) cpu_to_le32((x))
109 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current */
110 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect */
111 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect */
112 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */
113 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
114 #define EHCI_PS_PO 0x00002000 /* RW port owner */
115 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */
116 #define EHCI_PS_LS 0x00000c00 /* RO line status */
117 #define EHCI_PS_PR 0x00000100 /* RW port reset */
118 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */
119 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */
120 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */
121 #define EHCI_PS_OCA 0x00000010 /* RO over current active */
122 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
123 #define EHCI_PS_PE 0x00000004 /* RW port enable */
124 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
125 #define EHCI_PS_CS 0x00000001 /* RO connect status */
126 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
128 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
131 * Schedule Interface Space.
133 * IMPORTANT: Software must ensure that no interface data structure
134 * reachable by the EHCI host controller spans a 4K page boundary!
136 * Periodic transfers (i.e. isochronous and interrupt transfers) are
140 /* Queue Element Transfer Descriptor (qTD). */
143 #define QT_NEXT_TERMINATE 1
146 uint32_t qt_buffer[5];
149 /* Queue Head (QH). */
152 #define QH_LINK_TERMINATE 1
153 #define QH_LINK_TYPE_ITD 0
154 #define QH_LINK_TYPE_QH 2
155 #define QH_LINK_TYPE_SITD 4
156 #define QH_LINK_TYPE_FSTN 6
160 struct qTD qh_overlay;
163 /* Low level intit functions */
165 int ehci_hcd_init(void);
166 int ehci_hcd_stop(void);
167 #endif /* USB_EHCI_H */