2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/spinlock.h>
32 #include <linux/workqueue.h>
34 #include <linux/delay.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/musb-omap.h>
37 #include <linux/usb/ulpi.h>
38 #include <linux/i2c/twl.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/err.h>
41 #include <linux/slab.h>
43 /* Register defines */
45 #define MCPC_CTRL 0x30
46 #define MCPC_CTRL_RTSOL (1 << 7)
47 #define MCPC_CTRL_EXTSWR (1 << 6)
48 #define MCPC_CTRL_EXTSWC (1 << 5)
49 #define MCPC_CTRL_VOICESW (1 << 4)
50 #define MCPC_CTRL_OUT64K (1 << 3)
51 #define MCPC_CTRL_RTSCTSSW (1 << 2)
52 #define MCPC_CTRL_HS_UART (1 << 0)
54 #define MCPC_IO_CTRL 0x33
55 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
58 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
59 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
60 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
62 #define MCPC_CTRL2 0x36
63 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
65 #define OTHER_FUNC_CTRL 0x80
66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
69 #define OTHER_IFC_CTRL 0x83
70 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
77 #define OTHER_INT_EN_RISE 0x86
78 #define OTHER_INT_EN_FALL 0x89
79 #define OTHER_INT_STS 0x8C
80 #define OTHER_INT_LATCH 0x8D
81 #define OTHER_INT_VB_SESS_VLD (1 << 7)
82 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85 #define OTHER_INT_MANU (1 << 1)
86 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
88 #define ID_STATUS 0x96
89 #define ID_RES_FLOAT (1 << 4)
90 #define ID_RES_440K (1 << 3)
91 #define ID_RES_200K (1 << 2)
92 #define ID_RES_102K (1 << 1)
93 #define ID_RES_GND (1 << 0)
95 #define POWER_CTRL 0xAC
96 #define POWER_CTRL_OTG_ENAB (1 << 5)
98 #define OTHER_IFC_CTRL2 0xAF
99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
106 #define REG_CTRL_EN 0xB2
107 #define REG_CTRL_ERROR 0xB5
108 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
110 #define OTHER_FUNC_CTRL2 0xB8
111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
113 /* following registers do not have separate _clr and _set registers */
114 #define VBUS_DEBOUNCE 0xC0
115 #define ID_DEBOUNCE 0xC1
116 #define VBAT_TIMER 0xD3
117 #define PHY_PWR_CTRL 0xFD
118 #define PHY_PWR_PHYPWD (1 << 0)
119 #define PHY_CLK_CTRL 0xFE
120 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122 #define REQ_PHY_DPLL_CLK (1 << 0)
123 #define PHY_CLK_CTRL_STS 0xFF
124 #define PHY_DPLL_CLK (1 << 0)
126 /* In module TWL_MODULE_PM_MASTER */
127 #define STS_HW_CONDITIONS 0x0F
129 /* In module TWL_MODULE_PM_RECEIVER */
130 #define VUSB_DEDICATED1 0x7D
131 #define VUSB_DEDICATED2 0x7E
132 #define VUSB1V5_DEV_GRP 0x71
133 #define VUSB1V5_TYPE 0x72
134 #define VUSB1V5_REMAP 0x73
135 #define VUSB1V8_DEV_GRP 0x74
136 #define VUSB1V8_TYPE 0x75
137 #define VUSB1V8_REMAP 0x76
138 #define VUSB3V1_DEV_GRP 0x77
139 #define VUSB3V1_TYPE 0x78
140 #define VUSB3V1_REMAP 0x79
142 /* In module TWL4030_MODULE_INTBR */
144 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator *usb1v5;
152 struct regulator *usb1v8;
153 struct regulator *usb3v1;
155 /* for vbus reporting with irqs disabled */
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode;
162 enum omap_musb_vbus_id_status linkstat;
168 /* internal define on top of container_of */
169 #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
171 /*-------------------------------------------------------------------------*/
173 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
174 u8 module, u8 data, u8 address)
178 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
179 (twl_i2c_read_u8(module, &check, address) >= 0) &&
182 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
183 1, module, address, check, data);
185 /* Failed once: Try again */
186 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
187 (twl_i2c_read_u8(module, &check, address) >= 0) &&
190 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
191 2, module, address, check, data);
193 /* Failed again: Return error */
197 #define twl4030_usb_write_verify(twl, address, data) \
198 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
200 static inline int twl4030_usb_write(struct twl4030_usb *twl,
205 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
208 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
212 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
217 ret = twl_i2c_read_u8(module, &data, address);
222 "TWL4030:readb[0x%x,0x%x] Error %d\n",
223 module, address, ret);
228 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
230 return twl4030_readb(twl, TWL_MODULE_USB, address);
233 /*-------------------------------------------------------------------------*/
236 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
238 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
242 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
244 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
247 /*-------------------------------------------------------------------------*/
249 static enum omap_musb_vbus_id_status
250 twl4030_usb_linkstat(struct twl4030_usb *twl)
253 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
255 twl->vbus_supplied = false;
258 * For ID/VBUS sensing, see manual section 15.4.8 ...
259 * except when using only battery backup power, two
260 * comparators produce VBUS_PRES and ID_PRES signals,
261 * which don't match docs elsewhere. But ... BIT(7)
262 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
263 * seem to match up. If either is true the USB_PRES
264 * signal is active, the OTG module is activated, and
265 * its interrupt may be raised (may wake the system).
267 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
269 dev_err(twl->dev, "USB link status err %d\n", status);
270 else if (status & (BIT(7) | BIT(2))) {
271 if (status & (BIT(7)))
272 twl->vbus_supplied = true;
275 linkstat = OMAP_MUSB_ID_GROUND;
277 linkstat = OMAP_MUSB_VBUS_VALID;
279 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
280 linkstat = OMAP_MUSB_VBUS_OFF;
283 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
284 status, status, linkstat);
286 /* REVISIT this assumes host and peripheral controllers
287 * are registered, and that both are active...
290 spin_lock_irq(&twl->lock);
291 twl->linkstat = linkstat;
292 spin_unlock_irq(&twl->lock);
297 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
299 twl->usb_mode = mode;
302 case T2_USB_MODE_ULPI:
303 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
304 ULPI_IFC_CTRL_CARKITMODE);
305 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
306 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
307 ULPI_FUNC_CTRL_XCVRSEL_MASK |
308 ULPI_FUNC_CTRL_OPMODE_MASK);
311 /* FIXME: power on defaults */
314 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
320 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
322 unsigned long timeout;
323 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
327 /* enable DPLL to access PHY registers over I2C */
328 val |= REQ_PHY_DPLL_CLK;
329 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
332 timeout = jiffies + HZ;
333 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
335 && time_before(jiffies, timeout))
337 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
339 dev_err(twl->dev, "Timeout setting T2 HSUSB "
342 /* let ULPI control the DPLL clock */
343 val &= ~REQ_PHY_DPLL_CLK;
344 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
350 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
352 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
355 pwr &= ~PHY_PWR_PHYPWD;
357 pwr |= PHY_PWR_PHYPWD;
359 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
362 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
365 regulator_enable(twl->usb3v1);
366 regulator_enable(twl->usb1v8);
368 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
369 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
370 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
371 * SLEEP. We work around this by clearing the bit after usv3v1
372 * is re-activated. This ensures that VUSB3V1 is really active.
374 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
375 regulator_enable(twl->usb1v5);
376 __twl4030_phy_power(twl, 1);
377 twl4030_usb_write(twl, PHY_CLK_CTRL,
378 twl4030_usb_read(twl, PHY_CLK_CTRL) |
379 (PHY_CLK_CTRL_CLOCKGATING_EN |
380 PHY_CLK_CTRL_CLK32K_EN));
382 __twl4030_phy_power(twl, 0);
383 regulator_disable(twl->usb1v5);
384 regulator_disable(twl->usb1v8);
385 regulator_disable(twl->usb3v1);
389 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
394 twl4030_phy_power(twl, 0);
396 dev_dbg(twl->dev, "%s\n", __func__);
399 static void __twl4030_phy_resume(struct twl4030_usb *twl)
401 twl4030_phy_power(twl, 1);
402 twl4030_i2c_access(twl, 1);
403 twl4030_usb_set_mode(twl, twl->usb_mode);
404 if (twl->usb_mode == T2_USB_MODE_ULPI)
405 twl4030_i2c_access(twl, 0);
408 static void twl4030_phy_resume(struct twl4030_usb *twl)
412 __twl4030_phy_resume(twl);
414 dev_dbg(twl->dev, "%s\n", __func__);
417 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
419 /* Enable writing to power configuration registers */
420 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
421 TWL4030_PM_MASTER_PROTECT_KEY);
423 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
424 TWL4030_PM_MASTER_PROTECT_KEY);
426 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
427 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
429 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
430 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
432 /* Initialize 3.1V regulator */
433 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
435 twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
436 if (IS_ERR(twl->usb3v1))
439 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
441 /* Initialize 1.5V regulator */
442 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
444 twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
445 if (IS_ERR(twl->usb1v5))
448 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
450 /* Initialize 1.8V regulator */
451 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
453 twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
454 if (IS_ERR(twl->usb1v8))
457 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
459 /* disable access to power configuration registers */
460 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
461 TWL4030_PM_MASTER_PROTECT_KEY);
466 regulator_put(twl->usb1v5);
469 regulator_put(twl->usb3v1);
474 static ssize_t twl4030_usb_vbus_show(struct device *dev,
475 struct device_attribute *attr, char *buf)
477 struct twl4030_usb *twl = dev_get_drvdata(dev);
481 spin_lock_irqsave(&twl->lock, flags);
482 ret = sprintf(buf, "%s\n",
483 twl->vbus_supplied ? "on" : "off");
484 spin_unlock_irqrestore(&twl->lock, flags);
488 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
490 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
492 struct twl4030_usb *twl = _twl;
493 enum omap_musb_vbus_id_status status;
495 status = twl4030_usb_linkstat(twl);
497 /* FIXME add a set_power() method so that B-devices can
498 * configure the charger appropriately. It's not always
499 * correct to consume VBUS power, and how much current to
500 * consume is a function of the USB configuration chosen
503 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
504 * its disconnect() sibling, when changing to/from the
505 * USB_LINK_VBUS state. musb_hdrc won't care until it
506 * starts to handle softconnect right.
508 if (status == OMAP_MUSB_VBUS_OFF ||
509 status == OMAP_MUSB_ID_FLOAT)
510 twl4030_phy_suspend(twl, 0);
512 twl4030_phy_resume(twl);
514 omap_musb_mailbox(twl->linkstat);
516 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
521 static void twl4030_usb_phy_init(struct twl4030_usb *twl)
523 enum omap_musb_vbus_id_status status;
525 status = twl4030_usb_linkstat(twl);
527 if (status == OMAP_MUSB_VBUS_OFF ||
528 status == OMAP_MUSB_ID_FLOAT) {
529 __twl4030_phy_power(twl, 0);
532 __twl4030_phy_resume(twl);
536 omap_musb_mailbox(twl->linkstat);
538 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
541 static int twl4030_set_suspend(struct usb_phy *x, int suspend)
543 struct twl4030_usb *twl = phy_to_twl(x);
546 twl4030_phy_suspend(twl, 1);
548 twl4030_phy_resume(twl);
553 static int twl4030_set_peripheral(struct usb_otg *otg,
554 struct usb_gadget *gadget)
559 otg->gadget = gadget;
561 otg->phy->state = OTG_STATE_UNDEFINED;
566 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
573 otg->phy->state = OTG_STATE_UNDEFINED;
578 static int twl4030_usb_probe(struct platform_device *pdev)
580 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
581 struct twl4030_usb *twl;
584 struct device_node *np = pdev->dev.of_node;
586 twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
591 of_property_read_u32(np, "usb_mode",
592 (enum twl4030_usb_mode *)&twl->usb_mode);
594 twl->usb_mode = pdata->usb_mode;
596 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
600 otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
604 twl->dev = &pdev->dev;
605 twl->irq = platform_get_irq(pdev, 0);
606 twl->vbus_supplied = false;
608 twl->linkstat = OMAP_MUSB_UNKNOWN;
610 twl->phy.dev = twl->dev;
611 twl->phy.label = "twl4030";
613 twl->phy.set_suspend = twl4030_set_suspend;
615 otg->phy = &twl->phy;
616 otg->set_host = twl4030_set_host;
617 otg->set_peripheral = twl4030_set_peripheral;
619 /* init spinlock for workqueue */
620 spin_lock_init(&twl->lock);
622 err = twl4030_usb_ldo_init(twl);
624 dev_err(&pdev->dev, "ldo init failed\n");
627 usb_add_phy(&twl->phy, USB_PHY_TYPE_USB2);
629 platform_set_drvdata(pdev, twl);
630 if (device_create_file(&pdev->dev, &dev_attr_vbus))
631 dev_warn(&pdev->dev, "could not create sysfs file\n");
633 /* Our job is to use irqs and status from the power module
634 * to keep the transceiver disabled when nothing's connected.
636 * FIXME we actually shouldn't start enabling it until the
637 * USB controller drivers have said they're ready, by calling
638 * set_host() and/or set_peripheral() ... OTG_capable boards
639 * need both handles, otherwise just one suffices.
641 twl->irq_enabled = true;
642 status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
643 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
644 IRQF_ONESHOT, "twl4030_usb", twl);
646 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
651 /* Power down phy or make it work according to
652 * current link state.
654 twl4030_usb_phy_init(twl);
656 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
660 static int __exit twl4030_usb_remove(struct platform_device *pdev)
662 struct twl4030_usb *twl = platform_get_drvdata(pdev);
665 free_irq(twl->irq, twl);
666 device_remove_file(twl->dev, &dev_attr_vbus);
668 /* set transceiver mode to power on defaults */
669 twl4030_usb_set_mode(twl, -1);
671 /* autogate 60MHz ULPI clock,
672 * clear dpll clock request for i2c access,
675 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
677 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
678 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
679 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
682 /* disable complete OTG block */
683 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
686 twl4030_phy_power(twl, 0);
687 regulator_put(twl->usb1v5);
688 regulator_put(twl->usb1v8);
689 regulator_put(twl->usb3v1);
695 static const struct of_device_id twl4030_usb_id_table[] = {
696 { .compatible = "ti,twl4030-usb" },
699 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
702 static struct platform_driver twl4030_usb_driver = {
703 .probe = twl4030_usb_probe,
704 .remove = __exit_p(twl4030_usb_remove),
706 .name = "twl4030_usb",
707 .owner = THIS_MODULE,
708 .of_match_table = of_match_ptr(twl4030_usb_id_table),
712 static int __init twl4030_usb_init(void)
714 return platform_driver_register(&twl4030_usb_driver);
716 subsys_initcall(twl4030_usb_init);
718 static void __exit twl4030_usb_exit(void)
720 platform_driver_unregister(&twl4030_usb_driver);
722 module_exit(twl4030_usb_exit);
724 MODULE_ALIAS("platform:twl4030_usb");
725 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
726 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
727 MODULE_LICENSE("GPL");