1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver peripheral support
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
13 #include <dm/device_compat.h>
14 #include <dm/devres.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/module.h>
19 #include <linux/smp.h>
20 #include <linux/spinlock.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
27 #include <dm/device_compat.h>
28 #include <linux/bug.h>
29 #include <linux/usb/ch9.h>
30 #include "linux-compat.h"
33 #include "musb_core.h"
36 /* MUSB PERIPHERAL status 3-mar-2006:
38 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
41 * + remote wakeup to Linux hosts work, but saw USBCV failures;
42 * in one test run (operator error?)
43 * + endpoint halt tests -- in both usbtest and usbcv -- seem
44 * to break when dma is enabled ... is something wrongly
47 * - Mass storage behaved ok when last tested. Network traffic patterns
48 * (with lots of short transfers etc) need retesting; they turn up the
49 * worst cases of the DMA, since short packets are typical but are not
53 * + both pio and dma behave in with network and g_zero tests
54 * + no cppi throughput issues other than no-hw-queueing
55 * + failed with FLAT_REG (DaVinci)
56 * + seems to behave with double buffering, PIO -and- CPPI
57 * + with gadgetfs + AIO, requests got lost?
60 * + both pio and dma behave in with network and g_zero tests
61 * + dma is slow in typical case (short_not_ok is clear)
62 * + double buffering ok with PIO
63 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
64 * + request lossage observed with gadgetfs
66 * - ISO not tested ... might work, but only weakly isochronous
68 * - Gadget driver disabling of softconnect during bind() is ignored; so
69 * drivers can't hold off host requests until userspace is ready.
70 * (Workaround: they can turn it off later.)
72 * - PORTABILITY (assumes PIO works):
73 * + DaVinci, basically works with cppi dma
74 * + OMAP 2430, ditto with mentor dma
75 * + TUSB 6010, platform-specific dma in the works
78 /* ----------------------------------------------------------------------- */
80 #define is_buffer_mapped(req) (is_dma_capable() && \
81 (req->map_state != UN_MAPPED))
83 #ifndef CONFIG_USB_MUSB_PIO_ONLY
84 /* Maps the buffer to dma */
86 static inline void map_dma_buffer(struct musb_request *request,
87 struct musb *musb, struct musb_ep *musb_ep)
89 int compatible = true;
90 struct dma_controller *dma = musb->dma_controller;
92 request->map_state = UN_MAPPED;
94 if (!is_dma_capable() || !musb_ep->dma)
97 /* Check if DMA engine can handle this request.
98 * DMA code must reject the USB request explicitly.
99 * Default behaviour is to map the request.
101 if (dma->is_compatible)
102 compatible = dma->is_compatible(musb_ep->dma,
103 musb_ep->packet_sz, request->request.buf,
104 request->request.length);
108 if (request->request.dma == DMA_ADDR_INVALID) {
109 request->request.dma = dma_map_single(
111 request->request.buf,
112 request->request.length,
116 request->map_state = MUSB_MAPPED;
118 dma_sync_single_for_device(musb->controller,
119 request->request.dma,
120 request->request.length,
124 request->map_state = PRE_MAPPED;
128 /* Unmap the buffer from dma and maps it back to cpu */
129 static inline void unmap_dma_buffer(struct musb_request *request,
132 if (!is_buffer_mapped(request))
135 if (request->request.dma == DMA_ADDR_INVALID) {
136 dev_vdbg(musb->controller,
137 "not unmapping a never mapped buffer\n");
140 if (request->map_state == MUSB_MAPPED) {
141 dma_unmap_single(musb->controller,
142 request->request.dma,
143 request->request.length,
147 request->request.dma = DMA_ADDR_INVALID;
148 } else { /* PRE_MAPPED */
149 dma_sync_single_for_cpu(musb->controller,
150 request->request.dma,
151 request->request.length,
156 request->map_state = UN_MAPPED;
159 static inline void map_dma_buffer(struct musb_request *request,
160 struct musb *musb, struct musb_ep *musb_ep)
164 static inline void unmap_dma_buffer(struct musb_request *request,
171 * Immediately complete a request.
173 * @param request the request to complete
174 * @param status the status to complete the request with
175 * Context: controller locked, IRQs blocked.
177 void musb_g_giveback(
179 struct usb_request *request,
181 __releases(ep->musb->lock)
182 __acquires(ep->musb->lock)
184 struct musb_request *req;
188 req = to_musb_request(request);
190 list_del(&req->list);
191 if (req->request.status == -EINPROGRESS)
192 req->request.status = status;
196 spin_unlock(&musb->lock);
197 unmap_dma_buffer(req, musb);
198 if (request->status == 0)
199 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
200 ep->end_point.name, request,
201 req->request.actual, req->request.length);
203 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
204 ep->end_point.name, request,
205 req->request.actual, req->request.length,
207 req->request.complete(&req->ep->end_point, &req->request);
208 spin_lock(&musb->lock);
212 /* ----------------------------------------------------------------------- */
215 * Abort requests queued to an endpoint using the status. Synchronous.
216 * caller locked controller and blocked irqs, and selected this ep.
218 static void nuke(struct musb_ep *ep, const int status)
220 struct musb *musb = ep->musb;
221 struct musb_request *req = NULL;
222 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
226 if (is_dma_capable() && ep->dma) {
227 struct dma_controller *c = ep->musb->dma_controller;
232 * The programming guide says that we must not clear
233 * the DMAMODE bit before DMAENAB, so we only
234 * clear it in the second write...
236 musb_writew(epio, MUSB_TXCSR,
237 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
238 musb_writew(epio, MUSB_TXCSR,
239 0 | MUSB_TXCSR_FLUSHFIFO);
241 musb_writew(epio, MUSB_RXCSR,
242 0 | MUSB_RXCSR_FLUSHFIFO);
243 musb_writew(epio, MUSB_RXCSR,
244 0 | MUSB_RXCSR_FLUSHFIFO);
247 value = c->channel_abort(ep->dma);
248 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
250 c->channel_release(ep->dma);
254 while (!list_empty(&ep->req_list)) {
255 req = list_first_entry(&ep->req_list, struct musb_request, list);
256 musb_g_giveback(ep, &req->request, status);
260 /* ----------------------------------------------------------------------- */
262 /* Data transfers - pure PIO, pure DMA, or mixed mode */
265 * This assumes the separate CPPI engine is responding to DMA requests
266 * from the usb core ... sequenced a bit differently from mentor dma.
269 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
271 if (can_bulk_split(musb, ep->type))
272 return ep->hw_ep->max_packet_sz_tx;
274 return ep->packet_sz;
278 #ifdef CONFIG_USB_INVENTRA_DMA
280 /* Peripheral tx (IN) using Mentor DMA works as follows:
281 Only mode 0 is used for transfers <= wPktSize,
282 mode 1 is used for larger transfers,
284 One of the following happens:
285 - Host sends IN token which causes an endpoint interrupt
287 -> if DMA is currently busy, exit.
288 -> if queue is non-empty, txstate().
290 - Request is queued by the gadget driver.
291 -> if queue was previously empty, txstate()
296 | (data is transferred to the FIFO, then sent out when
297 | IN token(s) are recd from Host.
298 | -> DMA interrupt on completion
300 | -> stop DMA, ~DMAENAB,
301 | -> set TxPktRdy for last short pkt or zlp
302 | -> Complete Request
303 | -> Continue next request (call txstate)
304 |___________________________________|
306 * Non-Mentor DMA engines can of course work differently, such as by
307 * upleveling from irq-per-packet to irq-per-buffer.
313 * An endpoint is transmitting data. This can be called either from
314 * the IRQ routine or from ep.queue() to kickstart a request on an
317 * Context: controller locked, IRQs blocked, endpoint selected
319 static void txstate(struct musb *musb, struct musb_request *req)
321 u8 epnum = req->epnum;
322 struct musb_ep *musb_ep;
323 void __iomem *epio = musb->endpoints[epnum].regs;
324 struct usb_request *request;
325 u16 fifo_count = 0, csr;
330 /* Check if EP is disabled */
331 if (!musb_ep->desc) {
332 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
333 musb_ep->end_point.name);
337 /* we shouldn't get here while DMA is active ... but we do ... */
338 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
339 dev_dbg(musb->controller, "dma pending...\n");
343 /* read TXCSR before */
344 csr = musb_readw(epio, MUSB_TXCSR);
346 request = &req->request;
347 fifo_count = min(max_ep_writesize(musb, musb_ep),
348 (int)(request->length - request->actual));
350 if (csr & MUSB_TXCSR_TXPKTRDY) {
351 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
352 musb_ep->end_point.name, csr);
356 if (csr & MUSB_TXCSR_P_SENDSTALL) {
357 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
358 musb_ep->end_point.name, csr);
362 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
363 epnum, musb_ep->packet_sz, fifo_count,
366 #ifndef CONFIG_USB_MUSB_PIO_ONLY
367 if (is_buffer_mapped(req)) {
368 struct dma_controller *c = musb->dma_controller;
371 /* setup DMA, then program endpoint CSR */
372 request_size = min_t(size_t, request->length - request->actual,
373 musb_ep->dma->max_len);
375 use_dma = (request->dma != DMA_ADDR_INVALID);
377 /* MUSB_TXCSR_P_ISO is still set correctly */
379 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
381 if (request_size < musb_ep->packet_sz)
382 musb_ep->dma->desired_mode = 0;
384 musb_ep->dma->desired_mode = 1;
386 use_dma = use_dma && c->channel_program(
387 musb_ep->dma, musb_ep->packet_sz,
388 musb_ep->dma->desired_mode,
389 request->dma + request->actual, request_size);
391 if (musb_ep->dma->desired_mode == 0) {
393 * We must not clear the DMAMODE bit
394 * before the DMAENAB bit -- and the
395 * latter doesn't always get cleared
396 * before we get here...
398 csr &= ~(MUSB_TXCSR_AUTOSET
399 | MUSB_TXCSR_DMAENAB);
400 musb_writew(epio, MUSB_TXCSR, csr
401 | MUSB_TXCSR_P_WZC_BITS);
402 csr &= ~MUSB_TXCSR_DMAMODE;
403 csr |= (MUSB_TXCSR_DMAENAB |
405 /* against programming guide */
407 csr |= (MUSB_TXCSR_DMAENAB
410 if (!musb_ep->hb_mult)
411 csr |= MUSB_TXCSR_AUTOSET;
413 csr &= ~MUSB_TXCSR_P_UNDERRUN;
415 musb_writew(epio, MUSB_TXCSR, csr);
419 #elif defined(CONFIG_USB_TI_CPPI_DMA)
420 /* program endpoint CSR first, then setup DMA */
421 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
422 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
424 musb_writew(epio, MUSB_TXCSR,
425 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
428 /* ensure writebuffer is empty */
429 csr = musb_readw(epio, MUSB_TXCSR);
431 /* NOTE host side sets DMAENAB later than this; both are
432 * OK since the transfer dma glue (between CPPI and Mentor
433 * fifos) just tells CPPI it could start. Data only moves
434 * to the USB TX fifo when both fifos are ready.
437 /* "mode" is irrelevant here; handle terminating ZLPs like
438 * PIO does, since the hardware RNDIS mode seems unreliable
439 * except for the last-packet-is-already-short case.
441 use_dma = use_dma && c->channel_program(
442 musb_ep->dma, musb_ep->packet_sz,
444 request->dma + request->actual,
447 c->channel_release(musb_ep->dma);
449 csr &= ~MUSB_TXCSR_DMAENAB;
450 musb_writew(epio, MUSB_TXCSR, csr);
451 /* invariant: prequest->buf is non-null */
453 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
454 use_dma = use_dma && c->channel_program(
455 musb_ep->dma, musb_ep->packet_sz,
457 request->dma + request->actual,
465 * Unmap the dma buffer back to cpu if dma channel
468 unmap_dma_buffer(req, musb);
470 musb_write_fifo(musb_ep->hw_ep, fifo_count,
471 (u8 *) (request->buf + request->actual));
472 request->actual += fifo_count;
473 csr |= MUSB_TXCSR_TXPKTRDY;
474 csr &= ~MUSB_TXCSR_P_UNDERRUN;
475 musb_writew(epio, MUSB_TXCSR, csr);
478 /* host may already have the data when this message shows... */
479 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
480 musb_ep->end_point.name, use_dma ? "dma" : "pio",
481 request->actual, request->length,
482 musb_readw(epio, MUSB_TXCSR),
484 musb_readw(epio, MUSB_TXMAXP));
488 * FIFO state update (e.g. data ready).
489 * Called from IRQ, with controller locked.
491 void musb_g_tx(struct musb *musb, u8 epnum)
494 struct musb_request *req;
495 struct usb_request *request;
496 u8 __iomem *mbase = musb->mregs;
497 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
498 void __iomem *epio = musb->endpoints[epnum].regs;
499 struct dma_channel *dma;
501 musb_ep_select(mbase, epnum);
502 req = next_request(musb_ep);
503 request = &req->request;
505 csr = musb_readw(epio, MUSB_TXCSR);
506 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
508 dma = is_dma_capable() ? musb_ep->dma : NULL;
511 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
512 * probably rates reporting as a host error.
514 if (csr & MUSB_TXCSR_P_SENTSTALL) {
515 csr |= MUSB_TXCSR_P_WZC_BITS;
516 csr &= ~MUSB_TXCSR_P_SENTSTALL;
517 musb_writew(epio, MUSB_TXCSR, csr);
521 if (csr & MUSB_TXCSR_P_UNDERRUN) {
522 /* We NAKed, no big deal... little reason to care. */
523 csr |= MUSB_TXCSR_P_WZC_BITS;
524 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
525 musb_writew(epio, MUSB_TXCSR, csr);
526 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
530 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
532 * SHOULD NOT HAPPEN... has with CPPI though, after
533 * changing SENDSTALL (and other cases); harmless?
535 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
542 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
544 csr |= MUSB_TXCSR_P_WZC_BITS;
545 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
546 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
547 musb_writew(epio, MUSB_TXCSR, csr);
548 /* Ensure writebuffer is empty. */
549 csr = musb_readw(epio, MUSB_TXCSR);
550 request->actual += musb_ep->dma->actual_len;
551 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
552 epnum, csr, musb_ep->dma->actual_len, request);
556 * First, maybe a terminating short packet. Some DMA
557 * engines might handle this by themselves.
559 if ((request->zero && request->length
560 && (request->length % musb_ep->packet_sz == 0)
561 && (request->actual == request->length))
562 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
563 || (is_dma && (!dma->desired_mode ||
565 (musb_ep->packet_sz - 1))))
569 * On DMA completion, FIFO may not be
572 if (csr & MUSB_TXCSR_TXPKTRDY)
575 dev_dbg(musb->controller, "sending zero pkt\n");
576 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
577 | MUSB_TXCSR_TXPKTRDY);
581 if (request->actual == request->length) {
582 musb_g_giveback(musb_ep, request, 0);
584 * In the giveback function the MUSB lock is
585 * released and acquired after sometime. During
586 * this time period the INDEX register could get
587 * changed by the gadget_queue function especially
588 * on SMP systems. Reselect the INDEX to be sure
589 * we are reading/modifying the right registers
591 musb_ep_select(mbase, epnum);
592 req = musb_ep->desc ? next_request(musb_ep) : NULL;
594 dev_dbg(musb->controller, "%s idle now\n",
595 musb_ep->end_point.name);
604 /* ------------------------------------------------------------ */
606 #ifdef CONFIG_USB_INVENTRA_DMA
608 /* Peripheral rx (OUT) using Mentor DMA works as follows:
609 - Only mode 0 is used.
611 - Request is queued by the gadget class driver.
612 -> if queue was previously empty, rxstate()
614 - Host sends OUT token which causes an endpoint interrupt
616 | -> if request queued, call rxstate
618 | | -> DMA interrupt on completion
622 | | -> if data recd = max expected
623 | | by the request, or host
624 | | sent a short packet,
625 | | complete the request,
626 | | and start the next one.
627 | |_____________________________________|
628 | else just wait for the host
629 | to send the next OUT token.
630 |__________________________________________________|
632 * Non-Mentor DMA engines can of course work differently.
638 * Context: controller locked, IRQs blocked, endpoint selected
640 static void rxstate(struct musb *musb, struct musb_request *req)
642 const u8 epnum = req->epnum;
643 struct usb_request *request = &req->request;
644 struct musb_ep *musb_ep;
645 void __iomem *epio = musb->endpoints[epnum].regs;
646 unsigned fifo_count = 0;
648 u16 csr = musb_readw(epio, MUSB_RXCSR);
649 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
652 if (hw_ep->is_shared_fifo)
653 musb_ep = &hw_ep->ep_in;
655 musb_ep = &hw_ep->ep_out;
657 len = musb_ep->packet_sz;
659 /* Check if EP is disabled */
660 if (!musb_ep->desc) {
661 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
662 musb_ep->end_point.name);
666 /* We shouldn't get here while DMA is active, but we do... */
667 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
668 dev_dbg(musb->controller, "DMA pending...\n");
672 if (csr & MUSB_RXCSR_P_SENDSTALL) {
673 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
674 musb_ep->end_point.name, csr);
678 if (is_cppi_enabled() && is_buffer_mapped(req)) {
679 struct dma_controller *c = musb->dma_controller;
680 struct dma_channel *channel = musb_ep->dma;
682 /* NOTE: CPPI won't actually stop advancing the DMA
683 * queue after short packet transfers, so this is almost
684 * always going to run as IRQ-per-packet DMA so that
685 * faults will be handled correctly.
687 if (c->channel_program(channel,
689 !request->short_not_ok,
690 request->dma + request->actual,
691 request->length - request->actual)) {
693 /* make sure that if an rxpkt arrived after the irq,
694 * the cppi engine will be ready to take it as soon
697 csr &= ~(MUSB_RXCSR_AUTOCLEAR
698 | MUSB_RXCSR_DMAMODE);
699 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
700 musb_writew(epio, MUSB_RXCSR, csr);
705 if (csr & MUSB_RXCSR_RXPKTRDY) {
706 len = musb_readw(epio, MUSB_RXCOUNT);
709 * Enable Mode 1 on RX transfers only when short_not_ok flag
710 * is set. Currently short_not_ok flag is set only from
711 * file_storage and f_mass_storage drivers
714 if (request->short_not_ok && len == musb_ep->packet_sz)
719 if (request->actual < request->length) {
720 #ifdef CONFIG_USB_INVENTRA_DMA
721 if (is_buffer_mapped(req)) {
722 struct dma_controller *c;
723 struct dma_channel *channel;
726 c = musb->dma_controller;
727 channel = musb_ep->dma;
729 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
730 * mode 0 only. So we do not get endpoint interrupts due to DMA
731 * completion. We only get interrupts from DMA controller.
733 * We could operate in DMA mode 1 if we knew the size of the tranfer
734 * in advance. For mass storage class, request->length = what the host
735 * sends, so that'd work. But for pretty much everything else,
736 * request->length is routinely more than what the host sends. For
737 * most these gadgets, end of is signified either by a short packet,
738 * or filling the last byte of the buffer. (Sending extra data in
739 * that last pckate should trigger an overflow fault.) But in mode 1,
740 * we don't get DMA completion interrupt for short packets.
742 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
743 * to get endpoint interrupt on every DMA req, but that didn't seem
746 * REVISIT an updated g_file_storage can set req->short_not_ok, which
747 * then becomes usable as a runtime "use mode 1" hint...
750 /* Experimental: Mode1 works with mass storage use cases */
752 csr |= MUSB_RXCSR_AUTOCLEAR;
753 musb_writew(epio, MUSB_RXCSR, csr);
754 csr |= MUSB_RXCSR_DMAENAB;
755 musb_writew(epio, MUSB_RXCSR, csr);
758 * this special sequence (enabling and then
759 * disabling MUSB_RXCSR_DMAMODE) is required
760 * to get DMAReq to activate
762 musb_writew(epio, MUSB_RXCSR,
763 csr | MUSB_RXCSR_DMAMODE);
764 musb_writew(epio, MUSB_RXCSR, csr);
767 if (!musb_ep->hb_mult &&
768 musb_ep->hw_ep->rx_double_buffered)
769 csr |= MUSB_RXCSR_AUTOCLEAR;
770 csr |= MUSB_RXCSR_DMAENAB;
771 musb_writew(epio, MUSB_RXCSR, csr);
774 if (request->actual < request->length) {
775 int transfer_size = 0;
777 transfer_size = min(request->length - request->actual,
779 musb_ep->dma->desired_mode = 1;
781 transfer_size = min(request->length - request->actual,
783 musb_ep->dma->desired_mode = 0;
786 use_dma = c->channel_program(
789 channel->desired_mode,
798 #elif defined(CONFIG_USB_UX500_DMA)
799 if ((is_buffer_mapped(req)) &&
800 (request->actual < request->length)) {
802 struct dma_controller *c;
803 struct dma_channel *channel;
804 int transfer_size = 0;
806 c = musb->dma_controller;
807 channel = musb_ep->dma;
809 /* In case first packet is short */
810 if (len < musb_ep->packet_sz)
812 else if (request->short_not_ok)
813 transfer_size = min(request->length -
817 transfer_size = min(request->length -
821 csr &= ~MUSB_RXCSR_DMAMODE;
822 csr |= (MUSB_RXCSR_DMAENAB |
823 MUSB_RXCSR_AUTOCLEAR);
825 musb_writew(epio, MUSB_RXCSR, csr);
827 if (transfer_size <= musb_ep->packet_sz) {
828 musb_ep->dma->desired_mode = 0;
830 musb_ep->dma->desired_mode = 1;
831 /* Mode must be set after DMAENAB */
832 csr |= MUSB_RXCSR_DMAMODE;
833 musb_writew(epio, MUSB_RXCSR, csr);
836 if (c->channel_program(channel,
838 channel->desired_mode,
845 #endif /* Mentor's DMA */
847 fifo_count = request->length - request->actual;
848 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
849 musb_ep->end_point.name,
853 fifo_count = min_t(unsigned, len, fifo_count);
855 #ifdef CONFIG_USB_TUSB_OMAP_DMA
856 if (tusb_dma_omap() && is_buffer_mapped(req)) {
857 struct dma_controller *c = musb->dma_controller;
858 struct dma_channel *channel = musb_ep->dma;
859 u32 dma_addr = request->dma + request->actual;
862 ret = c->channel_program(channel,
864 channel->desired_mode,
872 * Unmap the dma buffer back to cpu if dma channel
873 * programming fails. This buffer is mapped if the
874 * channel allocation is successful
876 if (is_buffer_mapped(req)) {
877 unmap_dma_buffer(req, musb);
880 * Clear DMAENAB and AUTOCLEAR for the
883 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
884 musb_writew(epio, MUSB_RXCSR, csr);
887 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
888 (request->buf + request->actual));
889 request->actual += fifo_count;
891 /* REVISIT if we left anything in the fifo, flush
892 * it and report -EOVERFLOW
896 csr |= MUSB_RXCSR_P_WZC_BITS;
897 csr &= ~MUSB_RXCSR_RXPKTRDY;
898 musb_writew(epio, MUSB_RXCSR, csr);
902 /* reach the end or short packet detected */
903 if (request->actual == request->length || len < musb_ep->packet_sz)
904 musb_g_giveback(musb_ep, request, 0);
908 * Data ready for a request; called from IRQ
910 void musb_g_rx(struct musb *musb, u8 epnum)
913 struct musb_request *req;
914 struct usb_request *request;
915 void __iomem *mbase = musb->mregs;
916 struct musb_ep *musb_ep;
917 void __iomem *epio = musb->endpoints[epnum].regs;
918 struct dma_channel *dma;
919 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
921 if (hw_ep->is_shared_fifo)
922 musb_ep = &hw_ep->ep_in;
924 musb_ep = &hw_ep->ep_out;
926 musb_ep_select(mbase, epnum);
928 req = next_request(musb_ep);
932 request = &req->request;
934 csr = musb_readw(epio, MUSB_RXCSR);
935 dma = is_dma_capable() ? musb_ep->dma : NULL;
937 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
938 csr, dma ? " (dma)" : "", request);
940 if (csr & MUSB_RXCSR_P_SENTSTALL) {
941 csr |= MUSB_RXCSR_P_WZC_BITS;
942 csr &= ~MUSB_RXCSR_P_SENTSTALL;
943 musb_writew(epio, MUSB_RXCSR, csr);
947 if (csr & MUSB_RXCSR_P_OVERRUN) {
948 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
949 csr &= ~MUSB_RXCSR_P_OVERRUN;
950 musb_writew(epio, MUSB_RXCSR, csr);
952 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
953 if (request->status == -EINPROGRESS)
954 request->status = -EOVERFLOW;
956 if (csr & MUSB_RXCSR_INCOMPRX) {
957 /* REVISIT not necessarily an error */
958 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
961 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
962 /* "should not happen"; likely RXPKTRDY pending for DMA */
963 dev_dbg(musb->controller, "%s busy, csr %04x\n",
964 musb_ep->end_point.name, csr);
968 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
969 csr &= ~(MUSB_RXCSR_AUTOCLEAR
971 | MUSB_RXCSR_DMAMODE);
972 musb_writew(epio, MUSB_RXCSR,
973 MUSB_RXCSR_P_WZC_BITS | csr);
975 request->actual += musb_ep->dma->actual_len;
977 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
979 musb_readw(epio, MUSB_RXCSR),
980 musb_ep->dma->actual_len, request);
982 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
983 defined(CONFIG_USB_UX500_DMA)
984 /* Autoclear doesn't clear RxPktRdy for short packets */
985 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
987 & (musb_ep->packet_sz - 1))) {
989 csr &= ~MUSB_RXCSR_RXPKTRDY;
990 musb_writew(epio, MUSB_RXCSR, csr);
993 /* incomplete, and not short? wait for next IN packet */
994 if ((request->actual < request->length)
995 && (musb_ep->dma->actual_len
996 == musb_ep->packet_sz)) {
997 /* In double buffer case, continue to unload fifo if
998 * there is Rx packet in FIFO.
1000 csr = musb_readw(epio, MUSB_RXCSR);
1001 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
1002 hw_ep->rx_double_buffered)
1007 musb_g_giveback(musb_ep, request, 0);
1009 * In the giveback function the MUSB lock is
1010 * released and acquired after sometime. During
1011 * this time period the INDEX register could get
1012 * changed by the gadget_queue function especially
1013 * on SMP systems. Reselect the INDEX to be sure
1014 * we are reading/modifying the right registers
1016 musb_ep_select(mbase, epnum);
1018 req = next_request(musb_ep);
1022 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1023 defined(CONFIG_USB_UX500_DMA)
1026 /* Analyze request */
1030 /* ------------------------------------------------------------ */
1032 static int musb_gadget_enable(struct usb_ep *ep,
1033 const struct usb_endpoint_descriptor *desc)
1035 unsigned long flags;
1036 struct musb_ep *musb_ep;
1037 struct musb_hw_ep *hw_ep;
1040 void __iomem *mbase;
1044 int status = -EINVAL;
1049 musb_ep = to_musb_ep(ep);
1050 hw_ep = musb_ep->hw_ep;
1052 musb = musb_ep->musb;
1053 mbase = musb->mregs;
1054 epnum = musb_ep->current_epnum;
1056 spin_lock_irqsave(&musb->lock, flags);
1058 if (musb_ep->desc) {
1062 musb_ep->type = usb_endpoint_type(desc);
1064 /* check direction and (later) maxpacket size against endpoint */
1065 if (usb_endpoint_num(desc) != epnum)
1068 /* REVISIT this rules out high bandwidth periodic transfers */
1069 tmp = usb_endpoint_maxp(desc);
1070 if (tmp & ~0x07ff) {
1073 if (usb_endpoint_dir_in(desc))
1074 ok = musb->hb_iso_tx;
1076 ok = musb->hb_iso_rx;
1079 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1082 musb_ep->hb_mult = (tmp >> 11) & 3;
1084 musb_ep->hb_mult = 0;
1087 musb_ep->packet_sz = tmp & 0x7ff;
1088 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1090 /* enable the interrupts for the endpoint, set the endpoint
1091 * packet size (or fail), set the mode, clear the fifo
1093 musb_ep_select(mbase, epnum);
1094 if (usb_endpoint_dir_in(desc)) {
1095 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1097 if (hw_ep->is_shared_fifo)
1099 if (!musb_ep->is_in)
1102 if (tmp > hw_ep->max_packet_sz_tx) {
1103 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1107 int_txe |= (1 << epnum);
1108 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1110 /* REVISIT if can_bulk_split(), use by updating "tmp";
1111 * likewise high bandwidth periodic tx
1113 /* Set TXMAXP with the FIFO size of the endpoint
1114 * to disable double buffering mode.
1116 if (musb->double_buffer_not_ok)
1117 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1119 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1120 | (musb_ep->hb_mult << 11));
1122 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1123 if (musb_readw(regs, MUSB_TXCSR)
1124 & MUSB_TXCSR_FIFONOTEMPTY)
1125 csr |= MUSB_TXCSR_FLUSHFIFO;
1126 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1127 csr |= MUSB_TXCSR_P_ISO;
1129 /* set twice in case of double buffering */
1130 musb_writew(regs, MUSB_TXCSR, csr);
1131 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1132 musb_writew(regs, MUSB_TXCSR, csr);
1135 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1137 if (hw_ep->is_shared_fifo)
1142 if (tmp > hw_ep->max_packet_sz_rx) {
1143 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1147 int_rxe |= (1 << epnum);
1148 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1150 /* REVISIT if can_bulk_combine() use by updating "tmp"
1151 * likewise high bandwidth periodic rx
1153 /* Set RXMAXP with the FIFO size of the endpoint
1154 * to disable double buffering mode.
1156 if (musb->double_buffer_not_ok)
1157 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1159 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1160 | (musb_ep->hb_mult << 11));
1162 /* force shared fifo to OUT-only mode */
1163 if (hw_ep->is_shared_fifo) {
1164 csr = musb_readw(regs, MUSB_TXCSR);
1165 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1166 musb_writew(regs, MUSB_TXCSR, csr);
1169 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1170 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1171 csr |= MUSB_RXCSR_P_ISO;
1172 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1173 csr |= MUSB_RXCSR_DISNYET;
1175 /* set twice in case of double buffering */
1176 musb_writew(regs, MUSB_RXCSR, csr);
1177 musb_writew(regs, MUSB_RXCSR, csr);
1180 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1181 * for some reason you run out of channels here.
1183 if (is_dma_capable() && musb->dma_controller) {
1184 struct dma_controller *c = musb->dma_controller;
1186 musb_ep->dma = c->channel_alloc(c, hw_ep,
1187 (desc->bEndpointAddress & USB_DIR_IN));
1189 musb_ep->dma = NULL;
1191 musb_ep->end_point.desc = desc;
1192 musb_ep->desc = desc;
1194 musb_ep->wedged = 0;
1197 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1198 musb_driver_name, musb_ep->end_point.name,
1199 ({ char *s; switch (musb_ep->type) {
1200 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1201 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1202 default: s = "iso"; break;
1204 musb_ep->is_in ? "IN" : "OUT",
1205 musb_ep->dma ? "dma, " : "",
1206 musb_ep->packet_sz);
1208 schedule_work(&musb->irq_work);
1211 spin_unlock_irqrestore(&musb->lock, flags);
1216 * Disable an endpoint flushing all requests queued.
1218 static int musb_gadget_disable(struct usb_ep *ep)
1220 unsigned long flags;
1223 struct musb_ep *musb_ep;
1227 musb_ep = to_musb_ep(ep);
1228 musb = musb_ep->musb;
1229 epnum = musb_ep->current_epnum;
1230 epio = musb->endpoints[epnum].regs;
1232 spin_lock_irqsave(&musb->lock, flags);
1233 musb_ep_select(musb->mregs, epnum);
1235 /* zero the endpoint sizes */
1236 if (musb_ep->is_in) {
1237 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1238 int_txe &= ~(1 << epnum);
1239 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1240 musb_writew(epio, MUSB_TXMAXP, 0);
1242 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1243 int_rxe &= ~(1 << epnum);
1244 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1245 musb_writew(epio, MUSB_RXMAXP, 0);
1248 musb_ep->desc = NULL;
1249 musb_ep->end_point.desc = NULL;
1251 /* abort all pending DMA and requests */
1252 nuke(musb_ep, -ESHUTDOWN);
1254 schedule_work(&musb->irq_work);
1256 spin_unlock_irqrestore(&(musb->lock), flags);
1258 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1264 * Allocate a request for an endpoint.
1265 * Reused by ep0 code.
1267 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1269 struct musb_ep *musb_ep = to_musb_ep(ep);
1270 struct musb *musb = musb_ep->musb;
1271 struct musb_request *request = NULL;
1273 request = kzalloc(sizeof *request, gfp_flags);
1275 dev_dbg(musb->controller, "not enough memory\n");
1279 request->request.dma = DMA_ADDR_INVALID;
1280 request->epnum = musb_ep->current_epnum;
1281 request->ep = musb_ep;
1283 return &request->request;
1288 * Reused by ep0 code.
1290 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1292 kfree(to_musb_request(req));
1295 static LIST_HEAD(buffers);
1297 struct free_record {
1298 struct list_head list;
1305 * Context: controller locked, IRQs blocked.
1307 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1309 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1310 req->tx ? "TX/IN" : "RX/OUT",
1311 &req->request, req->request.length, req->epnum);
1313 musb_ep_select(musb->mregs, req->epnum);
1320 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1323 struct musb_ep *musb_ep;
1324 struct musb_request *request;
1327 unsigned long lockflags;
1334 musb_ep = to_musb_ep(ep);
1335 musb = musb_ep->musb;
1337 request = to_musb_request(req);
1338 request->musb = musb;
1340 if (request->ep != musb_ep)
1343 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1345 /* request is mine now... */
1346 request->request.actual = 0;
1347 request->request.status = -EINPROGRESS;
1348 request->epnum = musb_ep->current_epnum;
1349 request->tx = musb_ep->is_in;
1351 map_dma_buffer(request, musb, musb_ep);
1353 spin_lock_irqsave(&musb->lock, lockflags);
1355 /* don't queue if the ep is down */
1356 if (!musb_ep->desc) {
1357 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1358 req, ep->name, "disabled");
1359 status = -ESHUTDOWN;
1363 /* add request to the list */
1364 list_add_tail(&request->list, &musb_ep->req_list);
1366 /* it this is the head of the queue, start i/o ... */
1367 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1368 musb_ep_restart(musb, request);
1371 spin_unlock_irqrestore(&musb->lock, lockflags);
1375 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1377 struct musb_ep *musb_ep = to_musb_ep(ep);
1378 struct musb_request *req = to_musb_request(request);
1379 struct musb_request *r;
1380 unsigned long flags;
1382 struct musb *musb = musb_ep->musb;
1384 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1387 spin_lock_irqsave(&musb->lock, flags);
1389 list_for_each_entry(r, &musb_ep->req_list, list) {
1394 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1399 /* if the hardware doesn't have the request, easy ... */
1400 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1401 musb_g_giveback(musb_ep, request, -ECONNRESET);
1403 /* ... else abort the dma transfer ... */
1404 else if (is_dma_capable() && musb_ep->dma) {
1405 struct dma_controller *c = musb->dma_controller;
1407 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1408 if (c->channel_abort)
1409 status = c->channel_abort(musb_ep->dma);
1413 musb_g_giveback(musb_ep, request, -ECONNRESET);
1415 /* NOTE: by sticking to easily tested hardware/driver states,
1416 * we leave counting of in-flight packets imprecise.
1418 musb_g_giveback(musb_ep, request, -ECONNRESET);
1422 spin_unlock_irqrestore(&musb->lock, flags);
1427 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1428 * data but will queue requests.
1430 * exported to ep0 code
1432 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1434 struct musb_ep *musb_ep = to_musb_ep(ep);
1435 u8 epnum = musb_ep->current_epnum;
1436 struct musb *musb = musb_ep->musb;
1437 void __iomem *epio = musb->endpoints[epnum].regs;
1438 void __iomem *mbase;
1439 unsigned long flags;
1441 struct musb_request *request;
1446 mbase = musb->mregs;
1448 spin_lock_irqsave(&musb->lock, flags);
1450 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1455 musb_ep_select(mbase, epnum);
1457 request = next_request(musb_ep);
1460 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1465 /* Cannot portably stall with non-empty FIFO */
1466 if (musb_ep->is_in) {
1467 csr = musb_readw(epio, MUSB_TXCSR);
1468 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1469 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1475 musb_ep->wedged = 0;
1477 /* set/clear the stall and toggle bits */
1478 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1479 if (musb_ep->is_in) {
1480 csr = musb_readw(epio, MUSB_TXCSR);
1481 csr |= MUSB_TXCSR_P_WZC_BITS
1482 | MUSB_TXCSR_CLRDATATOG;
1484 csr |= MUSB_TXCSR_P_SENDSTALL;
1486 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1487 | MUSB_TXCSR_P_SENTSTALL);
1488 csr &= ~MUSB_TXCSR_TXPKTRDY;
1489 musb_writew(epio, MUSB_TXCSR, csr);
1491 csr = musb_readw(epio, MUSB_RXCSR);
1492 csr |= MUSB_RXCSR_P_WZC_BITS
1493 | MUSB_RXCSR_FLUSHFIFO
1494 | MUSB_RXCSR_CLRDATATOG;
1496 csr |= MUSB_RXCSR_P_SENDSTALL;
1498 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1499 | MUSB_RXCSR_P_SENTSTALL);
1500 musb_writew(epio, MUSB_RXCSR, csr);
1503 /* maybe start the first request in the queue */
1504 if (!musb_ep->busy && !value && request) {
1505 dev_dbg(musb->controller, "restarting the request\n");
1506 musb_ep_restart(musb, request);
1510 spin_unlock_irqrestore(&musb->lock, flags);
1516 * Sets the halt feature with the clear requests ignored
1518 static int musb_gadget_set_wedge(struct usb_ep *ep)
1520 struct musb_ep *musb_ep = to_musb_ep(ep);
1525 musb_ep->wedged = 1;
1527 return usb_ep_set_halt(ep);
1531 static int musb_gadget_fifo_status(struct usb_ep *ep)
1533 struct musb_ep *musb_ep = to_musb_ep(ep);
1534 void __iomem *epio = musb_ep->hw_ep->regs;
1535 int retval = -EINVAL;
1537 if (musb_ep->desc && !musb_ep->is_in) {
1538 struct musb *musb = musb_ep->musb;
1539 int epnum = musb_ep->current_epnum;
1540 void __iomem *mbase = musb->mregs;
1541 unsigned long flags;
1543 spin_lock_irqsave(&musb->lock, flags);
1545 musb_ep_select(mbase, epnum);
1546 /* FIXME return zero unless RXPKTRDY is set */
1547 retval = musb_readw(epio, MUSB_RXCOUNT);
1549 spin_unlock_irqrestore(&musb->lock, flags);
1554 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1556 struct musb_ep *musb_ep = to_musb_ep(ep);
1557 struct musb *musb = musb_ep->musb;
1558 u8 epnum = musb_ep->current_epnum;
1559 void __iomem *epio = musb->endpoints[epnum].regs;
1560 void __iomem *mbase;
1561 unsigned long flags;
1564 mbase = musb->mregs;
1566 spin_lock_irqsave(&musb->lock, flags);
1567 musb_ep_select(mbase, (u8) epnum);
1569 /* disable interrupts */
1570 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1571 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1573 if (musb_ep->is_in) {
1574 csr = musb_readw(epio, MUSB_TXCSR);
1575 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1576 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1578 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1579 * to interrupt current FIFO loading, but not flushing
1580 * the already loaded ones.
1582 csr &= ~MUSB_TXCSR_TXPKTRDY;
1583 musb_writew(epio, MUSB_TXCSR, csr);
1584 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1585 musb_writew(epio, MUSB_TXCSR, csr);
1588 csr = musb_readw(epio, MUSB_RXCSR);
1589 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1590 musb_writew(epio, MUSB_RXCSR, csr);
1591 musb_writew(epio, MUSB_RXCSR, csr);
1594 /* re-enable interrupt */
1595 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1596 spin_unlock_irqrestore(&musb->lock, flags);
1599 static const struct usb_ep_ops musb_ep_ops = {
1600 .enable = musb_gadget_enable,
1601 .disable = musb_gadget_disable,
1602 .alloc_request = musb_alloc_request,
1603 .free_request = musb_free_request,
1604 .queue = musb_gadget_queue,
1605 .dequeue = musb_gadget_dequeue,
1606 .set_halt = musb_gadget_set_halt,
1608 .set_wedge = musb_gadget_set_wedge,
1610 .fifo_status = musb_gadget_fifo_status,
1611 .fifo_flush = musb_gadget_fifo_flush
1614 /* ----------------------------------------------------------------------- */
1616 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1618 struct musb *musb = gadget_to_musb(gadget);
1620 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1623 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1626 struct musb *musb = gadget_to_musb(gadget);
1627 void __iomem *mregs = musb->mregs;
1628 unsigned long flags;
1629 int status = -EINVAL;
1633 spin_lock_irqsave(&musb->lock, flags);
1635 switch (musb->xceiv->state) {
1636 case OTG_STATE_B_PERIPHERAL:
1637 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1638 * that's part of the standard usb 1.1 state machine, and
1639 * doesn't affect OTG transitions.
1641 if (musb->may_wakeup && musb->is_suspended)
1644 case OTG_STATE_B_IDLE:
1645 /* Start SRP ... OTG not required. */
1646 devctl = musb_readb(mregs, MUSB_DEVCTL);
1647 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1648 devctl |= MUSB_DEVCTL_SESSION;
1649 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1650 devctl = musb_readb(mregs, MUSB_DEVCTL);
1652 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1653 devctl = musb_readb(mregs, MUSB_DEVCTL);
1658 while (devctl & MUSB_DEVCTL_SESSION) {
1659 devctl = musb_readb(mregs, MUSB_DEVCTL);
1664 spin_unlock_irqrestore(&musb->lock, flags);
1665 otg_start_srp(musb->xceiv->otg);
1666 spin_lock_irqsave(&musb->lock, flags);
1668 /* Block idling for at least 1s */
1669 musb_platform_try_idle(musb,
1670 jiffies + msecs_to_jiffies(1 * HZ));
1675 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1676 otg_state_string(musb->xceiv->state));
1682 power = musb_readb(mregs, MUSB_POWER);
1683 power |= MUSB_POWER_RESUME;
1684 musb_writeb(mregs, MUSB_POWER, power);
1685 dev_dbg(musb->controller, "issue wakeup\n");
1687 /* FIXME do this next chunk in a timer callback, no udelay */
1690 power = musb_readb(mregs, MUSB_POWER);
1691 power &= ~MUSB_POWER_RESUME;
1692 musb_writeb(mregs, MUSB_POWER, power);
1694 spin_unlock_irqrestore(&musb->lock, flags);
1702 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1704 struct musb *musb = gadget_to_musb(gadget);
1706 musb->is_self_powered = !!is_selfpowered;
1710 static void musb_pullup(struct musb *musb, int is_on)
1714 power = musb_readb(musb->mregs, MUSB_POWER);
1716 power |= MUSB_POWER_SOFTCONN;
1718 power &= ~MUSB_POWER_SOFTCONN;
1720 /* FIXME if on, HdrcStart; if off, HdrcStop */
1722 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1723 is_on ? "on" : "off");
1724 musb_writeb(musb->mregs, MUSB_POWER, power);
1728 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1730 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1733 * FIXME iff driver's softconnect flag is set (as it is during probe,
1734 * though that can clear it), just musb_pullup().
1741 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1744 struct musb *musb = gadget_to_musb(gadget);
1746 if (!musb->xceiv->set_power)
1748 return usb_phy_set_power(musb->xceiv, mA);
1754 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1756 struct musb *musb = gadget_to_musb(gadget);
1757 unsigned long flags;
1761 pm_runtime_get_sync(musb->controller);
1763 /* NOTE: this assumes we are sensing vbus; we'd rather
1764 * not pullup unless the B-session is active.
1766 spin_lock_irqsave(&musb->lock, flags);
1767 if (is_on != musb->softconnect) {
1768 musb->softconnect = is_on;
1769 musb_pullup(musb, is_on);
1771 spin_unlock_irqrestore(&musb->lock, flags);
1773 pm_runtime_put(musb->controller);
1779 static int musb_gadget_start(struct usb_gadget *g,
1780 struct usb_gadget_driver *driver);
1781 static int musb_gadget_stop(struct usb_gadget *g,
1782 struct usb_gadget_driver *driver);
1784 static int musb_gadget_stop(struct usb_gadget *g)
1786 struct musb *musb = gadget_to_musb(g);
1793 static const struct usb_gadget_ops musb_gadget_operations = {
1794 .get_frame = musb_gadget_get_frame,
1795 .wakeup = musb_gadget_wakeup,
1796 .set_selfpowered = musb_gadget_set_self_powered,
1797 /* .vbus_session = musb_gadget_vbus_session, */
1798 .vbus_draw = musb_gadget_vbus_draw,
1799 .pullup = musb_gadget_pullup,
1801 .udc_start = musb_gadget_start,
1802 .udc_stop = musb_gadget_stop,
1804 .udc_start = musb_gadget_start,
1805 .udc_stop = musb_gadget_stop,
1809 /* ----------------------------------------------------------------------- */
1813 /* Only this registration code "knows" the rule (from USB standards)
1814 * about there being only one external upstream port. It assumes
1815 * all peripheral ports are external...
1819 static void musb_gadget_release(struct device *dev)
1821 /* kref_put(WHAT) */
1822 dev_dbg(dev, "%s\n", __func__);
1827 static void __devinit
1828 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1830 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1832 memset(ep, 0, sizeof *ep);
1834 ep->current_epnum = epnum;
1839 INIT_LIST_HEAD(&ep->req_list);
1841 sprintf(ep->name, "ep%d%s", epnum,
1842 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1843 is_in ? "in" : "out"));
1844 ep->end_point.name = ep->name;
1845 INIT_LIST_HEAD(&ep->end_point.ep_list);
1847 ep->end_point.maxpacket = 64;
1848 ep->end_point.ops = &musb_g_ep0_ops;
1849 musb->g.ep0 = &ep->end_point;
1852 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1854 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1855 ep->end_point.ops = &musb_ep_ops;
1856 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1861 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1862 * to the rest of the driver state.
1864 static inline void __devinit musb_g_init_endpoints(struct musb *musb)
1867 struct musb_hw_ep *hw_ep;
1870 /* initialize endpoint list just once */
1871 INIT_LIST_HEAD(&(musb->g.ep_list));
1873 for (epnum = 0, hw_ep = musb->endpoints;
1874 epnum < musb->nr_endpoints;
1876 if (hw_ep->is_shared_fifo /* || !epnum */) {
1877 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1880 if (hw_ep->max_packet_sz_tx) {
1881 init_peripheral_ep(musb, &hw_ep->ep_in,
1885 if (hw_ep->max_packet_sz_rx) {
1886 init_peripheral_ep(musb, &hw_ep->ep_out,
1894 /* called once during driver setup to initialize and link into
1895 * the driver model; memory is zeroed.
1897 int __devinit musb_gadget_setup(struct musb *musb)
1901 /* REVISIT minor race: if (erroneously) setting up two
1902 * musb peripherals at the same time, only the bus lock
1906 musb->g.ops = &musb_gadget_operations;
1908 musb->g.max_speed = USB_SPEED_HIGH;
1910 musb->g.speed = USB_SPEED_UNKNOWN;
1913 /* this "gadget" abstracts/virtualizes the controller */
1914 dev_set_name(&musb->g.dev, "gadget");
1915 musb->g.dev.parent = musb->controller;
1916 musb->g.dev.dma_mask = musb->controller->dma_mask;
1917 musb->g.dev.release = musb_gadget_release;
1919 musb->g.name = musb_driver_name;
1922 if (is_otg_enabled(musb))
1926 musb_g_init_endpoints(musb);
1928 musb->is_active = 0;
1929 musb_platform_try_idle(musb, 0);
1932 status = device_register(&musb->g.dev);
1934 put_device(&musb->g.dev);
1937 status = usb_add_gadget_udc(musb->controller, &musb->g);
1945 musb->g.dev.parent = NULL;
1946 device_unregister(&musb->g.dev);
1951 void musb_gadget_cleanup(struct musb *musb)
1954 usb_del_gadget_udc(&musb->g);
1955 if (musb->g.dev.parent)
1956 device_unregister(&musb->g.dev);
1961 * Register the gadget driver. Used by gadget drivers when
1962 * registering themselves with the controller.
1964 * -EINVAL something went wrong (not driver)
1965 * -EBUSY another gadget is already using the controller
1966 * -ENOMEM no memory to perform the operation
1968 * @param driver the gadget driver
1969 * @return <0 if error, 0 if everything is fine
1972 static int musb_gadget_start(struct usb_gadget *g,
1973 struct usb_gadget_driver *driver)
1975 int musb_gadget_start(struct usb_gadget *g,
1976 struct usb_gadget_driver *driver)
1979 struct musb *musb = gadget_to_musb(g);
1981 struct usb_otg *otg = musb->xceiv->otg;
1983 unsigned long flags;
1984 int retval = -EINVAL;
1987 if (driver->max_speed < USB_SPEED_HIGH)
1991 pm_runtime_get_sync(musb->controller);
1994 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1997 musb->softconnect = 0;
1998 musb->gadget_driver = driver;
2000 spin_lock_irqsave(&musb->lock, flags);
2001 musb->is_active = 1;
2004 otg_set_peripheral(otg, &musb->g);
2005 musb->xceiv->state = OTG_STATE_B_IDLE;
2008 * FIXME this ignores the softconnect flag. Drivers are
2009 * allowed hold the peripheral inactive until for example
2010 * userspace hooks up printer hardware or DSP codecs, so
2011 * hosts only see fully functional devices.
2014 if (!is_otg_enabled(musb))
2018 spin_unlock_irqrestore(&musb->lock, flags);
2021 if (is_otg_enabled(musb)) {
2022 struct usb_hcd *hcd = musb_to_hcd(musb);
2024 dev_dbg(musb->controller, "OTG startup...\n");
2026 /* REVISIT: funcall to other code, which also
2027 * handles power budgeting ... this way also
2028 * ensures HdrcStart is indirectly called.
2030 retval = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2032 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
2036 if ((musb->xceiv->last_event == USB_EVENT_ID)
2038 otg_set_vbus(otg, 1);
2040 hcd->self.uses_pio_for_control = 1;
2042 if (musb->xceiv->last_event == USB_EVENT_NONE)
2043 pm_runtime_put(musb->controller);
2050 if (!is_otg_enabled(musb))
2058 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
2061 struct musb_hw_ep *hw_ep;
2063 /* don't disconnect if it's not connected */
2064 if (musb->g.speed == USB_SPEED_UNKNOWN)
2067 musb->g.speed = USB_SPEED_UNKNOWN;
2069 /* deactivate the hardware */
2070 if (musb->softconnect) {
2071 musb->softconnect = 0;
2072 musb_pullup(musb, 0);
2076 /* killing any outstanding requests will quiesce the driver;
2077 * then report disconnect
2080 for (i = 0, hw_ep = musb->endpoints;
2081 i < musb->nr_endpoints;
2083 musb_ep_select(musb->mregs, i);
2084 if (hw_ep->is_shared_fifo /* || !epnum */) {
2085 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2087 if (hw_ep->max_packet_sz_tx)
2088 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2089 if (hw_ep->max_packet_sz_rx)
2090 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2097 * Unregister the gadget driver. Used by gadget drivers when
2098 * unregistering themselves from the controller.
2100 * @param driver the gadget driver to unregister
2102 static int musb_gadget_stop(struct usb_gadget *g,
2103 struct usb_gadget_driver *driver)
2105 struct musb *musb = gadget_to_musb(g);
2106 unsigned long flags;
2108 if (musb->xceiv->last_event == USB_EVENT_NONE)
2109 pm_runtime_get_sync(musb->controller);
2112 * REVISIT always use otg_set_peripheral() here too;
2113 * this needs to shut down the OTG engine.
2116 spin_lock_irqsave(&musb->lock, flags);
2118 musb_hnp_stop(musb);
2120 (void) musb_gadget_vbus_draw(&musb->g, 0);
2122 musb->xceiv->state = OTG_STATE_UNDEFINED;
2123 stop_activity(musb, driver);
2124 otg_set_peripheral(musb->xceiv->otg, NULL);
2126 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2128 musb->is_active = 0;
2129 musb_platform_try_idle(musb, 0);
2130 spin_unlock_irqrestore(&musb->lock, flags);
2132 if (is_otg_enabled(musb)) {
2133 usb_remove_hcd(musb_to_hcd(musb));
2134 /* FIXME we need to be able to register another
2135 * gadget driver here and have everything work;
2136 * that currently misbehaves.
2140 if (!is_otg_enabled(musb))
2143 pm_runtime_put(musb->controller);
2149 /* ----------------------------------------------------------------------- */
2151 /* lifecycle operations called through plat_uds.c */
2153 void musb_g_resume(struct musb *musb)
2156 musb->is_suspended = 0;
2157 switch (musb->xceiv->state) {
2158 case OTG_STATE_B_IDLE:
2160 case OTG_STATE_B_WAIT_ACON:
2161 case OTG_STATE_B_PERIPHERAL:
2162 musb->is_active = 1;
2163 if (musb->gadget_driver && musb->gadget_driver->resume) {
2164 spin_unlock(&musb->lock);
2165 musb->gadget_driver->resume(&musb->g);
2166 spin_lock(&musb->lock);
2170 WARNING("unhandled RESUME transition (%s)\n",
2171 otg_state_string(musb->xceiv->state));
2176 /* called when SOF packets stop for 3+ msec */
2177 void musb_g_suspend(struct musb *musb)
2182 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2183 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2185 switch (musb->xceiv->state) {
2186 case OTG_STATE_B_IDLE:
2187 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2188 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2190 case OTG_STATE_B_PERIPHERAL:
2191 musb->is_suspended = 1;
2192 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2193 spin_unlock(&musb->lock);
2194 musb->gadget_driver->suspend(&musb->g);
2195 spin_lock(&musb->lock);
2199 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2200 * A_PERIPHERAL may need care too
2202 WARNING("unhandled SUSPEND transition (%s)\n",
2203 otg_state_string(musb->xceiv->state));
2208 /* Called during SRP */
2209 void musb_g_wakeup(struct musb *musb)
2211 musb_gadget_wakeup(&musb->g);
2214 /* called when VBUS drops below session threshold, and in other cases */
2215 void musb_g_disconnect(struct musb *musb)
2217 void __iomem *mregs = musb->mregs;
2218 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2220 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2223 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2225 /* don't draw vbus until new b-default session */
2226 (void) musb_gadget_vbus_draw(&musb->g, 0);
2228 musb->g.speed = USB_SPEED_UNKNOWN;
2229 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2230 spin_unlock(&musb->lock);
2231 musb->gadget_driver->disconnect(&musb->g);
2232 spin_lock(&musb->lock);
2236 switch (musb->xceiv->state) {
2238 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2239 otg_state_string(musb->xceiv->state));
2240 musb->xceiv->state = OTG_STATE_A_IDLE;
2241 MUSB_HST_MODE(musb);
2243 case OTG_STATE_A_PERIPHERAL:
2244 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2245 MUSB_HST_MODE(musb);
2247 case OTG_STATE_B_WAIT_ACON:
2248 case OTG_STATE_B_HOST:
2249 case OTG_STATE_B_PERIPHERAL:
2250 case OTG_STATE_B_IDLE:
2251 musb->xceiv->state = OTG_STATE_B_IDLE;
2253 case OTG_STATE_B_SRP_INIT:
2258 musb->is_active = 0;
2261 void musb_g_reset(struct musb *musb)
2262 __releases(musb->lock)
2263 __acquires(musb->lock)
2265 void __iomem *mbase = musb->mregs;
2266 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2270 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2271 (devctl & MUSB_DEVCTL_BDEVICE)
2272 ? "B-Device" : "A-Device",
2273 musb_readb(mbase, MUSB_FADDR),
2275 ? musb->gadget_driver->driver.name
2280 /* report disconnect, if we didn't already (flushing EP state) */
2281 if (musb->g.speed != USB_SPEED_UNKNOWN)
2282 musb_g_disconnect(musb);
2285 else if (devctl & MUSB_DEVCTL_HR)
2286 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2289 /* what speed did we negotiate? */
2290 power = musb_readb(mbase, MUSB_POWER);
2291 musb->g.speed = (power & MUSB_POWER_HSMODE)
2292 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2294 /* start in USB_STATE_DEFAULT */
2295 musb->is_active = 1;
2296 musb->is_suspended = 0;
2297 MUSB_DEV_MODE(musb);
2299 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2301 musb->may_wakeup = 0;
2302 musb->g.b_hnp_enable = 0;
2303 musb->g.a_alt_hnp_support = 0;
2304 musb->g.a_hnp_support = 0;
2307 /* Normal reset, as B-Device;
2308 * or else after HNP, as A-Device
2310 if (devctl & MUSB_DEVCTL_BDEVICE) {
2311 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2312 musb->g.is_a_peripheral = 0;
2313 } else if (is_otg_enabled(musb)) {
2314 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2315 musb->g.is_a_peripheral = 1;
2319 /* start with default limits on VBUS power draw */
2320 (void) musb_gadget_vbus_draw(&musb->g,
2321 is_otg_enabled(musb) ? 8 : 100);