1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver core code
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
43 * RESULT: one device may be perceived as blocking another one.
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific informarion
62 * (plus recentrly, SOC or family details)
64 * Most of the conditional compilation will (someday) vanish.
69 #include <dm/device_compat.h>
70 #include <dm/devres.h>
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/sched.h>
74 #include <linux/slab.h>
75 #include <linux/init.h>
76 #include <linux/list.h>
77 #include <linux/kobject.h>
78 #include <linux/prefetch.h>
79 #include <linux/platform_device.h>
84 #include <dm/device_compat.h>
86 #include <linux/bitops.h>
87 #include <linux/bug.h>
88 #include <linux/errno.h>
89 #include <linux/usb/ch9.h>
90 #include <linux/usb/gadget.h>
91 #include <linux/usb/musb.h>
92 #include <linux/usb/usb_urb_compat.h>
94 #include "linux-compat.h"
97 #include "musb_core.h"
99 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
102 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
103 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
105 #define MUSB_VERSION "6.0"
107 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
109 #define MUSB_DRIVER_NAME "musb-hdrc"
110 const char musb_driver_name[] = MUSB_DRIVER_NAME;
112 MODULE_DESCRIPTION(DRIVER_INFO);
113 MODULE_AUTHOR(DRIVER_AUTHOR);
114 MODULE_LICENSE("GPL");
115 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
119 /*-------------------------------------------------------------------------*/
121 static inline struct musb *dev_to_musb(struct device *dev)
123 return dev_get_drvdata(dev);
126 /*-------------------------------------------------------------------------*/
128 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
130 void __iomem *addr = phy->io_priv;
136 pm_runtime_get_sync(phy->io_dev);
138 /* Make sure the transceiver is not in low power mode */
139 power = musb_readb(addr, MUSB_POWER);
140 power &= ~MUSB_POWER_SUSPENDM;
141 musb_writeb(addr, MUSB_POWER, power);
143 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
144 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
147 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
148 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
149 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
151 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
152 & MUSB_ULPI_REG_CMPLT)) {
160 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
161 r &= ~MUSB_ULPI_REG_CMPLT;
162 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
167 pm_runtime_put(phy->io_dev);
172 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
174 void __iomem *addr = phy->io_priv;
180 pm_runtime_get_sync(phy->io_dev);
182 /* Make sure the transceiver is not in low power mode */
183 power = musb_readb(addr, MUSB_POWER);
184 power &= ~MUSB_POWER_SUSPENDM;
185 musb_writeb(addr, MUSB_POWER, power);
187 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
188 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
191 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
192 & MUSB_ULPI_REG_CMPLT)) {
200 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
201 r &= ~MUSB_ULPI_REG_CMPLT;
202 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
205 pm_runtime_put(phy->io_dev);
210 static struct usb_phy_io_ops musb_ulpi_access = {
211 .read = musb_ulpi_read,
212 .write = musb_ulpi_write,
216 /*-------------------------------------------------------------------------*/
218 #if !defined(CONFIG_USB_MUSB_TUSB6010)
221 * Load an endpoint's FIFO
223 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
225 struct musb *musb = hw_ep->musb;
226 void __iomem *fifo = hw_ep->fifo;
230 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
231 'T', hw_ep->epnum, fifo, len, src);
233 /* we can't assume unaligned reads work */
234 if (likely((0x01 & (unsigned long) src) == 0)) {
237 /* best case is 32bit-aligned source address */
238 if ((0x02 & (unsigned long) src) == 0) {
240 writesl(fifo, src + index, len >> 2);
241 index += len & ~0x03;
244 musb_writew(fifo, 0, *(u16 *)&src[index]);
249 writesw(fifo, src + index, len >> 1);
250 index += len & ~0x01;
254 musb_writeb(fifo, 0, src[index]);
257 writesb(fifo, src, len);
261 #if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
263 * Unload an endpoint's FIFO
265 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
267 struct musb *musb = hw_ep->musb;
268 void __iomem *fifo = hw_ep->fifo;
270 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
271 'R', hw_ep->epnum, fifo, len, dst);
273 /* we can't assume unaligned writes work */
274 if (likely((0x01 & (unsigned long) dst) == 0)) {
277 /* best case is 32bit-aligned destination address */
278 if ((0x02 & (unsigned long) dst) == 0) {
280 readsl(fifo, dst, len >> 2);
284 *(u16 *)&dst[index] = musb_readw(fifo, 0);
289 readsw(fifo, dst, len >> 1);
294 dst[index] = musb_readb(fifo, 0);
297 readsb(fifo, dst, len);
302 #endif /* normal PIO */
305 /*-------------------------------------------------------------------------*/
307 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
308 static const u8 musb_test_packet[53] = {
309 /* implicit SYNC then DATA0 to start */
312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
316 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
317 /* JJJJJJJKKKKKKK x8 */
318 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
320 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
321 /* JKKKKKKK x10, JK */
322 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
324 /* implicit CRC16 then EOP to end */
327 void musb_load_testpacket(struct musb *musb)
329 void __iomem *regs = musb->endpoints[0].regs;
331 musb_ep_select(musb->mregs, 0);
332 musb_write_fifo(musb->control_ep,
333 sizeof(musb_test_packet), musb_test_packet);
334 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
338 /*-------------------------------------------------------------------------*/
341 * Handles OTG hnp timeouts, such as b_ase0_brst
343 void musb_otg_timer_func(unsigned long data)
345 struct musb *musb = (struct musb *)data;
348 spin_lock_irqsave(&musb->lock, flags);
349 switch (musb->xceiv->state) {
350 case OTG_STATE_B_WAIT_ACON:
351 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
352 musb_g_disconnect(musb);
353 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
356 case OTG_STATE_A_SUSPEND:
357 case OTG_STATE_A_WAIT_BCON:
358 dev_dbg(musb->controller, "HNP: %s timeout\n",
359 otg_state_string(musb->xceiv->state));
360 musb_platform_set_vbus(musb, 0);
361 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
364 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
365 otg_state_string(musb->xceiv->state));
367 musb->ignore_disconnect = 0;
368 spin_unlock_irqrestore(&musb->lock, flags);
372 * Stops the HNP transition. Caller must take care of locking.
374 void musb_hnp_stop(struct musb *musb)
376 struct usb_hcd *hcd = musb_to_hcd(musb);
377 void __iomem *mbase = musb->mregs;
380 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
382 switch (musb->xceiv->state) {
383 case OTG_STATE_A_PERIPHERAL:
384 musb_g_disconnect(musb);
385 dev_dbg(musb->controller, "HNP: back to %s\n",
386 otg_state_string(musb->xceiv->state));
388 case OTG_STATE_B_HOST:
389 dev_dbg(musb->controller, "HNP: Disabling HR\n");
390 hcd->self.is_b_host = 0;
391 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
393 reg = musb_readb(mbase, MUSB_POWER);
394 reg |= MUSB_POWER_SUSPENDM;
395 musb_writeb(mbase, MUSB_POWER, reg);
396 /* REVISIT: Start SESSION_REQUEST here? */
399 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
400 otg_state_string(musb->xceiv->state));
404 * When returning to A state after HNP, avoid hub_port_rebounce(),
405 * which cause occasional OPT A "Did not receive reset after connect"
408 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
413 * Interrupt Service Routine to record USB "global" interrupts.
414 * Since these do not happen often and signify things of
415 * paramount importance, it seems OK to check them individually;
416 * the order of the tests is specified in the manual
418 * @param musb instance pointer
419 * @param int_usb register contents
424 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
428 struct usb_otg *otg = musb->xceiv->otg;
430 irqreturn_t handled = IRQ_NONE;
432 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
436 /* in host mode, the peripheral may issue remote wakeup.
437 * in peripheral mode, the host may resume the link.
438 * spurious RESUME irqs happen too, paired with SUSPEND.
440 if (int_usb & MUSB_INTR_RESUME) {
441 handled = IRQ_HANDLED;
442 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
444 if (devctl & MUSB_DEVCTL_HM) {
445 void __iomem *mbase = musb->mregs;
447 switch (musb->xceiv->state) {
448 case OTG_STATE_A_SUSPEND:
449 /* remote wakeup? later, GetPortStatus
450 * will stop RESUME signaling
453 if (power & MUSB_POWER_SUSPENDM) {
455 musb->int_usb &= ~MUSB_INTR_SUSPEND;
456 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
460 power &= ~MUSB_POWER_SUSPENDM;
461 musb_writeb(mbase, MUSB_POWER,
462 power | MUSB_POWER_RESUME);
464 musb->port1_status |=
465 (USB_PORT_STAT_C_SUSPEND << 16)
466 | MUSB_PORT_STAT_RESUME;
467 musb->rh_timer = jiffies
468 + msecs_to_jiffies(20);
470 musb->xceiv->state = OTG_STATE_A_HOST;
472 usb_hcd_resume_root_hub(musb_to_hcd(musb));
474 case OTG_STATE_B_WAIT_ACON:
475 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
480 WARNING("bogus %s RESUME (%s)\n",
482 otg_state_string(musb->xceiv->state));
485 switch (musb->xceiv->state) {
486 case OTG_STATE_A_SUSPEND:
487 /* possibly DISCONNECT is upcoming */
488 musb->xceiv->state = OTG_STATE_A_HOST;
489 usb_hcd_resume_root_hub(musb_to_hcd(musb));
491 case OTG_STATE_B_WAIT_ACON:
492 case OTG_STATE_B_PERIPHERAL:
493 /* disconnect while suspended? we may
494 * not get a disconnect irq...
496 if ((devctl & MUSB_DEVCTL_VBUS)
497 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
499 musb->int_usb |= MUSB_INTR_DISCONNECT;
500 musb->int_usb &= ~MUSB_INTR_SUSPEND;
505 case OTG_STATE_B_IDLE:
506 musb->int_usb &= ~MUSB_INTR_SUSPEND;
509 WARNING("bogus %s RESUME (%s)\n",
511 otg_state_string(musb->xceiv->state));
516 /* see manual for the order of the tests */
517 if (int_usb & MUSB_INTR_SESSREQ) {
518 void __iomem *mbase = musb->mregs;
520 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
521 && (devctl & MUSB_DEVCTL_BDEVICE)) {
522 dev_dbg(musb->controller, "SessReq while on B state\n");
526 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
527 otg_state_string(musb->xceiv->state));
529 /* IRQ arrives from ID pin sense or (later, if VBUS power
530 * is removed) SRP. responses are time critical:
531 * - turn on VBUS (with silicon-specific mechanism)
532 * - go through A_WAIT_VRISE
533 * - ... to A_WAIT_BCON.
534 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
536 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
537 musb->ep0_stage = MUSB_EP0_START;
538 musb->xceiv->state = OTG_STATE_A_IDLE;
540 musb_platform_set_vbus(musb, 1);
542 handled = IRQ_HANDLED;
545 if (int_usb & MUSB_INTR_VBUSERROR) {
548 /* During connection as an A-Device, we may see a short
549 * current spikes causing voltage drop, because of cable
550 * and peripheral capacitance combined with vbus draw.
551 * (So: less common with truly self-powered devices, where
552 * vbus doesn't act like a power supply.)
554 * Such spikes are short; usually less than ~500 usec, max
555 * of ~2 msec. That is, they're not sustained overcurrent
556 * errors, though they're reported using VBUSERROR irqs.
558 * Workarounds: (a) hardware: use self powered devices.
559 * (b) software: ignore non-repeated VBUS errors.
561 * REVISIT: do delays from lots of DEBUG_KERNEL checks
562 * make trouble here, keeping VBUS < 4.4V ?
564 switch (musb->xceiv->state) {
565 case OTG_STATE_A_HOST:
566 /* recovery is dicey once we've gotten past the
567 * initial stages of enumeration, but if VBUS
568 * stayed ok at the other end of the link, and
569 * another reset is due (at least for high speed,
570 * to redo the chirp etc), it might work OK...
572 case OTG_STATE_A_WAIT_BCON:
573 case OTG_STATE_A_WAIT_VRISE:
574 if (musb->vbuserr_retry) {
575 void __iomem *mbase = musb->mregs;
577 musb->vbuserr_retry--;
579 devctl |= MUSB_DEVCTL_SESSION;
580 musb_writeb(mbase, MUSB_DEVCTL, devctl);
582 musb->port1_status |=
583 USB_PORT_STAT_OVERCURRENT
584 | (USB_PORT_STAT_C_OVERCURRENT << 16);
591 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
592 otg_state_string(musb->xceiv->state),
595 switch (devctl & MUSB_DEVCTL_VBUS) {
596 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
597 s = "<SessEnd"; break;
598 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
599 s = "<AValid"; break;
600 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
601 s = "<VBusValid"; break;
602 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
606 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
609 /* go through A_WAIT_VFALL then start a new session */
611 musb_platform_set_vbus(musb, 0);
612 handled = IRQ_HANDLED;
615 if (int_usb & MUSB_INTR_SUSPEND) {
616 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
617 otg_state_string(musb->xceiv->state), devctl, power);
618 handled = IRQ_HANDLED;
620 switch (musb->xceiv->state) {
621 case OTG_STATE_A_PERIPHERAL:
622 /* We also come here if the cable is removed, since
623 * this silicon doesn't report ID-no-longer-grounded.
625 * We depend on T(a_wait_bcon) to shut us down, and
626 * hope users don't do anything dicey during this
627 * undesired detour through A_WAIT_BCON.
630 usb_hcd_resume_root_hub(musb_to_hcd(musb));
631 musb_root_disconnect(musb);
632 musb_platform_try_idle(musb, jiffies
633 + msecs_to_jiffies(musb->a_wait_bcon
634 ? : OTG_TIME_A_WAIT_BCON));
637 case OTG_STATE_B_IDLE:
638 if (!musb->is_active)
640 case OTG_STATE_B_PERIPHERAL:
641 musb_g_suspend(musb);
642 musb->is_active = is_otg_enabled(musb)
643 && otg->gadget->b_hnp_enable;
644 if (musb->is_active) {
645 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
646 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
647 mod_timer(&musb->otg_timer, jiffies
649 OTG_TIME_B_ASE0_BRST));
652 case OTG_STATE_A_WAIT_BCON:
653 if (musb->a_wait_bcon != 0)
654 musb_platform_try_idle(musb, jiffies
655 + msecs_to_jiffies(musb->a_wait_bcon));
657 case OTG_STATE_A_HOST:
658 musb->xceiv->state = OTG_STATE_A_SUSPEND;
659 musb->is_active = is_otg_enabled(musb)
660 && otg->host->b_hnp_enable;
662 case OTG_STATE_B_HOST:
663 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
664 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
667 /* "should not happen" */
674 if (int_usb & MUSB_INTR_CONNECT) {
675 struct usb_hcd *hcd = musb_to_hcd(musb);
677 handled = IRQ_HANDLED;
680 musb->ep0_stage = MUSB_EP0_START;
682 /* flush endpoints when transitioning from Device Mode */
683 if (is_peripheral_active(musb)) {
684 /* REVISIT HNP; just force disconnect */
686 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
687 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
688 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
690 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
691 |USB_PORT_STAT_HIGH_SPEED
692 |USB_PORT_STAT_ENABLE
694 musb->port1_status |= USB_PORT_STAT_CONNECTION
695 |(USB_PORT_STAT_C_CONNECTION << 16);
697 /* high vs full speed is just a guess until after reset */
698 if (devctl & MUSB_DEVCTL_LSDEV)
699 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
701 /* indicate new connection to OTG machine */
702 switch (musb->xceiv->state) {
703 case OTG_STATE_B_PERIPHERAL:
704 if (int_usb & MUSB_INTR_SUSPEND) {
705 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
706 int_usb &= ~MUSB_INTR_SUSPEND;
709 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
711 case OTG_STATE_B_WAIT_ACON:
712 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
714 musb->xceiv->state = OTG_STATE_B_HOST;
715 hcd->self.is_b_host = 1;
716 musb->ignore_disconnect = 0;
717 del_timer(&musb->otg_timer);
720 if ((devctl & MUSB_DEVCTL_VBUS)
721 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
722 musb->xceiv->state = OTG_STATE_A_HOST;
723 hcd->self.is_b_host = 0;
728 /* poke the root hub */
731 usb_hcd_poll_rh_status(hcd);
733 usb_hcd_resume_root_hub(hcd);
735 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
736 otg_state_string(musb->xceiv->state), devctl);
741 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
742 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
743 otg_state_string(musb->xceiv->state),
744 MUSB_MODE(musb), devctl);
745 handled = IRQ_HANDLED;
747 switch (musb->xceiv->state) {
748 case OTG_STATE_A_HOST:
749 case OTG_STATE_A_SUSPEND:
750 usb_hcd_resume_root_hub(musb_to_hcd(musb));
751 musb_root_disconnect(musb);
752 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
753 musb_platform_try_idle(musb, jiffies
754 + msecs_to_jiffies(musb->a_wait_bcon));
756 case OTG_STATE_B_HOST:
757 /* REVISIT this behaves for "real disconnect"
758 * cases; make sure the other transitions from
759 * from B_HOST act right too. The B_HOST code
760 * in hnp_stop() is currently not used...
762 musb_root_disconnect(musb);
763 musb_to_hcd(musb)->self.is_b_host = 0;
764 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
766 musb_g_disconnect(musb);
768 case OTG_STATE_A_PERIPHERAL:
770 musb_root_disconnect(musb);
772 case OTG_STATE_B_WAIT_ACON:
774 case OTG_STATE_B_PERIPHERAL:
775 case OTG_STATE_B_IDLE:
776 musb_g_disconnect(musb);
779 WARNING("unhandled DISCONNECT transition (%s)\n",
780 otg_state_string(musb->xceiv->state));
785 /* mentor saves a bit: bus reset and babble share the same irq.
786 * only host sees babble; only peripheral sees bus reset.
788 if (int_usb & MUSB_INTR_RESET) {
789 handled = IRQ_HANDLED;
790 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
792 * Looks like non-HS BABBLE can be ignored, but
793 * HS BABBLE is an error condition. For HS the solution
794 * is to avoid babble in the first place and fix what
795 * caused BABBLE. When HS BABBLE happens we can only
798 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
799 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
801 ERR("Stopping host session -- babble\n");
802 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
804 } else if (is_peripheral_capable()) {
805 dev_dbg(musb->controller, "BUS RESET as %s\n",
806 otg_state_string(musb->xceiv->state));
807 switch (musb->xceiv->state) {
808 case OTG_STATE_A_SUSPEND:
809 /* We need to ignore disconnect on suspend
810 * otherwise tusb 2.0 won't reconnect after a
811 * power cycle, which breaks otg compliance.
813 musb->ignore_disconnect = 1;
816 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
817 /* never use invalid T(a_wait_bcon) */
818 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
819 otg_state_string(musb->xceiv->state),
821 mod_timer(&musb->otg_timer, jiffies
822 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
824 case OTG_STATE_A_PERIPHERAL:
825 musb->ignore_disconnect = 0;
826 del_timer(&musb->otg_timer);
829 case OTG_STATE_B_WAIT_ACON:
830 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
831 otg_state_string(musb->xceiv->state));
832 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
835 case OTG_STATE_B_IDLE:
836 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
838 case OTG_STATE_B_PERIPHERAL:
842 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
843 otg_state_string(musb->xceiv->state));
850 /* REVISIT ... this would be for multiplexing periodic endpoints, or
851 * supporting transfer phasing to prevent exceeding ISO bandwidth
852 * limits of a given frame or microframe.
854 * It's not needed for peripheral side, which dedicates endpoints;
855 * though it _might_ use SOF irqs for other purposes.
857 * And it's not currently needed for host side, which also dedicates
858 * endpoints, relies on TX/RX interval registers, and isn't claimed
859 * to support ISO transfers yet.
861 if (int_usb & MUSB_INTR_SOF) {
862 void __iomem *mbase = musb->mregs;
863 struct musb_hw_ep *ep;
867 dev_dbg(musb->controller, "START_OF_FRAME\n");
868 handled = IRQ_HANDLED;
870 /* start any periodic Tx transfers waiting for current frame */
871 frame = musb_readw(mbase, MUSB_FRAME);
872 ep = musb->endpoints;
873 for (epnum = 1; (epnum < musb->nr_endpoints)
874 && (musb->epmask >= (1 << epnum));
877 * FIXME handle framecounter wraps (12 bits)
878 * eliminate duplicated StartUrb logic
880 if (ep->dwWaitFrame >= frame) {
882 pr_debug("SOF --> periodic TX%s on %d\n",
883 ep->tx_channel ? " DMA" : "",
886 musb_h_tx_start(musb, epnum);
888 cppi_hostdma_start(musb, epnum);
890 } /* end of for loop */
894 schedule_work(&musb->irq_work);
899 /*-------------------------------------------------------------------------*/
902 * Program the HDRC to start (enable interrupts, dma, etc.).
905 void musb_start(struct musb *musb)
907 int musb_start(struct musb *musb)
910 void __iomem *regs = musb->mregs;
911 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
916 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
918 /* Set INT enable registers, enable interrupts */
919 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
920 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
921 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
923 musb_writeb(regs, MUSB_TESTMODE, 0);
925 /* put into basic highspeed mode and start session */
926 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
928 /* ENSUSPEND wedges tusb */
929 /* | MUSB_POWER_ENSUSPEND */
933 devctl = musb_readb(regs, MUSB_DEVCTL);
934 devctl &= ~MUSB_DEVCTL_SESSION;
936 if (is_otg_enabled(musb)) {
938 /* session started after:
939 * (a) ID-grounded irq, host mode;
940 * (b) vbus present/connect IRQ, peripheral mode;
941 * (c) peripheral initiates, using SRP
943 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
946 devctl |= MUSB_DEVCTL_SESSION;
949 } else if (is_host_enabled(musb)) {
950 /* assume ID pin is hard-wired to ground */
951 devctl |= MUSB_DEVCTL_SESSION;
953 } else /* peripheral is enabled */ {
954 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
959 musb_platform_enable(musb);
961 ret = musb_platform_enable(musb);
967 musb_writeb(regs, MUSB_DEVCTL, devctl);
975 static void musb_generic_disable(struct musb *musb)
977 void __iomem *mbase = musb->mregs;
980 /* disable interrupts */
981 musb_writeb(mbase, MUSB_INTRUSBE, 0);
982 musb_writew(mbase, MUSB_INTRTXE, 0);
983 musb_writew(mbase, MUSB_INTRRXE, 0);
986 musb_writeb(mbase, MUSB_DEVCTL, 0);
988 /* flush pending interrupts */
989 temp = musb_readb(mbase, MUSB_INTRUSB);
990 temp = musb_readw(mbase, MUSB_INTRTX);
991 temp = musb_readw(mbase, MUSB_INTRRX);
996 * Make the HDRC stop (disable interrupts, etc.);
997 * reversible by musb_start
998 * called on gadget driver unregister
999 * with controller locked, irqs blocked
1000 * acts as a NOP unless some role activated the hardware
1002 void musb_stop(struct musb *musb)
1004 /* stop IRQs, timers, ... */
1005 musb_platform_disable(musb);
1006 musb_generic_disable(musb);
1007 dev_dbg(musb->controller, "HDRC disabled\n");
1010 * - mark host and/or peripheral drivers unusable/inactive
1011 * - disable DMA (and enable it in HdrcStart)
1012 * - make sure we can musb_start() after musb_stop(); with
1013 * OTG mode, gadget driver module rmmod/modprobe cycles that
1016 musb_platform_try_idle(musb, 0);
1017 musb_platform_exit(musb);
1021 static void musb_shutdown(struct platform_device *pdev)
1023 struct musb *musb = dev_to_musb(&pdev->dev);
1024 unsigned long flags;
1026 pm_runtime_get_sync(musb->controller);
1028 musb_gadget_cleanup(musb);
1030 spin_lock_irqsave(&musb->lock, flags);
1031 musb_platform_disable(musb);
1032 musb_generic_disable(musb);
1033 spin_unlock_irqrestore(&musb->lock, flags);
1035 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1036 usb_remove_hcd(musb_to_hcd(musb));
1037 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1038 musb_platform_exit(musb);
1040 pm_runtime_put(musb->controller);
1041 /* FIXME power down */
1046 /*-------------------------------------------------------------------------*/
1049 * The silicon either has hard-wired endpoint configurations, or else
1050 * "dynamic fifo" sizing. The driver has support for both, though at this
1051 * writing only the dynamic sizing is very well tested. Since we switched
1052 * away from compile-time hardware parameters, we can no longer rely on
1053 * dead code elimination to leave only the relevant one in the object file.
1055 * We don't currently use dynamic fifo setup capability to do anything
1056 * more than selecting one of a bunch of predefined configurations.
1058 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1059 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1060 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1061 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1062 || defined(CONFIG_USB_MUSB_AM35X) \
1063 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1064 || defined(CONFIG_USB_MUSB_DSPS) \
1065 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1066 static ushort __devinitdata fifo_mode = 4;
1067 #elif defined(CONFIG_USB_MUSB_UX500) \
1068 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1069 static ushort __devinitdata fifo_mode = 5;
1071 static ushort __devinitdata fifo_mode = 2;
1074 /* "modprobe ... fifo_mode=1" etc */
1075 module_param(fifo_mode, ushort, 0);
1076 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1079 * tables defining fifo_mode values. define more if you like.
1080 * for host side, make sure both halves of ep1 are set up.
1083 /* mode 0 - fits in 2KB */
1084 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1085 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1086 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1087 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1088 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1089 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1092 /* mode 1 - fits in 4KB */
1093 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1094 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1097 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1098 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1101 /* mode 2 - fits in 4KB */
1102 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1103 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1108 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1111 /* mode 3 - fits in 4KB */
1112 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1113 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1114 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1115 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1118 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1121 /* mode 4 - fits in 16KB */
1122 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1123 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1142 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1143 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1144 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1145 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1146 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1147 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1148 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1149 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1152 /* mode 5 - fits in 8KB */
1153 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1154 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1155 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1156 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1163 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1164 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1165 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1166 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1167 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1168 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1169 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1170 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1171 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1172 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1173 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1174 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1175 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1176 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1177 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1178 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1179 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1180 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1184 * configure a fifo; for non-shared endpoints, this may be called
1185 * once for a tx fifo and once for an rx fifo.
1187 * returns negative errno or offset for next fifo.
1189 static int __devinit
1190 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1191 const struct musb_fifo_cfg *cfg, u16 offset)
1193 void __iomem *mbase = musb->mregs;
1195 u16 maxpacket = cfg->maxpacket;
1196 u16 c_off = offset >> 3;
1199 /* expect hw_ep has already been zero-initialized */
1201 size = ffs(max(maxpacket, (u16) 8)) - 1;
1202 maxpacket = 1 << size;
1205 if (cfg->mode == BUF_DOUBLE) {
1206 if ((offset + (maxpacket << 1)) >
1207 (1 << (musb->config->ram_bits + 2)))
1209 c_size |= MUSB_FIFOSZ_DPB;
1211 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1215 /* configure the FIFO */
1216 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1218 /* EP0 reserved endpoint for control, bidirectional;
1219 * EP1 reserved for bulk, two unidirection halves.
1221 if (hw_ep->epnum == 1)
1222 musb->bulk_ep = hw_ep;
1223 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1224 switch (cfg->style) {
1226 musb_write_txfifosz(mbase, c_size);
1227 musb_write_txfifoadd(mbase, c_off);
1228 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1229 hw_ep->max_packet_sz_tx = maxpacket;
1232 musb_write_rxfifosz(mbase, c_size);
1233 musb_write_rxfifoadd(mbase, c_off);
1234 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1235 hw_ep->max_packet_sz_rx = maxpacket;
1238 musb_write_txfifosz(mbase, c_size);
1239 musb_write_txfifoadd(mbase, c_off);
1240 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1241 hw_ep->max_packet_sz_rx = maxpacket;
1243 musb_write_rxfifosz(mbase, c_size);
1244 musb_write_rxfifoadd(mbase, c_off);
1245 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1246 hw_ep->max_packet_sz_tx = maxpacket;
1248 hw_ep->is_shared_fifo = true;
1252 /* NOTE rx and tx endpoint irqs aren't managed separately,
1253 * which happens to be ok
1255 musb->epmask |= (1 << hw_ep->epnum);
1257 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1260 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1261 .style = FIFO_RXTX, .maxpacket = 64,
1264 static int __devinit ep_config_from_table(struct musb *musb)
1266 const struct musb_fifo_cfg *cfg;
1269 struct musb_hw_ep *hw_ep = musb->endpoints;
1271 if (musb->config->fifo_cfg) {
1272 cfg = musb->config->fifo_cfg;
1273 n = musb->config->fifo_cfg_size;
1277 switch (fifo_mode) {
1283 n = ARRAY_SIZE(mode_0_cfg);
1287 n = ARRAY_SIZE(mode_1_cfg);
1291 n = ARRAY_SIZE(mode_2_cfg);
1295 n = ARRAY_SIZE(mode_3_cfg);
1299 n = ARRAY_SIZE(mode_4_cfg);
1303 n = ARRAY_SIZE(mode_5_cfg);
1307 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1310 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1311 /* assert(offset > 0) */
1313 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1314 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1317 for (i = 0; i < n; i++) {
1318 u8 epn = cfg->hw_ep_num;
1320 if (epn >= musb->config->num_eps) {
1321 pr_debug("%s: invalid ep %d\n",
1322 musb_driver_name, epn);
1325 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1327 pr_debug("%s: mem overrun, ep %d\n",
1328 musb_driver_name, epn);
1332 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1335 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
1336 musb->config->num_eps * 2 - 1, offset,
1337 (1 << (musb->config->ram_bits + 2)));
1339 if (!musb->bulk_ep) {
1340 pr_debug("%s: missing bulk\n", musb_driver_name);
1349 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1350 * @param musb the controller
1352 static int __devinit ep_config_from_hw(struct musb *musb)
1355 struct musb_hw_ep *hw_ep;
1356 void *mbase = musb->mregs;
1359 dev_dbg(musb->controller, "<== static silicon ep config\n");
1361 /* FIXME pick up ep0 maxpacket size */
1363 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1364 musb_ep_select(mbase, epnum);
1365 hw_ep = musb->endpoints + epnum;
1367 ret = musb_read_fifosize(musb, hw_ep, epnum);
1371 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1373 /* pick an RX/TX endpoint for bulk */
1374 if (hw_ep->max_packet_sz_tx < 512
1375 || hw_ep->max_packet_sz_rx < 512)
1378 /* REVISIT: this algorithm is lazy, we should at least
1379 * try to pick a double buffered endpoint.
1383 musb->bulk_ep = hw_ep;
1386 if (!musb->bulk_ep) {
1387 pr_debug("%s: missing bulk\n", musb_driver_name);
1394 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1396 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1397 * configure endpoints, or take their config from silicon
1399 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1403 char aInfo[90], aRevision[32], aDate[12];
1404 void __iomem *mbase = musb->mregs;
1408 /* log core options (read using indexed model) */
1409 reg = musb_read_configdata(mbase);
1411 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1412 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1413 strcat(aInfo, ", dyn FIFOs");
1414 musb->dyn_fifo = true;
1416 #ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
1417 if (reg & MUSB_CONFIGDATA_MPRXE) {
1418 strcat(aInfo, ", bulk combine");
1419 musb->bulk_combine = true;
1421 if (reg & MUSB_CONFIGDATA_MPTXE) {
1422 strcat(aInfo, ", bulk split");
1423 musb->bulk_split = true;
1426 musb->bulk_combine = false;
1427 musb->bulk_split = false;
1429 if (reg & MUSB_CONFIGDATA_HBRXE) {
1430 strcat(aInfo, ", HB-ISO Rx");
1431 musb->hb_iso_rx = true;
1433 if (reg & MUSB_CONFIGDATA_HBTXE) {
1434 strcat(aInfo, ", HB-ISO Tx");
1435 musb->hb_iso_tx = true;
1437 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1438 strcat(aInfo, ", SoftConn");
1440 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1443 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1444 musb->is_multipoint = 1;
1447 musb->is_multipoint = 0;
1449 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1451 "%s: kernel must blacklist external hubs\n",
1456 /* log release info */
1457 musb->hwvers = musb_read_hwvers(mbase);
1458 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1459 MUSB_HWVERS_MINOR(musb->hwvers),
1460 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1461 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
1465 musb_configure_ep0(musb);
1467 /* discover endpoint configuration */
1468 musb->nr_endpoints = 1;
1472 status = ep_config_from_table(musb);
1474 status = ep_config_from_hw(musb);
1479 /* finish init, and print endpoint config */
1480 for (i = 0; i < musb->nr_endpoints; i++) {
1481 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1483 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1484 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1485 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1486 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1487 hw_ep->fifo_sync_va =
1488 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1491 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1493 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1496 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1497 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1498 hw_ep->rx_reinit = 1;
1499 hw_ep->tx_reinit = 1;
1501 if (hw_ep->max_packet_sz_tx) {
1502 dev_dbg(musb->controller,
1503 "%s: hw_ep %d%s, %smax %d\n",
1504 musb_driver_name, i,
1505 hw_ep->is_shared_fifo ? "shared" : "tx",
1506 hw_ep->tx_double_buffered
1507 ? "doublebuffer, " : "",
1508 hw_ep->max_packet_sz_tx);
1510 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1511 dev_dbg(musb->controller,
1512 "%s: hw_ep %d%s, %smax %d\n",
1513 musb_driver_name, i,
1515 hw_ep->rx_double_buffered
1516 ? "doublebuffer, " : "",
1517 hw_ep->max_packet_sz_rx);
1519 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1520 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1526 /*-------------------------------------------------------------------------*/
1528 #if defined(CONFIG_SOC_OMAP2430) || defined(CFG_SOC_OMAP3430) || \
1529 defined(CFG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1531 static irqreturn_t generic_interrupt(int irq, void *__hci)
1533 unsigned long flags;
1534 irqreturn_t retval = IRQ_NONE;
1535 struct musb *musb = __hci;
1537 spin_lock_irqsave(&musb->lock, flags);
1539 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1540 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1541 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1543 if (musb->int_usb || musb->int_tx || musb->int_rx)
1544 retval = musb_interrupt(musb);
1546 spin_unlock_irqrestore(&musb->lock, flags);
1552 #define generic_interrupt NULL
1556 * handle all the irqs defined by the HDRC core. for now we expect: other
1557 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1558 * will be assigned, and the irq will already have been acked.
1560 * called in irq context with spinlock held, irqs blocked
1562 irqreturn_t musb_interrupt(struct musb *musb)
1564 irqreturn_t retval = IRQ_NONE;
1569 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1570 power = musb_readb(musb->mregs, MUSB_POWER);
1572 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1573 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1574 musb->int_usb, musb->int_tx, musb->int_rx);
1576 /* the core can interrupt us for multiple reasons; docs have
1577 * a generic interrupt flowchart to follow
1580 retval |= musb_stage0_irq(musb, musb->int_usb,
1583 /* "stage 1" is handling endpoint irqs */
1585 /* handle endpoint 0 first */
1586 if (musb->int_tx & 1) {
1587 if (devctl & MUSB_DEVCTL_HM) {
1588 if (is_host_capable())
1589 retval |= musb_h_ep0_irq(musb);
1591 if (is_peripheral_capable())
1592 retval |= musb_g_ep0_irq(musb);
1596 /* RX on endpoints 1-15 */
1597 reg = musb->int_rx >> 1;
1601 /* musb_ep_select(musb->mregs, ep_num); */
1602 /* REVISIT just retval = ep->rx_irq(...) */
1603 retval = IRQ_HANDLED;
1604 if (devctl & MUSB_DEVCTL_HM) {
1605 if (is_host_capable())
1606 musb_host_rx(musb, ep_num);
1608 if (is_peripheral_capable())
1609 musb_g_rx(musb, ep_num);
1617 /* TX on endpoints 1-15 */
1618 reg = musb->int_tx >> 1;
1622 /* musb_ep_select(musb->mregs, ep_num); */
1623 /* REVISIT just retval |= ep->tx_irq(...) */
1624 retval = IRQ_HANDLED;
1625 if (devctl & MUSB_DEVCTL_HM) {
1626 if (is_host_capable())
1627 musb_host_tx(musb, ep_num);
1629 if (is_peripheral_capable())
1630 musb_g_tx(musb, ep_num);
1639 EXPORT_SYMBOL_GPL(musb_interrupt);
1641 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1642 static bool __devinitdata use_dma = 1;
1644 /* "modprobe ... use_dma=0" etc */
1645 module_param(use_dma, bool, 0);
1646 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1648 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1650 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1652 /* called with controller lock already held */
1655 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1656 if (!is_cppi_enabled()) {
1658 if (devctl & MUSB_DEVCTL_HM)
1659 musb_h_ep0_irq(musb);
1661 musb_g_ep0_irq(musb);
1665 /* endpoints 1..15 */
1667 if (devctl & MUSB_DEVCTL_HM) {
1668 if (is_host_capable())
1669 musb_host_tx(musb, epnum);
1671 if (is_peripheral_capable())
1672 musb_g_tx(musb, epnum);
1676 if (devctl & MUSB_DEVCTL_HM) {
1677 if (is_host_capable())
1678 musb_host_rx(musb, epnum);
1680 if (is_peripheral_capable())
1681 musb_g_rx(musb, epnum);
1686 EXPORT_SYMBOL_GPL(musb_dma_completion);
1692 /*-------------------------------------------------------------------------*/
1697 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1699 struct musb *musb = dev_to_musb(dev);
1700 unsigned long flags;
1703 spin_lock_irqsave(&musb->lock, flags);
1704 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1705 spin_unlock_irqrestore(&musb->lock, flags);
1711 musb_mode_store(struct device *dev, struct device_attribute *attr,
1712 const char *buf, size_t n)
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned long flags;
1718 spin_lock_irqsave(&musb->lock, flags);
1719 if (sysfs_streq(buf, "host"))
1720 status = musb_platform_set_mode(musb, MUSB_HOST);
1721 else if (sysfs_streq(buf, "peripheral"))
1722 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1723 else if (sysfs_streq(buf, "otg"))
1724 status = musb_platform_set_mode(musb, MUSB_OTG);
1727 spin_unlock_irqrestore(&musb->lock, flags);
1729 return (status == 0) ? n : status;
1731 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1734 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1735 const char *buf, size_t n)
1737 struct musb *musb = dev_to_musb(dev);
1738 unsigned long flags;
1741 if (sscanf(buf, "%lu", &val) < 1) {
1742 dev_err(dev, "Invalid VBUS timeout ms value\n");
1746 spin_lock_irqsave(&musb->lock, flags);
1747 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1748 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1749 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1750 musb->is_active = 0;
1751 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1752 spin_unlock_irqrestore(&musb->lock, flags);
1758 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1760 struct musb *musb = dev_to_musb(dev);
1761 unsigned long flags;
1765 spin_lock_irqsave(&musb->lock, flags);
1766 val = musb->a_wait_bcon;
1767 /* FIXME get_vbus_status() is normally #defined as false...
1768 * and is effectively TUSB-specific.
1770 vbus = musb_platform_get_vbus_status(musb);
1771 spin_unlock_irqrestore(&musb->lock, flags);
1773 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1774 vbus ? "on" : "off", val);
1776 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1778 /* Gadget drivers can't know that a host is connected so they might want
1779 * to start SRP, but users can. This allows userspace to trigger SRP.
1782 musb_srp_store(struct device *dev, struct device_attribute *attr,
1783 const char *buf, size_t n)
1785 struct musb *musb = dev_to_musb(dev);
1788 if (sscanf(buf, "%hu", &srp) != 1
1790 dev_err(dev, "SRP: Value must be 1\n");
1795 musb_g_wakeup(musb);
1799 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1801 static struct attribute *musb_attributes[] = {
1802 &dev_attr_mode.attr,
1803 &dev_attr_vbus.attr,
1808 static const struct attribute_group musb_attr_group = {
1809 .attrs = musb_attributes,
1815 /* Only used to provide driver mode change events */
1816 static void musb_irq_work(struct work_struct *data)
1818 struct musb *musb = container_of(data, struct musb, irq_work);
1819 static int old_state;
1821 if (musb->xceiv->state != old_state) {
1822 old_state = musb->xceiv->state;
1823 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1828 /* --------------------------------------------------------------------------
1832 static struct musb *__devinit
1833 allocate_instance(struct device *dev,
1834 struct musb_hdrc_config *config, void __iomem *mbase)
1837 struct musb_hw_ep *ep;
1840 struct usb_hcd *hcd;
1842 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1845 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1847 musb = hcd_to_musb(hcd);
1849 musb = calloc(1, sizeof(*musb));
1853 INIT_LIST_HEAD(&musb->control);
1854 INIT_LIST_HEAD(&musb->in_bulk);
1855 INIT_LIST_HEAD(&musb->out_bulk);
1858 hcd->uses_new_polling = 1;
1862 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1863 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1864 dev_set_drvdata(dev, musb);
1865 musb->mregs = mbase;
1866 musb->ctrl_base = mbase;
1867 musb->nIrq = -ENODEV;
1868 musb->config = config;
1870 assert_noisy(musb->config->num_eps <= MUSB_C_NUM_EPS);
1872 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1874 for (epnum = 0, ep = musb->endpoints;
1875 epnum < musb->config->num_eps;
1881 musb->controller = dev;
1886 static void musb_free(struct musb *musb)
1888 /* this has multiple entry modes. it handles fault cleanup after
1889 * probe(), where things may be partially set up, as well as rmmod
1890 * cleanup after everything's been de-activated.
1894 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1897 if (musb->nIrq >= 0) {
1899 disable_irq_wake(musb->nIrq);
1900 free_irq(musb->nIrq, musb);
1902 if (is_dma_capable() && musb->dma_controller) {
1903 struct dma_controller *c = musb->dma_controller;
1906 dma_controller_destroy(c);
1913 * Perform generic per-controller initialization.
1915 * @pDevice: the controller (already clocked, etc)
1917 * @mregs: virtual address of controller registers,
1918 * not yet corrected for platform-specific offsets
1921 static int __devinit
1922 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1925 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
1932 struct musb_hdrc_platform_data *plat = dev->platform_data;
1937 /* The driver might handle more features than the board; OK.
1938 * Fail when the board needs a feature that's not enabled.
1941 dev_dbg(dev, "no platform_data?\n");
1947 musb = allocate_instance(dev, plat->config, ctrl);
1953 pm_runtime_use_autosuspend(musb->controller);
1954 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1955 pm_runtime_enable(musb->controller);
1957 spin_lock_init(&musb->lock);
1958 musb->board_mode = plat->mode;
1959 musb->board_set_power = plat->set_power;
1960 musb->min_power = plat->min_power;
1961 musb->ops = plat->platform_ops;
1963 /* The musb_platform_init() call:
1964 * - adjusts musb->mregs and musb->isr if needed,
1965 * - may initialize an integrated tranceiver
1966 * - initializes musb->xceiv, usually by otg_get_phy()
1967 * - stops powering VBUS
1969 * There are various transceiver configurations. Blackfin,
1970 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1971 * external/discrete ones in various flavors (twl4030 family,
1972 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1974 musb->isr = generic_interrupt;
1975 status = musb_platform_init(musb);
1985 if (!musb->xceiv->io_ops) {
1986 musb->xceiv->io_dev = musb->controller;
1987 musb->xceiv->io_priv = musb->mregs;
1988 musb->xceiv->io_ops = &musb_ulpi_access;
1992 pm_runtime_get_sync(musb->controller);
1994 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1995 if (use_dma && dev->dma_mask) {
1996 struct dma_controller *c;
1998 c = dma_controller_create(musb, musb->mregs);
1999 musb->dma_controller = c;
2005 /* ideally this would be abstracted in platform setup */
2006 if (!is_dma_capable() || !musb->dma_controller)
2007 dev->dma_mask = NULL;
2010 /* be sure interrupts are disabled before connecting ISR */
2011 musb_platform_disable(musb);
2012 musb_generic_disable(musb);
2014 /* setup musb parts of the core (especially endpoints) */
2015 status = musb_core_init(plat->config->multipoint
2016 ? MUSB_CONTROLLER_MHDRC
2017 : MUSB_CONTROLLER_HDRC, musb);
2021 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2023 /* Init IRQ workqueue before request_irq */
2024 INIT_WORK(&musb->irq_work, musb_irq_work);
2026 /* attach to the IRQ */
2027 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2028 dev_err(dev, "request_irq %d failed!\n", nIrq);
2033 /* FIXME this handles wakeup irqs wrong */
2034 if (enable_irq_wake(nIrq) == 0) {
2036 device_init_wakeup(dev, 1);
2042 /* host side needs more setup */
2043 if (is_host_enabled(musb)) {
2044 struct usb_hcd *hcd = musb_to_hcd(musb);
2046 otg_set_host(musb->xceiv->otg, &hcd->self);
2048 if (is_otg_enabled(musb))
2049 hcd->self.otg_port = 1;
2050 musb->xceiv->otg->host = &hcd->self;
2051 hcd->power_budget = 2 * (plat->power ? : 250);
2053 /* program PHY to use external vBus if required */
2054 if (plat->extvbus) {
2055 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2056 busctl |= MUSB_ULPI_USE_EXTVBUS;
2057 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2062 /* For the host-only role, we can activate right away.
2063 * (We expect the ID pin to be forcibly grounded!!)
2064 * Otherwise, wait till the gadget driver hooks up.
2066 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2067 struct usb_hcd *hcd = musb_to_hcd(musb);
2069 MUSB_HST_MODE(musb);
2071 musb->xceiv->otg->default_a = 1;
2072 musb->xceiv->state = OTG_STATE_A_IDLE;
2074 status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2076 hcd->self.uses_pio_for_control = 1;
2077 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2079 musb_readb(musb->mregs, MUSB_DEVCTL),
2080 (musb_readb(musb->mregs, MUSB_DEVCTL)
2081 & MUSB_DEVCTL_BDEVICE
2085 } else /* peripheral is enabled */ {
2086 MUSB_DEV_MODE(musb);
2088 musb->xceiv->otg->default_a = 0;
2089 musb->xceiv->state = OTG_STATE_B_IDLE;
2092 if (is_peripheral_capable())
2093 status = musb_gadget_setup(musb);
2096 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2097 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2099 musb_readb(musb->mregs, MUSB_DEVCTL));
2106 status = musb_init_debugfs(musb);
2111 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2116 pm_runtime_put(musb->controller);
2118 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
2120 switch (musb->board_mode) {
2121 case MUSB_HOST: s = "Host"; break;
2122 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2123 default: s = "OTG"; break;
2126 (is_dma_capable() && musb->dma_controller)
2133 return status == 0 ? musb : NULL;
2137 musb_exit_debugfs(musb);
2141 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2142 usb_remove_hcd(musb_to_hcd(musb));
2145 musb_gadget_cleanup(musb);
2148 pm_runtime_put_sync(musb->controller);
2152 device_init_wakeup(dev, 0);
2153 musb_platform_exit(musb);
2156 dev_err(musb->controller,
2157 "musb_init_controller failed with status %d\n", status);
2166 return status == 0 ? musb : NULL;
2171 /*-------------------------------------------------------------------------*/
2173 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2174 * bridge to a platform device; this driver then suffices.
2177 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2178 static u64 *orig_dma_mask;
2182 static int __devinit musb_probe(struct platform_device *pdev)
2184 struct device *dev = &pdev->dev;
2185 int irq = platform_get_irq_byname(pdev, "mc");
2187 struct resource *iomem;
2190 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2191 if (!iomem || irq <= 0)
2194 base = ioremap(iomem->start, resource_size(iomem));
2196 dev_err(dev, "ioremap failed\n");
2200 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2201 /* clobbered by use_dma=n */
2202 orig_dma_mask = dev->dma_mask;
2204 status = musb_init_controller(dev, irq, base);
2211 static int __devexit musb_remove(struct platform_device *pdev)
2213 struct musb *musb = dev_to_musb(&pdev->dev);
2214 void __iomem *ctrl_base = musb->ctrl_base;
2216 /* this gets called on rmmod.
2217 * - Host mode: host may still be active
2218 * - Peripheral mode: peripheral is deactivated (or never-activated)
2219 * - OTG mode: both roles are deactivated (or never-activated)
2221 musb_exit_debugfs(musb);
2222 musb_shutdown(pdev);
2226 device_init_wakeup(&pdev->dev, 0);
2227 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2228 pdev->dev.dma_mask = orig_dma_mask;
2235 static void musb_save_context(struct musb *musb)
2238 void __iomem *musb_base = musb->mregs;
2241 if (is_host_enabled(musb)) {
2242 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2243 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2244 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2246 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2247 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2248 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2249 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2250 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2251 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2253 for (i = 0; i < musb->config->num_eps; ++i) {
2254 struct musb_hw_ep *hw_ep;
2256 hw_ep = &musb->endpoints[i];
2264 musb_writeb(musb_base, MUSB_INDEX, i);
2265 musb->context.index_regs[i].txmaxp =
2266 musb_readw(epio, MUSB_TXMAXP);
2267 musb->context.index_regs[i].txcsr =
2268 musb_readw(epio, MUSB_TXCSR);
2269 musb->context.index_regs[i].rxmaxp =
2270 musb_readw(epio, MUSB_RXMAXP);
2271 musb->context.index_regs[i].rxcsr =
2272 musb_readw(epio, MUSB_RXCSR);
2274 if (musb->dyn_fifo) {
2275 musb->context.index_regs[i].txfifoadd =
2276 musb_read_txfifoadd(musb_base);
2277 musb->context.index_regs[i].rxfifoadd =
2278 musb_read_rxfifoadd(musb_base);
2279 musb->context.index_regs[i].txfifosz =
2280 musb_read_txfifosz(musb_base);
2281 musb->context.index_regs[i].rxfifosz =
2282 musb_read_rxfifosz(musb_base);
2284 if (is_host_enabled(musb)) {
2285 musb->context.index_regs[i].txtype =
2286 musb_readb(epio, MUSB_TXTYPE);
2287 musb->context.index_regs[i].txinterval =
2288 musb_readb(epio, MUSB_TXINTERVAL);
2289 musb->context.index_regs[i].rxtype =
2290 musb_readb(epio, MUSB_RXTYPE);
2291 musb->context.index_regs[i].rxinterval =
2292 musb_readb(epio, MUSB_RXINTERVAL);
2294 musb->context.index_regs[i].txfunaddr =
2295 musb_read_txfunaddr(musb_base, i);
2296 musb->context.index_regs[i].txhubaddr =
2297 musb_read_txhubaddr(musb_base, i);
2298 musb->context.index_regs[i].txhubport =
2299 musb_read_txhubport(musb_base, i);
2301 musb->context.index_regs[i].rxfunaddr =
2302 musb_read_rxfunaddr(musb_base, i);
2303 musb->context.index_regs[i].rxhubaddr =
2304 musb_read_rxhubaddr(musb_base, i);
2305 musb->context.index_regs[i].rxhubport =
2306 musb_read_rxhubport(musb_base, i);
2311 static void musb_restore_context(struct musb *musb)
2314 void __iomem *musb_base = musb->mregs;
2315 void __iomem *ep_target_regs;
2318 if (is_host_enabled(musb)) {
2319 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2320 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2321 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2323 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2324 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2325 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2326 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2327 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2329 for (i = 0; i < musb->config->num_eps; ++i) {
2330 struct musb_hw_ep *hw_ep;
2332 hw_ep = &musb->endpoints[i];
2340 musb_writeb(musb_base, MUSB_INDEX, i);
2341 musb_writew(epio, MUSB_TXMAXP,
2342 musb->context.index_regs[i].txmaxp);
2343 musb_writew(epio, MUSB_TXCSR,
2344 musb->context.index_regs[i].txcsr);
2345 musb_writew(epio, MUSB_RXMAXP,
2346 musb->context.index_regs[i].rxmaxp);
2347 musb_writew(epio, MUSB_RXCSR,
2348 musb->context.index_regs[i].rxcsr);
2350 if (musb->dyn_fifo) {
2351 musb_write_txfifosz(musb_base,
2352 musb->context.index_regs[i].txfifosz);
2353 musb_write_rxfifosz(musb_base,
2354 musb->context.index_regs[i].rxfifosz);
2355 musb_write_txfifoadd(musb_base,
2356 musb->context.index_regs[i].txfifoadd);
2357 musb_write_rxfifoadd(musb_base,
2358 musb->context.index_regs[i].rxfifoadd);
2361 if (is_host_enabled(musb)) {
2362 musb_writeb(epio, MUSB_TXTYPE,
2363 musb->context.index_regs[i].txtype);
2364 musb_writeb(epio, MUSB_TXINTERVAL,
2365 musb->context.index_regs[i].txinterval);
2366 musb_writeb(epio, MUSB_RXTYPE,
2367 musb->context.index_regs[i].rxtype);
2368 musb_writeb(epio, MUSB_RXINTERVAL,
2370 musb->context.index_regs[i].rxinterval);
2371 musb_write_txfunaddr(musb_base, i,
2372 musb->context.index_regs[i].txfunaddr);
2373 musb_write_txhubaddr(musb_base, i,
2374 musb->context.index_regs[i].txhubaddr);
2375 musb_write_txhubport(musb_base, i,
2376 musb->context.index_regs[i].txhubport);
2379 musb_read_target_reg_base(i, musb_base);
2381 musb_write_rxfunaddr(ep_target_regs,
2382 musb->context.index_regs[i].rxfunaddr);
2383 musb_write_rxhubaddr(ep_target_regs,
2384 musb->context.index_regs[i].rxhubaddr);
2385 musb_write_rxhubport(ep_target_regs,
2386 musb->context.index_regs[i].rxhubport);
2389 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2392 static int musb_suspend(struct device *dev)
2394 struct musb *musb = dev_to_musb(dev);
2395 unsigned long flags;
2397 spin_lock_irqsave(&musb->lock, flags);
2399 if (is_peripheral_active(musb)) {
2400 /* FIXME force disconnect unless we know USB will wake
2401 * the system up quickly enough to respond ...
2403 } else if (is_host_active(musb)) {
2404 /* we know all the children are suspended; sometimes
2405 * they will even be wakeup-enabled.
2409 spin_unlock_irqrestore(&musb->lock, flags);
2413 static int musb_resume_noirq(struct device *dev)
2415 /* for static cmos like DaVinci, register values were preserved
2416 * unless for some reason the whole soc powered down or the USB
2417 * module got reset through the PSC (vs just being disabled).
2422 static int musb_runtime_suspend(struct device *dev)
2424 struct musb *musb = dev_to_musb(dev);
2426 musb_save_context(musb);
2431 static int musb_runtime_resume(struct device *dev)
2433 struct musb *musb = dev_to_musb(dev);
2434 static int first = 1;
2437 * When pm_runtime_get_sync called for the first time in driver
2438 * init, some of the structure is still not initialized which is
2439 * used in restore function. But clock needs to be
2440 * enabled before any register access, so
2441 * pm_runtime_get_sync has to be called.
2442 * Also context restore without save does not make
2446 musb_restore_context(musb);
2452 static const struct dev_pm_ops musb_dev_pm_ops = {
2453 .suspend = musb_suspend,
2454 .resume_noirq = musb_resume_noirq,
2455 .runtime_suspend = musb_runtime_suspend,
2456 .runtime_resume = musb_runtime_resume,
2459 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2461 #define MUSB_DEV_PM_OPS NULL
2464 static struct platform_driver musb_driver = {
2466 .name = (char *)musb_driver_name,
2467 .bus = &platform_bus_type,
2468 .owner = THIS_MODULE,
2469 .pm = MUSB_DEV_PM_OPS,
2471 .probe = musb_probe,
2472 .remove = __devexit_p(musb_remove),
2473 .shutdown = musb_shutdown,
2476 /*-------------------------------------------------------------------------*/
2478 static int __init musb_init(void)
2483 pr_info("%s: version " MUSB_VERSION ", "
2486 "otg (peripheral+host)",
2488 return platform_driver_register(&musb_driver);
2490 module_init(musb_init);
2492 static void __exit musb_cleanup(void)
2494 platform_driver_unregister(&musb_driver);
2496 module_exit(musb_cleanup);