1 // SPDX-License-Identifier: GPL-2.0+
3 * Mentor USB OTG Core host controller driver.
5 * Copyright (c) 2008 Texas Instruments
7 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
14 /* MSC control transfers */
15 #define USB_MSC_BBB_RESET 0xFF
16 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
18 /* Endpoint configuration information */
19 static const struct musb_epinfo epinfo[3] = {
20 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
21 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
22 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
25 /* --- Virtual Root Hub ---------------------------------------------------- */
26 #ifdef MUSB_NO_MULTIPOINT
28 static u32 port_status;
30 #include <usbroothubdes.h>
35 * This function writes the data toggle value.
37 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
39 u16 toggle = usb_gettoggle(dev, ep, dir_out);
43 csr = readw(&musbr->txcsr);
45 if (csr & MUSB_TXCSR_MODE)
46 csr = MUSB_TXCSR_CLRDATATOG;
49 writew(csr, &musbr->txcsr);
51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
52 writew(csr, &musbr->txcsr);
53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
54 writew(csr, &musbr->txcsr);
58 csr = readw(&musbr->txcsr);
59 if (csr & MUSB_TXCSR_MODE)
60 csr = MUSB_RXCSR_CLRDATATOG;
63 writew(csr, &musbr->rxcsr);
65 csr = readw(&musbr->rxcsr);
66 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
67 writew(csr, &musbr->rxcsr);
68 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
69 writew(csr, &musbr->rxcsr);
75 * This function checks if RxStall has occurred on the endpoint. If a RxStall
76 * has occurred, the RxStall is cleared and 1 is returned. If RxStall has
77 * not occurred, 0 is returned.
79 static u8 check_stall(u8 ep, u8 dir_out)
85 csr = readw(&musbr->txcsr);
86 if (csr & MUSB_CSR0_H_RXSTALL) {
87 csr &= ~MUSB_CSR0_H_RXSTALL;
88 writew(csr, &musbr->txcsr);
91 } else { /* For non-ep0 */
92 if (dir_out) { /* is it tx ep */
93 csr = readw(&musbr->txcsr);
94 if (csr & MUSB_TXCSR_H_RXSTALL) {
95 csr &= ~MUSB_TXCSR_H_RXSTALL;
96 writew(csr, &musbr->txcsr);
99 } else { /* is it rx ep */
100 csr = readw(&musbr->rxcsr);
101 if (csr & MUSB_RXCSR_H_RXSTALL) {
102 csr &= ~MUSB_RXCSR_H_RXSTALL;
103 writew(csr, &musbr->rxcsr);
112 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
113 * error and -2 for stall.
115 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
119 int timeout = CONFIG_USB_MUSB_TIMEOUT;
122 csr = readw(&musbr->txcsr);
123 if (csr & MUSB_CSR0_H_ERROR) {
124 csr &= ~MUSB_CSR0_H_ERROR;
125 writew(csr, &musbr->txcsr);
126 dev->status = USB_ST_CRC_ERR;
132 case MUSB_CSR0_TXPKTRDY:
133 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
134 if (check_stall(MUSB_CONTROL_EP, 0)) {
135 dev->status = USB_ST_STALLED;
142 case MUSB_CSR0_RXPKTRDY:
143 if (check_stall(MUSB_CONTROL_EP, 0)) {
144 dev->status = USB_ST_STALLED;
147 if (csr & MUSB_CSR0_RXPKTRDY)
151 case MUSB_CSR0_H_REQPKT:
152 if (!(csr & MUSB_CSR0_H_REQPKT)) {
153 if (check_stall(MUSB_CONTROL_EP, 0)) {
154 dev->status = USB_ST_STALLED;
162 /* Check the timeout */
166 dev->status = USB_ST_CRC_ERR;
176 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
178 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
181 int timeout = CONFIG_USB_MUSB_TIMEOUT;
184 if (check_stall(ep, 1)) {
185 dev->status = USB_ST_STALLED;
189 csr = readw(&musbr->txcsr);
190 if (csr & MUSB_TXCSR_H_ERROR) {
191 dev->status = USB_ST_CRC_ERR;
195 /* Check the timeout */
199 dev->status = USB_ST_CRC_ERR;
203 } while (csr & MUSB_TXCSR_TXPKTRDY);
208 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
210 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
213 int timeout = CONFIG_USB_MUSB_TIMEOUT;
216 if (check_stall(ep, 0)) {
217 dev->status = USB_ST_STALLED;
221 csr = readw(&musbr->rxcsr);
222 if (csr & MUSB_RXCSR_H_ERROR) {
223 dev->status = USB_ST_CRC_ERR;
227 /* Check the timeout */
231 dev->status = USB_ST_CRC_ERR;
235 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
240 * This function performs the setup phase of the control transfer
242 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
247 /* write the control request to ep0 fifo */
248 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
250 /* enable transfer of setup packet */
251 csr = readw(&musbr->txcsr);
252 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
253 writew(csr, &musbr->txcsr);
255 /* wait until the setup packet is transmitted */
256 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
262 * This function handles the control transfer in data phase
264 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
269 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
270 u8 *rxbuff = (u8 *)buffer;
274 while (rxlen < len) {
275 /* Determine the next read length */
276 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
278 /* Set the ReqPkt bit */
279 csr = readw(&musbr->txcsr);
280 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
281 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
285 /* Actual number of bytes received by usb */
286 rxedlength = readb(&musbr->rxcount);
288 /* Read the data from the RxFIFO */
289 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
291 /* Clear the RxPktRdy Bit */
292 csr = readw(&musbr->txcsr);
293 csr &= ~MUSB_CSR0_RXPKTRDY;
294 writew(csr, &musbr->txcsr);
297 if (rxedlength != nextlen) {
298 dev->act_len += rxedlength;
302 dev->act_len = rxlen;
308 * This function handles the control transfer out data phase
310 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
315 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
316 u8 *txbuff = (u8 *)buffer;
319 while (txlen < len) {
320 /* Determine the next write length */
321 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
323 /* Load the data to send in FIFO */
324 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
326 /* Set TXPKTRDY bit */
327 csr = readw(&musbr->txcsr);
329 csr |= MUSB_CSR0_TXPKTRDY;
330 #if !defined(CONFIG_SOC_DM365)
331 csr |= MUSB_CSR0_H_DIS_PING;
333 writew(csr, &musbr->txcsr);
334 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
339 dev->act_len = txlen;
345 * This function handles the control transfer out status phase
347 static int ctrlreq_out_status_phase(struct usb_device *dev)
352 /* Set the StatusPkt bit */
353 csr = readw(&musbr->txcsr);
354 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
355 #if !defined(CONFIG_SOC_DM365)
356 csr |= MUSB_CSR0_H_DIS_PING;
358 writew(csr, &musbr->txcsr);
360 /* Wait until TXPKTRDY bit is cleared */
361 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
366 * This function handles the control transfer in status phase
368 static int ctrlreq_in_status_phase(struct usb_device *dev)
373 /* Set the StatusPkt bit and ReqPkt bit */
374 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
375 #if !defined(CONFIG_SOC_DM365)
376 csr |= MUSB_CSR0_H_DIS_PING;
378 writew(csr, &musbr->txcsr);
379 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
381 /* clear StatusPkt bit and RxPktRdy bit */
382 csr = readw(&musbr->txcsr);
383 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
384 writew(csr, &musbr->txcsr);
389 * determines the speed of the device (High/Full/Slow)
391 static u8 get_dev_speed(struct usb_device *dev)
393 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
394 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
395 MUSB_TYPE_SPEED_FULL);
399 * configure the hub address and the port address.
401 static void config_hub_port(struct usb_device *dev, u8 ep)
406 /* Find out the nearest parent which is high speed */
407 while (dev->parent->parent != NULL)
408 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
413 /* determine the port address at that hub */
414 hub = dev->parent->devnum;
415 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
416 if (dev->parent->children[chid] == dev)
419 #ifndef MUSB_NO_MULTIPOINT
420 /* configure the hub address and the port address */
421 writeb(hub, &musbr->tar[ep].txhubaddr);
422 writeb((chid + 1), &musbr->tar[ep].txhubport);
423 writeb(hub, &musbr->tar[ep].rxhubaddr);
424 writeb((chid + 1), &musbr->tar[ep].rxhubport);
428 #ifdef MUSB_NO_MULTIPOINT
430 static void musb_port_reset(int do_reset)
432 u8 power = readb(&musbr->power);
436 writeb(power | MUSB_POWER_RESET, &musbr->power);
437 port_status |= USB_PORT_STAT_RESET;
438 port_status &= ~USB_PORT_STAT_ENABLE;
441 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
443 power = readb(&musbr->power);
444 if (power & MUSB_POWER_HSMODE)
445 port_status |= USB_PORT_STAT_HIGH_SPEED;
447 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
448 port_status |= USB_PORT_STAT_ENABLE
449 | (USB_PORT_STAT_C_RESET << 16)
450 | (USB_PORT_STAT_C_ENABLE << 16);
457 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
458 void *buffer, int transfer_len,
459 struct devrequest *cmd)
461 int leni = transfer_len;
465 const u8 *data_buf = (u8 *) datab;
472 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
473 debug("Root-Hub submit IRQ: NOT implemented\n");
477 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
478 wValue = swap_16(cmd->value);
479 wIndex = swap_16(cmd->index);
480 wLength = swap_16(cmd->length);
482 debug("--- HUB ----------------------------------------\n");
483 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
484 bmRType_bReq, wValue, wIndex, wLength);
485 debug("------------------------------------------------\n");
487 switch (bmRType_bReq) {
489 debug("RH_GET_STATUS\n");
491 *(__u16 *) data_buf = swap_16(1);
495 case RH_GET_STATUS | RH_INTERFACE:
496 debug("RH_GET_STATUS | RH_INTERFACE\n");
498 *(__u16 *) data_buf = swap_16(0);
502 case RH_GET_STATUS | RH_ENDPOINT:
503 debug("RH_GET_STATUS | RH_ENDPOINT\n");
505 *(__u16 *) data_buf = swap_16(0);
509 case RH_GET_STATUS | RH_CLASS:
510 debug("RH_GET_STATUS | RH_CLASS\n");
512 *(__u32 *) data_buf = swap_32(0);
516 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
517 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
519 int_usb = readw(&musbr->intrusb);
520 if (int_usb & MUSB_INTR_CONNECT) {
521 port_status |= USB_PORT_STAT_CONNECTION
522 | (USB_PORT_STAT_C_CONNECTION << 16);
523 port_status |= USB_PORT_STAT_HIGH_SPEED
524 | USB_PORT_STAT_ENABLE;
527 if (port_status & USB_PORT_STAT_RESET)
530 *(__u32 *) data_buf = swap_32(port_status);
534 case RH_CLEAR_FEATURE | RH_ENDPOINT:
535 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
538 case RH_ENDPOINT_STALL:
539 debug("C_HUB_ENDPOINT_STALL\n");
543 port_status &= ~(1 << wValue);
546 case RH_CLEAR_FEATURE | RH_CLASS:
547 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
550 case RH_C_HUB_LOCAL_POWER:
551 debug("C_HUB_LOCAL_POWER\n");
555 case RH_C_HUB_OVER_CURRENT:
556 debug("C_HUB_OVER_CURRENT\n");
560 port_status &= ~(1 << wValue);
563 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
564 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
571 case RH_PORT_SUSPEND:
579 case RH_C_PORT_CONNECTION:
583 case RH_C_PORT_ENABLE:
587 case RH_C_PORT_SUSPEND:
591 case RH_C_PORT_OVER_CURRENT:
595 case RH_C_PORT_RESET:
600 debug("invalid wValue\n");
601 stat = USB_ST_STALLED;
604 port_status &= ~(1 << wValue);
607 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
608 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
611 case RH_PORT_SUSPEND:
629 debug("invalid wValue\n");
630 stat = USB_ST_STALLED;
633 port_status |= 1 << wValue;
637 debug("RH_SET_ADDRESS\n");
643 case RH_GET_DESCRIPTOR:
644 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
647 case (USB_DT_DEVICE << 8): /* device descriptor */
648 len = min_t(unsigned int,
649 leni, min_t(unsigned int,
650 sizeof(root_hub_dev_des),
652 data_buf = root_hub_dev_des;
655 case (USB_DT_CONFIG << 8): /* configuration descriptor */
656 len = min_t(unsigned int,
657 leni, min_t(unsigned int,
658 sizeof(root_hub_config_des),
660 data_buf = root_hub_config_des;
663 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
664 len = min_t(unsigned int,
665 leni, min_t(unsigned int,
666 sizeof(root_hub_str_index0),
668 data_buf = root_hub_str_index0;
671 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
672 len = min_t(unsigned int,
673 leni, min_t(unsigned int,
674 sizeof(root_hub_str_index1),
676 data_buf = root_hub_str_index1;
680 debug("invalid wValue\n");
681 stat = USB_ST_STALLED;
686 case RH_GET_DESCRIPTOR | RH_CLASS: {
687 u8 *_data_buf = (u8 *) datab;
688 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
690 _data_buf[0] = 0x09; /* min length; */
692 _data_buf[2] = 0x1; /* 1 port */
693 _data_buf[3] = 0x01; /* per-port power switching */
694 _data_buf[3] |= 0x10; /* no overcurrent reporting */
696 /* Corresponds to data_buf[4-7] */
703 len = min_t(unsigned int, leni,
704 min_t(unsigned int, data_buf[0], wLength));
708 case RH_GET_CONFIGURATION:
709 debug("RH_GET_CONFIGURATION\n");
711 *(__u8 *) data_buf = 0x01;
715 case RH_SET_CONFIGURATION:
716 debug("RH_SET_CONFIGURATION\n");
722 debug("*** *** *** unsupported root hub command *** *** ***\n");
723 stat = USB_ST_STALLED;
726 len = min_t(int, len, leni);
727 if (buffer != data_buf)
728 memcpy(buffer, data_buf, len);
732 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
737 static void musb_rh_init(void)
745 static void musb_rh_init(void) {}
750 * do a control transfer
752 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
753 int len, struct devrequest *setup)
755 int devnum = usb_pipedevice(pipe);
758 #ifdef MUSB_NO_MULTIPOINT
759 /* Control message is for the HUB? */
760 if (devnum == rh_devnum) {
761 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
767 /* select control endpoint */
768 writeb(MUSB_CONTROL_EP, &musbr->index);
769 readw(&musbr->txcsr);
771 #ifndef MUSB_NO_MULTIPOINT
772 /* target addr and (for multipoint) hub addr/port */
773 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
774 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
777 /* configure the hub address and the port number as required */
778 devspeed = get_dev_speed(dev);
779 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
780 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
781 config_hub_port(dev, MUSB_CONTROL_EP);
782 writeb(devspeed << 6, &musbr->txtype);
784 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
785 #ifndef MUSB_NO_MULTIPOINT
786 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
787 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
788 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
789 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
793 /* Control transfer setup phase */
794 if (ctrlreq_setup_phase(dev, setup) < 0)
797 switch (setup->request) {
798 case USB_REQ_GET_DESCRIPTOR:
799 case USB_REQ_GET_CONFIGURATION:
800 case USB_REQ_GET_INTERFACE:
801 case USB_REQ_GET_STATUS:
802 case USB_MSC_BBB_GET_MAX_LUN:
803 /* control transfer in-data-phase */
804 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
806 /* control transfer out-status-phase */
807 if (ctrlreq_out_status_phase(dev) < 0)
811 case USB_REQ_SET_ADDRESS:
812 case USB_REQ_SET_CONFIGURATION:
813 case USB_REQ_SET_FEATURE:
814 case USB_REQ_SET_INTERFACE:
815 case USB_REQ_CLEAR_FEATURE:
816 case USB_MSC_BBB_RESET:
817 /* control transfer in status phase */
818 if (ctrlreq_in_status_phase(dev) < 0)
822 case USB_REQ_SET_DESCRIPTOR:
823 /* control transfer out data phase */
824 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
826 /* control transfer in status phase */
827 if (ctrlreq_in_status_phase(dev) < 0)
832 /* unhandled control transfer */
839 #ifdef MUSB_NO_MULTIPOINT
840 /* Set device address to USB_FADDR register */
841 if (setup->request == USB_REQ_SET_ADDRESS)
842 writeb(dev->devnum, &musbr->faddr);
851 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
852 void *buffer, int len)
854 int dir_out = usb_pipeout(pipe);
855 int ep = usb_pipeendpoint(pipe);
856 #ifndef MUSB_NO_MULTIPOINT
857 int devnum = usb_pipedevice(pipe);
865 /* select bulk endpoint */
866 writeb(MUSB_BULK_EP, &musbr->index);
868 #ifndef MUSB_NO_MULTIPOINT
869 /* write the address of the device */
871 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
873 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
876 /* configure the hub address and the port number as required */
877 devspeed = get_dev_speed(dev);
878 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
879 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
881 * MUSB is in high speed and the destination device is full
882 * speed device. So configure the hub address and port
885 config_hub_port(dev, MUSB_BULK_EP);
887 #ifndef MUSB_NO_MULTIPOINT
889 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
890 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
892 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
893 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
896 devspeed = musb_cfg.musb_speed;
899 /* Write the saved toggle bit value */
900 write_toggle(dev, ep, dir_out);
902 if (dir_out) { /* bulk-out transfer */
903 /* Program the TxType register */
904 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
905 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
906 (ep & MUSB_TYPE_REMOTE_END);
907 writeb(type, &musbr->txtype);
909 /* Write maximum packet size to the TxMaxp register */
910 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
911 while (txlen < len) {
912 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
913 (len-txlen) : dev->epmaxpacketout[ep];
915 /* Write the data to the FIFO */
916 write_fifo(MUSB_BULK_EP, nextlen,
917 (void *)(((u8 *)buffer) + txlen));
919 /* Set the TxPktRdy bit */
920 csr = readw(&musbr->txcsr);
921 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
923 /* Wait until the TxPktRdy bit is cleared */
924 if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
925 readw(&musbr->txcsr);
926 usb_settoggle(dev, ep, dir_out,
927 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
928 dev->act_len = txlen;
934 /* Keep a copy of the data toggle bit */
935 csr = readw(&musbr->txcsr);
936 usb_settoggle(dev, ep, dir_out,
937 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
938 } else { /* bulk-in transfer */
939 /* Write the saved toggle bit value */
940 write_toggle(dev, ep, dir_out);
942 /* Program the RxType register */
943 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
944 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
945 (ep & MUSB_TYPE_REMOTE_END);
946 writeb(type, &musbr->rxtype);
948 /* Write the maximum packet size to the RxMaxp register */
949 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
950 while (txlen < len) {
951 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
952 (len-txlen) : dev->epmaxpacketin[ep];
954 /* Set the ReqPkt bit */
955 csr = readw(&musbr->rxcsr);
956 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
958 /* Wait until the RxPktRdy bit is set */
959 if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
960 csr = readw(&musbr->rxcsr);
961 usb_settoggle(dev, ep, dir_out,
962 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
963 csr &= ~MUSB_RXCSR_RXPKTRDY;
964 writew(csr, &musbr->rxcsr);
965 dev->act_len = txlen;
969 /* Read the data from the FIFO */
970 read_fifo(MUSB_BULK_EP, nextlen,
971 (void *)(((u8 *)buffer) + txlen));
973 /* Clear the RxPktRdy bit */
974 csr = readw(&musbr->rxcsr);
975 csr &= ~MUSB_RXCSR_RXPKTRDY;
976 writew(csr, &musbr->rxcsr);
980 /* Keep a copy of the data toggle bit */
981 csr = readw(&musbr->rxcsr);
982 usb_settoggle(dev, ep, dir_out,
983 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
986 /* bulk transfer is complete */
993 * This function initializes the usb controller module.
995 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1002 if (musb_platform_init() == -1)
1005 /* Configure all the endpoint FIFO's and start usb controller */
1006 musbr = musb_cfg.regs;
1007 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1011 * Wait until musb is enabled in host mode with a timeout. There
1012 * should be a usb device connected.
1014 timeout = musb_cfg.timeout;
1016 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1019 /* if musb core is not in host mode, then return */
1023 /* start usb bus reset */
1024 power = readb(&musbr->power);
1025 writeb(power | MUSB_POWER_RESET, &musbr->power);
1027 /* After initiating a usb reset, wait for about 20ms to 30ms */
1030 /* stop usb bus reset */
1031 power = readb(&musbr->power);
1032 power &= ~MUSB_POWER_RESET;
1033 writeb(power, &musbr->power);
1035 /* Determine if the connected device is a high/full/low speed device */
1036 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1037 MUSB_TYPE_SPEED_HIGH :
1038 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1039 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1044 * This function stops the operation of the davinci usb module.
1046 int usb_lowlevel_stop(int index)
1048 /* Reset the USB module */
1049 musb_platform_deinit();
1050 writeb(0, &musbr->devctl);
1055 * This function supports usb interrupt transfers. Currently, usb interrupt
1056 * transfers are not supported.
1058 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1059 void *buffer, int len, int interval)
1061 int dir_out = usb_pipeout(pipe);
1062 int ep = usb_pipeendpoint(pipe);
1063 #ifndef MUSB_NO_MULTIPOINT
1064 int devnum = usb_pipedevice(pipe);
1072 /* select interrupt endpoint */
1073 writeb(MUSB_INTR_EP, &musbr->index);
1075 #ifndef MUSB_NO_MULTIPOINT
1076 /* write the address of the device */
1078 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1080 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1083 /* configure the hub address and the port number as required */
1084 devspeed = get_dev_speed(dev);
1085 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1086 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1088 * MUSB is in high speed and the destination device is full
1089 * speed device. So configure the hub address and port
1090 * address registers.
1092 config_hub_port(dev, MUSB_INTR_EP);
1094 #ifndef MUSB_NO_MULTIPOINT
1096 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1097 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1099 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1100 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1103 devspeed = musb_cfg.musb_speed;
1106 /* Write the saved toggle bit value */
1107 write_toggle(dev, ep, dir_out);
1109 if (!dir_out) { /* intrrupt-in transfer */
1110 /* Write the saved toggle bit value */
1111 write_toggle(dev, ep, dir_out);
1112 writeb(interval, &musbr->rxinterval);
1114 /* Program the RxType register */
1115 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1116 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1117 (ep & MUSB_TYPE_REMOTE_END);
1118 writeb(type, &musbr->rxtype);
1120 /* Write the maximum packet size to the RxMaxp register */
1121 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1123 while (txlen < len) {
1124 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1125 (len-txlen) : dev->epmaxpacketin[ep];
1127 /* Set the ReqPkt bit */
1128 csr = readw(&musbr->rxcsr);
1129 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1131 /* Wait until the RxPktRdy bit is set */
1132 if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1133 csr = readw(&musbr->rxcsr);
1134 usb_settoggle(dev, ep, dir_out,
1135 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1136 csr &= ~MUSB_RXCSR_RXPKTRDY;
1137 writew(csr, &musbr->rxcsr);
1138 dev->act_len = txlen;
1142 /* Read the data from the FIFO */
1143 read_fifo(MUSB_INTR_EP, nextlen,
1144 (void *)(((u8 *)buffer) + txlen));
1146 /* Clear the RxPktRdy bit */
1147 csr = readw(&musbr->rxcsr);
1148 csr &= ~MUSB_RXCSR_RXPKTRDY;
1149 writew(csr, &musbr->rxcsr);
1153 /* Keep a copy of the data toggle bit */
1154 csr = readw(&musbr->rxcsr);
1155 usb_settoggle(dev, ep, dir_out,
1156 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1159 /* interrupt transfer is complete */
1160 dev->irq_status = 0;
1161 dev->irq_act_len = len;
1162 dev->irq_handle(dev);