1 // SPDX-License-Identifier: GPL-2.0+
3 * Mentor USB OTG Core host controller driver.
5 * Copyright (c) 2008 Texas Instruments
7 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
13 #include <linux/delay.h>
16 /* MSC control transfers */
17 #define USB_MSC_BBB_RESET 0xFF
18 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
20 /* Endpoint configuration information */
21 static const struct musb_epinfo epinfo[3] = {
22 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
23 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
24 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
27 /* --- Virtual Root Hub ---------------------------------------------------- */
28 #ifdef MUSB_NO_MULTIPOINT
30 static u32 port_status;
32 #include <usbroothubdes.h>
37 * This function writes the data toggle value.
39 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
41 u16 toggle = usb_gettoggle(dev, ep, dir_out);
45 csr = readw(&musbr->txcsr);
47 if (csr & MUSB_TXCSR_MODE)
48 csr = MUSB_TXCSR_CLRDATATOG;
51 writew(csr, &musbr->txcsr);
53 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
54 writew(csr, &musbr->txcsr);
55 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
56 writew(csr, &musbr->txcsr);
60 csr = readw(&musbr->txcsr);
61 if (csr & MUSB_TXCSR_MODE)
62 csr = MUSB_RXCSR_CLRDATATOG;
65 writew(csr, &musbr->rxcsr);
67 csr = readw(&musbr->rxcsr);
68 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
69 writew(csr, &musbr->rxcsr);
70 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
71 writew(csr, &musbr->rxcsr);
77 * This function checks if RxStall has occurred on the endpoint. If a RxStall
78 * has occurred, the RxStall is cleared and 1 is returned. If RxStall has
79 * not occurred, 0 is returned.
81 static u8 check_stall(u8 ep, u8 dir_out)
87 csr = readw(&musbr->txcsr);
88 if (csr & MUSB_CSR0_H_RXSTALL) {
89 csr &= ~MUSB_CSR0_H_RXSTALL;
90 writew(csr, &musbr->txcsr);
93 } else { /* For non-ep0 */
94 if (dir_out) { /* is it tx ep */
95 csr = readw(&musbr->txcsr);
96 if (csr & MUSB_TXCSR_H_RXSTALL) {
97 csr &= ~MUSB_TXCSR_H_RXSTALL;
98 writew(csr, &musbr->txcsr);
101 } else { /* is it rx ep */
102 csr = readw(&musbr->rxcsr);
103 if (csr & MUSB_RXCSR_H_RXSTALL) {
104 csr &= ~MUSB_RXCSR_H_RXSTALL;
105 writew(csr, &musbr->rxcsr);
114 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
115 * error and -2 for stall.
117 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
121 int timeout = CONFIG_USB_MUSB_TIMEOUT;
124 csr = readw(&musbr->txcsr);
125 if (csr & MUSB_CSR0_H_ERROR) {
126 csr &= ~MUSB_CSR0_H_ERROR;
127 writew(csr, &musbr->txcsr);
128 dev->status = USB_ST_CRC_ERR;
134 case MUSB_CSR0_TXPKTRDY:
135 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
136 if (check_stall(MUSB_CONTROL_EP, 0)) {
137 dev->status = USB_ST_STALLED;
144 case MUSB_CSR0_RXPKTRDY:
145 if (check_stall(MUSB_CONTROL_EP, 0)) {
146 dev->status = USB_ST_STALLED;
149 if (csr & MUSB_CSR0_RXPKTRDY)
153 case MUSB_CSR0_H_REQPKT:
154 if (!(csr & MUSB_CSR0_H_REQPKT)) {
155 if (check_stall(MUSB_CONTROL_EP, 0)) {
156 dev->status = USB_ST_STALLED;
164 /* Check the timeout */
168 dev->status = USB_ST_CRC_ERR;
178 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
180 static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
183 int timeout = CONFIG_USB_MUSB_TIMEOUT;
186 if (check_stall(ep, 1)) {
187 dev->status = USB_ST_STALLED;
191 csr = readw(&musbr->txcsr);
192 if (csr & MUSB_TXCSR_H_ERROR) {
193 dev->status = USB_ST_CRC_ERR;
197 /* Check the timeout */
201 dev->status = USB_ST_CRC_ERR;
205 } while (csr & MUSB_TXCSR_TXPKTRDY);
210 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
212 static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
215 int timeout = CONFIG_USB_MUSB_TIMEOUT;
218 if (check_stall(ep, 0)) {
219 dev->status = USB_ST_STALLED;
223 csr = readw(&musbr->rxcsr);
224 if (csr & MUSB_RXCSR_H_ERROR) {
225 dev->status = USB_ST_CRC_ERR;
229 /* Check the timeout */
233 dev->status = USB_ST_CRC_ERR;
237 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
242 * This function performs the setup phase of the control transfer
244 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
249 /* write the control request to ep0 fifo */
250 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
252 /* enable transfer of setup packet */
253 csr = readw(&musbr->txcsr);
254 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
255 writew(csr, &musbr->txcsr);
257 /* wait until the setup packet is transmitted */
258 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
264 * This function handles the control transfer in data phase
266 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
271 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
272 u8 *rxbuff = (u8 *)buffer;
276 while (rxlen < len) {
277 /* Determine the next read length */
278 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
280 /* Set the ReqPkt bit */
281 csr = readw(&musbr->txcsr);
282 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
283 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
287 /* Actual number of bytes received by usb */
288 rxedlength = readb(&musbr->rxcount);
290 /* Read the data from the RxFIFO */
291 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
293 /* Clear the RxPktRdy Bit */
294 csr = readw(&musbr->txcsr);
295 csr &= ~MUSB_CSR0_RXPKTRDY;
296 writew(csr, &musbr->txcsr);
299 if (rxedlength != nextlen) {
300 dev->act_len += rxedlength;
304 dev->act_len = rxlen;
310 * This function handles the control transfer out data phase
312 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
317 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
318 u8 *txbuff = (u8 *)buffer;
321 while (txlen < len) {
322 /* Determine the next write length */
323 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
325 /* Load the data to send in FIFO */
326 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
328 /* Set TXPKTRDY bit */
329 csr = readw(&musbr->txcsr);
331 csr |= MUSB_CSR0_TXPKTRDY;
332 csr |= MUSB_CSR0_H_DIS_PING;
333 writew(csr, &musbr->txcsr);
334 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
339 dev->act_len = txlen;
345 * This function handles the control transfer out status phase
347 static int ctrlreq_out_status_phase(struct usb_device *dev)
352 /* Set the StatusPkt bit */
353 csr = readw(&musbr->txcsr);
354 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
355 csr |= MUSB_CSR0_H_DIS_PING;
356 writew(csr, &musbr->txcsr);
358 /* Wait until TXPKTRDY bit is cleared */
359 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
364 * This function handles the control transfer in status phase
366 static int ctrlreq_in_status_phase(struct usb_device *dev)
371 /* Set the StatusPkt bit and ReqPkt bit */
372 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
373 csr |= MUSB_CSR0_H_DIS_PING;
374 writew(csr, &musbr->txcsr);
375 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
377 /* clear StatusPkt bit and RxPktRdy bit */
378 csr = readw(&musbr->txcsr);
379 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
380 writew(csr, &musbr->txcsr);
385 * determines the speed of the device (High/Full/Slow)
387 static u8 get_dev_speed(struct usb_device *dev)
389 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
390 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
391 MUSB_TYPE_SPEED_FULL);
395 * configure the hub address and the port address.
397 static void config_hub_port(struct usb_device *dev, u8 ep)
402 /* Find out the nearest parent which is high speed */
403 while (dev->parent->parent != NULL)
404 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
409 /* determine the port address at that hub */
410 hub = dev->parent->devnum;
411 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
412 if (dev->parent->children[chid] == dev)
415 #ifndef MUSB_NO_MULTIPOINT
416 /* configure the hub address and the port address */
417 writeb(hub, &musbr->tar[ep].txhubaddr);
418 writeb((chid + 1), &musbr->tar[ep].txhubport);
419 writeb(hub, &musbr->tar[ep].rxhubaddr);
420 writeb((chid + 1), &musbr->tar[ep].rxhubport);
424 #ifdef MUSB_NO_MULTIPOINT
426 static void musb_port_reset(int do_reset)
428 u8 power = readb(&musbr->power);
432 writeb(power | MUSB_POWER_RESET, &musbr->power);
433 port_status |= USB_PORT_STAT_RESET;
434 port_status &= ~USB_PORT_STAT_ENABLE;
437 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
439 power = readb(&musbr->power);
440 if (power & MUSB_POWER_HSMODE)
441 port_status |= USB_PORT_STAT_HIGH_SPEED;
443 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
444 port_status |= USB_PORT_STAT_ENABLE
445 | (USB_PORT_STAT_C_RESET << 16)
446 | (USB_PORT_STAT_C_ENABLE << 16);
453 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
454 void *buffer, int transfer_len,
455 struct devrequest *cmd)
457 int leni = transfer_len;
461 const u8 *data_buf = (u8 *) datab;
468 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
469 debug("Root-Hub submit IRQ: NOT implemented\n");
473 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
474 wValue = swap_16(cmd->value);
475 wIndex = swap_16(cmd->index);
476 wLength = swap_16(cmd->length);
478 debug("--- HUB ----------------------------------------\n");
479 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
480 bmRType_bReq, wValue, wIndex, wLength);
481 debug("------------------------------------------------\n");
483 switch (bmRType_bReq) {
485 debug("RH_GET_STATUS\n");
487 *(__u16 *) data_buf = swap_16(1);
491 case RH_GET_STATUS | RH_INTERFACE:
492 debug("RH_GET_STATUS | RH_INTERFACE\n");
494 *(__u16 *) data_buf = swap_16(0);
498 case RH_GET_STATUS | RH_ENDPOINT:
499 debug("RH_GET_STATUS | RH_ENDPOINT\n");
501 *(__u16 *) data_buf = swap_16(0);
505 case RH_GET_STATUS | RH_CLASS:
506 debug("RH_GET_STATUS | RH_CLASS\n");
508 *(__u32 *) data_buf = swap_32(0);
512 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
513 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
515 int_usb = readw(&musbr->intrusb);
516 if (int_usb & MUSB_INTR_CONNECT) {
517 port_status |= USB_PORT_STAT_CONNECTION
518 | (USB_PORT_STAT_C_CONNECTION << 16);
519 port_status |= USB_PORT_STAT_HIGH_SPEED
520 | USB_PORT_STAT_ENABLE;
523 if (port_status & USB_PORT_STAT_RESET)
526 *(__u32 *) data_buf = swap_32(port_status);
530 case RH_CLEAR_FEATURE | RH_ENDPOINT:
531 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
534 case RH_ENDPOINT_STALL:
535 debug("C_HUB_ENDPOINT_STALL\n");
539 port_status &= ~(1 << wValue);
542 case RH_CLEAR_FEATURE | RH_CLASS:
543 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
546 case RH_C_HUB_LOCAL_POWER:
547 debug("C_HUB_LOCAL_POWER\n");
551 case RH_C_HUB_OVER_CURRENT:
552 debug("C_HUB_OVER_CURRENT\n");
556 port_status &= ~(1 << wValue);
559 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
560 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
567 case RH_PORT_SUSPEND:
575 case RH_C_PORT_CONNECTION:
579 case RH_C_PORT_ENABLE:
583 case RH_C_PORT_SUSPEND:
587 case RH_C_PORT_OVER_CURRENT:
591 case RH_C_PORT_RESET:
596 debug("invalid wValue\n");
597 stat = USB_ST_STALLED;
600 port_status &= ~(1 << wValue);
603 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
604 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
607 case RH_PORT_SUSPEND:
625 debug("invalid wValue\n");
626 stat = USB_ST_STALLED;
629 port_status |= 1 << wValue;
633 debug("RH_SET_ADDRESS\n");
639 case RH_GET_DESCRIPTOR:
640 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
643 case (USB_DT_DEVICE << 8): /* device descriptor */
644 len = min_t(unsigned int,
645 leni, min_t(unsigned int,
646 sizeof(root_hub_dev_des),
648 data_buf = root_hub_dev_des;
651 case (USB_DT_CONFIG << 8): /* configuration descriptor */
652 len = min_t(unsigned int,
653 leni, min_t(unsigned int,
654 sizeof(root_hub_config_des),
656 data_buf = root_hub_config_des;
659 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
660 len = min_t(unsigned int,
661 leni, min_t(unsigned int,
662 sizeof(root_hub_str_index0),
664 data_buf = root_hub_str_index0;
667 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
668 len = min_t(unsigned int,
669 leni, min_t(unsigned int,
670 sizeof(root_hub_str_index1),
672 data_buf = root_hub_str_index1;
676 debug("invalid wValue\n");
677 stat = USB_ST_STALLED;
682 case RH_GET_DESCRIPTOR | RH_CLASS: {
683 u8 *_data_buf = (u8 *) datab;
684 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
686 _data_buf[0] = 0x09; /* min length; */
688 _data_buf[2] = 0x1; /* 1 port */
689 _data_buf[3] = 0x01; /* per-port power switching */
690 _data_buf[3] |= 0x10; /* no overcurrent reporting */
692 /* Corresponds to data_buf[4-7] */
699 len = min_t(unsigned int, leni,
700 min_t(unsigned int, data_buf[0], wLength));
704 case RH_GET_CONFIGURATION:
705 debug("RH_GET_CONFIGURATION\n");
707 *(__u8 *) data_buf = 0x01;
711 case RH_SET_CONFIGURATION:
712 debug("RH_SET_CONFIGURATION\n");
718 debug("*** *** *** unsupported root hub command *** *** ***\n");
719 stat = USB_ST_STALLED;
722 len = min_t(int, len, leni);
723 if (buffer != data_buf)
724 memcpy(buffer, data_buf, len);
728 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
733 static void musb_rh_init(void)
741 static void musb_rh_init(void) {}
746 * do a control transfer
748 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
749 int len, struct devrequest *setup)
751 int devnum = usb_pipedevice(pipe);
754 #ifdef MUSB_NO_MULTIPOINT
755 /* Control message is for the HUB? */
756 if (devnum == rh_devnum) {
757 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
763 /* select control endpoint */
764 writeb(MUSB_CONTROL_EP, &musbr->index);
765 readw(&musbr->txcsr);
767 #ifndef MUSB_NO_MULTIPOINT
768 /* target addr and (for multipoint) hub addr/port */
769 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
770 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
773 /* configure the hub address and the port number as required */
774 devspeed = get_dev_speed(dev);
775 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
776 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
777 config_hub_port(dev, MUSB_CONTROL_EP);
778 writeb(devspeed << 6, &musbr->txtype);
780 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
781 #ifndef MUSB_NO_MULTIPOINT
782 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
783 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
784 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
785 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
789 /* Control transfer setup phase */
790 if (ctrlreq_setup_phase(dev, setup) < 0)
793 switch (setup->request) {
794 case USB_REQ_GET_DESCRIPTOR:
795 case USB_REQ_GET_CONFIGURATION:
796 case USB_REQ_GET_INTERFACE:
797 case USB_REQ_GET_STATUS:
798 case USB_MSC_BBB_GET_MAX_LUN:
799 /* control transfer in-data-phase */
800 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
802 /* control transfer out-status-phase */
803 if (ctrlreq_out_status_phase(dev) < 0)
807 case USB_REQ_SET_ADDRESS:
808 case USB_REQ_SET_CONFIGURATION:
809 case USB_REQ_SET_FEATURE:
810 case USB_REQ_SET_INTERFACE:
811 case USB_REQ_CLEAR_FEATURE:
812 case USB_MSC_BBB_RESET:
813 /* control transfer in status phase */
814 if (ctrlreq_in_status_phase(dev) < 0)
818 case USB_REQ_SET_DESCRIPTOR:
819 /* control transfer out data phase */
820 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
822 /* control transfer in status phase */
823 if (ctrlreq_in_status_phase(dev) < 0)
828 /* unhandled control transfer */
835 #ifdef MUSB_NO_MULTIPOINT
836 /* Set device address to USB_FADDR register */
837 if (setup->request == USB_REQ_SET_ADDRESS)
838 writeb(dev->devnum, &musbr->faddr);
847 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
848 void *buffer, int len)
850 int dir_out = usb_pipeout(pipe);
851 int ep = usb_pipeendpoint(pipe);
852 #ifndef MUSB_NO_MULTIPOINT
853 int devnum = usb_pipedevice(pipe);
861 /* select bulk endpoint */
862 writeb(MUSB_BULK_EP, &musbr->index);
864 #ifndef MUSB_NO_MULTIPOINT
865 /* write the address of the device */
867 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
869 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
872 /* configure the hub address and the port number as required */
873 devspeed = get_dev_speed(dev);
874 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
875 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
877 * MUSB is in high speed and the destination device is full
878 * speed device. So configure the hub address and port
881 config_hub_port(dev, MUSB_BULK_EP);
883 #ifndef MUSB_NO_MULTIPOINT
885 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
886 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
888 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
889 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
892 devspeed = musb_cfg.musb_speed;
895 /* Write the saved toggle bit value */
896 write_toggle(dev, ep, dir_out);
898 if (dir_out) { /* bulk-out transfer */
899 /* Program the TxType register */
900 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
901 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
902 (ep & MUSB_TYPE_REMOTE_END);
903 writeb(type, &musbr->txtype);
905 /* Write maximum packet size to the TxMaxp register */
906 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
907 while (txlen < len) {
908 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
909 (len-txlen) : dev->epmaxpacketout[ep];
911 /* Write the data to the FIFO */
912 write_fifo(MUSB_BULK_EP, nextlen,
913 (void *)(((u8 *)buffer) + txlen));
915 /* Set the TxPktRdy bit */
916 csr = readw(&musbr->txcsr);
917 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
919 /* Wait until the TxPktRdy bit is cleared */
920 if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
921 readw(&musbr->txcsr);
922 usb_settoggle(dev, ep, dir_out,
923 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
924 dev->act_len = txlen;
930 /* Keep a copy of the data toggle bit */
931 csr = readw(&musbr->txcsr);
932 usb_settoggle(dev, ep, dir_out,
933 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
934 } else { /* bulk-in transfer */
935 /* Write the saved toggle bit value */
936 write_toggle(dev, ep, dir_out);
938 /* Program the RxType register */
939 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
940 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
941 (ep & MUSB_TYPE_REMOTE_END);
942 writeb(type, &musbr->rxtype);
944 /* Write the maximum packet size to the RxMaxp register */
945 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
946 while (txlen < len) {
947 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
948 (len-txlen) : dev->epmaxpacketin[ep];
950 /* Set the ReqPkt bit */
951 csr = readw(&musbr->rxcsr);
952 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
954 /* Wait until the RxPktRdy bit is set */
955 if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
956 csr = readw(&musbr->rxcsr);
957 usb_settoggle(dev, ep, dir_out,
958 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
959 csr &= ~MUSB_RXCSR_RXPKTRDY;
960 writew(csr, &musbr->rxcsr);
961 dev->act_len = txlen;
965 /* Read the data from the FIFO */
966 read_fifo(MUSB_BULK_EP, nextlen,
967 (void *)(((u8 *)buffer) + txlen));
969 /* Clear the RxPktRdy bit */
970 csr = readw(&musbr->rxcsr);
971 csr &= ~MUSB_RXCSR_RXPKTRDY;
972 writew(csr, &musbr->rxcsr);
976 /* Keep a copy of the data toggle bit */
977 csr = readw(&musbr->rxcsr);
978 usb_settoggle(dev, ep, dir_out,
979 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
982 /* bulk transfer is complete */
989 * This function initializes the usb controller module.
991 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
998 if (musb_platform_init() == -1)
1001 /* Configure all the endpoint FIFO's and start usb controller */
1002 musbr = musb_cfg.regs;
1003 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1007 * Wait until musb is enabled in host mode with a timeout. There
1008 * should be a usb device connected.
1010 timeout = musb_cfg.timeout;
1012 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1015 /* if musb core is not in host mode, then return */
1019 /* start usb bus reset */
1020 power = readb(&musbr->power);
1021 writeb(power | MUSB_POWER_RESET, &musbr->power);
1023 /* After initiating a usb reset, wait for about 20ms to 30ms */
1026 /* stop usb bus reset */
1027 power = readb(&musbr->power);
1028 power &= ~MUSB_POWER_RESET;
1029 writeb(power, &musbr->power);
1031 /* Determine if the connected device is a high/full/low speed device */
1032 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1033 MUSB_TYPE_SPEED_HIGH :
1034 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1035 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1040 * This function stops the operation of the davinci usb module.
1042 int usb_lowlevel_stop(int index)
1044 /* Reset the USB module */
1045 musb_platform_deinit();
1046 writeb(0, &musbr->devctl);
1051 * This function supports usb interrupt transfers. Currently, usb interrupt
1052 * transfers are not supported.
1054 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1055 int len, int interval, bool nonblock)
1057 int dir_out = usb_pipeout(pipe);
1058 int ep = usb_pipeendpoint(pipe);
1059 #ifndef MUSB_NO_MULTIPOINT
1060 int devnum = usb_pipedevice(pipe);
1068 /* select interrupt endpoint */
1069 writeb(MUSB_INTR_EP, &musbr->index);
1071 #ifndef MUSB_NO_MULTIPOINT
1072 /* write the address of the device */
1074 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1076 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1079 /* configure the hub address and the port number as required */
1080 devspeed = get_dev_speed(dev);
1081 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1082 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1084 * MUSB is in high speed and the destination device is full
1085 * speed device. So configure the hub address and port
1086 * address registers.
1088 config_hub_port(dev, MUSB_INTR_EP);
1090 #ifndef MUSB_NO_MULTIPOINT
1092 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1093 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1095 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1096 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1099 devspeed = musb_cfg.musb_speed;
1102 /* Write the saved toggle bit value */
1103 write_toggle(dev, ep, dir_out);
1105 if (!dir_out) { /* intrrupt-in transfer */
1106 /* Write the saved toggle bit value */
1107 write_toggle(dev, ep, dir_out);
1108 writeb(interval, &musbr->rxinterval);
1110 /* Program the RxType register */
1111 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1112 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1113 (ep & MUSB_TYPE_REMOTE_END);
1114 writeb(type, &musbr->rxtype);
1116 /* Write the maximum packet size to the RxMaxp register */
1117 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1119 while (txlen < len) {
1120 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1121 (len-txlen) : dev->epmaxpacketin[ep];
1123 /* Set the ReqPkt bit */
1124 csr = readw(&musbr->rxcsr);
1125 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1127 /* Wait until the RxPktRdy bit is set */
1128 if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
1129 csr = readw(&musbr->rxcsr);
1130 usb_settoggle(dev, ep, dir_out,
1131 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1132 csr &= ~MUSB_RXCSR_RXPKTRDY;
1133 writew(csr, &musbr->rxcsr);
1134 dev->act_len = txlen;
1138 /* Read the data from the FIFO */
1139 read_fifo(MUSB_INTR_EP, nextlen,
1140 (void *)(((u8 *)buffer) + txlen));
1142 /* Clear the RxPktRdy bit */
1143 csr = readw(&musbr->rxcsr);
1144 csr &= ~MUSB_RXCSR_RXPKTRDY;
1145 writew(csr, &musbr->rxcsr);
1149 /* Keep a copy of the data toggle bit */
1150 csr = readw(&musbr->rxcsr);
1151 usb_settoggle(dev, ep, dir_out,
1152 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1155 /* interrupt transfer is complete */
1156 dev->irq_status = 0;
1157 dev->irq_act_len = len;
1158 dev->irq_handle(dev);