2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
79 * - ISO not tested ... might work, but only weakly isochronous
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
91 /* ----------------------------------------------------------------------- */
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
96 /* Maps the buffer to dma */
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
104 request->map_state = UN_MAPPED;
106 if (!is_dma_capable() || !musb_ep->dma)
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
123 request->request.buf,
124 request->request.length,
128 request->map_state = MUSB_MAPPED;
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
136 request->map_state = PRE_MAPPED;
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
144 if (!is_buffer_mapped(request))
147 if (request->request.dma == DMA_ADDR_INVALID) {
148 dev_vdbg(musb->controller,
149 "not unmapping a never mapped buffer\n");
152 if (request->map_state == MUSB_MAPPED) {
153 dma_unmap_single(musb->controller,
154 request->request.dma,
155 request->request.length,
159 request->request.dma = DMA_ADDR_INVALID;
160 } else { /* PRE_MAPPED */
161 dma_sync_single_for_cpu(musb->controller,
162 request->request.dma,
163 request->request.length,
168 request->map_state = UN_MAPPED;
172 * Immediately complete a request.
174 * @param request the request to complete
175 * @param status the status to complete the request with
176 * Context: controller locked, IRQs blocked.
178 void musb_g_giveback(
180 struct usb_request *request,
182 __releases(ep->musb->lock)
183 __acquires(ep->musb->lock)
185 struct musb_request *req;
189 req = to_musb_request(request);
191 list_del(&req->list);
192 if (req->request.status == -EINPROGRESS)
193 req->request.status = status;
197 spin_unlock(&musb->lock);
198 unmap_dma_buffer(req, musb);
199 if (request->status == 0)
200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
201 ep->end_point.name, request,
202 req->request.actual, req->request.length);
204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
205 ep->end_point.name, request,
206 req->request.actual, req->request.length,
208 req->request.complete(&req->ep->end_point, &req->request);
209 spin_lock(&musb->lock);
213 /* ----------------------------------------------------------------------- */
216 * Abort requests queued to an endpoint using the status. Synchronous.
217 * caller locked controller and blocked irqs, and selected this ep.
219 static void nuke(struct musb_ep *ep, const int status)
221 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
248 value = c->channel_abort(ep->dma);
249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
251 c->channel_release(ep->dma);
255 while (!list_empty(&ep->req_list)) {
256 req = list_first_entry(&ep->req_list, struct musb_request, list);
257 musb_g_giveback(ep, &req->request, status);
261 /* ----------------------------------------------------------------------- */
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
275 return ep->packet_sz;
279 #ifdef CONFIG_USB_INVENTRA_DMA
281 /* Peripheral tx (IN) using Mentor DMA works as follows:
282 Only mode 0 is used for transfers <= wPktSize,
283 mode 1 is used for larger transfers,
285 One of the following happens:
286 - Host sends IN token which causes an endpoint interrupt
288 -> if DMA is currently busy, exit.
289 -> if queue is non-empty, txstate().
291 - Request is queued by the gadget driver.
292 -> if queue was previously empty, txstate()
297 | (data is transferred to the FIFO, then sent out when
298 | IN token(s) are recd from Host.
299 | -> DMA interrupt on completion
301 | -> stop DMA, ~DMAENAB,
302 | -> set TxPktRdy for last short pkt or zlp
303 | -> Complete Request
304 | -> Continue next request (call txstate)
305 |___________________________________|
307 * Non-Mentor DMA engines can of course work differently, such as by
308 * upleveling from irq-per-packet to irq-per-buffer.
314 * An endpoint is transmitting data. This can be called either from
315 * the IRQ routine or from ep.queue() to kickstart a request on an
318 * Context: controller locked, IRQs blocked, endpoint selected
320 static void txstate(struct musb *musb, struct musb_request *req)
322 u8 epnum = req->epnum;
323 struct musb_ep *musb_ep;
324 void __iomem *epio = musb->endpoints[epnum].regs;
325 struct usb_request *request;
326 u16 fifo_count = 0, csr;
331 /* Check if EP is disabled */
332 if (!musb_ep->desc) {
333 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
334 musb_ep->end_point.name);
338 /* we shouldn't get here while DMA is active ... but we do ... */
339 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
340 dev_dbg(musb->controller, "dma pending...\n");
344 /* read TXCSR before */
345 csr = musb_readw(epio, MUSB_TXCSR);
347 request = &req->request;
348 fifo_count = min(max_ep_writesize(musb, musb_ep),
349 (int)(request->length - request->actual));
351 if (csr & MUSB_TXCSR_TXPKTRDY) {
352 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
353 musb_ep->end_point.name, csr);
357 if (csr & MUSB_TXCSR_P_SENDSTALL) {
358 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
359 musb_ep->end_point.name, csr);
363 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
364 epnum, musb_ep->packet_sz, fifo_count,
367 #ifndef CONFIG_MUSB_PIO_ONLY
368 if (is_buffer_mapped(req)) {
369 struct dma_controller *c = musb->dma_controller;
372 /* setup DMA, then program endpoint CSR */
373 request_size = min_t(size_t, request->length - request->actual,
374 musb_ep->dma->max_len);
376 use_dma = (request->dma != DMA_ADDR_INVALID);
378 /* MUSB_TXCSR_P_ISO is still set correctly */
380 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
382 if (request_size < musb_ep->packet_sz)
383 musb_ep->dma->desired_mode = 0;
385 musb_ep->dma->desired_mode = 1;
387 use_dma = use_dma && c->channel_program(
388 musb_ep->dma, musb_ep->packet_sz,
389 musb_ep->dma->desired_mode,
390 request->dma + request->actual, request_size);
392 if (musb_ep->dma->desired_mode == 0) {
394 * We must not clear the DMAMODE bit
395 * before the DMAENAB bit -- and the
396 * latter doesn't always get cleared
397 * before we get here...
399 csr &= ~(MUSB_TXCSR_AUTOSET
400 | MUSB_TXCSR_DMAENAB);
401 musb_writew(epio, MUSB_TXCSR, csr
402 | MUSB_TXCSR_P_WZC_BITS);
403 csr &= ~MUSB_TXCSR_DMAMODE;
404 csr |= (MUSB_TXCSR_DMAENAB |
406 /* against programming guide */
408 csr |= (MUSB_TXCSR_DMAENAB
411 if (!musb_ep->hb_mult)
412 csr |= MUSB_TXCSR_AUTOSET;
414 csr &= ~MUSB_TXCSR_P_UNDERRUN;
416 musb_writew(epio, MUSB_TXCSR, csr);
420 #elif defined(CONFIG_USB_TI_CPPI_DMA)
421 /* program endpoint CSR first, then setup DMA */
422 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
423 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
425 musb_writew(epio, MUSB_TXCSR,
426 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
429 /* ensure writebuffer is empty */
430 csr = musb_readw(epio, MUSB_TXCSR);
432 /* NOTE host side sets DMAENAB later than this; both are
433 * OK since the transfer dma glue (between CPPI and Mentor
434 * fifos) just tells CPPI it could start. Data only moves
435 * to the USB TX fifo when both fifos are ready.
438 /* "mode" is irrelevant here; handle terminating ZLPs like
439 * PIO does, since the hardware RNDIS mode seems unreliable
440 * except for the last-packet-is-already-short case.
442 use_dma = use_dma && c->channel_program(
443 musb_ep->dma, musb_ep->packet_sz,
445 request->dma + request->actual,
448 c->channel_release(musb_ep->dma);
450 csr &= ~MUSB_TXCSR_DMAENAB;
451 musb_writew(epio, MUSB_TXCSR, csr);
452 /* invariant: prequest->buf is non-null */
454 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
455 use_dma = use_dma && c->channel_program(
456 musb_ep->dma, musb_ep->packet_sz,
458 request->dma + request->actual,
466 * Unmap the dma buffer back to cpu if dma channel
469 unmap_dma_buffer(req, musb);
471 musb_write_fifo(musb_ep->hw_ep, fifo_count,
472 (u8 *) (request->buf + request->actual));
473 request->actual += fifo_count;
474 csr |= MUSB_TXCSR_TXPKTRDY;
475 csr &= ~MUSB_TXCSR_P_UNDERRUN;
476 musb_writew(epio, MUSB_TXCSR, csr);
479 /* host may already have the data when this message shows... */
480 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
481 musb_ep->end_point.name, use_dma ? "dma" : "pio",
482 request->actual, request->length,
483 musb_readw(epio, MUSB_TXCSR),
485 musb_readw(epio, MUSB_TXMAXP));
489 * FIFO state update (e.g. data ready).
490 * Called from IRQ, with controller locked.
492 void musb_g_tx(struct musb *musb, u8 epnum)
495 struct musb_request *req;
496 struct usb_request *request;
497 u8 __iomem *mbase = musb->mregs;
498 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
499 void __iomem *epio = musb->endpoints[epnum].regs;
500 struct dma_channel *dma;
502 musb_ep_select(mbase, epnum);
503 req = next_request(musb_ep);
504 request = &req->request;
506 csr = musb_readw(epio, MUSB_TXCSR);
507 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
509 dma = is_dma_capable() ? musb_ep->dma : NULL;
512 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
513 * probably rates reporting as a host error.
515 if (csr & MUSB_TXCSR_P_SENTSTALL) {
516 csr |= MUSB_TXCSR_P_WZC_BITS;
517 csr &= ~MUSB_TXCSR_P_SENTSTALL;
518 musb_writew(epio, MUSB_TXCSR, csr);
522 if (csr & MUSB_TXCSR_P_UNDERRUN) {
523 /* We NAKed, no big deal... little reason to care. */
524 csr |= MUSB_TXCSR_P_WZC_BITS;
525 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
526 musb_writew(epio, MUSB_TXCSR, csr);
527 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
531 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
533 * SHOULD NOT HAPPEN... has with CPPI though, after
534 * changing SENDSTALL (and other cases); harmless?
536 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
543 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
545 csr |= MUSB_TXCSR_P_WZC_BITS;
546 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
547 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
548 musb_writew(epio, MUSB_TXCSR, csr);
549 /* Ensure writebuffer is empty. */
550 csr = musb_readw(epio, MUSB_TXCSR);
551 request->actual += musb_ep->dma->actual_len;
552 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
553 epnum, csr, musb_ep->dma->actual_len, request);
557 * First, maybe a terminating short packet. Some DMA
558 * engines might handle this by themselves.
560 if ((request->zero && request->length
561 && (request->length % musb_ep->packet_sz == 0)
562 && (request->actual == request->length))
563 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
564 || (is_dma && (!dma->desired_mode ||
566 (musb_ep->packet_sz - 1))))
570 * On DMA completion, FIFO may not be
573 if (csr & MUSB_TXCSR_TXPKTRDY)
576 dev_dbg(musb->controller, "sending zero pkt\n");
577 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
578 | MUSB_TXCSR_TXPKTRDY);
582 if (request->actual == request->length) {
583 musb_g_giveback(musb_ep, request, 0);
585 * In the giveback function the MUSB lock is
586 * released and acquired after sometime. During
587 * this time period the INDEX register could get
588 * changed by the gadget_queue function especially
589 * on SMP systems. Reselect the INDEX to be sure
590 * we are reading/modifying the right registers
592 musb_ep_select(mbase, epnum);
593 req = musb_ep->desc ? next_request(musb_ep) : NULL;
595 dev_dbg(musb->controller, "%s idle now\n",
596 musb_ep->end_point.name);
605 /* ------------------------------------------------------------ */
607 #ifdef CONFIG_USB_INVENTRA_DMA
609 /* Peripheral rx (OUT) using Mentor DMA works as follows:
610 - Only mode 0 is used.
612 - Request is queued by the gadget class driver.
613 -> if queue was previously empty, rxstate()
615 - Host sends OUT token which causes an endpoint interrupt
617 | -> if request queued, call rxstate
619 | | -> DMA interrupt on completion
623 | | -> if data recd = max expected
624 | | by the request, or host
625 | | sent a short packet,
626 | | complete the request,
627 | | and start the next one.
628 | |_____________________________________|
629 | else just wait for the host
630 | to send the next OUT token.
631 |__________________________________________________|
633 * Non-Mentor DMA engines can of course work differently.
639 * Context: controller locked, IRQs blocked, endpoint selected
641 static void rxstate(struct musb *musb, struct musb_request *req)
643 const u8 epnum = req->epnum;
644 struct usb_request *request = &req->request;
645 struct musb_ep *musb_ep;
646 void __iomem *epio = musb->endpoints[epnum].regs;
647 unsigned fifo_count = 0;
649 u16 csr = musb_readw(epio, MUSB_RXCSR);
650 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
653 if (hw_ep->is_shared_fifo)
654 musb_ep = &hw_ep->ep_in;
656 musb_ep = &hw_ep->ep_out;
658 len = musb_ep->packet_sz;
660 /* Check if EP is disabled */
661 if (!musb_ep->desc) {
662 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
663 musb_ep->end_point.name);
667 /* We shouldn't get here while DMA is active, but we do... */
668 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
669 dev_dbg(musb->controller, "DMA pending...\n");
673 if (csr & MUSB_RXCSR_P_SENDSTALL) {
674 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
675 musb_ep->end_point.name, csr);
679 if (is_cppi_enabled() && is_buffer_mapped(req)) {
680 struct dma_controller *c = musb->dma_controller;
681 struct dma_channel *channel = musb_ep->dma;
683 /* NOTE: CPPI won't actually stop advancing the DMA
684 * queue after short packet transfers, so this is almost
685 * always going to run as IRQ-per-packet DMA so that
686 * faults will be handled correctly.
688 if (c->channel_program(channel,
690 !request->short_not_ok,
691 request->dma + request->actual,
692 request->length - request->actual)) {
694 /* make sure that if an rxpkt arrived after the irq,
695 * the cppi engine will be ready to take it as soon
698 csr &= ~(MUSB_RXCSR_AUTOCLEAR
699 | MUSB_RXCSR_DMAMODE);
700 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
701 musb_writew(epio, MUSB_RXCSR, csr);
706 if (csr & MUSB_RXCSR_RXPKTRDY) {
707 len = musb_readw(epio, MUSB_RXCOUNT);
710 * Enable Mode 1 on RX transfers only when short_not_ok flag
711 * is set. Currently short_not_ok flag is set only from
712 * file_storage and f_mass_storage drivers
715 if (request->short_not_ok && len == musb_ep->packet_sz)
720 if (request->actual < request->length) {
721 #ifdef CONFIG_USB_INVENTRA_DMA
722 if (is_buffer_mapped(req)) {
723 struct dma_controller *c;
724 struct dma_channel *channel;
727 c = musb->dma_controller;
728 channel = musb_ep->dma;
730 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
731 * mode 0 only. So we do not get endpoint interrupts due to DMA
732 * completion. We only get interrupts from DMA controller.
734 * We could operate in DMA mode 1 if we knew the size of the tranfer
735 * in advance. For mass storage class, request->length = what the host
736 * sends, so that'd work. But for pretty much everything else,
737 * request->length is routinely more than what the host sends. For
738 * most these gadgets, end of is signified either by a short packet,
739 * or filling the last byte of the buffer. (Sending extra data in
740 * that last pckate should trigger an overflow fault.) But in mode 1,
741 * we don't get DMA completion interrupt for short packets.
743 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
744 * to get endpoint interrupt on every DMA req, but that didn't seem
747 * REVISIT an updated g_file_storage can set req->short_not_ok, which
748 * then becomes usable as a runtime "use mode 1" hint...
751 /* Experimental: Mode1 works with mass storage use cases */
753 csr |= MUSB_RXCSR_AUTOCLEAR;
754 musb_writew(epio, MUSB_RXCSR, csr);
755 csr |= MUSB_RXCSR_DMAENAB;
756 musb_writew(epio, MUSB_RXCSR, csr);
759 * this special sequence (enabling and then
760 * disabling MUSB_RXCSR_DMAMODE) is required
761 * to get DMAReq to activate
763 musb_writew(epio, MUSB_RXCSR,
764 csr | MUSB_RXCSR_DMAMODE);
765 musb_writew(epio, MUSB_RXCSR, csr);
768 if (!musb_ep->hb_mult &&
769 musb_ep->hw_ep->rx_double_buffered)
770 csr |= MUSB_RXCSR_AUTOCLEAR;
771 csr |= MUSB_RXCSR_DMAENAB;
772 musb_writew(epio, MUSB_RXCSR, csr);
775 if (request->actual < request->length) {
776 int transfer_size = 0;
778 transfer_size = min(request->length - request->actual,
780 musb_ep->dma->desired_mode = 1;
782 transfer_size = min(request->length - request->actual,
784 musb_ep->dma->desired_mode = 0;
787 use_dma = c->channel_program(
790 channel->desired_mode,
799 #elif defined(CONFIG_USB_UX500_DMA)
800 if ((is_buffer_mapped(req)) &&
801 (request->actual < request->length)) {
803 struct dma_controller *c;
804 struct dma_channel *channel;
805 int transfer_size = 0;
807 c = musb->dma_controller;
808 channel = musb_ep->dma;
810 /* In case first packet is short */
811 if (len < musb_ep->packet_sz)
813 else if (request->short_not_ok)
814 transfer_size = min(request->length -
818 transfer_size = min(request->length -
822 csr &= ~MUSB_RXCSR_DMAMODE;
823 csr |= (MUSB_RXCSR_DMAENAB |
824 MUSB_RXCSR_AUTOCLEAR);
826 musb_writew(epio, MUSB_RXCSR, csr);
828 if (transfer_size <= musb_ep->packet_sz) {
829 musb_ep->dma->desired_mode = 0;
831 musb_ep->dma->desired_mode = 1;
832 /* Mode must be set after DMAENAB */
833 csr |= MUSB_RXCSR_DMAMODE;
834 musb_writew(epio, MUSB_RXCSR, csr);
837 if (c->channel_program(channel,
839 channel->desired_mode,
846 #endif /* Mentor's DMA */
848 fifo_count = request->length - request->actual;
849 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
850 musb_ep->end_point.name,
854 fifo_count = min_t(unsigned, len, fifo_count);
856 #ifdef CONFIG_USB_TUSB_OMAP_DMA
857 if (tusb_dma_omap() && is_buffer_mapped(req)) {
858 struct dma_controller *c = musb->dma_controller;
859 struct dma_channel *channel = musb_ep->dma;
860 u32 dma_addr = request->dma + request->actual;
863 ret = c->channel_program(channel,
865 channel->desired_mode,
873 * Unmap the dma buffer back to cpu if dma channel
874 * programming fails. This buffer is mapped if the
875 * channel allocation is successful
877 if (is_buffer_mapped(req)) {
878 unmap_dma_buffer(req, musb);
881 * Clear DMAENAB and AUTOCLEAR for the
884 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
885 musb_writew(epio, MUSB_RXCSR, csr);
888 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
889 (request->buf + request->actual));
890 request->actual += fifo_count;
892 /* REVISIT if we left anything in the fifo, flush
893 * it and report -EOVERFLOW
897 csr |= MUSB_RXCSR_P_WZC_BITS;
898 csr &= ~MUSB_RXCSR_RXPKTRDY;
899 musb_writew(epio, MUSB_RXCSR, csr);
903 /* reach the end or short packet detected */
904 if (request->actual == request->length || len < musb_ep->packet_sz)
905 musb_g_giveback(musb_ep, request, 0);
909 * Data ready for a request; called from IRQ
911 void musb_g_rx(struct musb *musb, u8 epnum)
914 struct musb_request *req;
915 struct usb_request *request;
916 void __iomem *mbase = musb->mregs;
917 struct musb_ep *musb_ep;
918 void __iomem *epio = musb->endpoints[epnum].regs;
919 struct dma_channel *dma;
920 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
922 if (hw_ep->is_shared_fifo)
923 musb_ep = &hw_ep->ep_in;
925 musb_ep = &hw_ep->ep_out;
927 musb_ep_select(mbase, epnum);
929 req = next_request(musb_ep);
933 request = &req->request;
935 csr = musb_readw(epio, MUSB_RXCSR);
936 dma = is_dma_capable() ? musb_ep->dma : NULL;
938 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
939 csr, dma ? " (dma)" : "", request);
941 if (csr & MUSB_RXCSR_P_SENTSTALL) {
942 csr |= MUSB_RXCSR_P_WZC_BITS;
943 csr &= ~MUSB_RXCSR_P_SENTSTALL;
944 musb_writew(epio, MUSB_RXCSR, csr);
948 if (csr & MUSB_RXCSR_P_OVERRUN) {
949 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
950 csr &= ~MUSB_RXCSR_P_OVERRUN;
951 musb_writew(epio, MUSB_RXCSR, csr);
953 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
954 if (request->status == -EINPROGRESS)
955 request->status = -EOVERFLOW;
957 if (csr & MUSB_RXCSR_INCOMPRX) {
958 /* REVISIT not necessarily an error */
959 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
962 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
963 /* "should not happen"; likely RXPKTRDY pending for DMA */
964 dev_dbg(musb->controller, "%s busy, csr %04x\n",
965 musb_ep->end_point.name, csr);
969 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
970 csr &= ~(MUSB_RXCSR_AUTOCLEAR
972 | MUSB_RXCSR_DMAMODE);
973 musb_writew(epio, MUSB_RXCSR,
974 MUSB_RXCSR_P_WZC_BITS | csr);
976 request->actual += musb_ep->dma->actual_len;
978 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
980 musb_readw(epio, MUSB_RXCSR),
981 musb_ep->dma->actual_len, request);
983 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
984 defined(CONFIG_USB_UX500_DMA)
985 /* Autoclear doesn't clear RxPktRdy for short packets */
986 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
988 & (musb_ep->packet_sz - 1))) {
990 csr &= ~MUSB_RXCSR_RXPKTRDY;
991 musb_writew(epio, MUSB_RXCSR, csr);
994 /* incomplete, and not short? wait for next IN packet */
995 if ((request->actual < request->length)
996 && (musb_ep->dma->actual_len
997 == musb_ep->packet_sz)) {
998 /* In double buffer case, continue to unload fifo if
999 * there is Rx packet in FIFO.
1001 csr = musb_readw(epio, MUSB_RXCSR);
1002 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
1003 hw_ep->rx_double_buffered)
1008 musb_g_giveback(musb_ep, request, 0);
1010 * In the giveback function the MUSB lock is
1011 * released and acquired after sometime. During
1012 * this time period the INDEX register could get
1013 * changed by the gadget_queue function especially
1014 * on SMP systems. Reselect the INDEX to be sure
1015 * we are reading/modifying the right registers
1017 musb_ep_select(mbase, epnum);
1019 req = next_request(musb_ep);
1023 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1024 defined(CONFIG_USB_UX500_DMA)
1027 /* Analyze request */
1031 /* ------------------------------------------------------------ */
1033 static int musb_gadget_enable(struct usb_ep *ep,
1034 const struct usb_endpoint_descriptor *desc)
1036 unsigned long flags;
1037 struct musb_ep *musb_ep;
1038 struct musb_hw_ep *hw_ep;
1041 void __iomem *mbase;
1045 int status = -EINVAL;
1050 musb_ep = to_musb_ep(ep);
1051 hw_ep = musb_ep->hw_ep;
1053 musb = musb_ep->musb;
1054 mbase = musb->mregs;
1055 epnum = musb_ep->current_epnum;
1057 spin_lock_irqsave(&musb->lock, flags);
1059 if (musb_ep->desc) {
1063 musb_ep->type = usb_endpoint_type(desc);
1065 /* check direction and (later) maxpacket size against endpoint */
1066 if (usb_endpoint_num(desc) != epnum)
1069 /* REVISIT this rules out high bandwidth periodic transfers */
1070 tmp = usb_endpoint_maxp(desc);
1071 if (tmp & ~0x07ff) {
1074 if (usb_endpoint_dir_in(desc))
1075 ok = musb->hb_iso_tx;
1077 ok = musb->hb_iso_rx;
1080 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1083 musb_ep->hb_mult = (tmp >> 11) & 3;
1085 musb_ep->hb_mult = 0;
1088 musb_ep->packet_sz = tmp & 0x7ff;
1089 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1091 /* enable the interrupts for the endpoint, set the endpoint
1092 * packet size (or fail), set the mode, clear the fifo
1094 musb_ep_select(mbase, epnum);
1095 if (usb_endpoint_dir_in(desc)) {
1096 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1098 if (hw_ep->is_shared_fifo)
1100 if (!musb_ep->is_in)
1103 if (tmp > hw_ep->max_packet_sz_tx) {
1104 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1108 int_txe |= (1 << epnum);
1109 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1111 /* REVISIT if can_bulk_split(), use by updating "tmp";
1112 * likewise high bandwidth periodic tx
1114 /* Set TXMAXP with the FIFO size of the endpoint
1115 * to disable double buffering mode.
1117 if (musb->double_buffer_not_ok)
1118 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1120 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1121 | (musb_ep->hb_mult << 11));
1123 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1124 if (musb_readw(regs, MUSB_TXCSR)
1125 & MUSB_TXCSR_FIFONOTEMPTY)
1126 csr |= MUSB_TXCSR_FLUSHFIFO;
1127 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1128 csr |= MUSB_TXCSR_P_ISO;
1130 /* set twice in case of double buffering */
1131 musb_writew(regs, MUSB_TXCSR, csr);
1132 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1133 musb_writew(regs, MUSB_TXCSR, csr);
1136 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1138 if (hw_ep->is_shared_fifo)
1143 if (tmp > hw_ep->max_packet_sz_rx) {
1144 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1148 int_rxe |= (1 << epnum);
1149 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1151 /* REVISIT if can_bulk_combine() use by updating "tmp"
1152 * likewise high bandwidth periodic rx
1154 /* Set RXMAXP with the FIFO size of the endpoint
1155 * to disable double buffering mode.
1157 if (musb->double_buffer_not_ok)
1158 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1160 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1161 | (musb_ep->hb_mult << 11));
1163 /* force shared fifo to OUT-only mode */
1164 if (hw_ep->is_shared_fifo) {
1165 csr = musb_readw(regs, MUSB_TXCSR);
1166 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1167 musb_writew(regs, MUSB_TXCSR, csr);
1170 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1171 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1172 csr |= MUSB_RXCSR_P_ISO;
1173 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1174 csr |= MUSB_RXCSR_DISNYET;
1176 /* set twice in case of double buffering */
1177 musb_writew(regs, MUSB_RXCSR, csr);
1178 musb_writew(regs, MUSB_RXCSR, csr);
1181 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1182 * for some reason you run out of channels here.
1184 if (is_dma_capable() && musb->dma_controller) {
1185 struct dma_controller *c = musb->dma_controller;
1187 musb_ep->dma = c->channel_alloc(c, hw_ep,
1188 (desc->bEndpointAddress & USB_DIR_IN));
1190 musb_ep->dma = NULL;
1192 musb_ep->desc = desc;
1194 musb_ep->wedged = 0;
1197 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1198 musb_driver_name, musb_ep->end_point.name,
1199 ({ char *s; switch (musb_ep->type) {
1200 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1201 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1202 default: s = "iso"; break;
1204 musb_ep->is_in ? "IN" : "OUT",
1205 musb_ep->dma ? "dma, " : "",
1206 musb_ep->packet_sz);
1208 schedule_work(&musb->irq_work);
1211 spin_unlock_irqrestore(&musb->lock, flags);
1216 * Disable an endpoint flushing all requests queued.
1218 static int musb_gadget_disable(struct usb_ep *ep)
1220 unsigned long flags;
1223 struct musb_ep *musb_ep;
1227 musb_ep = to_musb_ep(ep);
1228 musb = musb_ep->musb;
1229 epnum = musb_ep->current_epnum;
1230 epio = musb->endpoints[epnum].regs;
1232 spin_lock_irqsave(&musb->lock, flags);
1233 musb_ep_select(musb->mregs, epnum);
1235 /* zero the endpoint sizes */
1236 if (musb_ep->is_in) {
1237 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1238 int_txe &= ~(1 << epnum);
1239 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1240 musb_writew(epio, MUSB_TXMAXP, 0);
1242 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1243 int_rxe &= ~(1 << epnum);
1244 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1245 musb_writew(epio, MUSB_RXMAXP, 0);
1248 musb_ep->desc = NULL;
1249 musb_ep->end_point.desc = NULL;
1251 /* abort all pending DMA and requests */
1252 nuke(musb_ep, -ESHUTDOWN);
1254 schedule_work(&musb->irq_work);
1256 spin_unlock_irqrestore(&(musb->lock), flags);
1258 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1264 * Allocate a request for an endpoint.
1265 * Reused by ep0 code.
1267 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1269 struct musb_ep *musb_ep = to_musb_ep(ep);
1270 struct musb *musb = musb_ep->musb;
1271 struct musb_request *request = NULL;
1273 request = kzalloc(sizeof *request, gfp_flags);
1275 dev_dbg(musb->controller, "not enough memory\n");
1279 request->request.dma = DMA_ADDR_INVALID;
1280 request->epnum = musb_ep->current_epnum;
1281 request->ep = musb_ep;
1283 return &request->request;
1288 * Reused by ep0 code.
1290 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1292 kfree(to_musb_request(req));
1295 static LIST_HEAD(buffers);
1297 struct free_record {
1298 struct list_head list;
1305 * Context: controller locked, IRQs blocked.
1307 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1309 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1310 req->tx ? "TX/IN" : "RX/OUT",
1311 &req->request, req->request.length, req->epnum);
1313 musb_ep_select(musb->mregs, req->epnum);
1320 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1323 struct musb_ep *musb_ep;
1324 struct musb_request *request;
1327 unsigned long lockflags;
1334 musb_ep = to_musb_ep(ep);
1335 musb = musb_ep->musb;
1337 request = to_musb_request(req);
1338 request->musb = musb;
1340 if (request->ep != musb_ep)
1343 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1345 /* request is mine now... */
1346 request->request.actual = 0;
1347 request->request.status = -EINPROGRESS;
1348 request->epnum = musb_ep->current_epnum;
1349 request->tx = musb_ep->is_in;
1351 map_dma_buffer(request, musb, musb_ep);
1353 spin_lock_irqsave(&musb->lock, lockflags);
1355 /* don't queue if the ep is down */
1356 if (!musb_ep->desc) {
1357 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1358 req, ep->name, "disabled");
1359 status = -ESHUTDOWN;
1363 /* add request to the list */
1364 list_add_tail(&request->list, &musb_ep->req_list);
1366 /* it this is the head of the queue, start i/o ... */
1367 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1368 musb_ep_restart(musb, request);
1371 spin_unlock_irqrestore(&musb->lock, lockflags);
1375 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1377 struct musb_ep *musb_ep = to_musb_ep(ep);
1378 struct musb_request *req = to_musb_request(request);
1379 struct musb_request *r;
1380 unsigned long flags;
1382 struct musb *musb = musb_ep->musb;
1384 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1387 spin_lock_irqsave(&musb->lock, flags);
1389 list_for_each_entry(r, &musb_ep->req_list, list) {
1394 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1399 /* if the hardware doesn't have the request, easy ... */
1400 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1401 musb_g_giveback(musb_ep, request, -ECONNRESET);
1403 /* ... else abort the dma transfer ... */
1404 else if (is_dma_capable() && musb_ep->dma) {
1405 struct dma_controller *c = musb->dma_controller;
1407 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1408 if (c->channel_abort)
1409 status = c->channel_abort(musb_ep->dma);
1413 musb_g_giveback(musb_ep, request, -ECONNRESET);
1415 /* NOTE: by sticking to easily tested hardware/driver states,
1416 * we leave counting of in-flight packets imprecise.
1418 musb_g_giveback(musb_ep, request, -ECONNRESET);
1422 spin_unlock_irqrestore(&musb->lock, flags);
1427 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1428 * data but will queue requests.
1430 * exported to ep0 code
1432 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1434 struct musb_ep *musb_ep = to_musb_ep(ep);
1435 u8 epnum = musb_ep->current_epnum;
1436 struct musb *musb = musb_ep->musb;
1437 void __iomem *epio = musb->endpoints[epnum].regs;
1438 void __iomem *mbase;
1439 unsigned long flags;
1441 struct musb_request *request;
1446 mbase = musb->mregs;
1448 spin_lock_irqsave(&musb->lock, flags);
1450 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1455 musb_ep_select(mbase, epnum);
1457 request = next_request(musb_ep);
1460 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1465 /* Cannot portably stall with non-empty FIFO */
1466 if (musb_ep->is_in) {
1467 csr = musb_readw(epio, MUSB_TXCSR);
1468 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1469 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1475 musb_ep->wedged = 0;
1477 /* set/clear the stall and toggle bits */
1478 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1479 if (musb_ep->is_in) {
1480 csr = musb_readw(epio, MUSB_TXCSR);
1481 csr |= MUSB_TXCSR_P_WZC_BITS
1482 | MUSB_TXCSR_CLRDATATOG;
1484 csr |= MUSB_TXCSR_P_SENDSTALL;
1486 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1487 | MUSB_TXCSR_P_SENTSTALL);
1488 csr &= ~MUSB_TXCSR_TXPKTRDY;
1489 musb_writew(epio, MUSB_TXCSR, csr);
1491 csr = musb_readw(epio, MUSB_RXCSR);
1492 csr |= MUSB_RXCSR_P_WZC_BITS
1493 | MUSB_RXCSR_FLUSHFIFO
1494 | MUSB_RXCSR_CLRDATATOG;
1496 csr |= MUSB_RXCSR_P_SENDSTALL;
1498 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1499 | MUSB_RXCSR_P_SENTSTALL);
1500 musb_writew(epio, MUSB_RXCSR, csr);
1503 /* maybe start the first request in the queue */
1504 if (!musb_ep->busy && !value && request) {
1505 dev_dbg(musb->controller, "restarting the request\n");
1506 musb_ep_restart(musb, request);
1510 spin_unlock_irqrestore(&musb->lock, flags);
1515 * Sets the halt feature with the clear requests ignored
1517 static int musb_gadget_set_wedge(struct usb_ep *ep)
1519 struct musb_ep *musb_ep = to_musb_ep(ep);
1524 musb_ep->wedged = 1;
1526 return usb_ep_set_halt(ep);
1529 static int musb_gadget_fifo_status(struct usb_ep *ep)
1531 struct musb_ep *musb_ep = to_musb_ep(ep);
1532 void __iomem *epio = musb_ep->hw_ep->regs;
1533 int retval = -EINVAL;
1535 if (musb_ep->desc && !musb_ep->is_in) {
1536 struct musb *musb = musb_ep->musb;
1537 int epnum = musb_ep->current_epnum;
1538 void __iomem *mbase = musb->mregs;
1539 unsigned long flags;
1541 spin_lock_irqsave(&musb->lock, flags);
1543 musb_ep_select(mbase, epnum);
1544 /* FIXME return zero unless RXPKTRDY is set */
1545 retval = musb_readw(epio, MUSB_RXCOUNT);
1547 spin_unlock_irqrestore(&musb->lock, flags);
1552 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1554 struct musb_ep *musb_ep = to_musb_ep(ep);
1555 struct musb *musb = musb_ep->musb;
1556 u8 epnum = musb_ep->current_epnum;
1557 void __iomem *epio = musb->endpoints[epnum].regs;
1558 void __iomem *mbase;
1559 unsigned long flags;
1562 mbase = musb->mregs;
1564 spin_lock_irqsave(&musb->lock, flags);
1565 musb_ep_select(mbase, (u8) epnum);
1567 /* disable interrupts */
1568 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1569 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1571 if (musb_ep->is_in) {
1572 csr = musb_readw(epio, MUSB_TXCSR);
1573 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1574 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1576 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1577 * to interrupt current FIFO loading, but not flushing
1578 * the already loaded ones.
1580 csr &= ~MUSB_TXCSR_TXPKTRDY;
1581 musb_writew(epio, MUSB_TXCSR, csr);
1582 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1583 musb_writew(epio, MUSB_TXCSR, csr);
1586 csr = musb_readw(epio, MUSB_RXCSR);
1587 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1588 musb_writew(epio, MUSB_RXCSR, csr);
1589 musb_writew(epio, MUSB_RXCSR, csr);
1592 /* re-enable interrupt */
1593 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1594 spin_unlock_irqrestore(&musb->lock, flags);
1597 static const struct usb_ep_ops musb_ep_ops = {
1598 .enable = musb_gadget_enable,
1599 .disable = musb_gadget_disable,
1600 .alloc_request = musb_alloc_request,
1601 .free_request = musb_free_request,
1602 .queue = musb_gadget_queue,
1603 .dequeue = musb_gadget_dequeue,
1604 .set_halt = musb_gadget_set_halt,
1605 .set_wedge = musb_gadget_set_wedge,
1606 .fifo_status = musb_gadget_fifo_status,
1607 .fifo_flush = musb_gadget_fifo_flush
1610 /* ----------------------------------------------------------------------- */
1612 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1614 struct musb *musb = gadget_to_musb(gadget);
1616 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1619 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1621 struct musb *musb = gadget_to_musb(gadget);
1622 void __iomem *mregs = musb->mregs;
1623 unsigned long flags;
1624 int status = -EINVAL;
1628 spin_lock_irqsave(&musb->lock, flags);
1630 switch (musb->xceiv->state) {
1631 case OTG_STATE_B_PERIPHERAL:
1632 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1633 * that's part of the standard usb 1.1 state machine, and
1634 * doesn't affect OTG transitions.
1636 if (musb->may_wakeup && musb->is_suspended)
1639 case OTG_STATE_B_IDLE:
1640 /* Start SRP ... OTG not required. */
1641 devctl = musb_readb(mregs, MUSB_DEVCTL);
1642 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1643 devctl |= MUSB_DEVCTL_SESSION;
1644 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1645 devctl = musb_readb(mregs, MUSB_DEVCTL);
1647 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1648 devctl = musb_readb(mregs, MUSB_DEVCTL);
1653 while (devctl & MUSB_DEVCTL_SESSION) {
1654 devctl = musb_readb(mregs, MUSB_DEVCTL);
1659 spin_unlock_irqrestore(&musb->lock, flags);
1660 otg_start_srp(musb->xceiv->otg);
1661 spin_lock_irqsave(&musb->lock, flags);
1663 /* Block idling for at least 1s */
1664 musb_platform_try_idle(musb,
1665 jiffies + msecs_to_jiffies(1 * HZ));
1670 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1671 otg_state_string(musb->xceiv->state));
1677 power = musb_readb(mregs, MUSB_POWER);
1678 power |= MUSB_POWER_RESUME;
1679 musb_writeb(mregs, MUSB_POWER, power);
1680 dev_dbg(musb->controller, "issue wakeup\n");
1682 /* FIXME do this next chunk in a timer callback, no udelay */
1685 power = musb_readb(mregs, MUSB_POWER);
1686 power &= ~MUSB_POWER_RESUME;
1687 musb_writeb(mregs, MUSB_POWER, power);
1689 spin_unlock_irqrestore(&musb->lock, flags);
1694 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1696 struct musb *musb = gadget_to_musb(gadget);
1698 musb->is_self_powered = !!is_selfpowered;
1702 static void musb_pullup(struct musb *musb, int is_on)
1706 power = musb_readb(musb->mregs, MUSB_POWER);
1708 power |= MUSB_POWER_SOFTCONN;
1710 power &= ~MUSB_POWER_SOFTCONN;
1712 /* FIXME if on, HdrcStart; if off, HdrcStop */
1714 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1715 is_on ? "on" : "off");
1716 musb_writeb(musb->mregs, MUSB_POWER, power);
1720 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1722 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1725 * FIXME iff driver's softconnect flag is set (as it is during probe,
1726 * though that can clear it), just musb_pullup().
1733 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1735 struct musb *musb = gadget_to_musb(gadget);
1737 if (!musb->xceiv->set_power)
1739 return usb_phy_set_power(musb->xceiv, mA);
1742 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1744 struct musb *musb = gadget_to_musb(gadget);
1745 unsigned long flags;
1749 pm_runtime_get_sync(musb->controller);
1751 /* NOTE: this assumes we are sensing vbus; we'd rather
1752 * not pullup unless the B-session is active.
1754 spin_lock_irqsave(&musb->lock, flags);
1755 if (is_on != musb->softconnect) {
1756 musb->softconnect = is_on;
1757 musb_pullup(musb, is_on);
1759 spin_unlock_irqrestore(&musb->lock, flags);
1761 pm_runtime_put(musb->controller);
1766 static int musb_gadget_start(struct usb_gadget *g,
1767 struct usb_gadget_driver *driver);
1768 static int musb_gadget_stop(struct usb_gadget *g,
1769 struct usb_gadget_driver *driver);
1771 static const struct usb_gadget_ops musb_gadget_operations = {
1772 .get_frame = musb_gadget_get_frame,
1773 .wakeup = musb_gadget_wakeup,
1774 .set_selfpowered = musb_gadget_set_self_powered,
1775 /* .vbus_session = musb_gadget_vbus_session, */
1776 .vbus_draw = musb_gadget_vbus_draw,
1777 .pullup = musb_gadget_pullup,
1778 .udc_start = musb_gadget_start,
1779 .udc_stop = musb_gadget_stop,
1782 /* ----------------------------------------------------------------------- */
1786 /* Only this registration code "knows" the rule (from USB standards)
1787 * about there being only one external upstream port. It assumes
1788 * all peripheral ports are external...
1791 static void musb_gadget_release(struct device *dev)
1793 /* kref_put(WHAT) */
1794 dev_dbg(dev, "%s\n", __func__);
1798 static void __devinit
1799 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1801 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1803 memset(ep, 0, sizeof *ep);
1805 ep->current_epnum = epnum;
1810 INIT_LIST_HEAD(&ep->req_list);
1812 sprintf(ep->name, "ep%d%s", epnum,
1813 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1814 is_in ? "in" : "out"));
1815 ep->end_point.name = ep->name;
1816 INIT_LIST_HEAD(&ep->end_point.ep_list);
1818 ep->end_point.maxpacket = 64;
1819 ep->end_point.ops = &musb_g_ep0_ops;
1820 musb->g.ep0 = &ep->end_point;
1823 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1825 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1826 ep->end_point.ops = &musb_ep_ops;
1827 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1832 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1833 * to the rest of the driver state.
1835 static inline void __devinit musb_g_init_endpoints(struct musb *musb)
1838 struct musb_hw_ep *hw_ep;
1841 /* initialize endpoint list just once */
1842 INIT_LIST_HEAD(&(musb->g.ep_list));
1844 for (epnum = 0, hw_ep = musb->endpoints;
1845 epnum < musb->nr_endpoints;
1847 if (hw_ep->is_shared_fifo /* || !epnum */) {
1848 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1851 if (hw_ep->max_packet_sz_tx) {
1852 init_peripheral_ep(musb, &hw_ep->ep_in,
1856 if (hw_ep->max_packet_sz_rx) {
1857 init_peripheral_ep(musb, &hw_ep->ep_out,
1865 /* called once during driver setup to initialize and link into
1866 * the driver model; memory is zeroed.
1868 int __devinit musb_gadget_setup(struct musb *musb)
1872 /* REVISIT minor race: if (erroneously) setting up two
1873 * musb peripherals at the same time, only the bus lock
1877 musb->g.ops = &musb_gadget_operations;
1878 musb->g.max_speed = USB_SPEED_HIGH;
1879 musb->g.speed = USB_SPEED_UNKNOWN;
1881 /* this "gadget" abstracts/virtualizes the controller */
1882 dev_set_name(&musb->g.dev, "gadget");
1883 musb->g.dev.parent = musb->controller;
1884 musb->g.dev.dma_mask = musb->controller->dma_mask;
1885 musb->g.dev.release = musb_gadget_release;
1886 musb->g.name = musb_driver_name;
1888 if (is_otg_enabled(musb))
1891 musb_g_init_endpoints(musb);
1893 musb->is_active = 0;
1894 musb_platform_try_idle(musb, 0);
1896 status = device_register(&musb->g.dev);
1898 put_device(&musb->g.dev);
1901 status = usb_add_gadget_udc(musb->controller, &musb->g);
1907 musb->g.dev.parent = NULL;
1908 device_unregister(&musb->g.dev);
1912 void musb_gadget_cleanup(struct musb *musb)
1914 usb_del_gadget_udc(&musb->g);
1915 if (musb->g.dev.parent)
1916 device_unregister(&musb->g.dev);
1920 * Register the gadget driver. Used by gadget drivers when
1921 * registering themselves with the controller.
1923 * -EINVAL something went wrong (not driver)
1924 * -EBUSY another gadget is already using the controller
1925 * -ENOMEM no memory to perform the operation
1927 * @param driver the gadget driver
1928 * @return <0 if error, 0 if everything is fine
1930 static int musb_gadget_start(struct usb_gadget *g,
1931 struct usb_gadget_driver *driver)
1933 struct musb *musb = gadget_to_musb(g);
1934 struct usb_otg *otg = musb->xceiv->otg;
1935 unsigned long flags;
1936 int retval = -EINVAL;
1938 if (driver->max_speed < USB_SPEED_HIGH)
1941 pm_runtime_get_sync(musb->controller);
1943 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1945 musb->softconnect = 0;
1946 musb->gadget_driver = driver;
1948 spin_lock_irqsave(&musb->lock, flags);
1949 musb->is_active = 1;
1951 otg_set_peripheral(otg, &musb->g);
1952 musb->xceiv->state = OTG_STATE_B_IDLE;
1955 * FIXME this ignores the softconnect flag. Drivers are
1956 * allowed hold the peripheral inactive until for example
1957 * userspace hooks up printer hardware or DSP codecs, so
1958 * hosts only see fully functional devices.
1961 if (!is_otg_enabled(musb))
1964 spin_unlock_irqrestore(&musb->lock, flags);
1966 if (is_otg_enabled(musb)) {
1967 struct usb_hcd *hcd = musb_to_hcd(musb);
1969 dev_dbg(musb->controller, "OTG startup...\n");
1971 /* REVISIT: funcall to other code, which also
1972 * handles power budgeting ... this way also
1973 * ensures HdrcStart is indirectly called.
1975 retval = usb_add_hcd(musb_to_hcd(musb), 0, 0);
1977 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1981 if ((musb->xceiv->last_event == USB_EVENT_ID)
1983 otg_set_vbus(otg, 1);
1985 hcd->self.uses_pio_for_control = 1;
1987 if (musb->xceiv->last_event == USB_EVENT_NONE)
1988 pm_runtime_put(musb->controller);
1993 if (!is_otg_enabled(musb))
1999 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
2002 struct musb_hw_ep *hw_ep;
2004 /* don't disconnect if it's not connected */
2005 if (musb->g.speed == USB_SPEED_UNKNOWN)
2008 musb->g.speed = USB_SPEED_UNKNOWN;
2010 /* deactivate the hardware */
2011 if (musb->softconnect) {
2012 musb->softconnect = 0;
2013 musb_pullup(musb, 0);
2017 /* killing any outstanding requests will quiesce the driver;
2018 * then report disconnect
2021 for (i = 0, hw_ep = musb->endpoints;
2022 i < musb->nr_endpoints;
2024 musb_ep_select(musb->mregs, i);
2025 if (hw_ep->is_shared_fifo /* || !epnum */) {
2026 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2028 if (hw_ep->max_packet_sz_tx)
2029 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2030 if (hw_ep->max_packet_sz_rx)
2031 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2038 * Unregister the gadget driver. Used by gadget drivers when
2039 * unregistering themselves from the controller.
2041 * @param driver the gadget driver to unregister
2043 static int musb_gadget_stop(struct usb_gadget *g,
2044 struct usb_gadget_driver *driver)
2046 struct musb *musb = gadget_to_musb(g);
2047 unsigned long flags;
2049 if (musb->xceiv->last_event == USB_EVENT_NONE)
2050 pm_runtime_get_sync(musb->controller);
2053 * REVISIT always use otg_set_peripheral() here too;
2054 * this needs to shut down the OTG engine.
2057 spin_lock_irqsave(&musb->lock, flags);
2059 musb_hnp_stop(musb);
2061 (void) musb_gadget_vbus_draw(&musb->g, 0);
2063 musb->xceiv->state = OTG_STATE_UNDEFINED;
2064 stop_activity(musb, driver);
2065 otg_set_peripheral(musb->xceiv->otg, NULL);
2067 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2069 musb->is_active = 0;
2070 musb_platform_try_idle(musb, 0);
2071 spin_unlock_irqrestore(&musb->lock, flags);
2073 if (is_otg_enabled(musb)) {
2074 usb_remove_hcd(musb_to_hcd(musb));
2075 /* FIXME we need to be able to register another
2076 * gadget driver here and have everything work;
2077 * that currently misbehaves.
2081 if (!is_otg_enabled(musb))
2084 pm_runtime_put(musb->controller);
2089 /* ----------------------------------------------------------------------- */
2091 /* lifecycle operations called through plat_uds.c */
2093 void musb_g_resume(struct musb *musb)
2095 musb->is_suspended = 0;
2096 switch (musb->xceiv->state) {
2097 case OTG_STATE_B_IDLE:
2099 case OTG_STATE_B_WAIT_ACON:
2100 case OTG_STATE_B_PERIPHERAL:
2101 musb->is_active = 1;
2102 if (musb->gadget_driver && musb->gadget_driver->resume) {
2103 spin_unlock(&musb->lock);
2104 musb->gadget_driver->resume(&musb->g);
2105 spin_lock(&musb->lock);
2109 WARNING("unhandled RESUME transition (%s)\n",
2110 otg_state_string(musb->xceiv->state));
2114 /* called when SOF packets stop for 3+ msec */
2115 void musb_g_suspend(struct musb *musb)
2119 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2120 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2122 switch (musb->xceiv->state) {
2123 case OTG_STATE_B_IDLE:
2124 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2125 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2127 case OTG_STATE_B_PERIPHERAL:
2128 musb->is_suspended = 1;
2129 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2130 spin_unlock(&musb->lock);
2131 musb->gadget_driver->suspend(&musb->g);
2132 spin_lock(&musb->lock);
2136 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2137 * A_PERIPHERAL may need care too
2139 WARNING("unhandled SUSPEND transition (%s)\n",
2140 otg_state_string(musb->xceiv->state));
2144 /* Called during SRP */
2145 void musb_g_wakeup(struct musb *musb)
2147 musb_gadget_wakeup(&musb->g);
2150 /* called when VBUS drops below session threshold, and in other cases */
2151 void musb_g_disconnect(struct musb *musb)
2153 void __iomem *mregs = musb->mregs;
2154 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2156 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2159 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2161 /* don't draw vbus until new b-default session */
2162 (void) musb_gadget_vbus_draw(&musb->g, 0);
2164 musb->g.speed = USB_SPEED_UNKNOWN;
2165 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2166 spin_unlock(&musb->lock);
2167 musb->gadget_driver->disconnect(&musb->g);
2168 spin_lock(&musb->lock);
2171 switch (musb->xceiv->state) {
2173 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2174 otg_state_string(musb->xceiv->state));
2175 musb->xceiv->state = OTG_STATE_A_IDLE;
2176 MUSB_HST_MODE(musb);
2178 case OTG_STATE_A_PERIPHERAL:
2179 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2180 MUSB_HST_MODE(musb);
2182 case OTG_STATE_B_WAIT_ACON:
2183 case OTG_STATE_B_HOST:
2184 case OTG_STATE_B_PERIPHERAL:
2185 case OTG_STATE_B_IDLE:
2186 musb->xceiv->state = OTG_STATE_B_IDLE;
2188 case OTG_STATE_B_SRP_INIT:
2192 musb->is_active = 0;
2195 void musb_g_reset(struct musb *musb)
2196 __releases(musb->lock)
2197 __acquires(musb->lock)
2199 void __iomem *mbase = musb->mregs;
2200 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2203 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2204 (devctl & MUSB_DEVCTL_BDEVICE)
2205 ? "B-Device" : "A-Device",
2206 musb_readb(mbase, MUSB_FADDR),
2208 ? musb->gadget_driver->driver.name
2212 /* report disconnect, if we didn't already (flushing EP state) */
2213 if (musb->g.speed != USB_SPEED_UNKNOWN)
2214 musb_g_disconnect(musb);
2217 else if (devctl & MUSB_DEVCTL_HR)
2218 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2221 /* what speed did we negotiate? */
2222 power = musb_readb(mbase, MUSB_POWER);
2223 musb->g.speed = (power & MUSB_POWER_HSMODE)
2224 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2226 /* start in USB_STATE_DEFAULT */
2227 musb->is_active = 1;
2228 musb->is_suspended = 0;
2229 MUSB_DEV_MODE(musb);
2231 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2233 musb->may_wakeup = 0;
2234 musb->g.b_hnp_enable = 0;
2235 musb->g.a_alt_hnp_support = 0;
2236 musb->g.a_hnp_support = 0;
2238 /* Normal reset, as B-Device;
2239 * or else after HNP, as A-Device
2241 if (devctl & MUSB_DEVCTL_BDEVICE) {
2242 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2243 musb->g.is_a_peripheral = 0;
2244 } else if (is_otg_enabled(musb)) {
2245 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2246 musb->g.is_a_peripheral = 1;
2250 /* start with default limits on VBUS power draw */
2251 (void) musb_gadget_vbus_draw(&musb->g,
2252 is_otg_enabled(musb) ? 8 : 100);