1 #include <linux/device.h>
2 #include <linux/dma-mapping.h>
3 #include <linux/dmaengine.h>
4 #include <linux/sizes.h>
5 #include <linux/platform_device.h>
10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
12 #define EP_MODE_AUTOREQ_NONE 0
13 #define EP_MODE_AUTOREQ_ALL_NEOP 1
14 #define EP_MODE_AUTOREQ_ALWAYS 3
16 #define EP_MODE_DMA_TRANSPARENT 0
17 #define EP_MODE_DMA_RNDIS 1
18 #define EP_MODE_DMA_GEN_RNDIS 3
20 #define USB_CTRL_TX_MODE 0x70
21 #define USB_CTRL_RX_MODE 0x74
22 #define USB_CTRL_AUTOREQ 0xd0
23 #define USB_TDOWN 0xd8
25 struct cppi41_dma_channel {
26 struct dma_channel channel;
27 struct cppi41_dma_controller *controller;
28 struct musb_hw_ep *hw_ep;
41 struct list_head tx_check;
45 #define MUSB_DMA_NUM_CHANNELS 15
47 struct cppi41_dma_controller {
48 struct dma_controller controller;
49 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
50 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
52 struct hrtimer early_tx;
53 struct list_head early_tx_list;
59 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
64 if (cppi41_channel->is_tx)
66 if (!is_host_active(cppi41_channel->controller->musb))
69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
72 cppi41_channel->usb_toggle = toggle;
75 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
77 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
78 struct musb *musb = hw_ep->musb;
82 if (cppi41_channel->is_tx)
84 if (!is_host_active(musb))
87 musb_ep_select(musb->mregs, hw_ep->epnum);
88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
92 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
93 * data toggle may reset from DATA1 to DATA0 during receiving data from
94 * more than one endpoint.
96 if (!toggle && toggle == cppi41_channel->usb_toggle) {
97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
99 dev_dbg(cppi41_channel->controller->musb->controller,
100 "Restoring DATA1 toggle.\n");
103 cppi41_channel->usb_toggle = toggle;
106 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
108 u8 epnum = hw_ep->epnum;
109 struct musb *musb = hw_ep->musb;
110 void __iomem *epio = musb->endpoints[epnum].regs;
113 musb_ep_select(musb->mregs, hw_ep->epnum);
114 csr = musb_readw(epio, MUSB_TXCSR);
115 if (csr & MUSB_TXCSR_TXPKTRDY)
120 static void cppi41_dma_callback(void *private_data);
122 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
124 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
125 struct musb *musb = hw_ep->musb;
126 void __iomem *epio = hw_ep->regs;
129 if (!cppi41_channel->prog_len ||
130 (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
133 cppi41_channel->channel.actual_len =
134 cppi41_channel->transferred;
135 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
136 cppi41_channel->channel.rx_packet_done = true;
139 * transmit ZLP using PIO mode for transfers which size is
140 * multiple of EP packet size.
142 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
143 cppi41_channel->packet_sz) == 0) {
144 musb_ep_select(musb->mregs, hw_ep->epnum);
145 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
146 musb_writew(epio, MUSB_TXCSR, csr);
148 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
150 /* next iteration, reload */
151 struct dma_chan *dc = cppi41_channel->dc;
152 struct dma_async_tx_descriptor *dma_desc;
153 enum dma_transfer_direction direction;
156 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
158 remain_bytes = cppi41_channel->total_len;
159 remain_bytes -= cppi41_channel->transferred;
160 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
161 cppi41_channel->prog_len = remain_bytes;
163 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
165 dma_desc = dmaengine_prep_slave_single(dc,
166 cppi41_channel->buf_addr,
169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
170 if (WARN_ON(!dma_desc))
173 dma_desc->callback = cppi41_dma_callback;
174 dma_desc->callback_param = &cppi41_channel->channel;
175 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
176 dma_async_issue_pending(dc);
178 if (!cppi41_channel->is_tx) {
179 musb_ep_select(musb->mregs, hw_ep->epnum);
180 csr = musb_readw(epio, MUSB_RXCSR);
181 csr |= MUSB_RXCSR_H_REQPKT;
182 musb_writew(epio, MUSB_RXCSR, csr);
187 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
189 struct cppi41_dma_controller *controller;
190 struct cppi41_dma_channel *cppi41_channel, *n;
193 enum hrtimer_restart ret = HRTIMER_NORESTART;
195 controller = container_of(timer, struct cppi41_dma_controller,
197 musb = controller->musb;
199 spin_lock_irqsave(&musb->lock, flags);
200 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
203 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
205 empty = musb_is_tx_fifo_empty(hw_ep);
207 list_del_init(&cppi41_channel->tx_check);
208 cppi41_trans_done(cppi41_channel);
212 if (!list_empty(&controller->early_tx_list) &&
213 !hrtimer_is_queued(&controller->early_tx)) {
214 ret = HRTIMER_RESTART;
215 hrtimer_forward_now(&controller->early_tx,
216 ktime_set(0, 20 * NSEC_PER_USEC));
219 spin_unlock_irqrestore(&musb->lock, flags);
223 static void cppi41_dma_callback(void *private_data)
225 struct dma_channel *channel = private_data;
226 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
227 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
228 struct cppi41_dma_controller *controller;
229 struct musb *musb = hw_ep->musb;
231 struct dma_tx_state txstate;
236 spin_lock_irqsave(&musb->lock, flags);
238 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
240 transferred = cppi41_channel->prog_len - txstate.residue;
241 cppi41_channel->transferred += transferred;
243 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
244 hw_ep->epnum, cppi41_channel->transferred,
245 cppi41_channel->total_len);
247 update_rx_toggle(cppi41_channel);
249 if (cppi41_channel->transferred == cppi41_channel->total_len ||
250 transferred < cppi41_channel->packet_sz)
251 cppi41_channel->prog_len = 0;
253 if (cppi41_channel->is_tx)
254 empty = musb_is_tx_fifo_empty(hw_ep);
256 if (!cppi41_channel->is_tx || empty) {
257 cppi41_trans_done(cppi41_channel);
262 * On AM335x it has been observed that the TX interrupt fires
263 * too early that means the TXFIFO is not yet empty but the DMA
264 * engine says that it is done with the transfer. We don't
265 * receive a FIFO empty interrupt so the only thing we can do is
266 * to poll for the bit. On HS it usually takes 2us, on FS around
267 * 110us - 150us depending on the transfer size.
268 * We spin on HS (no longer than than 25us and setup a timer on
269 * FS to check for the bit and complete the transfer.
271 controller = cppi41_channel->controller;
273 if (is_host_active(musb)) {
274 if (musb->port1_status & USB_PORT_STAT_HIGH_SPEED)
277 if (musb->g.speed == USB_SPEED_HIGH)
284 empty = musb_is_tx_fifo_empty(hw_ep);
286 cppi41_trans_done(cppi41_channel);
295 list_add_tail(&cppi41_channel->tx_check,
296 &controller->early_tx_list);
297 if (!hrtimer_is_queued(&controller->early_tx)) {
298 unsigned long usecs = cppi41_channel->total_len / 10;
300 hrtimer_start_range_ns(&controller->early_tx,
301 ktime_set(0, usecs * NSEC_PER_USEC),
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
314 shift = (ep - 1) * 2;
315 old &= ~(3 << shift);
316 old |= mode << shift;
320 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
323 struct cppi41_dma_controller *controller = cppi41_channel->controller;
328 if (cppi41_channel->is_tx)
329 old_mode = controller->tx_mode;
331 old_mode = controller->rx_mode;
332 port = cppi41_channel->port_num;
333 new_mode = update_ep_mode(port, mode, old_mode);
335 if (new_mode == old_mode)
337 if (cppi41_channel->is_tx) {
338 controller->tx_mode = new_mode;
339 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
342 controller->rx_mode = new_mode;
343 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
348 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
351 struct cppi41_dma_controller *controller = cppi41_channel->controller;
356 old_mode = controller->auto_req;
357 port = cppi41_channel->port_num;
358 new_mode = update_ep_mode(port, mode, old_mode);
360 if (new_mode == old_mode)
362 controller->auto_req = new_mode;
363 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
366 static bool cppi41_configure_channel(struct dma_channel *channel,
367 u16 packet_sz, u8 mode,
368 dma_addr_t dma_addr, u32 len)
370 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
371 struct dma_chan *dc = cppi41_channel->dc;
372 struct dma_async_tx_descriptor *dma_desc;
373 enum dma_transfer_direction direction;
374 struct musb *musb = cppi41_channel->controller->musb;
375 unsigned use_gen_rndis = 0;
377 dev_dbg(musb->controller,
378 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
379 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
380 packet_sz, mode, (unsigned long long) dma_addr,
381 len, cppi41_channel->is_tx);
383 cppi41_channel->buf_addr = dma_addr;
384 cppi41_channel->total_len = len;
385 cppi41_channel->transferred = 0;
386 cppi41_channel->packet_sz = packet_sz;
387 cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
390 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
391 * than max packet size at a time.
393 if (cppi41_channel->is_tx)
398 if (len > packet_sz) {
399 musb_writel(musb->ctrl_base,
400 RNDIS_REG(cppi41_channel->port_num), len);
402 cppi41_set_dma_mode(cppi41_channel,
403 EP_MODE_DMA_GEN_RNDIS);
406 cppi41_set_autoreq_mode(cppi41_channel,
407 EP_MODE_AUTOREQ_ALL_NEOP);
409 musb_writel(musb->ctrl_base,
410 RNDIS_REG(cppi41_channel->port_num), 0);
411 cppi41_set_dma_mode(cppi41_channel,
412 EP_MODE_DMA_TRANSPARENT);
413 cppi41_set_autoreq_mode(cppi41_channel,
414 EP_MODE_AUTOREQ_NONE);
418 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
419 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
420 len = min_t(u32, packet_sz, len);
422 cppi41_channel->prog_len = len;
423 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
424 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
425 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
429 dma_desc->callback = cppi41_dma_callback;
430 dma_desc->callback_param = channel;
431 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
432 cppi41_channel->channel.rx_packet_done = false;
434 save_rx_toggle(cppi41_channel);
435 dma_async_issue_pending(dc);
439 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
440 struct musb_hw_ep *hw_ep, u8 is_tx)
442 struct cppi41_dma_controller *controller = container_of(c,
443 struct cppi41_dma_controller, controller);
444 struct cppi41_dma_channel *cppi41_channel = NULL;
445 u8 ch_num = hw_ep->epnum - 1;
447 if (ch_num >= MUSB_DMA_NUM_CHANNELS)
451 cppi41_channel = &controller->tx_channel[ch_num];
453 cppi41_channel = &controller->rx_channel[ch_num];
455 if (!cppi41_channel->dc)
458 if (cppi41_channel->is_allocated)
461 cppi41_channel->hw_ep = hw_ep;
462 cppi41_channel->is_allocated = 1;
464 return &cppi41_channel->channel;
467 static void cppi41_dma_channel_release(struct dma_channel *channel)
469 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
471 if (cppi41_channel->is_allocated) {
472 cppi41_channel->is_allocated = 0;
473 channel->status = MUSB_DMA_STATUS_FREE;
474 channel->actual_len = 0;
478 static int cppi41_dma_channel_program(struct dma_channel *channel,
479 u16 packet_sz, u8 mode,
480 dma_addr_t dma_addr, u32 len)
483 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
486 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
487 channel->status == MUSB_DMA_STATUS_BUSY);
489 if (is_host_active(cppi41_channel->controller->musb)) {
490 if (cppi41_channel->is_tx)
491 hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
493 hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
496 channel->status = MUSB_DMA_STATUS_BUSY;
497 channel->actual_len = 0;
500 packet_sz = hb_mult * (packet_sz & 0x7FF);
502 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
504 channel->status = MUSB_DMA_STATUS_FREE;
509 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
510 void *buf, u32 length)
512 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
513 struct cppi41_dma_controller *controller = cppi41_channel->controller;
514 struct musb *musb = controller->musb;
516 if (is_host_active(musb)) {
520 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
522 if (cppi41_channel->is_tx)
524 /* AM335x Advisory 1.0.13. No workaround for device RX mode */
528 static int cppi41_dma_channel_abort(struct dma_channel *channel)
530 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
531 struct cppi41_dma_controller *controller = cppi41_channel->controller;
532 struct musb *musb = controller->musb;
533 void __iomem *epio = cppi41_channel->hw_ep->regs;
539 is_tx = cppi41_channel->is_tx;
540 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
541 cppi41_channel->port_num, is_tx);
543 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
546 list_del_init(&cppi41_channel->tx_check);
548 csr = musb_readw(epio, MUSB_TXCSR);
549 csr &= ~MUSB_TXCSR_DMAENAB;
550 musb_writew(epio, MUSB_TXCSR, csr);
552 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
554 csr = musb_readw(epio, MUSB_RXCSR);
555 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
556 musb_writew(epio, MUSB_RXCSR, csr);
558 /* wait to drain cppi dma pipe line */
561 csr = musb_readw(epio, MUSB_RXCSR);
562 if (csr & MUSB_RXCSR_RXPKTRDY) {
563 csr |= MUSB_RXCSR_FLUSHFIFO;
564 musb_writew(epio, MUSB_RXCSR, csr);
565 musb_writew(epio, MUSB_RXCSR, csr);
569 tdbit = 1 << cppi41_channel->port_num;
575 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
576 ret = dmaengine_terminate_all(cppi41_channel->dc);
577 } while (ret == -EAGAIN);
580 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
582 csr = musb_readw(epio, MUSB_TXCSR);
583 if (csr & MUSB_TXCSR_TXPKTRDY) {
584 csr |= MUSB_TXCSR_FLUSHFIFO;
585 musb_writew(epio, MUSB_TXCSR, csr);
589 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
593 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
598 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
599 dc = ctrl->tx_channel[i].dc;
601 dma_release_channel(dc);
602 dc = ctrl->rx_channel[i].dc;
604 dma_release_channel(dc);
608 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
610 cppi41_release_all_dma_chans(controller);
613 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
615 struct musb *musb = controller->musb;
616 struct device *dev = musb->controller;
617 struct device_node *np = dev->of_node;
618 struct cppi41_dma_channel *cppi41_channel;
623 count = of_property_count_strings(np, "dma-names");
627 for (i = 0; i < count; i++) {
629 struct dma_channel *musb_dma;
634 ret = of_property_read_string_index(np, "dma-names", i, &str);
637 if (strstarts(str, "tx"))
639 else if (strstarts(str, "rx"))
642 dev_err(dev, "Wrong dmatype %s\n", str);
645 ret = kstrtouint(str + 2, 0, &port);
650 if (port > MUSB_DMA_NUM_CHANNELS || !port)
653 cppi41_channel = &controller->tx_channel[port - 1];
655 cppi41_channel = &controller->rx_channel[port - 1];
657 cppi41_channel->controller = controller;
658 cppi41_channel->port_num = port;
659 cppi41_channel->is_tx = is_tx;
660 INIT_LIST_HEAD(&cppi41_channel->tx_check);
662 musb_dma = &cppi41_channel->channel;
663 musb_dma->private_data = cppi41_channel;
664 musb_dma->status = MUSB_DMA_STATUS_FREE;
665 musb_dma->max_len = SZ_4M;
667 dc = dma_request_slave_channel(dev, str);
669 dev_err(dev, "Failed to request %s.\n", str);
673 cppi41_channel->dc = dc;
677 cppi41_release_all_dma_chans(controller);
681 void cppi41_dma_controller_destroy(struct dma_controller *c)
683 struct cppi41_dma_controller *controller = container_of(c,
684 struct cppi41_dma_controller, controller);
686 hrtimer_cancel(&controller->early_tx);
687 cppi41_dma_controller_stop(controller);
690 EXPORT_SYMBOL_GPL(cppi41_dma_controller_destroy);
692 struct dma_controller *
693 cppi41_dma_controller_create(struct musb *musb, void __iomem *base)
695 struct cppi41_dma_controller *controller;
698 if (!musb->controller->of_node) {
699 dev_err(musb->controller, "Need DT for the DMA engine.\n");
703 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
707 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
708 controller->early_tx.function = cppi41_recheck_tx_req;
709 INIT_LIST_HEAD(&controller->early_tx_list);
710 controller->musb = musb;
712 controller->controller.channel_alloc = cppi41_dma_channel_allocate;
713 controller->controller.channel_release = cppi41_dma_channel_release;
714 controller->controller.channel_program = cppi41_dma_channel_program;
715 controller->controller.channel_abort = cppi41_dma_channel_abort;
716 controller->controller.is_compatible = cppi41_is_compatible;
718 ret = cppi41_dma_controller_start(controller);
721 return &controller->controller;
726 if (ret == -EPROBE_DEFER)
730 EXPORT_SYMBOL_GPL(cppi41_dma_controller_create);