1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
6 * Copyright (C) 2016 MediaTek Inc.
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
11 #include <linux/dma-mapping.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
20 #include "mtu3_debug.h"
21 #include "mtu3_trace.h"
23 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
25 struct mtu3_fifo_info *fifo = mep->fifo;
26 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
29 /* ensure that @mep->fifo_seg_size is power of two */
30 num_bits = roundup_pow_of_two(num_bits);
31 if (num_bits > fifo->limit)
34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
35 num_bits = num_bits * (mep->slot + 1);
36 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
37 fifo->limit, 0, num_bits, 0);
38 if (start_bit >= fifo->limit)
41 bitmap_set(fifo->bitmap, start_bit, num_bits);
42 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
43 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
45 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
46 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
48 return mep->fifo_addr;
51 static void ep_fifo_free(struct mtu3_ep *mep)
53 struct mtu3_fifo_info *fifo = mep->fifo;
54 u32 addr = mep->fifo_addr;
55 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
58 if (unlikely(addr < fifo->base || bits > fifo->limit))
61 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
62 bitmap_clear(fifo->bitmap, start_bit, bits);
64 mep->fifo_seg_size = 0;
66 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
67 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
70 /* enable/disable U3D SS function */
71 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
73 /* If usb3_en==0, LTSSM will go to SS.Disable state */
75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
79 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
82 /* set/clear U3D HS device soft connect */
83 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
90 SOFT_CONN | SUSPENDM_ENABLE);
92 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
95 /* only port0 of U2/U3 supports device mode */
96 static int mtu3_device_enable(struct mtu3 *mtu)
98 void __iomem *ibase = mtu->ippc_base;
101 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
104 check_clk = SSUSB_U3_MAC_RST_B_STS;
105 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
106 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
107 SSUSB_U3_PORT_HOST_SEL));
109 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
110 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
111 SSUSB_U2_PORT_HOST_SEL));
113 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
114 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
116 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
117 SSUSB_U3_PORT_DUAL_MODE);
120 return ssusb_check_clocks(mtu->ssusb, check_clk);
123 static void mtu3_device_disable(struct mtu3 *mtu)
125 void __iomem *ibase = mtu->ippc_base;
128 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
129 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
131 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
132 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
134 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
135 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
137 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
138 SSUSB_U3_PORT_DUAL_MODE);
141 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
144 static void mtu3_dev_power_on(struct mtu3 *mtu)
146 void __iomem *ibase = mtu->ippc_base;
148 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
150 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
152 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
155 static void mtu3_dev_power_down(struct mtu3 *mtu)
157 void __iomem *ibase = mtu->ippc_base;
160 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
162 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
163 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
166 /* reset U3D's device module. */
167 static void mtu3_device_reset(struct mtu3 *mtu)
169 void __iomem *ibase = mtu->ippc_base;
171 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
173 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
176 static void mtu3_intr_status_clear(struct mtu3 *mtu)
178 void __iomem *mbase = mtu->mac_base;
180 /* Clear EP0 and Tx/Rx EPn interrupts status */
181 mtu3_writel(mbase, U3D_EPISR, ~0x0);
182 /* Clear U2 USB common interrupts status */
183 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
184 /* Clear U3 LTSSM interrupts status */
185 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
186 /* Clear speed change interrupt status */
187 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
188 /* Clear QMU interrupt status */
189 mtu3_writel(mbase, U3D_QISAR0, ~0x0);
192 /* disable all interrupts */
193 static void mtu3_intr_disable(struct mtu3 *mtu)
195 /* Disable level 1 interrupts */
196 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
197 /* Disable endpoint interrupts */
198 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
199 mtu3_intr_status_clear(mtu);
202 /* enable system global interrupt */
203 static void mtu3_intr_enable(struct mtu3 *mtu)
205 void __iomem *mbase = mtu->mac_base;
208 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
209 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
210 mtu3_writel(mbase, U3D_LV1IESR, value);
212 /* Enable U2 common USB interrupts */
213 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
214 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
217 /* Enable U3 LTSSM interrupts */
218 value = HOT_RST_INTR | WARM_RST_INTR |
219 ENTER_U3_INTR | EXIT_U3_INTR;
220 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
223 /* Enable QMU interrupts. */
224 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
225 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
226 mtu3_writel(mbase, U3D_QIESR1, value);
228 /* Enable speed change interrupt */
229 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
232 static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
234 void __iomem *mbase = mtu->mac_base;
236 if (speed > mtu->max_speed)
237 speed = mtu->max_speed;
241 /* disable U3 SS function */
242 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
243 /* disable HS function */
244 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
247 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
248 /* HS/FS detected by HW */
249 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
251 case USB_SPEED_SUPER:
252 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
253 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
254 SSUSB_U3_PORT_SSP_SPEED);
256 case USB_SPEED_SUPER_PLUS:
257 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
258 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
259 SSUSB_U3_PORT_SSP_SPEED);
262 dev_err(mtu->dev, "invalid speed: %s\n",
263 usb_speed_string(speed));
268 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
271 /* CSR registers will be reset to default value if port is disabled */
272 static void mtu3_csr_init(struct mtu3 *mtu)
274 void __iomem *mbase = mtu->mac_base;
277 /* disable LGO_U1/U2 by default */
278 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
279 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
280 /* enable accept LGO_U1/U2 link command from host */
281 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
282 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
283 /* device responses to u3_exit from host automatically */
284 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
285 /* automatically build U2 link when U3 detect fail */
286 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
287 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
288 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
291 /* delay about 0.1us from detecting reset to send chirp-K */
292 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
293 /* enable automatical HWRW from L1 */
294 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
297 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
298 static void mtu3_ep_reset(struct mtu3_ep *mep)
300 struct mtu3 *mtu = mep->mtu;
301 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
303 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
304 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
307 /* set/clear the stall and toggle bits for non-ep0 */
308 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
310 struct mtu3 *mtu = mep->mtu;
311 void __iomem *mbase = mtu->mac_base;
312 u8 epnum = mep->epnum;
315 if (mep->is_in) { /* TX */
316 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
320 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
321 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
323 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
327 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
328 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
333 mep->flags &= ~MTU3_EP_STALL;
335 mep->flags |= MTU3_EP_STALL;
338 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
339 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
342 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
344 if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
345 mtu3_ss_func_set(mtu, is_on);
347 mtu3_hs_softconn_set(mtu, is_on);
349 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
350 usb_speed_string(mtu->speed), is_on ? "+" : "-");
353 void mtu3_start(struct mtu3 *mtu)
355 void __iomem *mbase = mtu->mac_base;
357 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
358 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
360 mtu3_dev_power_on(mtu);
362 mtu3_set_speed(mtu, mtu->speed);
364 /* Initialize the default interrupts */
365 mtu3_intr_enable(mtu);
368 if (mtu->softconnect)
369 mtu3_dev_on_off(mtu, 1);
372 void mtu3_stop(struct mtu3 *mtu)
374 dev_dbg(mtu->dev, "%s\n", __func__);
376 mtu3_intr_disable(mtu);
378 if (mtu->softconnect)
379 mtu3_dev_on_off(mtu, 0);
382 mtu3_dev_power_down(mtu);
385 static void mtu3_dev_suspend(struct mtu3 *mtu)
390 mtu3_intr_disable(mtu);
391 mtu3_dev_power_down(mtu);
394 static void mtu3_dev_resume(struct mtu3 *mtu)
399 mtu3_dev_power_on(mtu);
400 mtu3_intr_enable(mtu);
404 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
405 int interval, int burst, int mult)
407 void __iomem *mbase = mtu->mac_base;
408 bool gen2cp = mtu->gen2cp;
409 int epnum = mep->epnum;
410 u32 csr0, csr1, csr2;
411 int fifo_sgsz, fifo_addr;
414 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
416 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
419 fifo_sgsz = ilog2(mep->fifo_seg_size);
420 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
421 mep->fifo_seg_size, mep->fifo_size);
424 csr0 = TX_TXMAXPKTSZ(mep->maxp);
427 num_pkts = (burst + 1) * (mult + 1) - 1;
428 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
429 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
431 csr2 = TX_FIFOADDR(fifo_addr >> 4);
432 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
435 case USB_ENDPOINT_XFER_BULK:
436 csr1 |= TX_TYPE(TYPE_BULK);
438 case USB_ENDPOINT_XFER_ISOC:
439 csr1 |= TX_TYPE(TYPE_ISO);
440 csr2 |= TX_BINTERVAL(interval);
442 case USB_ENDPOINT_XFER_INT:
443 csr1 |= TX_TYPE(TYPE_INT);
444 csr2 |= TX_BINTERVAL(interval);
448 /* Enable QMU Done interrupt */
449 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
451 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
452 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
453 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
455 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
456 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
457 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
458 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
460 csr0 = RX_RXMAXPKTSZ(mep->maxp);
463 num_pkts = (burst + 1) * (mult + 1) - 1;
464 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
465 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
467 csr2 = RX_FIFOADDR(fifo_addr >> 4);
468 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
471 case USB_ENDPOINT_XFER_BULK:
472 csr1 |= RX_TYPE(TYPE_BULK);
474 case USB_ENDPOINT_XFER_ISOC:
475 csr1 |= RX_TYPE(TYPE_ISO);
476 csr2 |= RX_BINTERVAL(interval);
478 case USB_ENDPOINT_XFER_INT:
479 csr1 |= RX_TYPE(TYPE_INT);
480 csr2 |= RX_BINTERVAL(interval);
484 /*Enable QMU Done interrupt */
485 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
487 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
488 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
489 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
491 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
492 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
493 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
494 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
497 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
498 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
499 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
500 fifo_sgsz, mep->fifo_seg_size);
506 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
508 void __iomem *mbase = mtu->mac_base;
509 int epnum = mep->epnum;
512 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
513 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
514 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
515 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
517 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
518 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
519 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
520 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
526 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
531 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
533 * 2. when supports only HS, the fifo is shared for all EPs, and
534 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
535 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
536 * so the total fifo size is 64B + @EPNTXFFSZ;
537 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
538 * starts from offset 64 and are divided into two equal parts for
539 * TX or RX EPs for simplification.
541 static void get_ep_fifo_config(struct mtu3 *mtu)
543 struct mtu3_fifo_info *tx_fifo;
544 struct mtu3_fifo_info *rx_fifo;
548 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
549 tx_fifo = &mtu->tx_fifo;
551 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
552 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
554 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
555 rx_fifo = &mtu->rx_fifo;
557 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
558 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
559 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
561 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
562 tx_fifo = &mtu->tx_fifo;
563 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
564 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
565 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
567 rx_fifo = &mtu->rx_fifo;
569 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
570 rx_fifo->limit = tx_fifo->limit;
571 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
572 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
575 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
576 __func__, tx_fifo->base, tx_fifo->limit,
577 rx_fifo->base, rx_fifo->limit);
580 static void mtu3_ep0_setup(struct mtu3 *mtu)
582 u32 maxpacket = mtu->g.ep0->maxpacket;
585 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
587 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
588 csr &= ~EP0_MAXPKTSZ_MSK;
589 csr |= EP0_MAXPKTSZ(maxpacket);
591 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
593 /* Enable EP0 interrupt */
594 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
597 static int mtu3_mem_alloc(struct mtu3 *mtu)
599 void __iomem *mbase = mtu->mac_base;
600 struct mtu3_ep *ep_array;
601 int in_ep_num, out_ep_num;
606 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
607 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
608 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
610 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
611 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
612 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
614 /* one for ep0, another is reserved */
615 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
616 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
617 if (ep_array == NULL)
620 mtu->ep_array = ep_array;
621 mtu->in_eps = ep_array;
622 mtu->out_eps = &ep_array[mtu->num_eps];
623 /* ep0 uses in_eps[0], out_eps[0] is reserved */
624 mtu->ep0 = mtu->in_eps;
628 for (i = 1; i < mtu->num_eps; i++) {
629 struct mtu3_ep *mep = mtu->in_eps + i;
631 mep->fifo = &mtu->tx_fifo;
632 mep = mtu->out_eps + i;
633 mep->fifo = &mtu->rx_fifo;
636 get_ep_fifo_config(mtu);
638 ret = mtu3_qmu_init(mtu);
640 kfree(mtu->ep_array);
645 static void mtu3_mem_free(struct mtu3 *mtu)
648 kfree(mtu->ep_array);
651 static void mtu3_regs_init(struct mtu3 *mtu)
653 void __iomem *mbase = mtu->mac_base;
655 /* be sure interrupts are disabled before registration of ISR */
656 mtu3_intr_disable(mtu);
660 /* U2/U3 detected by HW */
661 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
662 /* vbus detected by HW */
663 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
664 /* use new QMU format when HW version >= 0x1003 */
666 mtu3_writel(mbase, U3D_QFCR, ~0x0);
669 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
671 void __iomem *mbase = mtu->mac_base;
672 enum usb_device_speed udev_speed;
677 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
678 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
679 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
680 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
682 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
685 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
688 case MTU3_SPEED_FULL:
689 udev_speed = USB_SPEED_FULL;
690 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
691 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
692 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
693 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
694 LPM_BESL_STALL | LPM_BESLD_STALL);
696 case MTU3_SPEED_HIGH:
697 udev_speed = USB_SPEED_HIGH;
698 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
699 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
700 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
701 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
702 LPM_BESL_STALL | LPM_BESLD_STALL);
704 case MTU3_SPEED_SUPER:
705 udev_speed = USB_SPEED_SUPER;
708 case MTU3_SPEED_SUPER_PLUS:
709 udev_speed = USB_SPEED_SUPER_PLUS;
713 udev_speed = USB_SPEED_UNKNOWN;
716 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
717 mtu3_dbg_trace(mtu->dev, "link speed %s",
718 usb_speed_string(udev_speed));
720 mtu->g.speed = udev_speed;
721 mtu->g.ep0->maxpacket = maxpkt;
722 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
723 mtu->connected = !!(udev_speed != USB_SPEED_UNKNOWN);
725 if (udev_speed == USB_SPEED_UNKNOWN) {
726 mtu3_gadget_disconnect(mtu);
727 pm_runtime_put(mtu->dev);
729 pm_runtime_get(mtu->dev);
736 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
738 void __iomem *mbase = mtu->mac_base;
741 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
742 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
743 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
744 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
745 trace_mtu3_u3_ltssm_isr(ltssm);
747 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
748 mtu3_gadget_reset(mtu);
750 if (ltssm & VBUS_FALL_INTR) {
751 mtu3_ss_func_set(mtu, false);
752 mtu3_gadget_reset(mtu);
755 if (ltssm & VBUS_RISE_INTR)
756 mtu3_ss_func_set(mtu, true);
758 if (ltssm & EXIT_U3_INTR)
759 mtu3_gadget_resume(mtu);
761 if (ltssm & ENTER_U3_INTR)
762 mtu3_gadget_suspend(mtu);
767 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
769 void __iomem *mbase = mtu->mac_base;
772 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
773 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
774 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
775 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
776 trace_mtu3_u2_common_isr(u2comm);
778 if (u2comm & SUSPEND_INTR)
779 mtu3_gadget_suspend(mtu);
781 if (u2comm & RESUME_INTR)
782 mtu3_gadget_resume(mtu);
784 if (u2comm & RESET_INTR)
785 mtu3_gadget_reset(mtu);
790 static irqreturn_t mtu3_irq(int irq, void *data)
792 struct mtu3 *mtu = (struct mtu3 *)data;
796 spin_lock_irqsave(&mtu->lock, flags);
798 /* U3D_LV1ISR is RU */
799 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
800 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
802 if (level1 & EP_CTRL_INTR)
805 if (level1 & MAC2_INTR)
806 mtu3_u2_common_isr(mtu);
808 if (level1 & MAC3_INTR)
809 mtu3_u3_ltssm_isr(mtu);
811 if (level1 & BMU_INTR)
814 if (level1 & QMU_INTR)
817 spin_unlock_irqrestore(&mtu->lock, flags);
822 static void mtu3_check_params(struct mtu3 *mtu)
824 /* check the max_speed parameter */
825 switch (mtu->max_speed) {
828 case USB_SPEED_SUPER:
829 case USB_SPEED_SUPER_PLUS:
832 dev_err(mtu->dev, "invalid max_speed: %s\n",
833 usb_speed_string(mtu->max_speed));
835 case USB_SPEED_UNKNOWN:
837 mtu->max_speed = USB_SPEED_SUPER_PLUS;
841 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
842 mtu->max_speed = USB_SPEED_HIGH;
844 mtu->speed = mtu->max_speed;
846 dev_info(mtu->dev, "max_speed: %s\n",
847 usb_speed_string(mtu->max_speed));
850 static int mtu3_hw_init(struct mtu3 *mtu)
855 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
856 mtu->hw_version = IP_TRUNK_VERS(value);
857 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
859 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
860 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
862 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
863 mtu->is_u3_ip ? "U3" : "U2");
865 mtu3_check_params(mtu);
867 mtu3_device_reset(mtu);
869 ret = mtu3_device_enable(mtu);
871 dev_err(mtu->dev, "device enable failed %d\n", ret);
875 ret = mtu3_mem_alloc(mtu);
884 static void mtu3_hw_exit(struct mtu3 *mtu)
886 mtu3_device_disable(mtu);
891 * we set 32-bit DMA mask by default, here check whether the controller
892 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
894 static int mtu3_set_dma_mask(struct mtu3 *mtu)
896 struct device *dev = mtu->dev;
897 bool is_36bit = false;
901 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
902 if (value & DMA_ADDR_36BIT) {
904 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
905 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
908 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
911 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
916 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
918 struct device *dev = ssusb->dev;
919 struct platform_device *pdev = to_platform_device(dev);
920 struct mtu3 *mtu = NULL;
923 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
927 mtu->irq = platform_get_irq_byname_optional(pdev, "device");
929 if (mtu->irq == -EPROBE_DEFER)
932 /* for backward compatibility */
933 mtu->irq = platform_get_irq(pdev, 0);
937 dev_info(dev, "irq %d\n", mtu->irq);
939 mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
940 if (IS_ERR(mtu->mac_base)) {
941 dev_err(dev, "error mapping memory for dev mac\n");
942 return PTR_ERR(mtu->mac_base);
945 spin_lock_init(&mtu->lock);
947 mtu->ippc_base = ssusb->ippc_base;
948 ssusb->mac_base = mtu->mac_base;
951 mtu->max_speed = usb_get_maximum_speed(dev);
953 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
954 mtu->mac_base, mtu->ippc_base);
956 ret = mtu3_hw_init(mtu);
958 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
962 ret = mtu3_set_dma_mask(mtu);
964 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
968 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
970 dev_err(dev, "request irq %d failed!\n", mtu->irq);
974 /* power down device IP for power saving by default */
977 ret = mtu3_gadget_setup(mtu);
979 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
983 ssusb_dev_debugfs_init(ssusb);
985 dev_dbg(dev, " %s() done...\n", __func__);
990 device_init_wakeup(dev, false);
996 dev_err(dev, " %s() fail...\n", __func__);
1001 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
1003 struct mtu3 *mtu = ssusb->u3d;
1005 mtu3_gadget_cleanup(mtu);
1006 device_init_wakeup(ssusb->dev, false);
1010 bool ssusb_gadget_ip_sleep_check(struct ssusb_mtk *ssusb)
1012 struct mtu3 *mtu = ssusb->u3d;
1014 /* host only, should wait for ip sleep */
1018 /* device is started and pullup D+, ip can sleep */
1019 if (mtu->is_active && mtu->softconnect)
1022 /* ip can't sleep if not pullup D+ when support device mode */
1026 int ssusb_gadget_suspend(struct ssusb_mtk *ssusb, pm_message_t msg)
1028 struct mtu3 *mtu = ssusb->u3d;
1030 if (!mtu->gadget_driver)
1036 mtu3_dev_suspend(mtu);
1037 synchronize_irq(mtu->irq);
1042 int ssusb_gadget_resume(struct ssusb_mtk *ssusb, pm_message_t msg)
1044 struct mtu3 *mtu = ssusb->u3d;
1046 if (!mtu->gadget_driver)
1049 mtu3_dev_resume(mtu);