1 // SPDX-License-Identifier: GPL-2.0+
3 * USB HOST XHCI Controller stack
5 * Based on xHCI host controller driver in linux-kernel
8 * Copyright (C) 2008 Intel Corp.
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
17 * This file gives the xhci stack for usb3.0 looking into
18 * xhci specification Rev1.0 (5/21/10).
19 * The quirk devices support hasn't been given yet.
25 #include <dm/device_compat.h>
31 #include <asm/byteorder.h>
32 #include <asm/cache.h>
33 #include <asm/unaligned.h>
34 #include <linux/bitops.h>
35 #include <linux/bug.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/iopoll.h>
40 static struct descriptor {
41 struct usb_hub_descriptor hub;
42 struct usb_device_descriptor device;
43 struct usb_config_descriptor config;
44 struct usb_interface_descriptor interface;
45 struct usb_endpoint_descriptor endpoint;
46 struct usb_ss_ep_comp_descriptor ep_companion;
47 } __attribute__ ((packed)) descriptor = {
49 0xc, /* bDescLength */
50 0x2a, /* bDescriptorType: hub descriptor */
51 2, /* bNrPorts -- runtime modified */
52 cpu_to_le16(0x8), /* wHubCharacteristics */
53 10, /* bPwrOn2PwrGood */
54 0, /* bHubCntrCurrent */
55 { /* Device removable */
56 } /* at most 7 ports! XXX */
60 1, /* bDescriptorType: UDESC_DEVICE */
61 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
62 9, /* bDeviceClass: UDCLASS_HUB */
63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
64 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
65 9, /* bMaxPacketSize: 512 bytes 2^9 */
66 0x0000, /* idVendor */
67 0x0000, /* idProduct */
68 cpu_to_le16(0x0100), /* bcdDevice */
69 1, /* iManufacturer */
71 0, /* iSerialNumber */
72 1 /* bNumConfigurations: 1 */
76 2, /* bDescriptorType: UDESC_CONFIG */
77 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
78 1, /* bNumInterface */
79 1, /* bConfigurationValue */
80 0, /* iConfiguration */
81 0x40, /* bmAttributes: UC_SELF_POWER */
86 4, /* bDescriptorType: UDESC_INTERFACE */
87 0, /* bInterfaceNumber */
88 0, /* bAlternateSetting */
89 1, /* bNumEndpoints */
90 9, /* bInterfaceClass: UICLASS_HUB */
91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
97 5, /* bDescriptorType: UDESC_ENDPOINT */
98 0x81, /* bEndpointAddress: IN endpoint 1 */
99 3, /* bmAttributes: UE_INTERRUPT */
100 8, /* wMaxPacketSize */
104 0x06, /* ss_bLength */
105 0x30, /* ss_bDescriptorType: SS EP Companion */
106 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
107 /* ss_bmAttributes: 1 packet per service interval */
109 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
114 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
118 /* Find the USB controller */
119 for (dev = udev->dev;
120 device_get_uclass_id(dev) != UCLASS_USB;
123 return dev_get_priv(dev);
127 * Waits for as per specified amount of time
128 * for the "result" to match with "done"
130 * @param ptr pointer to the register to be read
131 * @param mask mask for the value read
132 * @param done value to be campared with result
133 * @param usec time to wait till
134 * Return: 0 if handshake is success else < 0 on failure
137 handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec)
142 ret = readx_poll_sleep_timeout(xhci_readl, ptr, result,
143 (result & mask) == done || result == U32_MAX,
145 if (result == U32_MAX) /* card removed */
152 * Set the run bit and wait for the host to be running.
154 * @param hcor pointer to host controller operation registers
155 * Return: status of the Handshake
157 static int xhci_start(struct xhci_hcor *hcor)
162 puts("Starting the controller\n");
163 temp = xhci_readl(&hcor->or_usbcmd);
165 xhci_writel(&hcor->or_usbcmd, temp);
168 * Wait for the HCHalted Status bit to be 0 to indicate the host is
171 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
173 debug("Host took too long to start, "
174 "waited %u microseconds.\n",
180 * Resets the XHCI Controller
182 * @param hcor pointer to host controller operation registers
183 * Return: -EBUSY if XHCI Controller is not halted else status of handshake
185 static int xhci_reset(struct xhci_hcor *hcor)
191 /* Halting the Host first */
192 debug("// Halt the HC: %p\n", hcor);
193 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
195 cmd = xhci_readl(&hcor->or_usbcmd);
197 xhci_writel(&hcor->or_usbcmd, cmd);
200 ret = handshake(&hcor->or_usbsts,
201 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
203 printf("Host not halted after %u microseconds.\n",
208 debug("// Reset the HC\n");
209 cmd = xhci_readl(&hcor->or_usbcmd);
211 xhci_writel(&hcor->or_usbcmd, cmd);
213 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
218 * xHCI cannot write to any doorbells or operational registers other
219 * than status until the "Controller Not Ready" flag is cleared.
221 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
225 * Used for passing endpoint bitmasks between the core and HCDs.
226 * Find the index for an endpoint given its descriptor.
227 * Use the return value to right shift 1 for the bitmask.
229 * Index = (epnum * 2) + direction - 1,
230 * where direction = 0 for OUT, 1 for IN.
231 * For control endpoints, the IN index is used (OUT index is unused), so
232 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
234 * @param desc USB enpdoint Descriptor
235 * Return: index of the Endpoint
237 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
241 if (usb_endpoint_xfer_control(desc))
242 index = (unsigned int)(usb_endpoint_num(desc) * 2);
244 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
245 (usb_endpoint_dir_in(desc) ? 0 : 1));
251 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
252 * microframes, rounded down to nearest power of 2.
254 static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
255 unsigned int min_exponent,
256 unsigned int max_exponent)
258 unsigned int interval;
260 interval = fls(desc_interval) - 1;
261 interval = clamp_val(interval, min_exponent, max_exponent);
262 if ((1 << interval) != desc_interval)
263 debug("rounding interval to %d microframes, "\
264 "ep desc says %d microframes\n",
265 1 << interval, desc_interval);
270 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
271 struct usb_endpoint_descriptor *endpt_desc)
273 if (endpt_desc->bInterval == 0)
276 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
279 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
280 struct usb_endpoint_descriptor *endpt_desc)
282 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
286 * Convert interval expressed as 2^(bInterval - 1) == interval into
287 * straight exponent value 2^n == interval.
289 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
290 struct usb_endpoint_descriptor *endpt_desc)
292 unsigned int interval;
294 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
295 if (interval != endpt_desc->bInterval - 1)
296 debug("ep %#x - rounding interval to %d %sframes\n",
297 endpt_desc->bEndpointAddress, 1 << interval,
298 udev->speed == USB_SPEED_FULL ? "" : "micro");
300 if (udev->speed == USB_SPEED_FULL) {
302 * Full speed isoc endpoints specify interval in frames,
303 * not microframes. We are using microframes everywhere,
304 * so adjust accordingly.
306 interval += 3; /* 1 frame = 2^3 uframes */
313 * Return the polling or NAK interval.
315 * The polling interval is expressed in "microframes". If xHCI's Interval field
316 * is set to N, it will service the endpoint every 2^(Interval)*125us.
318 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
321 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
322 struct usb_endpoint_descriptor *endpt_desc)
324 unsigned int interval = 0;
326 switch (udev->speed) {
329 if (usb_endpoint_xfer_control(endpt_desc) ||
330 usb_endpoint_xfer_bulk(endpt_desc)) {
331 interval = xhci_parse_microframe_interval(udev,
335 /* Fall through - SS and HS isoc/int have same decoding */
337 case USB_SPEED_SUPER:
338 if (usb_endpoint_xfer_int(endpt_desc) ||
339 usb_endpoint_xfer_isoc(endpt_desc)) {
340 interval = xhci_parse_exponent_interval(udev,
346 if (usb_endpoint_xfer_isoc(endpt_desc)) {
347 interval = xhci_parse_exponent_interval(udev,
352 * Fall through for interrupt endpoint interval decoding
353 * since it uses the same rules as low speed interrupt
358 if (usb_endpoint_xfer_int(endpt_desc) ||
359 usb_endpoint_xfer_isoc(endpt_desc)) {
360 interval = xhci_parse_frame_interval(udev, endpt_desc);
372 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
373 * High speed endpoint descriptors can define "the number of additional
374 * transaction opportunities per microframe", but that goes in the Max Burst
375 * endpoint context field.
377 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
378 struct usb_endpoint_descriptor *endpt_desc,
379 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
381 if (udev->speed < USB_SPEED_SUPER ||
382 !usb_endpoint_xfer_isoc(endpt_desc))
385 return ss_ep_comp_desc->bmAttributes;
388 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
389 struct usb_endpoint_descriptor *endpt_desc,
390 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
392 /* Super speed and Plus have max burst in ep companion desc */
393 if (udev->speed >= USB_SPEED_SUPER)
394 return ss_ep_comp_desc->bMaxBurst;
396 if (udev->speed == USB_SPEED_HIGH &&
397 (usb_endpoint_xfer_isoc(endpt_desc) ||
398 usb_endpoint_xfer_int(endpt_desc)))
399 return usb_endpoint_maxp_mult(endpt_desc) - 1;
405 * Return the maximum endpoint service interval time (ESIT) payload.
406 * Basically, this is the maxpacket size, multiplied by the burst size
409 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
410 struct usb_endpoint_descriptor *endpt_desc,
411 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
416 /* Only applies for interrupt or isochronous endpoints */
417 if (usb_endpoint_xfer_control(endpt_desc) ||
418 usb_endpoint_xfer_bulk(endpt_desc))
421 /* SuperSpeed Isoc ep with less than 48k per esit */
422 if (udev->speed >= USB_SPEED_SUPER)
423 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
425 max_packet = usb_endpoint_maxp(endpt_desc);
426 max_burst = usb_endpoint_maxp_mult(endpt_desc);
428 /* A 0 in max burst means 1 transfer per ESIT */
429 return max_packet * max_burst;
433 * Issue a configure endpoint command or evaluate context command
434 * and wait for it to finish.
436 * @param udev pointer to the Device Data Structure
437 * @param ctx_change flag to indicate the Context has changed or NOT
438 * Return: 0 on success, -1 on failure
440 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
442 struct xhci_container_ctx *in_ctx;
443 struct xhci_virt_device *virt_dev;
444 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
445 union xhci_trb *event;
447 virt_dev = ctrl->devs[udev->slot_id];
448 in_ctx = virt_dev->in_ctx;
450 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
451 xhci_queue_command(ctrl, in_ctx->dma, udev->slot_id, 0,
452 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
453 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
454 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
457 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
459 debug("Successful %s command\n",
460 ctx_change ? "Evaluate Context" : "Configure Endpoint");
463 printf("ERROR: %s command returned completion code %d.\n",
464 ctx_change ? "Evaluate Context" : "Configure Endpoint",
465 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
469 xhci_acknowledge_event(ctrl);
475 * Configure the endpoint, programming the device contexts.
477 * @param udev pointer to the USB device structure
478 * Return: returns the status of the xhci_configure_endpoints
480 static int xhci_set_configuration(struct usb_device *udev)
482 struct xhci_container_ctx *in_ctx;
483 struct xhci_container_ctx *out_ctx;
484 struct xhci_input_control_ctx *ctrl_ctx;
485 struct xhci_slot_ctx *slot_ctx;
486 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
491 unsigned int ep_type;
492 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
496 int slot_id = udev->slot_id;
497 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
498 struct usb_interface *ifdesc;
499 u32 max_esit_payload;
500 unsigned int interval;
502 unsigned int max_burst;
503 unsigned int avg_trb_len;
504 unsigned int err_count = 0;
506 out_ctx = virt_dev->out_ctx;
507 in_ctx = virt_dev->in_ctx;
509 num_of_ep = udev->config.if_desc[0].no_of_ep;
510 ifdesc = &udev->config.if_desc[0];
512 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
513 /* Initialize the input context control */
514 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
515 ctrl_ctx->drop_flags = 0;
517 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
518 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
519 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
520 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
521 if (max_ep_flag < ep_flag)
522 max_ep_flag = ep_flag;
525 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
528 xhci_slot_copy(ctrl, in_ctx, out_ctx);
529 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
530 slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
531 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
533 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
535 /* filling up ep contexts */
536 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
537 struct usb_endpoint_descriptor *endpt_desc = NULL;
538 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
540 endpt_desc = &ifdesc->ep_desc[cur_ep];
541 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
545 * Get values to fill the endpoint context, mostly from ep
546 * descriptor. The average TRB buffer lengt for bulk endpoints
547 * is unclear as we have no clue on scatter gather list entry
548 * size. For Isoc and Int, set it to max available.
549 * See xHCI 1.1 spec 4.14.1.1 for details.
551 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
553 interval = xhci_get_endpoint_interval(udev, endpt_desc);
554 mult = xhci_get_endpoint_mult(udev, endpt_desc,
556 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
558 avg_trb_len = max_esit_payload;
560 ep_index = xhci_get_ep_index(endpt_desc);
561 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
563 /* Allocate the ep rings */
564 virt_dev->eps[ep_index].ring = xhci_ring_alloc(ctrl, 1, true);
565 if (!virt_dev->eps[ep_index].ring)
568 /*NOTE: ep_desc[0] actually represents EP1 and so on */
569 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
570 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
572 ep_ctx[ep_index]->ep_info =
573 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
574 EP_INTERVAL(interval) | EP_MULT(mult));
576 ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
577 ep_ctx[ep_index]->ep_info2 |=
578 cpu_to_le32(MAX_PACKET
579 (get_unaligned(&endpt_desc->wMaxPacketSize)));
581 /* Allow 3 retries for everything but isoc, set CErr = 3 */
582 if (!usb_endpoint_xfer_isoc(endpt_desc))
584 ep_ctx[ep_index]->ep_info2 |=
585 cpu_to_le32(MAX_BURST(max_burst) |
586 ERROR_COUNT(err_count));
588 trb_64 = xhci_trb_virt_to_dma(virt_dev->eps[ep_index].ring->enq_seg,
589 virt_dev->eps[ep_index].ring->enqueue);
590 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
591 virt_dev->eps[ep_index].ring->cycle_state);
595 * 'Average TRB Length' should be 8 for control endpoints.
597 if (usb_endpoint_xfer_control(endpt_desc))
599 ep_ctx[ep_index]->tx_info =
600 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
601 EP_AVG_TRB_LENGTH(avg_trb_len));
604 * The MediaTek xHCI defines some extra SW parameters which
605 * are put into reserved DWs in Slot and Endpoint Contexts
606 * for synchronous endpoints.
608 if (ctrl->quirks & XHCI_MTK_HOST) {
609 ep_ctx[ep_index]->reserved[0] =
610 cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
614 return xhci_configure_endpoints(udev, false);
618 * Issue an Address Device command (which will issue a SetAddress request to
621 * @param udev pointer to the Device Data Structure
622 * Return: 0 if successful else error code on failure
624 static int xhci_address_device(struct usb_device *udev, int root_portnr)
627 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
628 struct xhci_slot_ctx *slot_ctx;
629 struct xhci_input_control_ctx *ctrl_ctx;
630 struct xhci_virt_device *virt_dev;
631 int slot_id = udev->slot_id;
632 union xhci_trb *event;
634 virt_dev = ctrl->devs[slot_id];
637 * This is the first Set Address since device plug-in
638 * so setting up the slot context.
640 debug("Setting up addressable devices %p\n", ctrl->dcbaa);
641 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
643 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
644 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
645 ctrl_ctx->drop_flags = 0;
647 xhci_queue_command(ctrl, virt_dev->in_ctx->dma,
648 slot_id, 0, TRB_ADDR_DEV);
649 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
650 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
652 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
655 printf("Setup ERROR: address device command for slot %d.\n",
660 puts("Device not responding to set address.\n");
664 puts("ERROR: Incompatible device"
665 "for address device command.\n");
669 debug("Successful Address Device command\n");
673 printf("ERROR: unexpected command completion code 0x%x.\n",
674 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
679 xhci_acknowledge_event(ctrl);
683 * TODO: Unsuccessful Address Device command shall leave the
684 * slot in default state. So, issue Disable Slot command now.
688 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
689 virt_dev->out_ctx->size);
690 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
692 debug("xHC internal address is: %d\n",
693 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
699 * Issue Enable slot command to the controller to allocate
700 * device slot and assign the slot id. It fails if the xHC
701 * ran out of device slots, the Enable Slot command timed out,
702 * or allocating memory failed.
704 * @param udev pointer to the Device Data Structure
705 * Return: Returns 0 on succes else return error code on failure
707 static int _xhci_alloc_device(struct usb_device *udev)
709 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
710 union xhci_trb *event;
714 * Root hub will be first device to be initailized.
715 * If this device is root-hub, don't do any xHC related
718 if (ctrl->rootdev == 0) {
719 udev->speed = USB_SPEED_SUPER;
723 xhci_queue_command(ctrl, 0, 0, 0, TRB_ENABLE_SLOT);
724 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
725 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
728 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
730 xhci_acknowledge_event(ctrl);
732 ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
735 * TODO: Unsuccessful Address Device command shall leave
736 * the slot in default. So, issue Disable Slot command now.
738 puts("Could not allocate xHCI USB device data structures\n");
746 * Full speed devices may have a max packet size greater than 8 bytes, but the
747 * USB core doesn't know that until it reads the first 8 bytes of the
748 * descriptor. If the usb_device's max packet size changes after that point,
749 * we need to issue an evaluate context command and wait on it.
751 * @param udev pointer to the Device Data Structure
752 * Return: returns the status of the xhci_configure_endpoints
754 int xhci_check_maxpacket(struct usb_device *udev)
756 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
757 unsigned int slot_id = udev->slot_id;
758 int ep_index = 0; /* control endpoint */
759 struct xhci_container_ctx *in_ctx;
760 struct xhci_container_ctx *out_ctx;
761 struct xhci_input_control_ctx *ctrl_ctx;
762 struct xhci_ep_ctx *ep_ctx;
764 int hw_max_packet_size;
767 out_ctx = ctrl->devs[slot_id]->out_ctx;
768 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
770 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
771 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
772 max_packet_size = udev->epmaxpacketin[0];
773 if (hw_max_packet_size != max_packet_size) {
774 debug("Max Packet Size for ep 0 changed.\n");
775 debug("Max packet size in usb_device = %d\n", max_packet_size);
776 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
777 debug("Issuing evaluate context command.\n");
779 /* Set up the modified control endpoint 0 */
780 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
781 ctrl->devs[slot_id]->out_ctx, ep_index);
782 in_ctx = ctrl->devs[slot_id]->in_ctx;
783 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
784 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
785 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
788 * Set up the input context flags for the command
789 * FIXME: This won't work if a non-default control endpoint
790 * changes max packet sizes.
792 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
793 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
794 ctrl_ctx->drop_flags = 0;
796 ret = xhci_configure_endpoints(udev, true);
802 * Clears the Change bits of the Port Status Register
804 * @param wValue request value
805 * @param wIndex request index
806 * @param addr address of posrt status register
807 * @param port_status state of port status register
810 static void xhci_clear_port_change_bit(u16 wValue,
811 u16 wIndex, volatile uint32_t *addr, u32 port_status)
813 char *port_change_bit;
817 case USB_PORT_FEAT_C_RESET:
819 port_change_bit = "reset";
821 case USB_PORT_FEAT_C_CONNECTION:
823 port_change_bit = "connect";
825 case USB_PORT_FEAT_C_OVER_CURRENT:
827 port_change_bit = "over-current";
829 case USB_PORT_FEAT_C_ENABLE:
831 port_change_bit = "enable/disable";
833 case USB_PORT_FEAT_C_SUSPEND:
835 port_change_bit = "suspend/resume";
838 /* Should never happen */
842 /* Change bits are all write 1 to clear */
843 xhci_writel(addr, port_status | status);
845 port_status = xhci_readl(addr);
846 debug("clear port %s change, actual port %d status = 0x%x\n",
847 port_change_bit, wIndex, port_status);
851 * Save Read Only (RO) bits and save read/write bits where
852 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
853 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
855 * @param state state of the Port Status and Control Regsiter
856 * Return: a value that would result in the port being in the
857 * same state, if the value was written to the port
858 * status control register.
860 static u32 xhci_port_state_to_neutral(u32 state)
862 /* Save read-only status and port state */
863 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
867 * Submits the Requests to the XHCI Host Controller
869 * @param udev pointer to the USB device structure
870 * @param pipe contains the DIR_IN or OUT , devnum
871 * @param buffer buffer to be read/written based on the request
872 * Return: returns 0 if successful else -1 on failure
874 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
875 void *buffer, struct devrequest *req)
882 volatile uint32_t *status_reg;
883 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
884 struct xhci_hccr *hccr = ctrl->hccr;
885 struct xhci_hcor *hcor = ctrl->hcor;
886 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
888 if ((req->requesttype & USB_RT_PORT) &&
889 le16_to_cpu(req->index) > max_ports) {
890 printf("The request port(%d) exceeds maximum port number\n",
891 le16_to_cpu(req->index) - 1);
895 status_reg = (volatile uint32_t *)
896 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
899 typeReq = req->request | req->requesttype << 8;
902 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
903 switch (le16_to_cpu(req->value) >> 8) {
905 debug("USB_DT_DEVICE request\n");
906 srcptr = &descriptor.device;
910 debug("USB_DT_CONFIG config\n");
911 srcptr = &descriptor.config;
915 debug("USB_DT_STRING config\n");
916 switch (le16_to_cpu(req->value) & 0xff) {
917 case 0: /* Language */
918 srcptr = "\4\3\11\4";
921 case 1: /* Vendor String */
922 srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
925 case 2: /* Product Name */
926 srcptr = "\52\3X\0H\0C\0I\0 "
928 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
932 printf("unknown value DT_STRING %x\n",
933 le16_to_cpu(req->value));
938 printf("unknown value %x\n", le16_to_cpu(req->value));
942 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
943 switch (le16_to_cpu(req->value) >> 8) {
946 debug("USB_DT_HUB config\n");
947 srcptr = &ctrl->hub_desc;
951 printf("unknown value %x\n", le16_to_cpu(req->value));
955 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
956 debug("USB_REQ_SET_ADDRESS\n");
957 ctrl->rootdev = le16_to_cpu(req->value);
959 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
962 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
963 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
968 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
969 memset(tmpbuf, 0, 4);
970 reg = xhci_readl(status_reg);
971 if (reg & PORT_CONNECT) {
972 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
973 switch (reg & DEV_SPEED_MASK) {
975 debug("SPEED = FULLSPEED\n");
978 debug("SPEED = LOWSPEED\n");
979 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
982 debug("SPEED = HIGHSPEED\n");
983 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
986 debug("SPEED = SUPERSPEED\n");
987 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
992 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
993 if ((reg & PORT_PLS_MASK) == XDEV_U3)
994 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
996 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
997 if (reg & PORT_RESET)
998 tmpbuf[0] |= USB_PORT_STAT_RESET;
999 if (reg & PORT_POWER)
1001 * XXX: This Port power bit (for USB 3.0 hub)
1002 * we are faking in USB 2.0 hub port status;
1003 * since there's a change in bit positions in
1005 * USB 2.0 port status PP is at position[8]
1006 * USB 3.0 port status PP is at position[9]
1007 * So, we are still keeping it at position [8]
1009 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
1011 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
1013 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
1015 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
1017 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
1022 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1023 reg = xhci_readl(status_reg);
1024 reg = xhci_port_state_to_neutral(reg);
1025 switch (le16_to_cpu(req->value)) {
1026 case USB_PORT_FEAT_ENABLE:
1028 xhci_writel(status_reg, reg);
1030 case USB_PORT_FEAT_POWER:
1032 xhci_writel(status_reg, reg);
1034 case USB_PORT_FEAT_RESET:
1036 xhci_writel(status_reg, reg);
1039 printf("unknown feature %x\n", le16_to_cpu(req->value));
1043 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1044 reg = xhci_readl(status_reg);
1045 reg = xhci_port_state_to_neutral(reg);
1046 switch (le16_to_cpu(req->value)) {
1047 case USB_PORT_FEAT_ENABLE:
1050 case USB_PORT_FEAT_POWER:
1053 case USB_PORT_FEAT_C_RESET:
1054 case USB_PORT_FEAT_C_CONNECTION:
1055 case USB_PORT_FEAT_C_OVER_CURRENT:
1056 case USB_PORT_FEAT_C_ENABLE:
1057 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
1058 le16_to_cpu(req->index),
1062 printf("unknown feature %x\n", le16_to_cpu(req->value));
1065 xhci_writel(status_reg, reg);
1068 puts("Unknown request\n");
1072 debug("scrlen = %d\n req->length = %d\n",
1073 srclen, le16_to_cpu(req->length));
1075 len = min(srclen, (int)le16_to_cpu(req->length));
1077 if (srcptr != NULL && len > 0)
1078 memcpy(buffer, srcptr, len);
1080 debug("Len is 0\n");
1082 udev->act_len = len;
1089 udev->status = USB_ST_STALLED;
1095 * Submits the INT request to XHCI Host cotroller
1097 * @param udev pointer to the USB device
1098 * @param pipe contains the DIR_IN or OUT , devnum
1099 * @param buffer buffer to be read/written based on the request
1100 * @param length length of the buffer
1101 * @param interval interval of the interrupt
1104 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
1105 void *buffer, int length, int interval,
1108 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1109 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1114 * xHCI uses normal TRBs for both bulk and interrupt. When the
1115 * interrupt endpoint is to be serviced, the xHC will consume
1116 * (at most) one TD. A TD (comprised of sg list entries) can
1117 * take several service intervals to transmit.
1119 return xhci_bulk_tx(udev, pipe, length, buffer);
1123 * submit the BULK type of request to the USB Device
1125 * @param udev pointer to the USB device
1126 * @param pipe contains the DIR_IN or OUT , devnum
1127 * @param buffer buffer to be read/written based on the request
1128 * @param length length of the buffer
1129 * Return: returns 0 if successful else -1 on failure
1131 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
1132 void *buffer, int length)
1134 if (usb_pipetype(pipe) != PIPE_BULK) {
1135 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1139 return xhci_bulk_tx(udev, pipe, length, buffer);
1143 * submit the control type of request to the Root hub/Device based on the devnum
1145 * @param udev pointer to the USB device
1146 * @param pipe contains the DIR_IN or OUT , devnum
1147 * @param buffer buffer to be read/written based on the request
1148 * @param length length of the buffer
1149 * @param setup Request type
1150 * @param root_portnr Root port number that this device is on
1151 * Return: returns 0 if successful else -1 on failure
1153 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
1154 void *buffer, int length,
1155 struct devrequest *setup, int root_portnr)
1157 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
1160 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1161 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
1165 if (usb_pipedevice(pipe) == ctrl->rootdev)
1166 return xhci_submit_root(udev, pipe, buffer, setup);
1168 if (setup->request == USB_REQ_SET_ADDRESS &&
1169 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1170 return xhci_address_device(udev, root_portnr);
1172 if (setup->request == USB_REQ_SET_CONFIGURATION &&
1173 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1174 ret = xhci_set_configuration(udev);
1176 puts("Failed to configure xHCI endpoint\n");
1181 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
1184 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
1186 struct xhci_hccr *hccr;
1187 struct xhci_hcor *hcor;
1195 * Program the Number of Device Slots Enabled field in the CONFIG
1196 * register with the max value of slots the HC can handle.
1198 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
1199 val2 = xhci_readl(&hcor->or_config);
1200 val |= (val2 & ~HCS_SLOTS_MASK);
1201 xhci_writel(&hcor->or_config, val);
1203 /* initializing xhci data structures */
1204 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
1206 ctrl->hub_desc = descriptor.hub;
1208 reg = xhci_readl(&hccr->cr_hcsparams1);
1209 ctrl->hub_desc.bNbrPorts = HCS_MAX_PORTS(reg);
1210 printf("Register %x NbrPorts %d\n", reg, ctrl->hub_desc.bNbrPorts);
1212 /* Port Indicators */
1213 reg = xhci_readl(&hccr->cr_hccparams);
1214 if (HCS_INDICATOR(reg))
1215 put_unaligned(get_unaligned(&ctrl->hub_desc.wHubCharacteristics)
1216 | 0x80, &ctrl->hub_desc.wHubCharacteristics);
1218 /* Port Power Control */
1220 put_unaligned(get_unaligned(&ctrl->hub_desc.wHubCharacteristics)
1221 | 0x01, &ctrl->hub_desc.wHubCharacteristics);
1223 if (xhci_start(hcor)) {
1228 /* Zero'ing IRQ control register and IRQ pending register */
1229 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1230 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1232 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1233 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1234 ctrl->hci_version = reg;
1239 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
1243 xhci_reset(ctrl->hcor);
1245 debug("// Disabling event ring interrupts\n");
1246 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1247 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1248 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1249 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1254 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1255 unsigned long pipe, void *buffer, int length,
1256 struct devrequest *setup)
1258 struct usb_device *uhop;
1259 struct udevice *hub;
1260 int root_portnr = 0;
1262 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1263 dev->name, udev, udev->dev->name, udev->portnr);
1265 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
1266 /* Figure out our port number on the root hub */
1267 if (usb_hub_is_root_hub(hub)) {
1268 root_portnr = udev->portnr;
1270 while (!usb_hub_is_root_hub(hub->parent))
1272 uhop = dev_get_parent_priv(hub);
1273 root_portnr = uhop->portnr;
1277 struct usb_device *hop = udev;
1280 while (hop->parent->parent)
1283 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1287 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1288 unsigned long pipe, void *buffer, int length)
1290 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1291 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1294 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1295 unsigned long pipe, void *buffer, int length,
1296 int interval, bool nonblock)
1298 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1299 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
1303 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
1305 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1306 return _xhci_alloc_device(udev);
1309 static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
1311 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1312 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
1313 struct xhci_virt_device *virt_dev;
1314 struct xhci_input_control_ctx *ctrl_ctx;
1315 struct xhci_container_ctx *out_ctx;
1316 struct xhci_container_ctx *in_ctx;
1317 struct xhci_slot_ctx *slot_ctx;
1318 int slot_id = udev->slot_id;
1319 unsigned think_time;
1321 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1323 /* Ignore root hubs */
1324 if (usb_hub_is_root_hub(udev->dev))
1327 virt_dev = ctrl->devs[slot_id];
1330 out_ctx = virt_dev->out_ctx;
1331 in_ctx = virt_dev->in_ctx;
1333 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1334 /* Initialize the input context control */
1335 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1336 ctrl_ctx->drop_flags = 0;
1338 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
1341 xhci_slot_copy(ctrl, in_ctx, out_ctx);
1342 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
1344 /* Update hub related fields */
1345 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
1347 * refer to section 6.2.2: MTT should be 0 for full speed hub,
1348 * but it may be already set to 1 when setup an xHCI virtual
1349 * device, so clear it anyway.
1352 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1353 else if (udev->speed == USB_SPEED_FULL)
1354 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
1355 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
1357 * Set TT think time - convert from ns to FS bit times.
1358 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
1360 * 0 = 8 FS bit times, 1 = 16 FS bit times,
1361 * 2 = 24 FS bit times, 3 = 32 FS bit times.
1363 * This field shall be 0 if the device is not a high-spped hub.
1365 think_time = hub->tt.think_time;
1366 if (think_time != 0)
1367 think_time = (think_time / 666) - 1;
1368 if (udev->speed == USB_SPEED_HIGH)
1369 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
1370 slot_ctx->dev_state = 0;
1372 return xhci_configure_endpoints(udev, false);
1375 static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
1378 * xHCD allocates one segment which includes 64 TRBs for each endpoint
1379 * and the last TRB in this segment is configured as a link TRB to form
1380 * a TRB ring. Each TRB can transfer up to 64K bytes, however data
1381 * buffers referenced by transfer TRBs shall not span 64KB boundaries.
1382 * Hence the maximum number of TRBs we can use in one transfer is 62.
1384 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
1389 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
1390 struct xhci_hcor *hcor)
1392 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1393 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1396 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
1402 * XHCI needs to issue a Address device command to setup
1403 * proper device context structures, before it can interact
1404 * with the device. So a get_descriptor will fail before any
1405 * of that is done for XHCI unlike EHCI.
1407 priv->desc_before_addr = false;
1409 ret = xhci_reset(hcor);
1415 ret = xhci_lowlevel_init(ctrl);
1421 debug("%s: failed, ret=%d\n", __func__, ret);
1425 int xhci_deregister(struct udevice *dev)
1427 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1429 xhci_lowlevel_stop(ctrl);
1435 struct dm_usb_ops xhci_usb_ops = {
1436 .control = xhci_submit_control_msg,
1437 .bulk = xhci_submit_bulk_msg,
1438 .interrupt = xhci_submit_int_msg,
1439 .alloc_device = xhci_alloc_device,
1440 .update_hub_device = xhci_update_hub_device,
1441 .get_max_xfer_size = xhci_get_max_xfer_size,