1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
157 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
166 * This resets pipelines, timers, counters, state machines, etc.
167 * Transactions will be terminated immediately, and operational registers
168 * will be set to their defaults.
170 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
176 state = readl(&xhci->op_regs->status);
178 if (state == ~(u32)0) {
179 xhci_warn(xhci, "Host not accessible, reset failed.\n");
183 if ((state & STS_HALT) == 0) {
184 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
188 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
189 command = readl(&xhci->op_regs->command);
190 command |= CMD_RESET;
191 writel(command, &xhci->op_regs->command);
193 /* Existing Intel xHCI controllers require a delay of 1 mS,
194 * after setting the CMD_RESET bit, and before accessing any
195 * HC registers. This allows the HC to complete the
196 * reset operation and be ready for HC register access.
197 * Without this delay, the subsequent HC register access,
198 * may result in a system hang very rarely.
200 if (xhci->quirks & XHCI_INTEL_HOST)
203 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
207 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
208 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
210 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
211 "Wait for controller to be ready for doorbell rings");
213 * xHCI cannot write to any doorbells or operational registers other
214 * than status until the "Controller Not Ready" flag is cleared.
216 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
228 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
249 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
252 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
254 /* Clear HSEIE so that faults do not get signaled */
255 val = readl(&xhci->op_regs->command);
257 writel(val, &xhci->op_regs->command);
259 /* Clear HSE (aka FATAL) */
260 val = readl(&xhci->op_regs->status);
262 writel(val, &xhci->op_regs->status);
264 /* Now zero the registers, and brace for impact */
265 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
268 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
269 if (upper_32_bits(val))
270 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
272 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
273 ARRAY_SIZE(xhci->run_regs->ir_set));
275 for (i = 0; i < intrs; i++) {
276 struct xhci_intr_reg __iomem *ir;
278 ir = &xhci->run_regs->ir_set[i];
279 val = xhci_read_64(xhci, &ir->erst_base);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_base);
282 val= xhci_read_64(xhci, &ir->erst_dequeue);
283 if (upper_32_bits(val))
284 xhci_write_64(xhci, 0, &ir->erst_dequeue);
287 /* Wait for the fault to appear. It will be cleared on reset */
288 err = xhci_handshake(&xhci->op_regs->status,
289 STS_FATAL, STS_FATAL,
292 xhci_info(xhci, "Fault detected\n");
295 #ifdef CONFIG_USB_PCI
299 static int xhci_setup_msi(struct xhci_hcd *xhci)
303 * TODO:Check with MSI Soc for sysdev
305 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
307 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "failed to allocate MSI entry");
314 ret = request_irq(pdev->irq, xhci_msi_irq,
315 0, "xhci_hcd", xhci_to_hcd(xhci));
317 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
318 "disable MSI interrupt");
319 pci_free_irq_vectors(pdev);
328 static int xhci_setup_msix(struct xhci_hcd *xhci)
331 struct usb_hcd *hcd = xhci_to_hcd(xhci);
332 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
335 * calculate number of msi-x vectors supported.
336 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
337 * with max number of interrupters based on the xhci HCSPARAMS1.
338 * - num_online_cpus: maximum msi-x vectors per CPUs core.
339 * Add additional 1 vector to ensure always available interrupt.
341 xhci->msix_count = min(num_online_cpus() + 1,
342 HCS_MAX_INTRS(xhci->hcs_params1));
344 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
347 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
348 "Failed to enable MSI-X");
352 for (i = 0; i < xhci->msix_count; i++) {
353 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
354 "xhci_hcd", xhci_to_hcd(xhci));
359 hcd->msix_enabled = 1;
363 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
365 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
366 pci_free_irq_vectors(pdev);
370 /* Free any IRQs and disable MSI-X */
371 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
373 struct usb_hcd *hcd = xhci_to_hcd(xhci);
374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
376 if (xhci->quirks & XHCI_PLAT)
379 /* return if using legacy interrupt */
383 if (hcd->msix_enabled) {
386 for (i = 0; i < xhci->msix_count; i++)
387 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
389 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
392 pci_free_irq_vectors(pdev);
393 hcd->msix_enabled = 0;
396 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
398 struct usb_hcd *hcd = xhci_to_hcd(xhci);
400 if (hcd->msix_enabled) {
401 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
404 for (i = 0; i < xhci->msix_count; i++)
405 synchronize_irq(pci_irq_vector(pdev, i));
409 static int xhci_try_enable_msi(struct usb_hcd *hcd)
411 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
412 struct pci_dev *pdev;
415 /* The xhci platform device has set up IRQs through usb_add_hcd. */
416 if (xhci->quirks & XHCI_PLAT)
419 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
421 * Some Fresco Logic host controllers advertise MSI, but fail to
422 * generate interrupts. Don't even try to enable MSI.
424 if (xhci->quirks & XHCI_BROKEN_MSI)
427 /* unregister the legacy interrupt */
429 free_irq(hcd->irq, hcd);
432 ret = xhci_setup_msix(xhci);
434 /* fall back to msi*/
435 ret = xhci_setup_msi(xhci);
438 hcd->msi_enabled = 1;
443 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
448 if (!strlen(hcd->irq_descr))
449 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
450 hcd->driver->description, hcd->self.busnum);
452 /* fall back to legacy interrupt*/
453 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
454 hcd->irq_descr, hcd);
456 xhci_err(xhci, "request interrupt %d failed\n",
460 hcd->irq = pdev->irq;
466 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
471 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
475 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
481 static void compliance_mode_recovery(struct timer_list *t)
483 struct xhci_hcd *xhci;
485 struct xhci_hub *rhub;
489 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
490 rhub = &xhci->usb3_rhub;
496 for (i = 0; i < rhub->num_ports; i++) {
497 temp = readl(rhub->ports[i]->addr);
498 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
500 * Compliance Mode Detected. Letting USB Core
501 * handle the Warm Reset
503 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
504 "Compliance mode detected->port %d",
506 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
507 "Attempting compliance mode recovery");
509 if (hcd->state == HC_STATE_SUSPENDED)
510 usb_hcd_resume_root_hub(hcd);
512 usb_hcd_poll_rh_status(hcd);
516 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
517 mod_timer(&xhci->comp_mode_recovery_timer,
518 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
522 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
523 * that causes ports behind that hardware to enter compliance mode sometimes.
524 * The quirk creates a timer that polls every 2 seconds the link state of
525 * each host controller's port and recovers it by issuing a Warm reset
526 * if Compliance mode is detected, otherwise the port will become "dead" (no
527 * device connections or disconnections will be detected anymore). Becasue no
528 * status event is generated when entering compliance mode (per xhci spec),
529 * this quirk is needed on systems that have the failing hardware installed.
531 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
533 xhci->port_status_u0 = 0;
534 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
536 xhci->comp_mode_recovery_timer.expires = jiffies +
537 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
539 add_timer(&xhci->comp_mode_recovery_timer);
540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
541 "Compliance mode recovery timer initialized");
545 * This function identifies the systems that have installed the SN65LVPE502CP
546 * USB3.0 re-driver and that need the Compliance Mode Quirk.
548 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
550 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
552 const char *dmi_product_name, *dmi_sys_vendor;
554 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
555 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
556 if (!dmi_product_name || !dmi_sys_vendor)
559 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
562 if (strstr(dmi_product_name, "Z420") ||
563 strstr(dmi_product_name, "Z620") ||
564 strstr(dmi_product_name, "Z820") ||
565 strstr(dmi_product_name, "Z1 Workstation"))
571 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
573 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
578 * Initialize memory for HCD and xHC (one-time init).
580 * Program the PAGESIZE register, initialize the device context array, create
581 * device contexts (?), set up a command ring segment (or two?), create event
582 * ring (one for now).
584 static int xhci_init(struct usb_hcd *hcd)
586 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
590 spin_lock_init(&xhci->lock);
591 if (xhci->hci_version == 0x95 && link_quirk) {
592 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
593 "QUIRK: Not clearing Link TRB chain bits.");
594 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
596 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
597 "xHCI doesn't need link TRB QUIRK");
599 retval = xhci_mem_init(xhci, GFP_KERNEL);
600 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
602 /* Initializing Compliance Mode Recovery Data If Needed */
603 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
604 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
605 compliance_mode_recovery_timer_init(xhci);
611 /*-------------------------------------------------------------------------*/
614 static int xhci_run_finished(struct xhci_hcd *xhci)
620 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
621 * Protect the short window before host is running with a lock
623 spin_lock_irqsave(&xhci->lock, flags);
625 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
626 temp = readl(&xhci->op_regs->command);
628 writel(temp, &xhci->op_regs->command);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
631 temp = readl(&xhci->ir_set->irq_pending);
632 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
634 if (xhci_start(xhci)) {
636 spin_unlock_irqrestore(&xhci->lock, flags);
640 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
642 if (xhci->quirks & XHCI_NEC_HOST)
643 xhci_ring_cmd_db(xhci);
645 spin_unlock_irqrestore(&xhci->lock, flags);
651 * Start the HC after it was halted.
653 * This function is called by the USB core when the HC driver is added.
654 * Its opposite is xhci_stop().
656 * xhci_init() must be called once before this function can be called.
657 * Reset the HC, enable device slot contexts, program DCBAAP, and
658 * set command ring pointer and event ring pointer.
660 * Setup MSI-X vectors and enable interrupts.
662 int xhci_run(struct usb_hcd *hcd)
667 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
669 /* Start the xHCI host controller running only after the USB 2.0 roothub
673 hcd->uses_new_polling = 1;
674 if (!usb_hcd_is_primary_hcd(hcd))
675 return xhci_run_finished(xhci);
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
679 ret = xhci_try_enable_msi(hcd);
683 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
684 temp_64 &= ~ERST_PTR_MASK;
685 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
686 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
688 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
689 "// Set the interrupt modulation register");
690 temp = readl(&xhci->ir_set->irq_control);
691 temp &= ~ER_IRQ_INTERVAL_MASK;
692 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
693 writel(temp, &xhci->ir_set->irq_control);
695 if (xhci->quirks & XHCI_NEC_HOST) {
696 struct xhci_command *command;
698 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
702 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
703 TRB_TYPE(TRB_NEC_GET_FW));
705 xhci_free_command(xhci, command);
707 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
708 "Finished %s for main hcd", __func__);
710 xhci_create_dbc_dev(xhci);
712 xhci_debugfs_init(xhci);
714 if (xhci_has_one_roothub(xhci))
715 return xhci_run_finished(xhci);
717 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
721 EXPORT_SYMBOL_GPL(xhci_run);
726 * This function is called by the USB core when the HC driver is removed.
727 * Its opposite is xhci_run().
729 * Disable device contexts, disable IRQs, and quiesce the HC.
730 * Reset the HC, finish any completed transactions, and cleanup memory.
732 static void xhci_stop(struct usb_hcd *hcd)
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
737 mutex_lock(&xhci->mutex);
739 /* Only halt host and free memory after both hcds are removed */
740 if (!usb_hcd_is_primary_hcd(hcd)) {
741 mutex_unlock(&xhci->mutex);
745 xhci_remove_dbc_dev(xhci);
747 spin_lock_irq(&xhci->lock);
748 xhci->xhc_state |= XHCI_STATE_HALTED;
749 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
751 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
752 spin_unlock_irq(&xhci->lock);
754 xhci_cleanup_msix(xhci);
756 /* Deleting Compliance Mode Recovery Timer */
757 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
758 (!(xhci_all_ports_seen_u0(xhci)))) {
759 del_timer_sync(&xhci->comp_mode_recovery_timer);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
761 "%s: compliance mode recovery timer deleted",
765 if (xhci->quirks & XHCI_AMD_PLL_FIX)
768 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
769 "// Disabling event ring interrupts");
770 temp = readl(&xhci->op_regs->status);
771 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
772 temp = readl(&xhci->ir_set->irq_pending);
773 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
775 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
776 xhci_mem_cleanup(xhci);
777 xhci_debugfs_exit(xhci);
778 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
779 "xhci_stop completed - status = %x",
780 readl(&xhci->op_regs->status));
781 mutex_unlock(&xhci->mutex);
785 * Shutdown HC (not bus-specific)
787 * This is called when the machine is rebooting or halting. We assume that the
788 * machine will be powered off, and the HC's internal state will be reset.
789 * Don't bother to free memory.
791 * This will only ever be called with the main usb_hcd (the USB3 roothub).
793 void xhci_shutdown(struct usb_hcd *hcd)
795 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
797 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
798 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
800 /* Don't poll the roothubs after shutdown. */
801 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
802 __func__, hcd->self.busnum);
803 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
804 del_timer_sync(&hcd->rh_timer);
806 if (xhci->shared_hcd) {
807 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
808 del_timer_sync(&xhci->shared_hcd->rh_timer);
811 spin_lock_irq(&xhci->lock);
813 /* Workaround for spurious wakeups at shutdown with HSW */
814 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
815 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
816 spin_unlock_irq(&xhci->lock);
818 xhci_cleanup_msix(xhci);
820 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
821 "xhci_shutdown completed - status = %x",
822 readl(&xhci->op_regs->status));
824 EXPORT_SYMBOL_GPL(xhci_shutdown);
827 static void xhci_save_registers(struct xhci_hcd *xhci)
829 xhci->s3.command = readl(&xhci->op_regs->command);
830 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
831 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
832 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
833 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
834 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
835 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
836 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
837 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
840 static void xhci_restore_registers(struct xhci_hcd *xhci)
842 writel(xhci->s3.command, &xhci->op_regs->command);
843 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
844 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
845 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
846 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
847 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
848 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
849 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
850 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
853 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
857 /* step 2: initialize command ring buffer */
858 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
859 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
860 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
861 xhci->cmd_ring->dequeue) &
862 (u64) ~CMD_RING_RSVD_BITS) |
863 xhci->cmd_ring->cycle_state;
864 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
865 "// Setting command ring address to 0x%llx",
866 (long unsigned long) val_64);
867 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
871 * The whole command ring must be cleared to zero when we suspend the host.
873 * The host doesn't save the command ring pointer in the suspend well, so we
874 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
875 * aligned, because of the reserved bits in the command ring dequeue pointer
876 * register. Therefore, we can't just set the dequeue pointer back in the
877 * middle of the ring (TRBs are 16-byte aligned).
879 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
881 struct xhci_ring *ring;
882 struct xhci_segment *seg;
884 ring = xhci->cmd_ring;
888 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
889 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
890 cpu_to_le32(~TRB_CYCLE);
892 } while (seg != ring->deq_seg);
894 /* Reset the software enqueue and dequeue pointers */
895 ring->deq_seg = ring->first_seg;
896 ring->dequeue = ring->first_seg->trbs;
897 ring->enq_seg = ring->deq_seg;
898 ring->enqueue = ring->dequeue;
900 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
902 * Ring is now zeroed, so the HW should look for change of ownership
903 * when the cycle bit is set to 1.
905 ring->cycle_state = 1;
908 * Reset the hardware dequeue pointer.
909 * Yes, this will need to be re-written after resume, but we're paranoid
910 * and want to make sure the hardware doesn't access bogus memory
911 * because, say, the BIOS or an SMI started the host without changing
912 * the command ring pointers.
914 xhci_set_cmd_ring_deq(xhci);
918 * Disable port wake bits if do_wakeup is not set.
920 * Also clear a possible internal port wake state left hanging for ports that
921 * detected termination but never successfully enumerated (trained to 0U).
922 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
923 * at enumeration clears this wake, force one here as well for unconnected ports
926 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
927 struct xhci_hub *rhub,
934 spin_lock_irqsave(&xhci->lock, flags);
936 for (i = 0; i < rhub->num_ports; i++) {
937 portsc = readl(rhub->ports[i]->addr);
938 t1 = xhci_port_state_to_neutral(portsc);
941 /* clear wake bits if do_wake is not set */
943 t2 &= ~PORT_WAKE_BITS;
945 /* Don't touch csc bit if connected or connect change is set */
946 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
950 writel(t2, rhub->ports[i]->addr);
951 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
952 rhub->hcd->self.busnum, i + 1, portsc, t2);
955 spin_unlock_irqrestore(&xhci->lock, flags);
958 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
960 struct xhci_port **ports;
965 status = readl(&xhci->op_regs->status);
966 if (status & STS_EINT)
969 * Checking STS_EINT is not enough as there is a lag between a change
970 * bit being set and the Port Status Change Event that it generated
971 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
974 port_index = xhci->usb2_rhub.num_ports;
975 ports = xhci->usb2_rhub.ports;
976 while (port_index--) {
977 portsc = readl(ports[port_index]->addr);
978 if (portsc & PORT_CHANGE_MASK ||
979 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
982 port_index = xhci->usb3_rhub.num_ports;
983 ports = xhci->usb3_rhub.ports;
984 while (port_index--) {
985 portsc = readl(ports[port_index]->addr);
986 if (portsc & PORT_CHANGE_MASK ||
987 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
994 * Stop HC (not bus-specific)
996 * This is called when the machine transition into S3/S4 mode.
999 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1002 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1003 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1010 if (hcd->state != HC_STATE_SUSPENDED ||
1011 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1014 /* Clear root port wake on bits if wakeup not allowed. */
1015 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1016 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1018 if (!HCD_HW_ACCESSIBLE(hcd))
1021 xhci_dbc_suspend(xhci);
1023 /* Don't poll the roothubs on bus suspend. */
1024 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1025 __func__, hcd->self.busnum);
1026 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1027 del_timer_sync(&hcd->rh_timer);
1028 if (xhci->shared_hcd) {
1029 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1030 del_timer_sync(&xhci->shared_hcd->rh_timer);
1033 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1034 usleep_range(1000, 1500);
1036 spin_lock_irq(&xhci->lock);
1037 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1038 if (xhci->shared_hcd)
1039 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1040 /* step 1: stop endpoint */
1041 /* skipped assuming that port suspend has done */
1043 /* step 2: clear Run/Stop bit */
1044 command = readl(&xhci->op_regs->command);
1045 command &= ~CMD_RUN;
1046 writel(command, &xhci->op_regs->command);
1048 /* Some chips from Fresco Logic need an extraordinary delay */
1049 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1051 if (xhci_handshake(&xhci->op_regs->status,
1052 STS_HALT, STS_HALT, delay)) {
1053 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1054 spin_unlock_irq(&xhci->lock);
1057 xhci_clear_command_ring(xhci);
1059 /* step 3: save registers */
1060 xhci_save_registers(xhci);
1062 /* step 4: set CSS flag */
1063 command = readl(&xhci->op_regs->command);
1065 writel(command, &xhci->op_regs->command);
1066 xhci->broken_suspend = 0;
1067 if (xhci_handshake(&xhci->op_regs->status,
1068 STS_SAVE, 0, 20 * 1000)) {
1070 * AMD SNPS xHC 3.0 occasionally does not clear the
1071 * SSS bit of USBSTS and when driver tries to poll
1072 * to see if the xHC clears BIT(8) which never happens
1073 * and driver assumes that controller is not responding
1074 * and times out. To workaround this, its good to check
1075 * if SRE and HCE bits are not set (as per xhci
1076 * Section 5.4.2) and bypass the timeout.
1078 res = readl(&xhci->op_regs->status);
1079 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1080 (((res & STS_SRE) == 0) &&
1081 ((res & STS_HCE) == 0))) {
1082 xhci->broken_suspend = 1;
1084 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1085 spin_unlock_irq(&xhci->lock);
1089 spin_unlock_irq(&xhci->lock);
1092 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1093 * is about to be suspended.
1095 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1096 (!(xhci_all_ports_seen_u0(xhci)))) {
1097 del_timer_sync(&xhci->comp_mode_recovery_timer);
1098 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1099 "%s: compliance mode recovery timer deleted",
1103 /* step 5: remove core well power */
1104 /* synchronize irq when using MSI-X */
1105 xhci_msix_sync_irqs(xhci);
1109 EXPORT_SYMBOL_GPL(xhci_suspend);
1112 * start xHC (not bus-specific)
1114 * This is called when the machine transition from S3/S4 mode.
1117 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1119 u32 command, temp = 0;
1120 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1122 bool comp_timer_running = false;
1123 bool pending_portevent = false;
1124 bool reinit_xhc = false;
1129 /* Wait a bit if either of the roothubs need to settle from the
1130 * transition into bus suspend.
1133 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1134 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1137 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1138 if (xhci->shared_hcd)
1139 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1141 spin_lock_irq(&xhci->lock);
1143 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1148 * Some controllers might lose power during suspend, so wait
1149 * for controller not ready bit to clear, just as in xHC init.
1151 retval = xhci_handshake(&xhci->op_regs->status,
1152 STS_CNR, 0, 10 * 1000 * 1000);
1154 xhci_warn(xhci, "Controller not ready at resume %d\n",
1156 spin_unlock_irq(&xhci->lock);
1159 /* step 1: restore register */
1160 xhci_restore_registers(xhci);
1161 /* step 2: initialize command ring buffer */
1162 xhci_set_cmd_ring_deq(xhci);
1163 /* step 3: restore state and start state*/
1164 /* step 3: set CRS flag */
1165 command = readl(&xhci->op_regs->command);
1167 writel(command, &xhci->op_regs->command);
1169 * Some controllers take up to 55+ ms to complete the controller
1170 * restore so setting the timeout to 100ms. Xhci specification
1171 * doesn't mention any timeout value.
1173 if (xhci_handshake(&xhci->op_regs->status,
1174 STS_RESTORE, 0, 100 * 1000)) {
1175 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1176 spin_unlock_irq(&xhci->lock);
1181 temp = readl(&xhci->op_regs->status);
1183 /* re-initialize the HC on Restore Error, or Host Controller Error */
1184 if (temp & (STS_SRE | STS_HCE)) {
1186 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1190 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1191 !(xhci_all_ports_seen_u0(xhci))) {
1192 del_timer_sync(&xhci->comp_mode_recovery_timer);
1193 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1194 "Compliance Mode Recovery Timer deleted!");
1197 /* Let the USB core know _both_ roothubs lost power. */
1198 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1199 if (xhci->shared_hcd)
1200 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1202 xhci_dbg(xhci, "Stop HCD\n");
1204 xhci_zero_64b_regs(xhci);
1205 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1206 spin_unlock_irq(&xhci->lock);
1209 xhci_cleanup_msix(xhci);
1211 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1212 temp = readl(&xhci->op_regs->status);
1213 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1214 temp = readl(&xhci->ir_set->irq_pending);
1215 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1217 xhci_dbg(xhci, "cleaning up memory\n");
1218 xhci_mem_cleanup(xhci);
1219 xhci_debugfs_exit(xhci);
1220 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1221 readl(&xhci->op_regs->status));
1223 /* USB core calls the PCI reinit and start functions twice:
1224 * first with the primary HCD, and then with the secondary HCD.
1225 * If we don't do the same, the host will never be started.
1227 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1228 retval = xhci_init(hcd);
1231 comp_timer_running = true;
1233 xhci_dbg(xhci, "Start the primary HCD\n");
1234 retval = xhci_run(hcd);
1235 if (!retval && xhci->shared_hcd) {
1236 xhci_dbg(xhci, "Start the secondary HCD\n");
1237 retval = xhci_run(xhci->shared_hcd);
1240 hcd->state = HC_STATE_SUSPENDED;
1241 if (xhci->shared_hcd)
1242 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1246 /* step 4: set Run/Stop bit */
1247 command = readl(&xhci->op_regs->command);
1249 writel(command, &xhci->op_regs->command);
1250 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1253 /* step 5: walk topology and initialize portsc,
1254 * portpmsc and portli
1256 /* this is done in bus_resume */
1258 /* step 6: restart each of the previously
1259 * Running endpoints by ringing their doorbells
1262 spin_unlock_irq(&xhci->lock);
1264 xhci_dbc_resume(xhci);
1269 * Resume roothubs only if there are pending events.
1270 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1271 * the first wake signalling failed, give it that chance.
1273 pending_portevent = xhci_pending_portevent(xhci);
1274 if (!pending_portevent) {
1276 pending_portevent = xhci_pending_portevent(xhci);
1279 if (pending_portevent) {
1280 if (xhci->shared_hcd)
1281 usb_hcd_resume_root_hub(xhci->shared_hcd);
1282 usb_hcd_resume_root_hub(hcd);
1286 * If system is subject to the Quirk, Compliance Mode Timer needs to
1287 * be re-initialized Always after a system resume. Ports are subject
1288 * to suffer the Compliance Mode issue again. It doesn't matter if
1289 * ports have entered previously to U0 before system's suspension.
1291 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1292 compliance_mode_recovery_timer_init(xhci);
1294 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1295 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1297 /* Re-enable port polling. */
1298 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1299 __func__, hcd->self.busnum);
1300 if (xhci->shared_hcd) {
1301 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1302 usb_hcd_poll_rh_status(xhci->shared_hcd);
1304 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1305 usb_hcd_poll_rh_status(hcd);
1309 EXPORT_SYMBOL_GPL(xhci_resume);
1310 #endif /* CONFIG_PM */
1312 /*-------------------------------------------------------------------------*/
1314 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1318 unsigned int buf_len;
1319 enum dma_data_direction dir;
1321 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1322 buf_len = urb->transfer_buffer_length;
1324 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1325 dev_to_node(hcd->self.sysdev));
1327 if (usb_urb_dir_out(urb))
1328 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1331 urb->transfer_buffer = temp;
1332 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1333 urb->transfer_buffer,
1334 urb->transfer_buffer_length,
1337 if (dma_mapping_error(hcd->self.sysdev,
1338 urb->transfer_dma)) {
1342 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1348 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1353 unsigned int len = 0;
1354 unsigned int trb_size;
1355 unsigned int max_pkt;
1356 struct scatterlist *sg;
1357 struct scatterlist *tail_sg;
1360 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1365 if (urb->dev->speed >= USB_SPEED_SUPER)
1366 trb_size = TRB_CACHE_SIZE_SS;
1368 trb_size = TRB_CACHE_SIZE_HS;
1370 if (urb->transfer_buffer_length != 0 &&
1371 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1372 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1373 len = len + sg->length;
1374 if (i > trb_size - 2) {
1375 len = len - tail_sg->length;
1376 if (len < max_pkt) {
1381 tail_sg = sg_next(tail_sg);
1388 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1391 unsigned int buf_len;
1392 enum dma_data_direction dir;
1394 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1396 buf_len = urb->transfer_buffer_length;
1398 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1399 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1400 dma_unmap_single(hcd->self.sysdev,
1402 urb->transfer_buffer_length,
1405 if (usb_urb_dir_in(urb)) {
1406 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1407 urb->transfer_buffer,
1410 if (len != buf_len) {
1411 xhci_dbg(hcd_to_xhci(hcd),
1412 "Copy from tmp buf to urb sg list failed\n");
1413 urb->actual_length = len;
1416 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1417 kfree(urb->transfer_buffer);
1418 urb->transfer_buffer = NULL;
1422 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1423 * we'll copy the actual data into the TRB address register. This is limited to
1424 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1425 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1427 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1430 struct xhci_hcd *xhci;
1432 xhci = hcd_to_xhci(hcd);
1434 if (xhci_urb_suitable_for_idt(urb))
1437 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1438 if (xhci_urb_temp_buffer_required(hcd, urb))
1439 return xhci_map_temp_buffer(hcd, urb);
1441 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1444 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1446 struct xhci_hcd *xhci;
1447 bool unmap_temp_buf = false;
1449 xhci = hcd_to_xhci(hcd);
1451 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1452 unmap_temp_buf = true;
1454 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1455 xhci_unmap_temp_buf(hcd, urb);
1457 usb_hcd_unmap_urb_for_dma(hcd, urb);
1461 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1462 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1463 * value to right shift 1 for the bitmask.
1465 * Index = (epnum * 2) + direction - 1,
1466 * where direction = 0 for OUT, 1 for IN.
1467 * For control endpoints, the IN index is used (OUT index is unused), so
1468 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1470 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1473 if (usb_endpoint_xfer_control(desc))
1474 index = (unsigned int) (usb_endpoint_num(desc)*2);
1476 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1477 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1480 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1482 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1483 * address from the XHCI endpoint index.
1485 static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1487 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1488 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1489 return direction | number;
1492 /* Find the flag for this endpoint (for use in the control context). Use the
1493 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1496 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1498 return 1 << (xhci_get_endpoint_index(desc) + 1);
1501 /* Compute the last valid endpoint context index. Basically, this is the
1502 * endpoint index plus one. For slot contexts with more than valid endpoint,
1503 * we find the most significant bit set in the added contexts flags.
1504 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1505 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1507 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1509 return fls(added_ctxs) - 1;
1512 /* Returns 1 if the arguments are OK;
1513 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1515 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1516 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1518 struct xhci_hcd *xhci;
1519 struct xhci_virt_device *virt_dev;
1521 if (!hcd || (check_ep && !ep) || !udev) {
1522 pr_debug("xHCI %s called with invalid args\n", func);
1525 if (!udev->parent) {
1526 pr_debug("xHCI %s called for root hub\n", func);
1530 xhci = hcd_to_xhci(hcd);
1531 if (check_virt_dev) {
1532 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1533 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1538 virt_dev = xhci->devs[udev->slot_id];
1539 if (virt_dev->udev != udev) {
1540 xhci_dbg(xhci, "xHCI %s called with udev and "
1541 "virt_dev does not match\n", func);
1546 if (xhci->xhc_state & XHCI_STATE_HALTED)
1552 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1553 struct usb_device *udev, struct xhci_command *command,
1554 bool ctx_change, bool must_succeed);
1557 * Full speed devices may have a max packet size greater than 8 bytes, but the
1558 * USB core doesn't know that until it reads the first 8 bytes of the
1559 * descriptor. If the usb_device's max packet size changes after that point,
1560 * we need to issue an evaluate context command and wait on it.
1562 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1563 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1565 struct xhci_container_ctx *out_ctx;
1566 struct xhci_input_control_ctx *ctrl_ctx;
1567 struct xhci_ep_ctx *ep_ctx;
1568 struct xhci_command *command;
1569 int max_packet_size;
1570 int hw_max_packet_size;
1573 out_ctx = xhci->devs[slot_id]->out_ctx;
1574 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1575 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1576 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1577 if (hw_max_packet_size != max_packet_size) {
1578 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1579 "Max Packet Size for ep 0 changed.");
1580 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1581 "Max packet size in usb_device = %d",
1583 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1584 "Max packet size in xHCI HW = %d",
1585 hw_max_packet_size);
1586 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1587 "Issuing evaluate context command.");
1589 /* Set up the input context flags for the command */
1590 /* FIXME: This won't work if a non-default control endpoint
1591 * changes max packet sizes.
1594 command = xhci_alloc_command(xhci, true, mem_flags);
1598 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1599 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1601 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1604 goto command_cleanup;
1606 /* Set up the modified control endpoint 0 */
1607 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1608 xhci->devs[slot_id]->out_ctx, ep_index);
1610 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1611 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1612 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1613 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1615 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1616 ctrl_ctx->drop_flags = 0;
1618 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1621 /* Clean up the input context for later use by bandwidth
1624 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1626 kfree(command->completion);
1633 * non-error returns are a promise to giveback() the urb later
1634 * we drop ownership so next owner (or urb unlink) can get it
1636 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1638 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1639 unsigned long flags;
1641 unsigned int slot_id, ep_index;
1642 unsigned int *ep_state;
1643 struct urb_priv *urb_priv;
1648 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1649 true, true, __func__);
1651 return ret ? ret : -EINVAL;
1653 slot_id = urb->dev->slot_id;
1654 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1655 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1657 if (!HCD_HW_ACCESSIBLE(hcd))
1660 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1661 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1665 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1666 num_tds = urb->number_of_packets;
1667 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1668 urb->transfer_buffer_length > 0 &&
1669 urb->transfer_flags & URB_ZERO_PACKET &&
1670 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1675 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1679 urb_priv->num_tds = num_tds;
1680 urb_priv->num_tds_done = 0;
1681 urb->hcpriv = urb_priv;
1683 trace_xhci_urb_enqueue(urb);
1685 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1686 /* Check to see if the max packet size for the default control
1687 * endpoint changed during FS device enumeration
1689 if (urb->dev->speed == USB_SPEED_FULL) {
1690 ret = xhci_check_maxpacket(xhci, slot_id,
1691 ep_index, urb, mem_flags);
1693 xhci_urb_free_priv(urb_priv);
1700 spin_lock_irqsave(&xhci->lock, flags);
1702 if (xhci->xhc_state & XHCI_STATE_DYING) {
1703 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1704 urb->ep->desc.bEndpointAddress, urb);
1708 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1709 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1714 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1715 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1720 switch (usb_endpoint_type(&urb->ep->desc)) {
1722 case USB_ENDPOINT_XFER_CONTROL:
1723 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1726 case USB_ENDPOINT_XFER_BULK:
1727 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1730 case USB_ENDPOINT_XFER_INT:
1731 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1734 case USB_ENDPOINT_XFER_ISOC:
1735 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1741 xhci_urb_free_priv(urb_priv);
1744 spin_unlock_irqrestore(&xhci->lock, flags);
1749 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1750 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1751 * should pick up where it left off in the TD, unless a Set Transfer Ring
1752 * Dequeue Pointer is issued.
1754 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1755 * the ring. Since the ring is a contiguous structure, they can't be physically
1756 * removed. Instead, there are two options:
1758 * 1) If the HC is in the middle of processing the URB to be canceled, we
1759 * simply move the ring's dequeue pointer past those TRBs using the Set
1760 * Transfer Ring Dequeue Pointer command. This will be the common case,
1761 * when drivers timeout on the last submitted URB and attempt to cancel.
1763 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1764 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1765 * HC will need to invalidate the any TRBs it has cached after the stop
1766 * endpoint command, as noted in the xHCI 0.95 errata.
1768 * 3) The TD may have completed by the time the Stop Endpoint Command
1769 * completes, so software needs to handle that case too.
1771 * This function should protect against the TD enqueueing code ringing the
1772 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1773 * It also needs to account for multiple cancellations on happening at the same
1774 * time for the same endpoint.
1776 * Note that this function can be called in any context, or so says
1777 * usb_hcd_unlink_urb()
1779 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1781 unsigned long flags;
1784 struct xhci_hcd *xhci;
1785 struct urb_priv *urb_priv;
1787 unsigned int ep_index;
1788 struct xhci_ring *ep_ring;
1789 struct xhci_virt_ep *ep;
1790 struct xhci_command *command;
1791 struct xhci_virt_device *vdev;
1793 xhci = hcd_to_xhci(hcd);
1794 spin_lock_irqsave(&xhci->lock, flags);
1796 trace_xhci_urb_dequeue(urb);
1798 /* Make sure the URB hasn't completed or been unlinked already */
1799 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1803 /* give back URB now if we can't queue it for cancel */
1804 vdev = xhci->devs[urb->dev->slot_id];
1805 urb_priv = urb->hcpriv;
1806 if (!vdev || !urb_priv)
1809 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1810 ep = &vdev->eps[ep_index];
1811 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1812 if (!ep || !ep_ring)
1815 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1816 temp = readl(&xhci->op_regs->status);
1817 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1823 * check ring is not re-allocated since URB was enqueued. If it is, then
1824 * make sure none of the ring related pointers in this URB private data
1825 * are touched, such as td_list, otherwise we overwrite freed data
1827 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1828 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1829 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1830 td = &urb_priv->td[i];
1831 if (!list_empty(&td->cancelled_td_list))
1832 list_del_init(&td->cancelled_td_list);
1837 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1838 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1839 "HC halted, freeing TD manually.");
1840 for (i = urb_priv->num_tds_done;
1841 i < urb_priv->num_tds;
1843 td = &urb_priv->td[i];
1844 if (!list_empty(&td->td_list))
1845 list_del_init(&td->td_list);
1846 if (!list_empty(&td->cancelled_td_list))
1847 list_del_init(&td->cancelled_td_list);
1852 i = urb_priv->num_tds_done;
1853 if (i < urb_priv->num_tds)
1854 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1855 "Cancel URB %p, dev %s, ep 0x%x, "
1856 "starting at offset 0x%llx",
1857 urb, urb->dev->devpath,
1858 urb->ep->desc.bEndpointAddress,
1859 (unsigned long long) xhci_trb_virt_to_dma(
1860 urb_priv->td[i].start_seg,
1861 urb_priv->td[i].first_trb));
1863 for (; i < urb_priv->num_tds; i++) {
1864 td = &urb_priv->td[i];
1865 /* TD can already be on cancelled list if ep halted on it */
1866 if (list_empty(&td->cancelled_td_list)) {
1867 td->cancel_status = TD_DIRTY;
1868 list_add_tail(&td->cancelled_td_list,
1869 &ep->cancelled_td_list);
1873 /* Queue a stop endpoint command, but only if this is
1874 * the first cancellation to be handled.
1876 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1877 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1882 ep->ep_state |= EP_STOP_CMD_PENDING;
1883 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1885 xhci_ring_cmd_db(xhci);
1888 spin_unlock_irqrestore(&xhci->lock, flags);
1893 xhci_urb_free_priv(urb_priv);
1894 usb_hcd_unlink_urb_from_ep(hcd, urb);
1895 spin_unlock_irqrestore(&xhci->lock, flags);
1896 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1900 /* Drop an endpoint from a new bandwidth configuration for this device.
1901 * Only one call to this function is allowed per endpoint before
1902 * check_bandwidth() or reset_bandwidth() must be called.
1903 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1904 * add the endpoint to the schedule with possibly new parameters denoted by a
1905 * different endpoint descriptor in usb_host_endpoint.
1906 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1909 * The USB core will not allow URBs to be queued to an endpoint that is being
1910 * disabled, so there's no need for mutual exclusion to protect
1911 * the xhci->devs[slot_id] structure.
1913 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1914 struct usb_host_endpoint *ep)
1916 struct xhci_hcd *xhci;
1917 struct xhci_container_ctx *in_ctx, *out_ctx;
1918 struct xhci_input_control_ctx *ctrl_ctx;
1919 unsigned int ep_index;
1920 struct xhci_ep_ctx *ep_ctx;
1922 u32 new_add_flags, new_drop_flags;
1925 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1928 xhci = hcd_to_xhci(hcd);
1929 if (xhci->xhc_state & XHCI_STATE_DYING)
1932 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1933 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1934 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1935 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1936 __func__, drop_flag);
1940 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1941 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1942 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1944 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1949 ep_index = xhci_get_endpoint_index(&ep->desc);
1950 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1951 /* If the HC already knows the endpoint is disabled,
1952 * or the HCD has noted it is disabled, ignore this request
1954 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1955 le32_to_cpu(ctrl_ctx->drop_flags) &
1956 xhci_get_endpoint_flag(&ep->desc)) {
1957 /* Do not warn when called after a usb_device_reset */
1958 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1959 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1964 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1965 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1967 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1968 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1970 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1972 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1974 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1975 (unsigned int) ep->desc.bEndpointAddress,
1977 (unsigned int) new_drop_flags,
1978 (unsigned int) new_add_flags);
1981 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1983 /* Add an endpoint to a new possible bandwidth configuration for this device.
1984 * Only one call to this function is allowed per endpoint before
1985 * check_bandwidth() or reset_bandwidth() must be called.
1986 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1987 * add the endpoint to the schedule with possibly new parameters denoted by a
1988 * different endpoint descriptor in usb_host_endpoint.
1989 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1992 * The USB core will not allow URBs to be queued to an endpoint until the
1993 * configuration or alt setting is installed in the device, so there's no need
1994 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1996 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1997 struct usb_host_endpoint *ep)
1999 struct xhci_hcd *xhci;
2000 struct xhci_container_ctx *in_ctx;
2001 unsigned int ep_index;
2002 struct xhci_input_control_ctx *ctrl_ctx;
2003 struct xhci_ep_ctx *ep_ctx;
2005 u32 new_add_flags, new_drop_flags;
2006 struct xhci_virt_device *virt_dev;
2009 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2011 /* So we won't queue a reset ep command for a root hub */
2015 xhci = hcd_to_xhci(hcd);
2016 if (xhci->xhc_state & XHCI_STATE_DYING)
2019 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2020 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2021 /* FIXME when we have to issue an evaluate endpoint command to
2022 * deal with ep0 max packet size changing once we get the
2025 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2026 __func__, added_ctxs);
2030 virt_dev = xhci->devs[udev->slot_id];
2031 in_ctx = virt_dev->in_ctx;
2032 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2034 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2039 ep_index = xhci_get_endpoint_index(&ep->desc);
2040 /* If this endpoint is already in use, and the upper layers are trying
2041 * to add it again without dropping it, reject the addition.
2043 if (virt_dev->eps[ep_index].ring &&
2044 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2045 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2046 "without dropping it.\n",
2047 (unsigned int) ep->desc.bEndpointAddress);
2051 /* If the HCD has already noted the endpoint is enabled,
2052 * ignore this request.
2054 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2055 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2061 * Configuration and alternate setting changes must be done in
2062 * process context, not interrupt context (or so documenation
2063 * for usb_set_interface() and usb_set_configuration() claim).
2065 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2066 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2067 __func__, ep->desc.bEndpointAddress);
2071 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2072 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2074 /* If xhci_endpoint_disable() was called for this endpoint, but the
2075 * xHC hasn't been notified yet through the check_bandwidth() call,
2076 * this re-adds a new state for the endpoint from the new endpoint
2077 * descriptors. We must drop and re-add this endpoint, so we leave the
2080 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2082 /* Store the usb_device pointer for later use */
2085 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2086 trace_xhci_add_endpoint(ep_ctx);
2088 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2089 (unsigned int) ep->desc.bEndpointAddress,
2091 (unsigned int) new_drop_flags,
2092 (unsigned int) new_add_flags);
2095 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2097 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2099 struct xhci_input_control_ctx *ctrl_ctx;
2100 struct xhci_ep_ctx *ep_ctx;
2101 struct xhci_slot_ctx *slot_ctx;
2104 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2106 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2111 /* When a device's add flag and drop flag are zero, any subsequent
2112 * configure endpoint command will leave that endpoint's state
2113 * untouched. Make sure we don't leave any old state in the input
2114 * endpoint contexts.
2116 ctrl_ctx->drop_flags = 0;
2117 ctrl_ctx->add_flags = 0;
2118 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2119 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2120 /* Endpoint 0 is always valid */
2121 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2122 for (i = 1; i < 31; i++) {
2123 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2124 ep_ctx->ep_info = 0;
2125 ep_ctx->ep_info2 = 0;
2127 ep_ctx->tx_info = 0;
2131 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2132 struct usb_device *udev, u32 *cmd_status)
2136 switch (*cmd_status) {
2137 case COMP_COMMAND_ABORTED:
2138 case COMP_COMMAND_RING_STOPPED:
2139 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2142 case COMP_RESOURCE_ERROR:
2143 dev_warn(&udev->dev,
2144 "Not enough host controller resources for new device state.\n");
2146 /* FIXME: can we allocate more resources for the HC? */
2148 case COMP_BANDWIDTH_ERROR:
2149 case COMP_SECONDARY_BANDWIDTH_ERROR:
2150 dev_warn(&udev->dev,
2151 "Not enough bandwidth for new device state.\n");
2153 /* FIXME: can we go back to the old state? */
2155 case COMP_TRB_ERROR:
2156 /* the HCD set up something wrong */
2157 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2159 "and endpoint is not disabled.\n");
2162 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2163 dev_warn(&udev->dev,
2164 "ERROR: Incompatible device for endpoint configure command.\n");
2168 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2169 "Successful Endpoint Configure command");
2173 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2181 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2182 struct usb_device *udev, u32 *cmd_status)
2186 switch (*cmd_status) {
2187 case COMP_COMMAND_ABORTED:
2188 case COMP_COMMAND_RING_STOPPED:
2189 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2192 case COMP_PARAMETER_ERROR:
2193 dev_warn(&udev->dev,
2194 "WARN: xHCI driver setup invalid evaluate context command.\n");
2197 case COMP_SLOT_NOT_ENABLED_ERROR:
2198 dev_warn(&udev->dev,
2199 "WARN: slot not enabled for evaluate context command.\n");
2202 case COMP_CONTEXT_STATE_ERROR:
2203 dev_warn(&udev->dev,
2204 "WARN: invalid context state for evaluate context command.\n");
2207 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2208 dev_warn(&udev->dev,
2209 "ERROR: Incompatible device for evaluate context command.\n");
2212 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2213 /* Max Exit Latency too large error */
2214 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2218 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2219 "Successful evaluate context command");
2223 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2231 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2232 struct xhci_input_control_ctx *ctrl_ctx)
2234 u32 valid_add_flags;
2235 u32 valid_drop_flags;
2237 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2238 * (bit 1). The default control endpoint is added during the Address
2239 * Device command and is never removed until the slot is disabled.
2241 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2242 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2244 /* Use hweight32 to count the number of ones in the add flags, or
2245 * number of endpoints added. Don't count endpoints that are changed
2246 * (both added and dropped).
2248 return hweight32(valid_add_flags) -
2249 hweight32(valid_add_flags & valid_drop_flags);
2252 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2253 struct xhci_input_control_ctx *ctrl_ctx)
2255 u32 valid_add_flags;
2256 u32 valid_drop_flags;
2258 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2259 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2261 return hweight32(valid_drop_flags) -
2262 hweight32(valid_add_flags & valid_drop_flags);
2266 * We need to reserve the new number of endpoints before the configure endpoint
2267 * command completes. We can't subtract the dropped endpoints from the number
2268 * of active endpoints until the command completes because we can oversubscribe
2269 * the host in this case:
2271 * - the first configure endpoint command drops more endpoints than it adds
2272 * - a second configure endpoint command that adds more endpoints is queued
2273 * - the first configure endpoint command fails, so the config is unchanged
2274 * - the second command may succeed, even though there isn't enough resources
2276 * Must be called with xhci->lock held.
2278 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2279 struct xhci_input_control_ctx *ctrl_ctx)
2283 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2284 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2285 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2286 "Not enough ep ctxs: "
2287 "%u active, need to add %u, limit is %u.",
2288 xhci->num_active_eps, added_eps,
2289 xhci->limit_active_eps);
2292 xhci->num_active_eps += added_eps;
2293 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2294 "Adding %u ep ctxs, %u now active.", added_eps,
2295 xhci->num_active_eps);
2300 * The configure endpoint was failed by the xHC for some other reason, so we
2301 * need to revert the resources that failed configuration would have used.
2303 * Must be called with xhci->lock held.
2305 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2306 struct xhci_input_control_ctx *ctrl_ctx)
2310 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2311 xhci->num_active_eps -= num_failed_eps;
2312 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2313 "Removing %u failed ep ctxs, %u now active.",
2315 xhci->num_active_eps);
2319 * Now that the command has completed, clean up the active endpoint count by
2320 * subtracting out the endpoints that were dropped (but not changed).
2322 * Must be called with xhci->lock held.
2324 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2325 struct xhci_input_control_ctx *ctrl_ctx)
2327 u32 num_dropped_eps;
2329 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2330 xhci->num_active_eps -= num_dropped_eps;
2331 if (num_dropped_eps)
2332 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2333 "Removing %u dropped ep ctxs, %u now active.",
2335 xhci->num_active_eps);
2338 static unsigned int xhci_get_block_size(struct usb_device *udev)
2340 switch (udev->speed) {
2342 case USB_SPEED_FULL:
2344 case USB_SPEED_HIGH:
2346 case USB_SPEED_SUPER:
2347 case USB_SPEED_SUPER_PLUS:
2349 case USB_SPEED_UNKNOWN:
2350 case USB_SPEED_WIRELESS:
2352 /* Should never happen */
2358 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2360 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2362 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2367 /* If we are changing a LS/FS device under a HS hub,
2368 * make sure (if we are activating a new TT) that the HS bus has enough
2369 * bandwidth for this new TT.
2371 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2372 struct xhci_virt_device *virt_dev,
2375 struct xhci_interval_bw_table *bw_table;
2376 struct xhci_tt_bw_info *tt_info;
2378 /* Find the bandwidth table for the root port this TT is attached to. */
2379 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2380 tt_info = virt_dev->tt_info;
2381 /* If this TT already had active endpoints, the bandwidth for this TT
2382 * has already been added. Removing all periodic endpoints (and thus
2383 * making the TT enactive) will only decrease the bandwidth used.
2387 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2388 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2392 /* Not sure why we would have no new active endpoints...
2394 * Maybe because of an Evaluate Context change for a hub update or a
2395 * control endpoint 0 max packet size change?
2396 * FIXME: skip the bandwidth calculation in that case.
2401 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2402 struct xhci_virt_device *virt_dev)
2404 unsigned int bw_reserved;
2406 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2407 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2410 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2411 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2418 * This algorithm is a very conservative estimate of the worst-case scheduling
2419 * scenario for any one interval. The hardware dynamically schedules the
2420 * packets, so we can't tell which microframe could be the limiting factor in
2421 * the bandwidth scheduling. This only takes into account periodic endpoints.
2423 * Obviously, we can't solve an NP complete problem to find the minimum worst
2424 * case scenario. Instead, we come up with an estimate that is no less than
2425 * the worst case bandwidth used for any one microframe, but may be an
2428 * We walk the requirements for each endpoint by interval, starting with the
2429 * smallest interval, and place packets in the schedule where there is only one
2430 * possible way to schedule packets for that interval. In order to simplify
2431 * this algorithm, we record the largest max packet size for each interval, and
2432 * assume all packets will be that size.
2434 * For interval 0, we obviously must schedule all packets for each interval.
2435 * The bandwidth for interval 0 is just the amount of data to be transmitted
2436 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2437 * the number of packets).
2439 * For interval 1, we have two possible microframes to schedule those packets
2440 * in. For this algorithm, if we can schedule the same number of packets for
2441 * each possible scheduling opportunity (each microframe), we will do so. The
2442 * remaining number of packets will be saved to be transmitted in the gaps in
2443 * the next interval's scheduling sequence.
2445 * As we move those remaining packets to be scheduled with interval 2 packets,
2446 * we have to double the number of remaining packets to transmit. This is
2447 * because the intervals are actually powers of 2, and we would be transmitting
2448 * the previous interval's packets twice in this interval. We also have to be
2449 * sure that when we look at the largest max packet size for this interval, we
2450 * also look at the largest max packet size for the remaining packets and take
2451 * the greater of the two.
2453 * The algorithm continues to evenly distribute packets in each scheduling
2454 * opportunity, and push the remaining packets out, until we get to the last
2455 * interval. Then those packets and their associated overhead are just added
2456 * to the bandwidth used.
2458 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2459 struct xhci_virt_device *virt_dev,
2462 unsigned int bw_reserved;
2463 unsigned int max_bandwidth;
2464 unsigned int bw_used;
2465 unsigned int block_size;
2466 struct xhci_interval_bw_table *bw_table;
2467 unsigned int packet_size = 0;
2468 unsigned int overhead = 0;
2469 unsigned int packets_transmitted = 0;
2470 unsigned int packets_remaining = 0;
2473 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2474 return xhci_check_ss_bw(xhci, virt_dev);
2476 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2477 max_bandwidth = HS_BW_LIMIT;
2478 /* Convert percent of bus BW reserved to blocks reserved */
2479 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2481 max_bandwidth = FS_BW_LIMIT;
2482 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2485 bw_table = virt_dev->bw_table;
2486 /* We need to translate the max packet size and max ESIT payloads into
2487 * the units the hardware uses.
2489 block_size = xhci_get_block_size(virt_dev->udev);
2491 /* If we are manipulating a LS/FS device under a HS hub, double check
2492 * that the HS bus has enough bandwidth if we are activing a new TT.
2494 if (virt_dev->tt_info) {
2495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2496 "Recalculating BW for rootport %u",
2497 virt_dev->real_port);
2498 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2499 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2500 "newly activated TT.\n");
2503 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2504 "Recalculating BW for TT slot %u port %u",
2505 virt_dev->tt_info->slot_id,
2506 virt_dev->tt_info->ttport);
2508 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2509 "Recalculating BW for rootport %u",
2510 virt_dev->real_port);
2513 /* Add in how much bandwidth will be used for interval zero, or the
2514 * rounded max ESIT payload + number of packets * largest overhead.
2516 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2517 bw_table->interval_bw[0].num_packets *
2518 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2520 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2521 unsigned int bw_added;
2522 unsigned int largest_mps;
2523 unsigned int interval_overhead;
2526 * How many packets could we transmit in this interval?
2527 * If packets didn't fit in the previous interval, we will need
2528 * to transmit that many packets twice within this interval.
2530 packets_remaining = 2 * packets_remaining +
2531 bw_table->interval_bw[i].num_packets;
2533 /* Find the largest max packet size of this or the previous
2536 if (list_empty(&bw_table->interval_bw[i].endpoints))
2539 struct xhci_virt_ep *virt_ep;
2540 struct list_head *ep_entry;
2542 ep_entry = bw_table->interval_bw[i].endpoints.next;
2543 virt_ep = list_entry(ep_entry,
2544 struct xhci_virt_ep, bw_endpoint_list);
2545 /* Convert to blocks, rounding up */
2546 largest_mps = DIV_ROUND_UP(
2547 virt_ep->bw_info.max_packet_size,
2550 if (largest_mps > packet_size)
2551 packet_size = largest_mps;
2553 /* Use the larger overhead of this or the previous interval. */
2554 interval_overhead = xhci_get_largest_overhead(
2555 &bw_table->interval_bw[i]);
2556 if (interval_overhead > overhead)
2557 overhead = interval_overhead;
2559 /* How many packets can we evenly distribute across
2560 * (1 << (i + 1)) possible scheduling opportunities?
2562 packets_transmitted = packets_remaining >> (i + 1);
2564 /* Add in the bandwidth used for those scheduled packets */
2565 bw_added = packets_transmitted * (overhead + packet_size);
2567 /* How many packets do we have remaining to transmit? */
2568 packets_remaining = packets_remaining % (1 << (i + 1));
2570 /* What largest max packet size should those packets have? */
2571 /* If we've transmitted all packets, don't carry over the
2572 * largest packet size.
2574 if (packets_remaining == 0) {
2577 } else if (packets_transmitted > 0) {
2578 /* Otherwise if we do have remaining packets, and we've
2579 * scheduled some packets in this interval, take the
2580 * largest max packet size from endpoints with this
2583 packet_size = largest_mps;
2584 overhead = interval_overhead;
2586 /* Otherwise carry over packet_size and overhead from the last
2587 * time we had a remainder.
2589 bw_used += bw_added;
2590 if (bw_used > max_bandwidth) {
2591 xhci_warn(xhci, "Not enough bandwidth. "
2592 "Proposed: %u, Max: %u\n",
2593 bw_used, max_bandwidth);
2598 * Ok, we know we have some packets left over after even-handedly
2599 * scheduling interval 15. We don't know which microframes they will
2600 * fit into, so we over-schedule and say they will be scheduled every
2603 if (packets_remaining > 0)
2604 bw_used += overhead + packet_size;
2606 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2607 unsigned int port_index = virt_dev->real_port - 1;
2609 /* OK, we're manipulating a HS device attached to a
2610 * root port bandwidth domain. Include the number of active TTs
2611 * in the bandwidth used.
2613 bw_used += TT_HS_OVERHEAD *
2614 xhci->rh_bw[port_index].num_active_tts;
2617 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2618 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2619 "Available: %u " "percent",
2620 bw_used, max_bandwidth, bw_reserved,
2621 (max_bandwidth - bw_used - bw_reserved) * 100 /
2624 bw_used += bw_reserved;
2625 if (bw_used > max_bandwidth) {
2626 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2627 bw_used, max_bandwidth);
2631 bw_table->bw_used = bw_used;
2635 static bool xhci_is_async_ep(unsigned int ep_type)
2637 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2638 ep_type != ISOC_IN_EP &&
2639 ep_type != INT_IN_EP);
2642 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2644 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2647 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2649 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2651 if (ep_bw->ep_interval == 0)
2652 return SS_OVERHEAD_BURST +
2653 (ep_bw->mult * ep_bw->num_packets *
2654 (SS_OVERHEAD + mps));
2655 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2656 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2657 1 << ep_bw->ep_interval);
2661 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2662 struct xhci_bw_info *ep_bw,
2663 struct xhci_interval_bw_table *bw_table,
2664 struct usb_device *udev,
2665 struct xhci_virt_ep *virt_ep,
2666 struct xhci_tt_bw_info *tt_info)
2668 struct xhci_interval_bw *interval_bw;
2669 int normalized_interval;
2671 if (xhci_is_async_ep(ep_bw->type))
2674 if (udev->speed >= USB_SPEED_SUPER) {
2675 if (xhci_is_sync_in_ep(ep_bw->type))
2676 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2677 xhci_get_ss_bw_consumed(ep_bw);
2679 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2680 xhci_get_ss_bw_consumed(ep_bw);
2684 /* SuperSpeed endpoints never get added to intervals in the table, so
2685 * this check is only valid for HS/FS/LS devices.
2687 if (list_empty(&virt_ep->bw_endpoint_list))
2689 /* For LS/FS devices, we need to translate the interval expressed in
2690 * microframes to frames.
2692 if (udev->speed == USB_SPEED_HIGH)
2693 normalized_interval = ep_bw->ep_interval;
2695 normalized_interval = ep_bw->ep_interval - 3;
2697 if (normalized_interval == 0)
2698 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2699 interval_bw = &bw_table->interval_bw[normalized_interval];
2700 interval_bw->num_packets -= ep_bw->num_packets;
2701 switch (udev->speed) {
2703 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2705 case USB_SPEED_FULL:
2706 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2708 case USB_SPEED_HIGH:
2709 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2711 case USB_SPEED_SUPER:
2712 case USB_SPEED_SUPER_PLUS:
2713 case USB_SPEED_UNKNOWN:
2714 case USB_SPEED_WIRELESS:
2715 /* Should never happen because only LS/FS/HS endpoints will get
2716 * added to the endpoint list.
2721 tt_info->active_eps -= 1;
2722 list_del_init(&virt_ep->bw_endpoint_list);
2725 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2726 struct xhci_bw_info *ep_bw,
2727 struct xhci_interval_bw_table *bw_table,
2728 struct usb_device *udev,
2729 struct xhci_virt_ep *virt_ep,
2730 struct xhci_tt_bw_info *tt_info)
2732 struct xhci_interval_bw *interval_bw;
2733 struct xhci_virt_ep *smaller_ep;
2734 int normalized_interval;
2736 if (xhci_is_async_ep(ep_bw->type))
2739 if (udev->speed == USB_SPEED_SUPER) {
2740 if (xhci_is_sync_in_ep(ep_bw->type))
2741 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2742 xhci_get_ss_bw_consumed(ep_bw);
2744 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2745 xhci_get_ss_bw_consumed(ep_bw);
2749 /* For LS/FS devices, we need to translate the interval expressed in
2750 * microframes to frames.
2752 if (udev->speed == USB_SPEED_HIGH)
2753 normalized_interval = ep_bw->ep_interval;
2755 normalized_interval = ep_bw->ep_interval - 3;
2757 if (normalized_interval == 0)
2758 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2759 interval_bw = &bw_table->interval_bw[normalized_interval];
2760 interval_bw->num_packets += ep_bw->num_packets;
2761 switch (udev->speed) {
2763 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2765 case USB_SPEED_FULL:
2766 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2768 case USB_SPEED_HIGH:
2769 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2771 case USB_SPEED_SUPER:
2772 case USB_SPEED_SUPER_PLUS:
2773 case USB_SPEED_UNKNOWN:
2774 case USB_SPEED_WIRELESS:
2775 /* Should never happen because only LS/FS/HS endpoints will get
2776 * added to the endpoint list.
2782 tt_info->active_eps += 1;
2783 /* Insert the endpoint into the list, largest max packet size first. */
2784 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2786 if (ep_bw->max_packet_size >=
2787 smaller_ep->bw_info.max_packet_size) {
2788 /* Add the new ep before the smaller endpoint */
2789 list_add_tail(&virt_ep->bw_endpoint_list,
2790 &smaller_ep->bw_endpoint_list);
2794 /* Add the new endpoint at the end of the list. */
2795 list_add_tail(&virt_ep->bw_endpoint_list,
2796 &interval_bw->endpoints);
2799 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2800 struct xhci_virt_device *virt_dev,
2803 struct xhci_root_port_bw_info *rh_bw_info;
2804 if (!virt_dev->tt_info)
2807 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2808 if (old_active_eps == 0 &&
2809 virt_dev->tt_info->active_eps != 0) {
2810 rh_bw_info->num_active_tts += 1;
2811 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2812 } else if (old_active_eps != 0 &&
2813 virt_dev->tt_info->active_eps == 0) {
2814 rh_bw_info->num_active_tts -= 1;
2815 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2819 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2820 struct xhci_virt_device *virt_dev,
2821 struct xhci_container_ctx *in_ctx)
2823 struct xhci_bw_info ep_bw_info[31];
2825 struct xhci_input_control_ctx *ctrl_ctx;
2826 int old_active_eps = 0;
2828 if (virt_dev->tt_info)
2829 old_active_eps = virt_dev->tt_info->active_eps;
2831 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2833 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2838 for (i = 0; i < 31; i++) {
2839 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2842 /* Make a copy of the BW info in case we need to revert this */
2843 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2844 sizeof(ep_bw_info[i]));
2845 /* Drop the endpoint from the interval table if the endpoint is
2846 * being dropped or changed.
2848 if (EP_IS_DROPPED(ctrl_ctx, i))
2849 xhci_drop_ep_from_interval_table(xhci,
2850 &virt_dev->eps[i].bw_info,
2856 /* Overwrite the information stored in the endpoints' bw_info */
2857 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2858 for (i = 0; i < 31; i++) {
2859 /* Add any changed or added endpoints to the interval table */
2860 if (EP_IS_ADDED(ctrl_ctx, i))
2861 xhci_add_ep_to_interval_table(xhci,
2862 &virt_dev->eps[i].bw_info,
2869 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2870 /* Ok, this fits in the bandwidth we have.
2871 * Update the number of active TTs.
2873 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2877 /* We don't have enough bandwidth for this, revert the stored info. */
2878 for (i = 0; i < 31; i++) {
2879 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2882 /* Drop the new copies of any added or changed endpoints from
2883 * the interval table.
2885 if (EP_IS_ADDED(ctrl_ctx, i)) {
2886 xhci_drop_ep_from_interval_table(xhci,
2887 &virt_dev->eps[i].bw_info,
2893 /* Revert the endpoint back to its old information */
2894 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2895 sizeof(ep_bw_info[i]));
2896 /* Add any changed or dropped endpoints back into the table */
2897 if (EP_IS_DROPPED(ctrl_ctx, i))
2898 xhci_add_ep_to_interval_table(xhci,
2899 &virt_dev->eps[i].bw_info,
2909 /* Issue a configure endpoint command or evaluate context command
2910 * and wait for it to finish.
2912 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2913 struct usb_device *udev,
2914 struct xhci_command *command,
2915 bool ctx_change, bool must_succeed)
2918 unsigned long flags;
2919 struct xhci_input_control_ctx *ctrl_ctx;
2920 struct xhci_virt_device *virt_dev;
2921 struct xhci_slot_ctx *slot_ctx;
2926 spin_lock_irqsave(&xhci->lock, flags);
2928 if (xhci->xhc_state & XHCI_STATE_DYING) {
2929 spin_unlock_irqrestore(&xhci->lock, flags);
2933 virt_dev = xhci->devs[udev->slot_id];
2935 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2937 spin_unlock_irqrestore(&xhci->lock, flags);
2938 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2943 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2944 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2945 spin_unlock_irqrestore(&xhci->lock, flags);
2946 xhci_warn(xhci, "Not enough host resources, "
2947 "active endpoint contexts = %u\n",
2948 xhci->num_active_eps);
2951 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2952 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2953 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2954 xhci_free_host_resources(xhci, ctrl_ctx);
2955 spin_unlock_irqrestore(&xhci->lock, flags);
2956 xhci_warn(xhci, "Not enough bandwidth\n");
2960 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2962 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2963 trace_xhci_configure_endpoint(slot_ctx);
2966 ret = xhci_queue_configure_endpoint(xhci, command,
2967 command->in_ctx->dma,
2968 udev->slot_id, must_succeed);
2970 ret = xhci_queue_evaluate_context(xhci, command,
2971 command->in_ctx->dma,
2972 udev->slot_id, must_succeed);
2974 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2975 xhci_free_host_resources(xhci, ctrl_ctx);
2976 spin_unlock_irqrestore(&xhci->lock, flags);
2977 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2978 "FIXME allocate a new ring segment");
2981 xhci_ring_cmd_db(xhci);
2982 spin_unlock_irqrestore(&xhci->lock, flags);
2984 /* Wait for the configure endpoint command to complete */
2985 wait_for_completion(command->completion);
2988 ret = xhci_configure_endpoint_result(xhci, udev,
2991 ret = xhci_evaluate_context_result(xhci, udev,
2994 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2995 spin_lock_irqsave(&xhci->lock, flags);
2996 /* If the command failed, remove the reserved resources.
2997 * Otherwise, clean up the estimate to include dropped eps.
3000 xhci_free_host_resources(xhci, ctrl_ctx);
3002 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3003 spin_unlock_irqrestore(&xhci->lock, flags);
3008 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3009 struct xhci_virt_device *vdev, int i)
3011 struct xhci_virt_ep *ep = &vdev->eps[i];
3013 if (ep->ep_state & EP_HAS_STREAMS) {
3014 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3015 xhci_get_endpoint_address(i));
3016 xhci_free_stream_info(xhci, ep->stream_info);
3017 ep->stream_info = NULL;
3018 ep->ep_state &= ~EP_HAS_STREAMS;
3022 /* Called after one or more calls to xhci_add_endpoint() or
3023 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3024 * to call xhci_reset_bandwidth().
3026 * Since we are in the middle of changing either configuration or
3027 * installing a new alt setting, the USB core won't allow URBs to be
3028 * enqueued for any endpoint on the old config or interface. Nothing
3029 * else should be touching the xhci->devs[slot_id] structure, so we
3030 * don't need to take the xhci->lock for manipulating that.
3032 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3036 struct xhci_hcd *xhci;
3037 struct xhci_virt_device *virt_dev;
3038 struct xhci_input_control_ctx *ctrl_ctx;
3039 struct xhci_slot_ctx *slot_ctx;
3040 struct xhci_command *command;
3042 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3045 xhci = hcd_to_xhci(hcd);
3046 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3047 (xhci->xhc_state & XHCI_STATE_REMOVING))
3050 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3051 virt_dev = xhci->devs[udev->slot_id];
3053 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3057 command->in_ctx = virt_dev->in_ctx;
3059 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3060 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3062 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3065 goto command_cleanup;
3067 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3068 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3069 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3071 /* Don't issue the command if there's no endpoints to update. */
3072 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3073 ctrl_ctx->drop_flags == 0) {
3075 goto command_cleanup;
3077 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3078 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3079 for (i = 31; i >= 1; i--) {
3080 __le32 le32 = cpu_to_le32(BIT(i));
3082 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3083 || (ctrl_ctx->add_flags & le32) || i == 1) {
3084 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3085 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3090 ret = xhci_configure_endpoint(xhci, udev, command,
3093 /* Callee should call reset_bandwidth() */
3094 goto command_cleanup;
3096 /* Free any rings that were dropped, but not changed. */
3097 for (i = 1; i < 31; i++) {
3098 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3099 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3100 xhci_free_endpoint_ring(xhci, virt_dev, i);
3101 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3104 xhci_zero_in_ctx(xhci, virt_dev);
3106 * Install any rings for completely new endpoints or changed endpoints,
3107 * and free any old rings from changed endpoints.
3109 for (i = 1; i < 31; i++) {
3110 if (!virt_dev->eps[i].new_ring)
3112 /* Only free the old ring if it exists.
3113 * It may not if this is the first add of an endpoint.
3115 if (virt_dev->eps[i].ring) {
3116 xhci_free_endpoint_ring(xhci, virt_dev, i);
3118 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3119 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3120 virt_dev->eps[i].new_ring = NULL;
3121 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3124 kfree(command->completion);
3129 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3131 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3133 struct xhci_hcd *xhci;
3134 struct xhci_virt_device *virt_dev;
3137 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3140 xhci = hcd_to_xhci(hcd);
3142 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3143 virt_dev = xhci->devs[udev->slot_id];
3144 /* Free any rings allocated for added endpoints */
3145 for (i = 0; i < 31; i++) {
3146 if (virt_dev->eps[i].new_ring) {
3147 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3148 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3149 virt_dev->eps[i].new_ring = NULL;
3152 xhci_zero_in_ctx(xhci, virt_dev);
3154 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3156 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3157 struct xhci_container_ctx *in_ctx,
3158 struct xhci_container_ctx *out_ctx,
3159 struct xhci_input_control_ctx *ctrl_ctx,
3160 u32 add_flags, u32 drop_flags)
3162 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3163 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3164 xhci_slot_copy(xhci, in_ctx, out_ctx);
3165 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3168 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3169 struct usb_host_endpoint *host_ep)
3171 struct xhci_hcd *xhci;
3172 struct xhci_virt_device *vdev;
3173 struct xhci_virt_ep *ep;
3174 struct usb_device *udev;
3175 unsigned long flags;
3176 unsigned int ep_index;
3178 xhci = hcd_to_xhci(hcd);
3180 spin_lock_irqsave(&xhci->lock, flags);
3182 udev = (struct usb_device *)host_ep->hcpriv;
3183 if (!udev || !udev->slot_id)
3186 vdev = xhci->devs[udev->slot_id];
3190 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3191 ep = &vdev->eps[ep_index];
3193 /* wait for hub_tt_work to finish clearing hub TT */
3194 if (ep->ep_state & EP_CLEARING_TT) {
3195 spin_unlock_irqrestore(&xhci->lock, flags);
3196 schedule_timeout_uninterruptible(1);
3201 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3204 host_ep->hcpriv = NULL;
3205 spin_unlock_irqrestore(&xhci->lock, flags);
3209 * Called after usb core issues a clear halt control message.
3210 * The host side of the halt should already be cleared by a reset endpoint
3211 * command issued when the STALL event was received.
3213 * The reset endpoint command may only be issued to endpoints in the halted
3214 * state. For software that wishes to reset the data toggle or sequence number
3215 * of an endpoint that isn't in the halted state this function will issue a
3216 * configure endpoint command with the Drop and Add bits set for the target
3217 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3220 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3221 struct usb_host_endpoint *host_ep)
3223 struct xhci_hcd *xhci;
3224 struct usb_device *udev;
3225 struct xhci_virt_device *vdev;
3226 struct xhci_virt_ep *ep;
3227 struct xhci_input_control_ctx *ctrl_ctx;
3228 struct xhci_command *stop_cmd, *cfg_cmd;
3229 unsigned int ep_index;
3230 unsigned long flags;
3234 xhci = hcd_to_xhci(hcd);
3235 if (!host_ep->hcpriv)
3237 udev = (struct usb_device *) host_ep->hcpriv;
3238 vdev = xhci->devs[udev->slot_id];
3241 * vdev may be lost due to xHC restore error and re-initialization
3242 * during S3/S4 resume. A new vdev will be allocated later by
3243 * xhci_discover_or_reset_device()
3245 if (!udev->slot_id || !vdev)
3247 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3248 ep = &vdev->eps[ep_index];
3250 /* Bail out if toggle is already being cleared by a endpoint reset */
3251 spin_lock_irqsave(&xhci->lock, flags);
3252 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3253 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3254 spin_unlock_irqrestore(&xhci->lock, flags);
3257 spin_unlock_irqrestore(&xhci->lock, flags);
3258 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3259 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3260 usb_endpoint_xfer_isoc(&host_ep->desc))
3263 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3265 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3268 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3272 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3276 spin_lock_irqsave(&xhci->lock, flags);
3278 /* block queuing new trbs and ringing ep doorbell */
3279 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3282 * Make sure endpoint ring is empty before resetting the toggle/seq.
3283 * Driver is required to synchronously cancel all transfer request.
3284 * Stop the endpoint to force xHC to update the output context
3287 if (!list_empty(&ep->ring->td_list)) {
3288 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3289 spin_unlock_irqrestore(&xhci->lock, flags);
3290 xhci_free_command(xhci, cfg_cmd);
3294 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3297 spin_unlock_irqrestore(&xhci->lock, flags);
3298 xhci_free_command(xhci, cfg_cmd);
3299 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3304 xhci_ring_cmd_db(xhci);
3305 spin_unlock_irqrestore(&xhci->lock, flags);
3307 wait_for_completion(stop_cmd->completion);
3309 spin_lock_irqsave(&xhci->lock, flags);
3311 /* config ep command clears toggle if add and drop ep flags are set */
3312 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3314 spin_unlock_irqrestore(&xhci->lock, flags);
3315 xhci_free_command(xhci, cfg_cmd);
3316 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3321 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3322 ctrl_ctx, ep_flag, ep_flag);
3323 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3325 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3326 udev->slot_id, false);
3328 spin_unlock_irqrestore(&xhci->lock, flags);
3329 xhci_free_command(xhci, cfg_cmd);
3330 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3335 xhci_ring_cmd_db(xhci);
3336 spin_unlock_irqrestore(&xhci->lock, flags);
3338 wait_for_completion(cfg_cmd->completion);
3340 xhci_free_command(xhci, cfg_cmd);
3342 xhci_free_command(xhci, stop_cmd);
3343 spin_lock_irqsave(&xhci->lock, flags);
3344 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3345 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3346 spin_unlock_irqrestore(&xhci->lock, flags);
3349 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3350 struct usb_device *udev, struct usb_host_endpoint *ep,
3351 unsigned int slot_id)
3354 unsigned int ep_index;
3355 unsigned int ep_state;
3359 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3361 return ret ? ret : -EINVAL;
3362 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3363 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3364 " descriptor for ep 0x%x does not support streams\n",
3365 ep->desc.bEndpointAddress);
3369 ep_index = xhci_get_endpoint_index(&ep->desc);
3370 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3371 if (ep_state & EP_HAS_STREAMS ||
3372 ep_state & EP_GETTING_STREAMS) {
3373 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3374 "already has streams set up.\n",
3375 ep->desc.bEndpointAddress);
3376 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3377 "dynamic stream context array reallocation.\n");
3380 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3381 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3382 "endpoint 0x%x; URBs are pending.\n",
3383 ep->desc.bEndpointAddress);
3389 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3390 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3392 unsigned int max_streams;
3394 /* The stream context array size must be a power of two */
3395 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3397 * Find out how many primary stream array entries the host controller
3398 * supports. Later we may use secondary stream arrays (similar to 2nd
3399 * level page entries), but that's an optional feature for xHCI host
3400 * controllers. xHCs must support at least 4 stream IDs.
3402 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3403 if (*num_stream_ctxs > max_streams) {
3404 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3406 *num_stream_ctxs = max_streams;
3407 *num_streams = max_streams;
3411 /* Returns an error code if one of the endpoint already has streams.
3412 * This does not change any data structures, it only checks and gathers
3415 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3416 struct usb_device *udev,
3417 struct usb_host_endpoint **eps, unsigned int num_eps,
3418 unsigned int *num_streams, u32 *changed_ep_bitmask)
3420 unsigned int max_streams;
3421 unsigned int endpoint_flag;
3425 for (i = 0; i < num_eps; i++) {
3426 ret = xhci_check_streams_endpoint(xhci, udev,
3427 eps[i], udev->slot_id);
3431 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3432 if (max_streams < (*num_streams - 1)) {
3433 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3434 eps[i]->desc.bEndpointAddress,
3436 *num_streams = max_streams+1;
3439 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3440 if (*changed_ep_bitmask & endpoint_flag)
3442 *changed_ep_bitmask |= endpoint_flag;
3447 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3448 struct usb_device *udev,
3449 struct usb_host_endpoint **eps, unsigned int num_eps)
3451 u32 changed_ep_bitmask = 0;
3452 unsigned int slot_id;
3453 unsigned int ep_index;
3454 unsigned int ep_state;
3457 slot_id = udev->slot_id;
3458 if (!xhci->devs[slot_id])
3461 for (i = 0; i < num_eps; i++) {
3462 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3463 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3464 /* Are streams already being freed for the endpoint? */
3465 if (ep_state & EP_GETTING_NO_STREAMS) {
3466 xhci_warn(xhci, "WARN Can't disable streams for "
3468 "streams are being disabled already\n",
3469 eps[i]->desc.bEndpointAddress);
3472 /* Are there actually any streams to free? */
3473 if (!(ep_state & EP_HAS_STREAMS) &&
3474 !(ep_state & EP_GETTING_STREAMS)) {
3475 xhci_warn(xhci, "WARN Can't disable streams for "
3477 "streams are already disabled!\n",
3478 eps[i]->desc.bEndpointAddress);
3479 xhci_warn(xhci, "WARN xhci_free_streams() called "
3480 "with non-streams endpoint\n");
3483 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3485 return changed_ep_bitmask;
3489 * The USB device drivers use this function (through the HCD interface in USB
3490 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3491 * coordinate mass storage command queueing across multiple endpoints (basically
3492 * a stream ID == a task ID).
3494 * Setting up streams involves allocating the same size stream context array
3495 * for each endpoint and issuing a configure endpoint command for all endpoints.
3497 * Don't allow the call to succeed if one endpoint only supports one stream
3498 * (which means it doesn't support streams at all).
3500 * Drivers may get less stream IDs than they asked for, if the host controller
3501 * hardware or endpoints claim they can't support the number of requested
3504 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3505 struct usb_host_endpoint **eps, unsigned int num_eps,
3506 unsigned int num_streams, gfp_t mem_flags)
3509 struct xhci_hcd *xhci;
3510 struct xhci_virt_device *vdev;
3511 struct xhci_command *config_cmd;
3512 struct xhci_input_control_ctx *ctrl_ctx;
3513 unsigned int ep_index;
3514 unsigned int num_stream_ctxs;
3515 unsigned int max_packet;
3516 unsigned long flags;
3517 u32 changed_ep_bitmask = 0;
3522 /* Add one to the number of streams requested to account for
3523 * stream 0 that is reserved for xHCI usage.
3526 xhci = hcd_to_xhci(hcd);
3527 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3530 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3531 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3532 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3533 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3537 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3541 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3543 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3545 xhci_free_command(xhci, config_cmd);
3549 /* Check to make sure all endpoints are not already configured for
3550 * streams. While we're at it, find the maximum number of streams that
3551 * all the endpoints will support and check for duplicate endpoints.
3553 spin_lock_irqsave(&xhci->lock, flags);
3554 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3555 num_eps, &num_streams, &changed_ep_bitmask);
3557 xhci_free_command(xhci, config_cmd);
3558 spin_unlock_irqrestore(&xhci->lock, flags);
3561 if (num_streams <= 1) {
3562 xhci_warn(xhci, "WARN: endpoints can't handle "
3563 "more than one stream.\n");
3564 xhci_free_command(xhci, config_cmd);
3565 spin_unlock_irqrestore(&xhci->lock, flags);
3568 vdev = xhci->devs[udev->slot_id];
3569 /* Mark each endpoint as being in transition, so
3570 * xhci_urb_enqueue() will reject all URBs.
3572 for (i = 0; i < num_eps; i++) {
3573 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3574 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3576 spin_unlock_irqrestore(&xhci->lock, flags);
3578 /* Setup internal data structures and allocate HW data structures for
3579 * streams (but don't install the HW structures in the input context
3580 * until we're sure all memory allocation succeeded).
3582 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3583 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3584 num_stream_ctxs, num_streams);
3586 for (i = 0; i < num_eps; i++) {
3587 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3588 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3589 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3592 max_packet, mem_flags);
3593 if (!vdev->eps[ep_index].stream_info)
3595 /* Set maxPstreams in endpoint context and update deq ptr to
3596 * point to stream context array. FIXME
3600 /* Set up the input context for a configure endpoint command. */
3601 for (i = 0; i < num_eps; i++) {
3602 struct xhci_ep_ctx *ep_ctx;
3604 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3605 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3607 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3608 vdev->out_ctx, ep_index);
3609 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3610 vdev->eps[ep_index].stream_info);
3612 /* Tell the HW to drop its old copy of the endpoint context info
3613 * and add the updated copy from the input context.
3615 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3616 vdev->out_ctx, ctrl_ctx,
3617 changed_ep_bitmask, changed_ep_bitmask);
3619 /* Issue and wait for the configure endpoint command */
3620 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3623 /* xHC rejected the configure endpoint command for some reason, so we
3624 * leave the old ring intact and free our internal streams data
3630 spin_lock_irqsave(&xhci->lock, flags);
3631 for (i = 0; i < num_eps; i++) {
3632 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3633 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3634 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3635 udev->slot_id, ep_index);
3636 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3638 xhci_free_command(xhci, config_cmd);
3639 spin_unlock_irqrestore(&xhci->lock, flags);
3641 for (i = 0; i < num_eps; i++) {
3642 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3643 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3645 /* Subtract 1 for stream 0, which drivers can't use */
3646 return num_streams - 1;
3649 /* If it didn't work, free the streams! */
3650 for (i = 0; i < num_eps; i++) {
3651 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3652 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3653 vdev->eps[ep_index].stream_info = NULL;
3654 /* FIXME Unset maxPstreams in endpoint context and
3655 * update deq ptr to point to normal string ring.
3657 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3658 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3659 xhci_endpoint_zero(xhci, vdev, eps[i]);
3661 xhci_free_command(xhci, config_cmd);
3665 /* Transition the endpoint from using streams to being a "normal" endpoint
3668 * Modify the endpoint context state, submit a configure endpoint command,
3669 * and free all endpoint rings for streams if that completes successfully.
3671 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3672 struct usb_host_endpoint **eps, unsigned int num_eps,
3676 struct xhci_hcd *xhci;
3677 struct xhci_virt_device *vdev;
3678 struct xhci_command *command;
3679 struct xhci_input_control_ctx *ctrl_ctx;
3680 unsigned int ep_index;
3681 unsigned long flags;
3682 u32 changed_ep_bitmask;
3684 xhci = hcd_to_xhci(hcd);
3685 vdev = xhci->devs[udev->slot_id];
3687 /* Set up a configure endpoint command to remove the streams rings */
3688 spin_lock_irqsave(&xhci->lock, flags);
3689 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3690 udev, eps, num_eps);
3691 if (changed_ep_bitmask == 0) {
3692 spin_unlock_irqrestore(&xhci->lock, flags);
3696 /* Use the xhci_command structure from the first endpoint. We may have
3697 * allocated too many, but the driver may call xhci_free_streams() for
3698 * each endpoint it grouped into one call to xhci_alloc_streams().
3700 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3701 command = vdev->eps[ep_index].stream_info->free_streams_command;
3702 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3704 spin_unlock_irqrestore(&xhci->lock, flags);
3705 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3710 for (i = 0; i < num_eps; i++) {
3711 struct xhci_ep_ctx *ep_ctx;
3713 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3714 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3715 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3716 EP_GETTING_NO_STREAMS;
3718 xhci_endpoint_copy(xhci, command->in_ctx,
3719 vdev->out_ctx, ep_index);
3720 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3721 &vdev->eps[ep_index]);
3723 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3724 vdev->out_ctx, ctrl_ctx,
3725 changed_ep_bitmask, changed_ep_bitmask);
3726 spin_unlock_irqrestore(&xhci->lock, flags);
3728 /* Issue and wait for the configure endpoint command,
3729 * which must succeed.
3731 ret = xhci_configure_endpoint(xhci, udev, command,
3734 /* xHC rejected the configure endpoint command for some reason, so we
3735 * leave the streams rings intact.
3740 spin_lock_irqsave(&xhci->lock, flags);
3741 for (i = 0; i < num_eps; i++) {
3742 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3743 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3744 vdev->eps[ep_index].stream_info = NULL;
3745 /* FIXME Unset maxPstreams in endpoint context and
3746 * update deq ptr to point to normal string ring.
3748 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3749 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3751 spin_unlock_irqrestore(&xhci->lock, flags);
3757 * Deletes endpoint resources for endpoints that were active before a Reset
3758 * Device command, or a Disable Slot command. The Reset Device command leaves
3759 * the control endpoint intact, whereas the Disable Slot command deletes it.
3761 * Must be called with xhci->lock held.
3763 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3764 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3767 unsigned int num_dropped_eps = 0;
3768 unsigned int drop_flags = 0;
3770 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3771 if (virt_dev->eps[i].ring) {
3772 drop_flags |= 1 << i;
3776 xhci->num_active_eps -= num_dropped_eps;
3777 if (num_dropped_eps)
3778 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3779 "Dropped %u ep ctxs, flags = 0x%x, "
3781 num_dropped_eps, drop_flags,
3782 xhci->num_active_eps);
3786 * This submits a Reset Device Command, which will set the device state to 0,
3787 * set the device address to 0, and disable all the endpoints except the default
3788 * control endpoint. The USB core should come back and call
3789 * xhci_address_device(), and then re-set up the configuration. If this is
3790 * called because of a usb_reset_and_verify_device(), then the old alternate
3791 * settings will be re-installed through the normal bandwidth allocation
3794 * Wait for the Reset Device command to finish. Remove all structures
3795 * associated with the endpoints that were disabled. Clear the input device
3796 * structure? Reset the control endpoint 0 max packet size?
3798 * If the virt_dev to be reset does not exist or does not match the udev,
3799 * it means the device is lost, possibly due to the xHC restore error and
3800 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3801 * re-allocate the device.
3803 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3804 struct usb_device *udev)
3807 unsigned long flags;
3808 struct xhci_hcd *xhci;
3809 unsigned int slot_id;
3810 struct xhci_virt_device *virt_dev;
3811 struct xhci_command *reset_device_cmd;
3812 struct xhci_slot_ctx *slot_ctx;
3813 int old_active_eps = 0;
3815 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3818 xhci = hcd_to_xhci(hcd);
3819 slot_id = udev->slot_id;
3820 virt_dev = xhci->devs[slot_id];
3822 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3823 "not exist. Re-allocate the device\n", slot_id);
3824 ret = xhci_alloc_dev(hcd, udev);
3831 if (virt_dev->tt_info)
3832 old_active_eps = virt_dev->tt_info->active_eps;
3834 if (virt_dev->udev != udev) {
3835 /* If the virt_dev and the udev does not match, this virt_dev
3836 * may belong to another udev.
3837 * Re-allocate the device.
3839 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3840 "not match the udev. Re-allocate the device\n",
3842 ret = xhci_alloc_dev(hcd, udev);
3849 /* If device is not setup, there is no point in resetting it */
3850 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3851 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3852 SLOT_STATE_DISABLED)
3855 trace_xhci_discover_or_reset_device(slot_ctx);
3857 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3858 /* Allocate the command structure that holds the struct completion.
3859 * Assume we're in process context, since the normal device reset
3860 * process has to wait for the device anyway. Storage devices are
3861 * reset as part of error handling, so use GFP_NOIO instead of
3864 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3865 if (!reset_device_cmd) {
3866 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3870 /* Attempt to submit the Reset Device command to the command ring */
3871 spin_lock_irqsave(&xhci->lock, flags);
3873 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3875 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3876 spin_unlock_irqrestore(&xhci->lock, flags);
3877 goto command_cleanup;
3879 xhci_ring_cmd_db(xhci);
3880 spin_unlock_irqrestore(&xhci->lock, flags);
3882 /* Wait for the Reset Device command to finish */
3883 wait_for_completion(reset_device_cmd->completion);
3885 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3886 * unless we tried to reset a slot ID that wasn't enabled,
3887 * or the device wasn't in the addressed or configured state.
3889 ret = reset_device_cmd->status;
3891 case COMP_COMMAND_ABORTED:
3892 case COMP_COMMAND_RING_STOPPED:
3893 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3895 goto command_cleanup;
3896 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3897 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3898 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3900 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3901 xhci_dbg(xhci, "Not freeing device rings.\n");
3902 /* Don't treat this as an error. May change my mind later. */
3904 goto command_cleanup;
3906 xhci_dbg(xhci, "Successful reset device command.\n");
3909 if (xhci_is_vendor_info_code(xhci, ret))
3911 xhci_warn(xhci, "Unknown completion code %u for "
3912 "reset device command.\n", ret);
3914 goto command_cleanup;
3917 /* Free up host controller endpoint resources */
3918 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3919 spin_lock_irqsave(&xhci->lock, flags);
3920 /* Don't delete the default control endpoint resources */
3921 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3922 spin_unlock_irqrestore(&xhci->lock, flags);
3925 /* Everything but endpoint 0 is disabled, so free the rings. */
3926 for (i = 1; i < 31; i++) {
3927 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3929 if (ep->ep_state & EP_HAS_STREAMS) {
3930 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3931 xhci_get_endpoint_address(i));
3932 xhci_free_stream_info(xhci, ep->stream_info);
3933 ep->stream_info = NULL;
3934 ep->ep_state &= ~EP_HAS_STREAMS;
3938 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3939 xhci_free_endpoint_ring(xhci, virt_dev, i);
3941 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3942 xhci_drop_ep_from_interval_table(xhci,
3943 &virt_dev->eps[i].bw_info,
3948 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3950 /* If necessary, update the number of active TTs on this root port */
3951 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3952 virt_dev->flags = 0;
3956 xhci_free_command(xhci, reset_device_cmd);
3961 * At this point, the struct usb_device is about to go away, the device has
3962 * disconnected, and all traffic has been stopped and the endpoints have been
3963 * disabled. Free any HC data structures associated with that device.
3965 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3967 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3968 struct xhci_virt_device *virt_dev;
3969 struct xhci_slot_ctx *slot_ctx;
3973 * We called pm_runtime_get_noresume when the device was attached.
3974 * Decrement the counter here to allow controller to runtime suspend
3975 * if no devices remain.
3977 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3978 pm_runtime_put_noidle(hcd->self.controller);
3980 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3981 /* If the host is halted due to driver unload, we still need to free the
3984 if (ret <= 0 && ret != -ENODEV)
3987 virt_dev = xhci->devs[udev->slot_id];
3988 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3989 trace_xhci_free_dev(slot_ctx);
3991 /* Stop any wayward timer functions (which may grab the lock) */
3992 for (i = 0; i < 31; i++)
3993 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3994 virt_dev->udev = NULL;
3995 xhci_disable_slot(xhci, udev->slot_id);
3996 xhci_free_virt_device(xhci, udev->slot_id);
3999 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4001 struct xhci_command *command;
4002 unsigned long flags;
4006 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4010 xhci_debugfs_remove_slot(xhci, slot_id);
4012 spin_lock_irqsave(&xhci->lock, flags);
4013 /* Don't disable the slot if the host controller is dead. */
4014 state = readl(&xhci->op_regs->status);
4015 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4016 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4017 spin_unlock_irqrestore(&xhci->lock, flags);
4022 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4025 spin_unlock_irqrestore(&xhci->lock, flags);
4029 xhci_ring_cmd_db(xhci);
4030 spin_unlock_irqrestore(&xhci->lock, flags);
4032 wait_for_completion(command->completion);
4034 if (command->status != COMP_SUCCESS)
4035 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4036 slot_id, command->status);
4038 xhci_free_command(xhci, command);
4044 * Checks if we have enough host controller resources for the default control
4047 * Must be called with xhci->lock held.
4049 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4051 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4052 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4053 "Not enough ep ctxs: "
4054 "%u active, need to add 1, limit is %u.",
4055 xhci->num_active_eps, xhci->limit_active_eps);
4058 xhci->num_active_eps += 1;
4059 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4060 "Adding 1 ep ctx, %u now active.",
4061 xhci->num_active_eps);
4067 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4068 * timed out, or allocating memory failed. Returns 1 on success.
4070 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4072 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4073 struct xhci_virt_device *vdev;
4074 struct xhci_slot_ctx *slot_ctx;
4075 unsigned long flags;
4077 struct xhci_command *command;
4079 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4083 spin_lock_irqsave(&xhci->lock, flags);
4084 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4086 spin_unlock_irqrestore(&xhci->lock, flags);
4087 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4088 xhci_free_command(xhci, command);
4091 xhci_ring_cmd_db(xhci);
4092 spin_unlock_irqrestore(&xhci->lock, flags);
4094 wait_for_completion(command->completion);
4095 slot_id = command->slot_id;
4097 if (!slot_id || command->status != COMP_SUCCESS) {
4098 xhci_err(xhci, "Error while assigning device slot ID\n");
4099 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4101 readl(&xhci->cap_regs->hcs_params1)));
4102 xhci_free_command(xhci, command);
4106 xhci_free_command(xhci, command);
4108 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4109 spin_lock_irqsave(&xhci->lock, flags);
4110 ret = xhci_reserve_host_control_ep_resources(xhci);
4112 spin_unlock_irqrestore(&xhci->lock, flags);
4113 xhci_warn(xhci, "Not enough host resources, "
4114 "active endpoint contexts = %u\n",
4115 xhci->num_active_eps);
4118 spin_unlock_irqrestore(&xhci->lock, flags);
4120 /* Use GFP_NOIO, since this function can be called from
4121 * xhci_discover_or_reset_device(), which may be called as part of
4122 * mass storage driver error handling.
4124 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4125 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4128 vdev = xhci->devs[slot_id];
4129 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4130 trace_xhci_alloc_dev(slot_ctx);
4132 udev->slot_id = slot_id;
4134 xhci_debugfs_create_slot(xhci, slot_id);
4137 * If resetting upon resume, we can't put the controller into runtime
4138 * suspend if there is a device attached.
4140 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4141 pm_runtime_get_noresume(hcd->self.controller);
4143 /* Is this a LS or FS device under a HS hub? */
4144 /* Hub or peripherial? */
4148 xhci_disable_slot(xhci, udev->slot_id);
4149 xhci_free_virt_device(xhci, udev->slot_id);
4155 * Issue an Address Device command and optionally send a corresponding
4156 * SetAddress request to the device.
4158 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4159 enum xhci_setup_dev setup)
4161 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4162 unsigned long flags;
4163 struct xhci_virt_device *virt_dev;
4165 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4166 struct xhci_slot_ctx *slot_ctx;
4167 struct xhci_input_control_ctx *ctrl_ctx;
4169 struct xhci_command *command = NULL;
4171 mutex_lock(&xhci->mutex);
4173 if (xhci->xhc_state) { /* dying, removing or halted */
4178 if (!udev->slot_id) {
4179 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4180 "Bad Slot ID %d", udev->slot_id);
4185 virt_dev = xhci->devs[udev->slot_id];
4187 if (WARN_ON(!virt_dev)) {
4189 * In plug/unplug torture test with an NEC controller,
4190 * a zero-dereference was observed once due to virt_dev = 0.
4191 * Print useful debug rather than crash if it is observed again!
4193 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4198 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4199 trace_xhci_setup_device_slot(slot_ctx);
4201 if (setup == SETUP_CONTEXT_ONLY) {
4202 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4203 SLOT_STATE_DEFAULT) {
4204 xhci_dbg(xhci, "Slot already in default state\n");
4209 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4215 command->in_ctx = virt_dev->in_ctx;
4217 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4218 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4220 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4226 * If this is the first Set Address since device plug-in or
4227 * virt_device realloaction after a resume with an xHCI power loss,
4228 * then set up the slot context.
4230 if (!slot_ctx->dev_info)
4231 xhci_setup_addressable_virt_dev(xhci, udev);
4232 /* Otherwise, update the control endpoint ring enqueue pointer. */
4234 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4235 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4236 ctrl_ctx->drop_flags = 0;
4238 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4239 le32_to_cpu(slot_ctx->dev_info) >> 27);
4241 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4242 spin_lock_irqsave(&xhci->lock, flags);
4243 trace_xhci_setup_device(virt_dev);
4244 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4245 udev->slot_id, setup);
4247 spin_unlock_irqrestore(&xhci->lock, flags);
4248 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4249 "FIXME: allocate a command ring segment");
4252 xhci_ring_cmd_db(xhci);
4253 spin_unlock_irqrestore(&xhci->lock, flags);
4255 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4256 wait_for_completion(command->completion);
4258 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4259 * the SetAddress() "recovery interval" required by USB and aborting the
4260 * command on a timeout.
4262 switch (command->status) {
4263 case COMP_COMMAND_ABORTED:
4264 case COMP_COMMAND_RING_STOPPED:
4265 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4268 case COMP_CONTEXT_STATE_ERROR:
4269 case COMP_SLOT_NOT_ENABLED_ERROR:
4270 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4271 act, udev->slot_id);
4274 case COMP_USB_TRANSACTION_ERROR:
4275 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4277 mutex_unlock(&xhci->mutex);
4278 ret = xhci_disable_slot(xhci, udev->slot_id);
4279 xhci_free_virt_device(xhci, udev->slot_id);
4281 xhci_alloc_dev(hcd, udev);
4282 kfree(command->completion);
4285 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4286 dev_warn(&udev->dev,
4287 "ERROR: Incompatible device for setup %s command\n", act);
4291 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4292 "Successful setup %s command", act);
4296 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4297 act, command->status);
4298 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4304 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4305 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4306 "Op regs DCBAA ptr = %#016llx", temp_64);
4307 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4308 "Slot ID %d dcbaa entry @%p = %#016llx",
4310 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4311 (unsigned long long)
4312 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4313 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4314 "Output Context DMA address = %#08llx",
4315 (unsigned long long)virt_dev->out_ctx->dma);
4316 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4317 le32_to_cpu(slot_ctx->dev_info) >> 27);
4319 * USB core uses address 1 for the roothubs, so we add one to the
4320 * address given back to us by the HC.
4322 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4323 le32_to_cpu(slot_ctx->dev_info) >> 27);
4324 /* Zero the input context control for later use */
4325 ctrl_ctx->add_flags = 0;
4326 ctrl_ctx->drop_flags = 0;
4327 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4328 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4330 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4331 "Internal device address = %d",
4332 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4334 mutex_unlock(&xhci->mutex);
4336 kfree(command->completion);
4342 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4344 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4347 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4349 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4353 * Transfer the port index into real index in the HW port status
4354 * registers. Caculate offset between the port's PORTSC register
4355 * and port status base. Divide the number of per port register
4356 * to get the real index. The raw port number bases 1.
4358 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4360 struct xhci_hub *rhub;
4362 rhub = xhci_get_rhub(hcd);
4363 return rhub->ports[port1 - 1]->hw_portnum + 1;
4367 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4368 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4370 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4371 struct usb_device *udev, u16 max_exit_latency)
4373 struct xhci_virt_device *virt_dev;
4374 struct xhci_command *command;
4375 struct xhci_input_control_ctx *ctrl_ctx;
4376 struct xhci_slot_ctx *slot_ctx;
4377 unsigned long flags;
4380 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4384 spin_lock_irqsave(&xhci->lock, flags);
4386 virt_dev = xhci->devs[udev->slot_id];
4389 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4390 * xHC was re-initialized. Exit latency will be set later after
4391 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4394 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4395 spin_unlock_irqrestore(&xhci->lock, flags);
4399 /* Attempt to issue an Evaluate Context command to change the MEL. */
4400 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4402 spin_unlock_irqrestore(&xhci->lock, flags);
4403 xhci_free_command(xhci, command);
4404 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4409 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4410 spin_unlock_irqrestore(&xhci->lock, flags);
4412 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4413 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4414 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4415 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4416 slot_ctx->dev_state = 0;
4418 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4419 "Set up evaluate context for LPM MEL change.");
4421 /* Issue and wait for the evaluate context command. */
4422 ret = xhci_configure_endpoint(xhci, udev, command,
4426 spin_lock_irqsave(&xhci->lock, flags);
4427 virt_dev->current_mel = max_exit_latency;
4428 spin_unlock_irqrestore(&xhci->lock, flags);
4431 xhci_free_command(xhci, command);
4438 /* BESL to HIRD Encoding array for USB2 LPM */
4439 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4440 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4442 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4443 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4444 struct usb_device *udev)
4446 int u2del, besl, besl_host;
4447 int besl_device = 0;
4450 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4451 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4453 if (field & USB_BESL_SUPPORT) {
4454 for (besl_host = 0; besl_host < 16; besl_host++) {
4455 if (xhci_besl_encoding[besl_host] >= u2del)
4458 /* Use baseline BESL value as default */
4459 if (field & USB_BESL_BASELINE_VALID)
4460 besl_device = USB_GET_BESL_BASELINE(field);
4461 else if (field & USB_BESL_DEEP_VALID)
4462 besl_device = USB_GET_BESL_DEEP(field);
4467 besl_host = (u2del - 51) / 75 + 1;
4470 besl = besl_host + besl_device;
4477 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4478 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4485 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4487 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4488 l1 = udev->l1_params.timeout / 256;
4490 /* device has preferred BESLD */
4491 if (field & USB_BESL_DEEP_VALID) {
4492 besld = USB_GET_BESL_DEEP(field);
4496 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4499 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4500 struct usb_device *udev, int enable)
4502 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4503 struct xhci_port **ports;
4504 __le32 __iomem *pm_addr, *hlpm_addr;
4505 u32 pm_val, hlpm_val, field;
4506 unsigned int port_num;
4507 unsigned long flags;
4508 int hird, exit_latency;
4511 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4514 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4518 if (!udev->parent || udev->parent->parent ||
4519 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4522 if (udev->usb2_hw_lpm_capable != 1)
4525 spin_lock_irqsave(&xhci->lock, flags);
4527 ports = xhci->usb2_rhub.ports;
4528 port_num = udev->portnum - 1;
4529 pm_addr = ports[port_num]->addr + PORTPMSC;
4530 pm_val = readl(pm_addr);
4531 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4533 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4534 enable ? "enable" : "disable", port_num + 1);
4537 /* Host supports BESL timeout instead of HIRD */
4538 if (udev->usb2_hw_lpm_besl_capable) {
4539 /* if device doesn't have a preferred BESL value use a
4540 * default one which works with mixed HIRD and BESL
4541 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4543 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4544 if ((field & USB_BESL_SUPPORT) &&
4545 (field & USB_BESL_BASELINE_VALID))
4546 hird = USB_GET_BESL_BASELINE(field);
4548 hird = udev->l1_params.besl;
4550 exit_latency = xhci_besl_encoding[hird];
4551 spin_unlock_irqrestore(&xhci->lock, flags);
4553 ret = xhci_change_max_exit_latency(xhci, udev,
4557 spin_lock_irqsave(&xhci->lock, flags);
4559 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4560 writel(hlpm_val, hlpm_addr);
4564 hird = xhci_calculate_hird_besl(xhci, udev);
4567 pm_val &= ~PORT_HIRD_MASK;
4568 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4569 writel(pm_val, pm_addr);
4570 pm_val = readl(pm_addr);
4572 writel(pm_val, pm_addr);
4576 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4577 writel(pm_val, pm_addr);
4580 if (udev->usb2_hw_lpm_besl_capable) {
4581 spin_unlock_irqrestore(&xhci->lock, flags);
4582 xhci_change_max_exit_latency(xhci, udev, 0);
4583 readl_poll_timeout(ports[port_num]->addr, pm_val,
4584 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4590 spin_unlock_irqrestore(&xhci->lock, flags);
4594 /* check if a usb2 port supports a given extened capability protocol
4595 * only USB2 ports extended protocol capability values are cached.
4596 * Return 1 if capability is supported
4598 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4599 unsigned capability)
4601 u32 port_offset, port_count;
4604 for (i = 0; i < xhci->num_ext_caps; i++) {
4605 if (xhci->ext_caps[i] & capability) {
4606 /* port offsets starts at 1 */
4607 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4608 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4609 if (port >= port_offset &&
4610 port < port_offset + port_count)
4617 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4619 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4620 int portnum = udev->portnum - 1;
4622 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4625 /* we only support lpm for non-hub device connected to root hub yet */
4626 if (!udev->parent || udev->parent->parent ||
4627 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4630 if (xhci->hw_lpm_support == 1 &&
4631 xhci_check_usb2_port_capability(
4632 xhci, portnum, XHCI_HLC)) {
4633 udev->usb2_hw_lpm_capable = 1;
4634 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4635 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4636 if (xhci_check_usb2_port_capability(xhci, portnum,
4638 udev->usb2_hw_lpm_besl_capable = 1;
4644 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4646 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4647 static unsigned long long xhci_service_interval_to_ns(
4648 struct usb_endpoint_descriptor *desc)
4650 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4653 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4654 enum usb3_link_state state)
4656 unsigned long long sel;
4657 unsigned long long pel;
4658 unsigned int max_sel_pel;
4663 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4664 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4665 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4666 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4670 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4671 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4672 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4676 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4678 return USB3_LPM_DISABLED;
4681 if (sel <= max_sel_pel && pel <= max_sel_pel)
4682 return USB3_LPM_DEVICE_INITIATED;
4684 if (sel > max_sel_pel)
4685 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4686 "due to long SEL %llu ms\n",
4689 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4690 "due to long PEL %llu ms\n",
4692 return USB3_LPM_DISABLED;
4695 /* The U1 timeout should be the maximum of the following values:
4696 * - For control endpoints, U1 system exit latency (SEL) * 3
4697 * - For bulk endpoints, U1 SEL * 5
4698 * - For interrupt endpoints:
4699 * - Notification EPs, U1 SEL * 3
4700 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4701 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4703 static unsigned long long xhci_calculate_intel_u1_timeout(
4704 struct usb_device *udev,
4705 struct usb_endpoint_descriptor *desc)
4707 unsigned long long timeout_ns;
4711 ep_type = usb_endpoint_type(desc);
4713 case USB_ENDPOINT_XFER_CONTROL:
4714 timeout_ns = udev->u1_params.sel * 3;
4716 case USB_ENDPOINT_XFER_BULK:
4717 timeout_ns = udev->u1_params.sel * 5;
4719 case USB_ENDPOINT_XFER_INT:
4720 intr_type = usb_endpoint_interrupt_type(desc);
4721 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4722 timeout_ns = udev->u1_params.sel * 3;
4725 /* Otherwise the calculation is the same as isoc eps */
4727 case USB_ENDPOINT_XFER_ISOC:
4728 timeout_ns = xhci_service_interval_to_ns(desc);
4729 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4730 if (timeout_ns < udev->u1_params.sel * 2)
4731 timeout_ns = udev->u1_params.sel * 2;
4740 /* Returns the hub-encoded U1 timeout value. */
4741 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4742 struct usb_device *udev,
4743 struct usb_endpoint_descriptor *desc)
4745 unsigned long long timeout_ns;
4747 /* Prevent U1 if service interval is shorter than U1 exit latency */
4748 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4749 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4750 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4751 return USB3_LPM_DISABLED;
4755 if (xhci->quirks & XHCI_INTEL_HOST)
4756 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4758 timeout_ns = udev->u1_params.sel;
4760 /* The U1 timeout is encoded in 1us intervals.
4761 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4763 if (timeout_ns == USB3_LPM_DISABLED)
4766 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4768 /* If the necessary timeout value is bigger than what we can set in the
4769 * USB 3.0 hub, we have to disable hub-initiated U1.
4771 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4773 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4774 "due to long timeout %llu ms\n", timeout_ns);
4775 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4778 /* The U2 timeout should be the maximum of:
4779 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4780 * - largest bInterval of any active periodic endpoint (to avoid going
4781 * into lower power link states between intervals).
4782 * - the U2 Exit Latency of the device
4784 static unsigned long long xhci_calculate_intel_u2_timeout(
4785 struct usb_device *udev,
4786 struct usb_endpoint_descriptor *desc)
4788 unsigned long long timeout_ns;
4789 unsigned long long u2_del_ns;
4791 timeout_ns = 10 * 1000 * 1000;
4793 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4794 (xhci_service_interval_to_ns(desc) > timeout_ns))
4795 timeout_ns = xhci_service_interval_to_ns(desc);
4797 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4798 if (u2_del_ns > timeout_ns)
4799 timeout_ns = u2_del_ns;
4804 /* Returns the hub-encoded U2 timeout value. */
4805 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4806 struct usb_device *udev,
4807 struct usb_endpoint_descriptor *desc)
4809 unsigned long long timeout_ns;
4811 /* Prevent U2 if service interval is shorter than U2 exit latency */
4812 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4813 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4814 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4815 return USB3_LPM_DISABLED;
4819 if (xhci->quirks & XHCI_INTEL_HOST)
4820 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4822 timeout_ns = udev->u2_params.sel;
4824 /* The U2 timeout is encoded in 256us intervals */
4825 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4826 /* If the necessary timeout value is bigger than what we can set in the
4827 * USB 3.0 hub, we have to disable hub-initiated U2.
4829 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4831 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4832 "due to long timeout %llu ms\n", timeout_ns);
4833 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4836 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4837 struct usb_device *udev,
4838 struct usb_endpoint_descriptor *desc,
4839 enum usb3_link_state state,
4842 if (state == USB3_LPM_U1)
4843 return xhci_calculate_u1_timeout(xhci, udev, desc);
4844 else if (state == USB3_LPM_U2)
4845 return xhci_calculate_u2_timeout(xhci, udev, desc);
4847 return USB3_LPM_DISABLED;
4850 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4851 struct usb_device *udev,
4852 struct usb_endpoint_descriptor *desc,
4853 enum usb3_link_state state,
4858 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4859 desc, state, timeout);
4861 /* If we found we can't enable hub-initiated LPM, and
4862 * the U1 or U2 exit latency was too high to allow
4863 * device-initiated LPM as well, then we will disable LPM
4864 * for this device, so stop searching any further.
4866 if (alt_timeout == USB3_LPM_DISABLED) {
4867 *timeout = alt_timeout;
4870 if (alt_timeout > *timeout)
4871 *timeout = alt_timeout;
4875 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4876 struct usb_device *udev,
4877 struct usb_host_interface *alt,
4878 enum usb3_link_state state,
4883 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4884 if (xhci_update_timeout_for_endpoint(xhci, udev,
4885 &alt->endpoint[j].desc, state, timeout))
4891 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4892 enum usb3_link_state state)
4894 struct usb_device *parent;
4895 unsigned int num_hubs;
4897 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4898 for (parent = udev->parent, num_hubs = 0; parent->parent;
4899 parent = parent->parent)
4905 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4906 " below second-tier hub.\n");
4907 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4908 "to decrease power consumption.\n");
4912 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4913 struct usb_device *udev,
4914 enum usb3_link_state state)
4916 if (xhci->quirks & XHCI_INTEL_HOST)
4917 return xhci_check_intel_tier_policy(udev, state);
4922 /* Returns the U1 or U2 timeout that should be enabled.
4923 * If the tier check or timeout setting functions return with a non-zero exit
4924 * code, that means the timeout value has been finalized and we shouldn't look
4925 * at any more endpoints.
4927 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4928 struct usb_device *udev, enum usb3_link_state state)
4930 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4931 struct usb_host_config *config;
4934 u16 timeout = USB3_LPM_DISABLED;
4936 if (state == USB3_LPM_U1)
4938 else if (state == USB3_LPM_U2)
4941 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4946 /* Gather some information about the currently installed configuration
4947 * and alternate interface settings.
4949 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4953 config = udev->actconfig;
4957 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4958 struct usb_driver *driver;
4959 struct usb_interface *intf = config->interface[i];
4964 /* Check if any currently bound drivers want hub-initiated LPM
4967 if (intf->dev.driver) {
4968 driver = to_usb_driver(intf->dev.driver);
4969 if (driver && driver->disable_hub_initiated_lpm) {
4970 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4971 state_name, driver->name);
4972 timeout = xhci_get_timeout_no_hub_lpm(udev,
4974 if (timeout == USB3_LPM_DISABLED)
4979 /* Not sure how this could happen... */
4980 if (!intf->cur_altsetting)
4983 if (xhci_update_timeout_for_interface(xhci, udev,
4984 intf->cur_altsetting,
4991 static int calculate_max_exit_latency(struct usb_device *udev,
4992 enum usb3_link_state state_changed,
4993 u16 hub_encoded_timeout)
4995 unsigned long long u1_mel_us = 0;
4996 unsigned long long u2_mel_us = 0;
4997 unsigned long long mel_us = 0;
5003 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5004 hub_encoded_timeout == USB3_LPM_DISABLED);
5005 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5006 hub_encoded_timeout == USB3_LPM_DISABLED);
5008 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5009 hub_encoded_timeout != USB3_LPM_DISABLED);
5010 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5011 hub_encoded_timeout != USB3_LPM_DISABLED);
5013 /* If U1 was already enabled and we're not disabling it,
5014 * or we're going to enable U1, account for the U1 max exit latency.
5016 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5018 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5019 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5021 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5023 mel_us = max(u1_mel_us, u2_mel_us);
5025 /* xHCI host controller max exit latency field is only 16 bits wide. */
5026 if (mel_us > MAX_EXIT) {
5027 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5028 "is too big.\n", mel_us);
5034 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5035 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5036 struct usb_device *udev, enum usb3_link_state state)
5038 struct xhci_hcd *xhci;
5039 u16 hub_encoded_timeout;
5043 xhci = hcd_to_xhci(hcd);
5044 /* The LPM timeout values are pretty host-controller specific, so don't
5045 * enable hub-initiated timeouts unless the vendor has provided
5046 * information about their timeout algorithm.
5048 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5049 !xhci->devs[udev->slot_id])
5050 return USB3_LPM_DISABLED;
5052 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5053 return USB3_LPM_DISABLED;
5055 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5056 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5058 /* Max Exit Latency is too big, disable LPM. */
5059 hub_encoded_timeout = USB3_LPM_DISABLED;
5063 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5066 return hub_encoded_timeout;
5069 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5070 struct usb_device *udev, enum usb3_link_state state)
5072 struct xhci_hcd *xhci;
5075 xhci = hcd_to_xhci(hcd);
5076 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5077 !xhci->devs[udev->slot_id])
5080 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5081 return xhci_change_max_exit_latency(xhci, udev, mel);
5083 #else /* CONFIG_PM */
5085 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5086 struct usb_device *udev, int enable)
5091 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5096 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5097 struct usb_device *udev, enum usb3_link_state state)
5099 return USB3_LPM_DISABLED;
5102 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5103 struct usb_device *udev, enum usb3_link_state state)
5107 #endif /* CONFIG_PM */
5109 /*-------------------------------------------------------------------------*/
5111 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5112 * internal data structures for the device.
5114 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5115 struct usb_tt *tt, gfp_t mem_flags)
5117 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5118 struct xhci_virt_device *vdev;
5119 struct xhci_command *config_cmd;
5120 struct xhci_input_control_ctx *ctrl_ctx;
5121 struct xhci_slot_ctx *slot_ctx;
5122 unsigned long flags;
5123 unsigned think_time;
5126 /* Ignore root hubs */
5130 vdev = xhci->devs[hdev->slot_id];
5132 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5136 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5140 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5142 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5144 xhci_free_command(xhci, config_cmd);
5148 spin_lock_irqsave(&xhci->lock, flags);
5149 if (hdev->speed == USB_SPEED_HIGH &&
5150 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5151 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5152 xhci_free_command(xhci, config_cmd);
5153 spin_unlock_irqrestore(&xhci->lock, flags);
5157 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5158 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5159 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5160 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5162 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5163 * but it may be already set to 1 when setup an xHCI virtual
5164 * device, so clear it anyway.
5167 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5168 else if (hdev->speed == USB_SPEED_FULL)
5169 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5171 if (xhci->hci_version > 0x95) {
5172 xhci_dbg(xhci, "xHCI version %x needs hub "
5173 "TT think time and number of ports\n",
5174 (unsigned int) xhci->hci_version);
5175 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5176 /* Set TT think time - convert from ns to FS bit times.
5177 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5178 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5180 * xHCI 1.0: this field shall be 0 if the device is not a
5183 think_time = tt->think_time;
5184 if (think_time != 0)
5185 think_time = (think_time / 666) - 1;
5186 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5187 slot_ctx->tt_info |=
5188 cpu_to_le32(TT_THINK_TIME(think_time));
5190 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5191 "TT think time or number of ports\n",
5192 (unsigned int) xhci->hci_version);
5194 slot_ctx->dev_state = 0;
5195 spin_unlock_irqrestore(&xhci->lock, flags);
5197 xhci_dbg(xhci, "Set up %s for hub device.\n",
5198 (xhci->hci_version > 0x95) ?
5199 "configure endpoint" : "evaluate context");
5201 /* Issue and wait for the configure endpoint or
5202 * evaluate context command.
5204 if (xhci->hci_version > 0x95)
5205 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5208 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5211 xhci_free_command(xhci, config_cmd);
5215 static int xhci_get_frame(struct usb_hcd *hcd)
5217 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5218 /* EHCI mods by the periodic size. Why? */
5219 return readl(&xhci->run_regs->microframe_index) >> 3;
5222 static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5224 xhci->usb2_rhub.hcd = hcd;
5225 hcd->speed = HCD_USB2;
5226 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5228 * USB 2.0 roothub under xHCI has an integrated TT,
5229 * (rate matching hub) as opposed to having an OHCI/UHCI
5230 * companion controller.
5235 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5237 unsigned int minor_rev;
5240 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5241 * should return 0x31 for sbrn, or that the minor revision
5242 * is a two digit BCD containig minor and sub-minor numbers.
5243 * This was later clarified in xHCI 1.2.
5245 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5246 * minor revision set to 0x1 instead of 0x10.
5248 if (xhci->usb3_rhub.min_rev == 0x1)
5251 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5253 switch (minor_rev) {
5255 hcd->speed = HCD_USB32;
5256 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5257 hcd->self.root_hub->rx_lanes = 2;
5258 hcd->self.root_hub->tx_lanes = 2;
5259 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5262 hcd->speed = HCD_USB31;
5263 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5264 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5267 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5268 minor_rev, minor_rev ? "Enhanced " : "");
5270 xhci->usb3_rhub.hcd = hcd;
5273 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5275 struct xhci_hcd *xhci;
5277 * TODO: Check with DWC3 clients for sysdev according to
5280 struct device *dev = hcd->self.sysdev;
5283 /* Accept arbitrarily long scatter-gather lists */
5284 hcd->self.sg_tablesize = ~0;
5286 /* support to build packet from discontinuous buffers */
5287 hcd->self.no_sg_constraint = 1;
5289 /* XHCI controllers don't stop the ep queue on short packets :| */
5290 hcd->self.no_stop_on_short = 1;
5292 xhci = hcd_to_xhci(hcd);
5294 if (!usb_hcd_is_primary_hcd(hcd)) {
5295 xhci_hcd_init_usb3_data(xhci, hcd);
5299 mutex_init(&xhci->mutex);
5300 xhci->main_hcd = hcd;
5301 xhci->cap_regs = hcd->regs;
5302 xhci->op_regs = hcd->regs +
5303 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5304 xhci->run_regs = hcd->regs +
5305 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5306 /* Cache read-only capability registers */
5307 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5308 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5309 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5310 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5311 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5312 if (xhci->hci_version > 0x100)
5313 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5315 xhci->quirks |= quirks;
5317 get_quirks(dev, xhci);
5319 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5320 * success event after a short transfer. This quirk will ignore such
5323 if (xhci->hci_version > 0x96)
5324 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5326 /* Make sure the HC is halted. */
5327 retval = xhci_halt(xhci);
5331 xhci_zero_64b_regs(xhci);
5333 xhci_dbg(xhci, "Resetting HCD\n");
5334 /* Reset the internal HC memory state and registers. */
5335 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5338 xhci_dbg(xhci, "Reset complete\n");
5341 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5342 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5343 * address memory pointers actually. So, this driver clears the AC64
5344 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5345 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5347 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5348 xhci->hcc_params &= ~BIT(0);
5350 /* Set dma_mask and coherent_dma_mask to 64-bits,
5351 * if xHC supports 64-bit addressing */
5352 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5353 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5354 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5355 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5358 * This is to avoid error in cases where a 32-bit USB
5359 * controller is used on a 64-bit capable system.
5361 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5364 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5365 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5368 xhci_dbg(xhci, "Calling HCD init\n");
5369 /* Initialize HCD and host controller data structures. */
5370 retval = xhci_init(hcd);
5373 xhci_dbg(xhci, "Called HCD init\n");
5375 if (xhci_hcd_is_usb3(hcd))
5376 xhci_hcd_init_usb3_data(xhci, hcd);
5378 xhci_hcd_init_usb2_data(xhci, hcd);
5380 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5381 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5385 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5387 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5388 struct usb_host_endpoint *ep)
5390 struct xhci_hcd *xhci;
5391 struct usb_device *udev;
5392 unsigned int slot_id;
5393 unsigned int ep_index;
5394 unsigned long flags;
5396 xhci = hcd_to_xhci(hcd);
5398 spin_lock_irqsave(&xhci->lock, flags);
5399 udev = (struct usb_device *)ep->hcpriv;
5400 slot_id = udev->slot_id;
5401 ep_index = xhci_get_endpoint_index(&ep->desc);
5403 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5404 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5405 spin_unlock_irqrestore(&xhci->lock, flags);
5408 static const struct hc_driver xhci_hc_driver = {
5409 .description = "xhci-hcd",
5410 .product_desc = "xHCI Host Controller",
5411 .hcd_priv_size = sizeof(struct xhci_hcd),
5414 * generic hardware linkage
5417 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5421 * basic lifecycle operations
5423 .reset = NULL, /* set in xhci_init_driver() */
5426 .shutdown = xhci_shutdown,
5429 * managing i/o requests and associated device resources
5431 .map_urb_for_dma = xhci_map_urb_for_dma,
5432 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5433 .urb_enqueue = xhci_urb_enqueue,
5434 .urb_dequeue = xhci_urb_dequeue,
5435 .alloc_dev = xhci_alloc_dev,
5436 .free_dev = xhci_free_dev,
5437 .alloc_streams = xhci_alloc_streams,
5438 .free_streams = xhci_free_streams,
5439 .add_endpoint = xhci_add_endpoint,
5440 .drop_endpoint = xhci_drop_endpoint,
5441 .endpoint_disable = xhci_endpoint_disable,
5442 .endpoint_reset = xhci_endpoint_reset,
5443 .check_bandwidth = xhci_check_bandwidth,
5444 .reset_bandwidth = xhci_reset_bandwidth,
5445 .address_device = xhci_address_device,
5446 .enable_device = xhci_enable_device,
5447 .update_hub_device = xhci_update_hub_device,
5448 .reset_device = xhci_discover_or_reset_device,
5451 * scheduling support
5453 .get_frame_number = xhci_get_frame,
5458 .hub_control = xhci_hub_control,
5459 .hub_status_data = xhci_hub_status_data,
5460 .bus_suspend = xhci_bus_suspend,
5461 .bus_resume = xhci_bus_resume,
5462 .get_resuming_ports = xhci_get_resuming_ports,
5465 * call back when device connected and addressed
5467 .update_device = xhci_update_device,
5468 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5469 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5470 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5471 .find_raw_port_number = xhci_find_raw_port_number,
5472 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5475 void xhci_init_driver(struct hc_driver *drv,
5476 const struct xhci_driver_overrides *over)
5480 /* Copy the generic table to drv then apply the overrides */
5481 *drv = xhci_hc_driver;
5484 drv->hcd_priv_size += over->extra_priv_size;
5486 drv->reset = over->reset;
5488 drv->start = over->start;
5489 if (over->add_endpoint)
5490 drv->add_endpoint = over->add_endpoint;
5491 if (over->drop_endpoint)
5492 drv->drop_endpoint = over->drop_endpoint;
5493 if (over->check_bandwidth)
5494 drv->check_bandwidth = over->check_bandwidth;
5495 if (over->reset_bandwidth)
5496 drv->reset_bandwidth = over->reset_bandwidth;
5499 EXPORT_SYMBOL_GPL(xhci_init_driver);
5501 MODULE_DESCRIPTION(DRIVER_DESC);
5502 MODULE_AUTHOR(DRIVER_AUTHOR);
5503 MODULE_LICENSE("GPL");
5505 static int __init xhci_hcd_init(void)
5508 * Check the compiler generated sizes of structures that must be laid
5509 * out in specific ways for hardware access.
5511 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5512 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5513 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5514 /* xhci_device_control has eight fields, and also
5515 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5517 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5518 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5519 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5520 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5521 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5522 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5523 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5528 xhci_debugfs_create_root();
5535 * If an init function is provided, an exit function must also be provided
5536 * to allow module unload.
5538 static void __exit xhci_hcd_fini(void)
5540 xhci_debugfs_remove_root();
5544 module_init(xhci_hcd_init);
5545 module_exit(xhci_hcd_fini);