1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/log2.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/slab.h>
19 #include <linux/dmi.h>
20 #include <linux/dma-mapping.h>
23 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
115 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
118 ret = xhci_handshake(&xhci->op_regs->status,
119 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
121 xhci_warn(xhci, "Host halt failed, %d\n", ret);
125 xhci->xhc_state |= XHCI_STATE_HALTED;
126 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
132 * Set the run bit and wait for the host to be running.
134 int xhci_start(struct xhci_hcd *xhci)
139 temp = readl(&xhci->op_regs->command);
141 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
143 writel(temp, &xhci->op_regs->command);
146 * Wait for the HCHalted Status bit to be 0 to indicate the host is
149 ret = xhci_handshake(&xhci->op_regs->status,
150 STS_HALT, 0, XHCI_MAX_HALT_USEC);
151 if (ret == -ETIMEDOUT)
152 xhci_err(xhci, "Host took too long to start, "
153 "waited %u microseconds.\n",
156 /* clear state flags. Including dying, halted or removing */
158 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
167 * This resets pipelines, timers, counters, state machines, etc.
168 * Transactions will be terminated immediately, and operational registers
169 * will be set to their defaults.
171 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
177 state = readl(&xhci->op_regs->status);
179 if (state == ~(u32)0) {
180 xhci_warn(xhci, "Host not accessible, reset failed.\n");
184 if ((state & STS_HALT) == 0) {
185 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
189 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
190 command = readl(&xhci->op_regs->command);
191 command |= CMD_RESET;
192 writel(command, &xhci->op_regs->command);
194 /* Existing Intel xHCI controllers require a delay of 1 mS,
195 * after setting the CMD_RESET bit, and before accessing any
196 * HC registers. This allows the HC to complete the
197 * reset operation and be ready for HC register access.
198 * Without this delay, the subsequent HC register access,
199 * may result in a system hang very rarely.
201 if (xhci->quirks & XHCI_INTEL_HOST)
204 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
208 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
209 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
211 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
212 "Wait for controller to be ready for doorbell rings");
214 * xHCI cannot write to any doorbells or operational registers other
215 * than status until the "Controller Not Ready" flag is cleared.
217 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
219 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb2_rhub.bus_state.suspended_ports = 0;
221 xhci->usb2_rhub.bus_state.resuming_ports = 0;
222 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
223 xhci->usb3_rhub.bus_state.suspended_ports = 0;
224 xhci->usb3_rhub.bus_state.resuming_ports = 0;
229 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
231 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
232 struct iommu_domain *domain;
238 * Some Renesas controllers get into a weird state if they are
239 * reset while programmed with 64bit addresses (they will preserve
240 * the top half of the address in internal, non visible
241 * registers). You end up with half the address coming from the
242 * kernel, and the other half coming from the firmware. Also,
243 * changing the programming leads to extra accesses even if the
244 * controller is supposed to be halted. The controller ends up with
245 * a fatal fault, and is then ripe for being properly reset.
247 * Special care is taken to only apply this if the device is behind
248 * an iommu. Doing anything when there is no iommu is definitely
251 domain = iommu_get_domain_for_dev(dev);
252 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
253 domain->type == IOMMU_DOMAIN_IDENTITY)
256 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
258 /* Clear HSEIE so that faults do not get signaled */
259 val = readl(&xhci->op_regs->command);
261 writel(val, &xhci->op_regs->command);
263 /* Clear HSE (aka FATAL) */
264 val = readl(&xhci->op_regs->status);
266 writel(val, &xhci->op_regs->status);
268 /* Now zero the registers, and brace for impact */
269 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
270 if (upper_32_bits(val))
271 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
272 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
273 if (upper_32_bits(val))
274 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
276 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
277 ARRAY_SIZE(xhci->run_regs->ir_set));
279 for (i = 0; i < intrs; i++) {
280 struct xhci_intr_reg __iomem *ir;
282 ir = &xhci->run_regs->ir_set[i];
283 val = xhci_read_64(xhci, &ir->erst_base);
284 if (upper_32_bits(val))
285 xhci_write_64(xhci, 0, &ir->erst_base);
286 val= xhci_read_64(xhci, &ir->erst_dequeue);
287 if (upper_32_bits(val))
288 xhci_write_64(xhci, 0, &ir->erst_dequeue);
291 /* Wait for the fault to appear. It will be cleared on reset */
292 err = xhci_handshake(&xhci->op_regs->status,
293 STS_FATAL, STS_FATAL,
296 xhci_info(xhci, "Fault detected\n");
299 static int xhci_enable_interrupter(struct xhci_interrupter *ir)
303 if (!ir || !ir->ir_set)
306 iman = readl(&ir->ir_set->irq_pending);
307 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
312 static int xhci_disable_interrupter(struct xhci_interrupter *ir)
316 if (!ir || !ir->ir_set)
319 iman = readl(&ir->ir_set->irq_pending);
320 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
325 #ifdef CONFIG_USB_PCI
329 static int xhci_setup_msi(struct xhci_hcd *xhci)
333 * TODO:Check with MSI Soc for sysdev
335 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
337 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
339 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
340 "failed to allocate MSI entry");
344 ret = request_irq(pdev->irq, xhci_msi_irq,
345 0, "xhci_hcd", xhci_to_hcd(xhci));
347 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
348 "disable MSI interrupt");
349 pci_free_irq_vectors(pdev);
358 static int xhci_setup_msix(struct xhci_hcd *xhci)
361 struct usb_hcd *hcd = xhci_to_hcd(xhci);
362 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
365 * calculate number of msi-x vectors supported.
366 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
367 * with max number of interrupters based on the xhci HCSPARAMS1.
368 * - num_online_cpus: maximum msi-x vectors per CPUs core.
369 * Add additional 1 vector to ensure always available interrupt.
371 xhci->msix_count = min(num_online_cpus() + 1,
372 HCS_MAX_INTRS(xhci->hcs_params1));
374 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
377 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
378 "Failed to enable MSI-X");
382 for (i = 0; i < xhci->msix_count; i++) {
383 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
384 "xhci_hcd", xhci_to_hcd(xhci));
389 hcd->msix_enabled = 1;
393 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
395 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
396 pci_free_irq_vectors(pdev);
400 /* Free any IRQs and disable MSI-X */
401 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
403 struct usb_hcd *hcd = xhci_to_hcd(xhci);
404 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
406 if (xhci->quirks & XHCI_PLAT)
409 /* return if using legacy interrupt */
413 if (hcd->msix_enabled) {
416 for (i = 0; i < xhci->msix_count; i++)
417 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
419 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
422 pci_free_irq_vectors(pdev);
423 hcd->msix_enabled = 0;
426 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
428 struct usb_hcd *hcd = xhci_to_hcd(xhci);
430 if (hcd->msix_enabled) {
431 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
434 for (i = 0; i < xhci->msix_count; i++)
435 synchronize_irq(pci_irq_vector(pdev, i));
439 static int xhci_try_enable_msi(struct usb_hcd *hcd)
441 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
442 struct pci_dev *pdev;
445 /* The xhci platform device has set up IRQs through usb_add_hcd. */
446 if (xhci->quirks & XHCI_PLAT)
449 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
451 * Some Fresco Logic host controllers advertise MSI, but fail to
452 * generate interrupts. Don't even try to enable MSI.
454 if (xhci->quirks & XHCI_BROKEN_MSI)
457 /* unregister the legacy interrupt */
459 free_irq(hcd->irq, hcd);
462 ret = xhci_setup_msix(xhci);
464 /* fall back to msi*/
465 ret = xhci_setup_msi(xhci);
468 hcd->msi_enabled = 1;
473 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
478 if (!strlen(hcd->irq_descr))
479 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
480 hcd->driver->description, hcd->self.busnum);
482 /* fall back to legacy interrupt*/
483 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
484 hcd->irq_descr, hcd);
486 xhci_err(xhci, "request interrupt %d failed\n",
490 hcd->irq = pdev->irq;
496 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
501 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
505 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
511 static void compliance_mode_recovery(struct timer_list *t)
513 struct xhci_hcd *xhci;
515 struct xhci_hub *rhub;
519 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
520 rhub = &xhci->usb3_rhub;
526 for (i = 0; i < rhub->num_ports; i++) {
527 temp = readl(rhub->ports[i]->addr);
528 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
530 * Compliance Mode Detected. Letting USB Core
531 * handle the Warm Reset
533 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
534 "Compliance mode detected->port %d",
536 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
537 "Attempting compliance mode recovery");
539 if (hcd->state == HC_STATE_SUSPENDED)
540 usb_hcd_resume_root_hub(hcd);
542 usb_hcd_poll_rh_status(hcd);
546 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
547 mod_timer(&xhci->comp_mode_recovery_timer,
548 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
552 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
553 * that causes ports behind that hardware to enter compliance mode sometimes.
554 * The quirk creates a timer that polls every 2 seconds the link state of
555 * each host controller's port and recovers it by issuing a Warm reset
556 * if Compliance mode is detected, otherwise the port will become "dead" (no
557 * device connections or disconnections will be detected anymore). Becasue no
558 * status event is generated when entering compliance mode (per xhci spec),
559 * this quirk is needed on systems that have the failing hardware installed.
561 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
563 xhci->port_status_u0 = 0;
564 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
566 xhci->comp_mode_recovery_timer.expires = jiffies +
567 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
569 add_timer(&xhci->comp_mode_recovery_timer);
570 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
571 "Compliance mode recovery timer initialized");
575 * This function identifies the systems that have installed the SN65LVPE502CP
576 * USB3.0 re-driver and that need the Compliance Mode Quirk.
578 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
580 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
582 const char *dmi_product_name, *dmi_sys_vendor;
584 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
585 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
586 if (!dmi_product_name || !dmi_sys_vendor)
589 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
592 if (strstr(dmi_product_name, "Z420") ||
593 strstr(dmi_product_name, "Z620") ||
594 strstr(dmi_product_name, "Z820") ||
595 strstr(dmi_product_name, "Z1 Workstation"))
601 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
603 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
608 * Initialize memory for HCD and xHC (one-time init).
610 * Program the PAGESIZE register, initialize the device context array, create
611 * device contexts (?), set up a command ring segment (or two?), create event
612 * ring (one for now).
614 static int xhci_init(struct usb_hcd *hcd)
616 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
619 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
620 spin_lock_init(&xhci->lock);
621 if (xhci->hci_version == 0x95 && link_quirk) {
622 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
623 "QUIRK: Not clearing Link TRB chain bits.");
624 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
626 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
627 "xHCI doesn't need link TRB QUIRK");
629 retval = xhci_mem_init(xhci, GFP_KERNEL);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
632 /* Initializing Compliance Mode Recovery Data If Needed */
633 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
634 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
635 compliance_mode_recovery_timer_init(xhci);
641 /*-------------------------------------------------------------------------*/
643 static int xhci_run_finished(struct xhci_hcd *xhci)
645 struct xhci_interrupter *ir = xhci->interrupter;
650 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
651 * Protect the short window before host is running with a lock
653 spin_lock_irqsave(&xhci->lock, flags);
655 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
656 temp = readl(&xhci->op_regs->command);
658 writel(temp, &xhci->op_regs->command);
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
661 xhci_enable_interrupter(ir);
663 if (xhci_start(xhci)) {
665 spin_unlock_irqrestore(&xhci->lock, flags);
669 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
671 if (xhci->quirks & XHCI_NEC_HOST)
672 xhci_ring_cmd_db(xhci);
674 spin_unlock_irqrestore(&xhci->lock, flags);
680 * Start the HC after it was halted.
682 * This function is called by the USB core when the HC driver is added.
683 * Its opposite is xhci_stop().
685 * xhci_init() must be called once before this function can be called.
686 * Reset the HC, enable device slot contexts, program DCBAAP, and
687 * set command ring pointer and event ring pointer.
689 * Setup MSI-X vectors and enable interrupts.
691 int xhci_run(struct usb_hcd *hcd)
696 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
697 struct xhci_interrupter *ir = xhci->interrupter;
698 /* Start the xHCI host controller running only after the USB 2.0 roothub
702 hcd->uses_new_polling = 1;
703 if (!usb_hcd_is_primary_hcd(hcd))
704 return xhci_run_finished(xhci);
706 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
708 ret = xhci_try_enable_msi(hcd);
712 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
713 temp_64 &= ~ERST_PTR_MASK;
714 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
715 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Set the interrupt modulation register");
719 temp = readl(&ir->ir_set->irq_control);
720 temp &= ~ER_IRQ_INTERVAL_MASK;
721 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
722 writel(temp, &ir->ir_set->irq_control);
724 if (xhci->quirks & XHCI_NEC_HOST) {
725 struct xhci_command *command;
727 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
731 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
732 TRB_TYPE(TRB_NEC_GET_FW));
734 xhci_free_command(xhci, command);
736 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
737 "Finished %s for main hcd", __func__);
739 xhci_create_dbc_dev(xhci);
741 xhci_debugfs_init(xhci);
743 if (xhci_has_one_roothub(xhci))
744 return xhci_run_finished(xhci);
746 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
750 EXPORT_SYMBOL_GPL(xhci_run);
755 * This function is called by the USB core when the HC driver is removed.
756 * Its opposite is xhci_run().
758 * Disable device contexts, disable IRQs, and quiesce the HC.
759 * Reset the HC, finish any completed transactions, and cleanup memory.
761 static void xhci_stop(struct usb_hcd *hcd)
764 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
765 struct xhci_interrupter *ir = xhci->interrupter;
767 mutex_lock(&xhci->mutex);
769 /* Only halt host and free memory after both hcds are removed */
770 if (!usb_hcd_is_primary_hcd(hcd)) {
771 mutex_unlock(&xhci->mutex);
775 xhci_remove_dbc_dev(xhci);
777 spin_lock_irq(&xhci->lock);
778 xhci->xhc_state |= XHCI_STATE_HALTED;
779 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
781 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
782 spin_unlock_irq(&xhci->lock);
784 xhci_cleanup_msix(xhci);
786 /* Deleting Compliance Mode Recovery Timer */
787 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
788 (!(xhci_all_ports_seen_u0(xhci)))) {
789 del_timer_sync(&xhci->comp_mode_recovery_timer);
790 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
791 "%s: compliance mode recovery timer deleted",
795 if (xhci->quirks & XHCI_AMD_PLL_FIX)
798 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
799 "// Disabling event ring interrupts");
800 temp = readl(&xhci->op_regs->status);
801 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
802 xhci_disable_interrupter(ir);
804 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
805 xhci_mem_cleanup(xhci);
806 xhci_debugfs_exit(xhci);
807 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
808 "xhci_stop completed - status = %x",
809 readl(&xhci->op_regs->status));
810 mutex_unlock(&xhci->mutex);
814 * Shutdown HC (not bus-specific)
816 * This is called when the machine is rebooting or halting. We assume that the
817 * machine will be powered off, and the HC's internal state will be reset.
818 * Don't bother to free memory.
820 * This will only ever be called with the main usb_hcd (the USB3 roothub).
822 void xhci_shutdown(struct usb_hcd *hcd)
824 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
826 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
827 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
829 /* Don't poll the roothubs after shutdown. */
830 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
831 __func__, hcd->self.busnum);
832 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
833 del_timer_sync(&hcd->rh_timer);
835 if (xhci->shared_hcd) {
836 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
837 del_timer_sync(&xhci->shared_hcd->rh_timer);
840 spin_lock_irq(&xhci->lock);
844 * Workaround for spurious wakeps at shutdown with HSW, and for boot
845 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
847 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
848 xhci->quirks & XHCI_RESET_TO_DEFAULT)
849 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
851 spin_unlock_irq(&xhci->lock);
853 xhci_cleanup_msix(xhci);
855 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
856 "xhci_shutdown completed - status = %x",
857 readl(&xhci->op_regs->status));
859 EXPORT_SYMBOL_GPL(xhci_shutdown);
862 static void xhci_save_registers(struct xhci_hcd *xhci)
864 struct xhci_interrupter *ir = xhci->interrupter;
866 xhci->s3.command = readl(&xhci->op_regs->command);
867 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
868 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
869 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
874 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
875 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
876 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
877 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
878 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
881 static void xhci_restore_registers(struct xhci_hcd *xhci)
883 struct xhci_interrupter *ir = xhci->interrupter;
885 writel(xhci->s3.command, &xhci->op_regs->command);
886 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
887 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
888 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
889 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
890 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
891 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
892 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
893 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
896 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
900 /* step 2: initialize command ring buffer */
901 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
902 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
903 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
904 xhci->cmd_ring->dequeue) &
905 (u64) ~CMD_RING_RSVD_BITS) |
906 xhci->cmd_ring->cycle_state;
907 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
908 "// Setting command ring address to 0x%llx",
909 (long unsigned long) val_64);
910 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
914 * The whole command ring must be cleared to zero when we suspend the host.
916 * The host doesn't save the command ring pointer in the suspend well, so we
917 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
918 * aligned, because of the reserved bits in the command ring dequeue pointer
919 * register. Therefore, we can't just set the dequeue pointer back in the
920 * middle of the ring (TRBs are 16-byte aligned).
922 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
924 struct xhci_ring *ring;
925 struct xhci_segment *seg;
927 ring = xhci->cmd_ring;
931 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
932 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
933 cpu_to_le32(~TRB_CYCLE);
935 } while (seg != ring->deq_seg);
937 /* Reset the software enqueue and dequeue pointers */
938 ring->deq_seg = ring->first_seg;
939 ring->dequeue = ring->first_seg->trbs;
940 ring->enq_seg = ring->deq_seg;
941 ring->enqueue = ring->dequeue;
943 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
945 * Ring is now zeroed, so the HW should look for change of ownership
946 * when the cycle bit is set to 1.
948 ring->cycle_state = 1;
951 * Reset the hardware dequeue pointer.
952 * Yes, this will need to be re-written after resume, but we're paranoid
953 * and want to make sure the hardware doesn't access bogus memory
954 * because, say, the BIOS or an SMI started the host without changing
955 * the command ring pointers.
957 xhci_set_cmd_ring_deq(xhci);
961 * Disable port wake bits if do_wakeup is not set.
963 * Also clear a possible internal port wake state left hanging for ports that
964 * detected termination but never successfully enumerated (trained to 0U).
965 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
966 * at enumeration clears this wake, force one here as well for unconnected ports
969 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
970 struct xhci_hub *rhub,
977 spin_lock_irqsave(&xhci->lock, flags);
979 for (i = 0; i < rhub->num_ports; i++) {
980 portsc = readl(rhub->ports[i]->addr);
981 t1 = xhci_port_state_to_neutral(portsc);
984 /* clear wake bits if do_wake is not set */
986 t2 &= ~PORT_WAKE_BITS;
988 /* Don't touch csc bit if connected or connect change is set */
989 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
993 writel(t2, rhub->ports[i]->addr);
994 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
995 rhub->hcd->self.busnum, i + 1, portsc, t2);
998 spin_unlock_irqrestore(&xhci->lock, flags);
1001 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
1003 struct xhci_port **ports;
1008 status = readl(&xhci->op_regs->status);
1009 if (status & STS_EINT)
1012 * Checking STS_EINT is not enough as there is a lag between a change
1013 * bit being set and the Port Status Change Event that it generated
1014 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
1017 port_index = xhci->usb2_rhub.num_ports;
1018 ports = xhci->usb2_rhub.ports;
1019 while (port_index--) {
1020 portsc = readl(ports[port_index]->addr);
1021 if (portsc & PORT_CHANGE_MASK ||
1022 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
1025 port_index = xhci->usb3_rhub.num_ports;
1026 ports = xhci->usb3_rhub.ports;
1027 while (port_index--) {
1028 portsc = readl(ports[port_index]->addr);
1029 if (portsc & PORT_CHANGE_MASK ||
1030 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
1037 * Stop HC (not bus-specific)
1039 * This is called when the machine transition into S3/S4 mode.
1042 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1045 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1046 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1053 if (hcd->state != HC_STATE_SUSPENDED ||
1054 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1057 /* Clear root port wake on bits if wakeup not allowed. */
1058 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1059 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1061 if (!HCD_HW_ACCESSIBLE(hcd))
1064 xhci_dbc_suspend(xhci);
1066 /* Don't poll the roothubs on bus suspend. */
1067 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1068 __func__, hcd->self.busnum);
1069 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1070 del_timer_sync(&hcd->rh_timer);
1071 if (xhci->shared_hcd) {
1072 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1073 del_timer_sync(&xhci->shared_hcd->rh_timer);
1076 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1077 usleep_range(1000, 1500);
1079 spin_lock_irq(&xhci->lock);
1080 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1081 if (xhci->shared_hcd)
1082 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1083 /* step 1: stop endpoint */
1084 /* skipped assuming that port suspend has done */
1086 /* step 2: clear Run/Stop bit */
1087 command = readl(&xhci->op_regs->command);
1088 command &= ~CMD_RUN;
1089 writel(command, &xhci->op_regs->command);
1091 /* Some chips from Fresco Logic need an extraordinary delay */
1092 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1094 if (xhci_handshake(&xhci->op_regs->status,
1095 STS_HALT, STS_HALT, delay)) {
1096 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1097 spin_unlock_irq(&xhci->lock);
1100 xhci_clear_command_ring(xhci);
1102 /* step 3: save registers */
1103 xhci_save_registers(xhci);
1105 /* step 4: set CSS flag */
1106 command = readl(&xhci->op_regs->command);
1108 writel(command, &xhci->op_regs->command);
1109 xhci->broken_suspend = 0;
1110 if (xhci_handshake(&xhci->op_regs->status,
1111 STS_SAVE, 0, 20 * 1000)) {
1113 * AMD SNPS xHC 3.0 occasionally does not clear the
1114 * SSS bit of USBSTS and when driver tries to poll
1115 * to see if the xHC clears BIT(8) which never happens
1116 * and driver assumes that controller is not responding
1117 * and times out. To workaround this, its good to check
1118 * if SRE and HCE bits are not set (as per xhci
1119 * Section 5.4.2) and bypass the timeout.
1121 res = readl(&xhci->op_regs->status);
1122 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1123 (((res & STS_SRE) == 0) &&
1124 ((res & STS_HCE) == 0))) {
1125 xhci->broken_suspend = 1;
1127 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1128 spin_unlock_irq(&xhci->lock);
1132 spin_unlock_irq(&xhci->lock);
1135 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1136 * is about to be suspended.
1138 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1139 (!(xhci_all_ports_seen_u0(xhci)))) {
1140 del_timer_sync(&xhci->comp_mode_recovery_timer);
1141 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1142 "%s: compliance mode recovery timer deleted",
1146 /* step 5: remove core well power */
1147 /* synchronize irq when using MSI-X */
1148 xhci_msix_sync_irqs(xhci);
1152 EXPORT_SYMBOL_GPL(xhci_suspend);
1155 * start xHC (not bus-specific)
1157 * This is called when the machine transition from S3/S4 mode.
1160 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1162 u32 command, temp = 0;
1163 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1165 bool comp_timer_running = false;
1166 bool pending_portevent = false;
1167 bool reinit_xhc = false;
1172 /* Wait a bit if either of the roothubs need to settle from the
1173 * transition into bus suspend.
1176 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1177 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1180 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1181 if (xhci->shared_hcd)
1182 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1184 spin_lock_irq(&xhci->lock);
1186 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1191 * Some controllers might lose power during suspend, so wait
1192 * for controller not ready bit to clear, just as in xHC init.
1194 retval = xhci_handshake(&xhci->op_regs->status,
1195 STS_CNR, 0, 10 * 1000 * 1000);
1197 xhci_warn(xhci, "Controller not ready at resume %d\n",
1199 spin_unlock_irq(&xhci->lock);
1202 /* step 1: restore register */
1203 xhci_restore_registers(xhci);
1204 /* step 2: initialize command ring buffer */
1205 xhci_set_cmd_ring_deq(xhci);
1206 /* step 3: restore state and start state*/
1207 /* step 3: set CRS flag */
1208 command = readl(&xhci->op_regs->command);
1210 writel(command, &xhci->op_regs->command);
1212 * Some controllers take up to 55+ ms to complete the controller
1213 * restore so setting the timeout to 100ms. Xhci specification
1214 * doesn't mention any timeout value.
1216 if (xhci_handshake(&xhci->op_regs->status,
1217 STS_RESTORE, 0, 100 * 1000)) {
1218 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1219 spin_unlock_irq(&xhci->lock);
1224 temp = readl(&xhci->op_regs->status);
1226 /* re-initialize the HC on Restore Error, or Host Controller Error */
1227 if (temp & (STS_SRE | STS_HCE)) {
1229 if (!xhci->broken_suspend)
1230 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1234 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1235 !(xhci_all_ports_seen_u0(xhci))) {
1236 del_timer_sync(&xhci->comp_mode_recovery_timer);
1237 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1238 "Compliance Mode Recovery Timer deleted!");
1241 /* Let the USB core know _both_ roothubs lost power. */
1242 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1243 if (xhci->shared_hcd)
1244 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1246 xhci_dbg(xhci, "Stop HCD\n");
1248 xhci_zero_64b_regs(xhci);
1249 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1250 spin_unlock_irq(&xhci->lock);
1253 xhci_cleanup_msix(xhci);
1255 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1256 temp = readl(&xhci->op_regs->status);
1257 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1258 xhci_disable_interrupter(xhci->interrupter);
1260 xhci_dbg(xhci, "cleaning up memory\n");
1261 xhci_mem_cleanup(xhci);
1262 xhci_debugfs_exit(xhci);
1263 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1264 readl(&xhci->op_regs->status));
1266 /* USB core calls the PCI reinit and start functions twice:
1267 * first with the primary HCD, and then with the secondary HCD.
1268 * If we don't do the same, the host will never be started.
1270 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1271 retval = xhci_init(hcd);
1274 comp_timer_running = true;
1276 xhci_dbg(xhci, "Start the primary HCD\n");
1277 retval = xhci_run(hcd);
1278 if (!retval && xhci->shared_hcd) {
1279 xhci_dbg(xhci, "Start the secondary HCD\n");
1280 retval = xhci_run(xhci->shared_hcd);
1283 hcd->state = HC_STATE_SUSPENDED;
1284 if (xhci->shared_hcd)
1285 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1289 /* step 4: set Run/Stop bit */
1290 command = readl(&xhci->op_regs->command);
1292 writel(command, &xhci->op_regs->command);
1293 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1296 /* step 5: walk topology and initialize portsc,
1297 * portpmsc and portli
1299 /* this is done in bus_resume */
1301 /* step 6: restart each of the previously
1302 * Running endpoints by ringing their doorbells
1305 spin_unlock_irq(&xhci->lock);
1307 xhci_dbc_resume(xhci);
1312 * Resume roothubs only if there are pending events.
1313 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1314 * the first wake signalling failed, give it that chance.
1316 pending_portevent = xhci_pending_portevent(xhci);
1317 if (!pending_portevent) {
1319 pending_portevent = xhci_pending_portevent(xhci);
1322 if (pending_portevent) {
1323 if (xhci->shared_hcd)
1324 usb_hcd_resume_root_hub(xhci->shared_hcd);
1325 usb_hcd_resume_root_hub(hcd);
1329 * If system is subject to the Quirk, Compliance Mode Timer needs to
1330 * be re-initialized Always after a system resume. Ports are subject
1331 * to suffer the Compliance Mode issue again. It doesn't matter if
1332 * ports have entered previously to U0 before system's suspension.
1334 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1335 compliance_mode_recovery_timer_init(xhci);
1337 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1338 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1340 /* Re-enable port polling. */
1341 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1342 __func__, hcd->self.busnum);
1343 if (xhci->shared_hcd) {
1344 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1345 usb_hcd_poll_rh_status(xhci->shared_hcd);
1347 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1348 usb_hcd_poll_rh_status(hcd);
1352 EXPORT_SYMBOL_GPL(xhci_resume);
1353 #endif /* CONFIG_PM */
1355 /*-------------------------------------------------------------------------*/
1357 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1361 unsigned int buf_len;
1362 enum dma_data_direction dir;
1364 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1365 buf_len = urb->transfer_buffer_length;
1367 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1368 dev_to_node(hcd->self.sysdev));
1370 if (usb_urb_dir_out(urb))
1371 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1374 urb->transfer_buffer = temp;
1375 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1376 urb->transfer_buffer,
1377 urb->transfer_buffer_length,
1380 if (dma_mapping_error(hcd->self.sysdev,
1381 urb->transfer_dma)) {
1385 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1391 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1396 unsigned int len = 0;
1397 unsigned int trb_size;
1398 unsigned int max_pkt;
1399 struct scatterlist *sg;
1400 struct scatterlist *tail_sg;
1403 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1408 if (urb->dev->speed >= USB_SPEED_SUPER)
1409 trb_size = TRB_CACHE_SIZE_SS;
1411 trb_size = TRB_CACHE_SIZE_HS;
1413 if (urb->transfer_buffer_length != 0 &&
1414 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1415 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1416 len = len + sg->length;
1417 if (i > trb_size - 2) {
1418 len = len - tail_sg->length;
1419 if (len < max_pkt) {
1424 tail_sg = sg_next(tail_sg);
1431 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1434 unsigned int buf_len;
1435 enum dma_data_direction dir;
1437 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1439 buf_len = urb->transfer_buffer_length;
1441 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1442 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1443 dma_unmap_single(hcd->self.sysdev,
1445 urb->transfer_buffer_length,
1448 if (usb_urb_dir_in(urb)) {
1449 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1450 urb->transfer_buffer,
1453 if (len != buf_len) {
1454 xhci_dbg(hcd_to_xhci(hcd),
1455 "Copy from tmp buf to urb sg list failed\n");
1456 urb->actual_length = len;
1459 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1460 kfree(urb->transfer_buffer);
1461 urb->transfer_buffer = NULL;
1465 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1466 * we'll copy the actual data into the TRB address register. This is limited to
1467 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1468 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1470 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1473 struct xhci_hcd *xhci;
1475 xhci = hcd_to_xhci(hcd);
1477 if (xhci_urb_suitable_for_idt(urb))
1480 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1481 if (xhci_urb_temp_buffer_required(hcd, urb))
1482 return xhci_map_temp_buffer(hcd, urb);
1484 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1487 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1489 struct xhci_hcd *xhci;
1490 bool unmap_temp_buf = false;
1492 xhci = hcd_to_xhci(hcd);
1494 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1495 unmap_temp_buf = true;
1497 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1498 xhci_unmap_temp_buf(hcd, urb);
1500 usb_hcd_unmap_urb_for_dma(hcd, urb);
1504 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1505 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1506 * value to right shift 1 for the bitmask.
1508 * Index = (epnum * 2) + direction - 1,
1509 * where direction = 0 for OUT, 1 for IN.
1510 * For control endpoints, the IN index is used (OUT index is unused), so
1511 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1513 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1516 if (usb_endpoint_xfer_control(desc))
1517 index = (unsigned int) (usb_endpoint_num(desc)*2);
1519 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1520 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1523 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1525 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1526 * address from the XHCI endpoint index.
1528 static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1530 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1531 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1532 return direction | number;
1535 /* Find the flag for this endpoint (for use in the control context). Use the
1536 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1539 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1541 return 1 << (xhci_get_endpoint_index(desc) + 1);
1544 /* Compute the last valid endpoint context index. Basically, this is the
1545 * endpoint index plus one. For slot contexts with more than valid endpoint,
1546 * we find the most significant bit set in the added contexts flags.
1547 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1548 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1550 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1552 return fls(added_ctxs) - 1;
1555 /* Returns 1 if the arguments are OK;
1556 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1558 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1559 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1561 struct xhci_hcd *xhci;
1562 struct xhci_virt_device *virt_dev;
1564 if (!hcd || (check_ep && !ep) || !udev) {
1565 pr_debug("xHCI %s called with invalid args\n", func);
1568 if (!udev->parent) {
1569 pr_debug("xHCI %s called for root hub\n", func);
1573 xhci = hcd_to_xhci(hcd);
1574 if (check_virt_dev) {
1575 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1576 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1581 virt_dev = xhci->devs[udev->slot_id];
1582 if (virt_dev->udev != udev) {
1583 xhci_dbg(xhci, "xHCI %s called with udev and "
1584 "virt_dev does not match\n", func);
1589 if (xhci->xhc_state & XHCI_STATE_HALTED)
1595 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1596 struct usb_device *udev, struct xhci_command *command,
1597 bool ctx_change, bool must_succeed);
1600 * Full speed devices may have a max packet size greater than 8 bytes, but the
1601 * USB core doesn't know that until it reads the first 8 bytes of the
1602 * descriptor. If the usb_device's max packet size changes after that point,
1603 * we need to issue an evaluate context command and wait on it.
1605 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1606 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1608 struct xhci_container_ctx *out_ctx;
1609 struct xhci_input_control_ctx *ctrl_ctx;
1610 struct xhci_ep_ctx *ep_ctx;
1611 struct xhci_command *command;
1612 int max_packet_size;
1613 int hw_max_packet_size;
1616 out_ctx = xhci->devs[slot_id]->out_ctx;
1617 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1618 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1619 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1620 if (hw_max_packet_size != max_packet_size) {
1621 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1622 "Max Packet Size for ep 0 changed.");
1623 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1624 "Max packet size in usb_device = %d",
1626 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1627 "Max packet size in xHCI HW = %d",
1628 hw_max_packet_size);
1629 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1630 "Issuing evaluate context command.");
1632 /* Set up the input context flags for the command */
1633 /* FIXME: This won't work if a non-default control endpoint
1634 * changes max packet sizes.
1637 command = xhci_alloc_command(xhci, true, mem_flags);
1641 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1642 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1644 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1647 goto command_cleanup;
1649 /* Set up the modified control endpoint 0 */
1650 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1651 xhci->devs[slot_id]->out_ctx, ep_index);
1653 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1654 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1655 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1656 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1658 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1659 ctrl_ctx->drop_flags = 0;
1661 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1664 /* Clean up the input context for later use by bandwidth
1667 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1669 kfree(command->completion);
1676 * non-error returns are a promise to giveback() the urb later
1677 * we drop ownership so next owner (or urb unlink) can get it
1679 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1681 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1682 unsigned long flags;
1684 unsigned int slot_id, ep_index;
1685 unsigned int *ep_state;
1686 struct urb_priv *urb_priv;
1691 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1692 true, true, __func__);
1694 return ret ? ret : -EINVAL;
1696 slot_id = urb->dev->slot_id;
1697 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1698 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1700 if (!HCD_HW_ACCESSIBLE(hcd))
1703 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1704 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1708 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1709 num_tds = urb->number_of_packets;
1710 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1711 urb->transfer_buffer_length > 0 &&
1712 urb->transfer_flags & URB_ZERO_PACKET &&
1713 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1718 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1722 urb_priv->num_tds = num_tds;
1723 urb_priv->num_tds_done = 0;
1724 urb->hcpriv = urb_priv;
1726 trace_xhci_urb_enqueue(urb);
1728 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1729 /* Check to see if the max packet size for the default control
1730 * endpoint changed during FS device enumeration
1732 if (urb->dev->speed == USB_SPEED_FULL) {
1733 ret = xhci_check_maxpacket(xhci, slot_id,
1734 ep_index, urb, mem_flags);
1736 xhci_urb_free_priv(urb_priv);
1743 spin_lock_irqsave(&xhci->lock, flags);
1745 if (xhci->xhc_state & XHCI_STATE_DYING) {
1746 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1747 urb->ep->desc.bEndpointAddress, urb);
1751 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1752 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1757 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1758 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1763 switch (usb_endpoint_type(&urb->ep->desc)) {
1765 case USB_ENDPOINT_XFER_CONTROL:
1766 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1769 case USB_ENDPOINT_XFER_BULK:
1770 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1773 case USB_ENDPOINT_XFER_INT:
1774 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1777 case USB_ENDPOINT_XFER_ISOC:
1778 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1784 xhci_urb_free_priv(urb_priv);
1787 spin_unlock_irqrestore(&xhci->lock, flags);
1792 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1793 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1794 * should pick up where it left off in the TD, unless a Set Transfer Ring
1795 * Dequeue Pointer is issued.
1797 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1798 * the ring. Since the ring is a contiguous structure, they can't be physically
1799 * removed. Instead, there are two options:
1801 * 1) If the HC is in the middle of processing the URB to be canceled, we
1802 * simply move the ring's dequeue pointer past those TRBs using the Set
1803 * Transfer Ring Dequeue Pointer command. This will be the common case,
1804 * when drivers timeout on the last submitted URB and attempt to cancel.
1806 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1807 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1808 * HC will need to invalidate the any TRBs it has cached after the stop
1809 * endpoint command, as noted in the xHCI 0.95 errata.
1811 * 3) The TD may have completed by the time the Stop Endpoint Command
1812 * completes, so software needs to handle that case too.
1814 * This function should protect against the TD enqueueing code ringing the
1815 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1816 * It also needs to account for multiple cancellations on happening at the same
1817 * time for the same endpoint.
1819 * Note that this function can be called in any context, or so says
1820 * usb_hcd_unlink_urb()
1822 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1824 unsigned long flags;
1827 struct xhci_hcd *xhci;
1828 struct urb_priv *urb_priv;
1830 unsigned int ep_index;
1831 struct xhci_ring *ep_ring;
1832 struct xhci_virt_ep *ep;
1833 struct xhci_command *command;
1834 struct xhci_virt_device *vdev;
1836 xhci = hcd_to_xhci(hcd);
1837 spin_lock_irqsave(&xhci->lock, flags);
1839 trace_xhci_urb_dequeue(urb);
1841 /* Make sure the URB hasn't completed or been unlinked already */
1842 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1846 /* give back URB now if we can't queue it for cancel */
1847 vdev = xhci->devs[urb->dev->slot_id];
1848 urb_priv = urb->hcpriv;
1849 if (!vdev || !urb_priv)
1852 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1853 ep = &vdev->eps[ep_index];
1854 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1855 if (!ep || !ep_ring)
1858 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1859 temp = readl(&xhci->op_regs->status);
1860 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1866 * check ring is not re-allocated since URB was enqueued. If it is, then
1867 * make sure none of the ring related pointers in this URB private data
1868 * are touched, such as td_list, otherwise we overwrite freed data
1870 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1871 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1872 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1873 td = &urb_priv->td[i];
1874 if (!list_empty(&td->cancelled_td_list))
1875 list_del_init(&td->cancelled_td_list);
1880 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1881 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1882 "HC halted, freeing TD manually.");
1883 for (i = urb_priv->num_tds_done;
1884 i < urb_priv->num_tds;
1886 td = &urb_priv->td[i];
1887 if (!list_empty(&td->td_list))
1888 list_del_init(&td->td_list);
1889 if (!list_empty(&td->cancelled_td_list))
1890 list_del_init(&td->cancelled_td_list);
1895 i = urb_priv->num_tds_done;
1896 if (i < urb_priv->num_tds)
1897 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1898 "Cancel URB %p, dev %s, ep 0x%x, "
1899 "starting at offset 0x%llx",
1900 urb, urb->dev->devpath,
1901 urb->ep->desc.bEndpointAddress,
1902 (unsigned long long) xhci_trb_virt_to_dma(
1903 urb_priv->td[i].start_seg,
1904 urb_priv->td[i].first_trb));
1906 for (; i < urb_priv->num_tds; i++) {
1907 td = &urb_priv->td[i];
1908 /* TD can already be on cancelled list if ep halted on it */
1909 if (list_empty(&td->cancelled_td_list)) {
1910 td->cancel_status = TD_DIRTY;
1911 list_add_tail(&td->cancelled_td_list,
1912 &ep->cancelled_td_list);
1916 /* Queue a stop endpoint command, but only if this is
1917 * the first cancellation to be handled.
1919 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1920 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1925 ep->ep_state |= EP_STOP_CMD_PENDING;
1926 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1928 xhci_ring_cmd_db(xhci);
1931 spin_unlock_irqrestore(&xhci->lock, flags);
1936 xhci_urb_free_priv(urb_priv);
1937 usb_hcd_unlink_urb_from_ep(hcd, urb);
1938 spin_unlock_irqrestore(&xhci->lock, flags);
1939 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1943 /* Drop an endpoint from a new bandwidth configuration for this device.
1944 * Only one call to this function is allowed per endpoint before
1945 * check_bandwidth() or reset_bandwidth() must be called.
1946 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1947 * add the endpoint to the schedule with possibly new parameters denoted by a
1948 * different endpoint descriptor in usb_host_endpoint.
1949 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1952 * The USB core will not allow URBs to be queued to an endpoint that is being
1953 * disabled, so there's no need for mutual exclusion to protect
1954 * the xhci->devs[slot_id] structure.
1956 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1957 struct usb_host_endpoint *ep)
1959 struct xhci_hcd *xhci;
1960 struct xhci_container_ctx *in_ctx, *out_ctx;
1961 struct xhci_input_control_ctx *ctrl_ctx;
1962 unsigned int ep_index;
1963 struct xhci_ep_ctx *ep_ctx;
1965 u32 new_add_flags, new_drop_flags;
1968 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1971 xhci = hcd_to_xhci(hcd);
1972 if (xhci->xhc_state & XHCI_STATE_DYING)
1975 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1976 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1977 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1978 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1979 __func__, drop_flag);
1983 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1984 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1985 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1987 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1992 ep_index = xhci_get_endpoint_index(&ep->desc);
1993 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1994 /* If the HC already knows the endpoint is disabled,
1995 * or the HCD has noted it is disabled, ignore this request
1997 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1998 le32_to_cpu(ctrl_ctx->drop_flags) &
1999 xhci_get_endpoint_flag(&ep->desc)) {
2000 /* Do not warn when called after a usb_device_reset */
2001 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
2002 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
2007 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
2008 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2010 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
2011 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2013 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
2015 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
2017 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2018 (unsigned int) ep->desc.bEndpointAddress,
2020 (unsigned int) new_drop_flags,
2021 (unsigned int) new_add_flags);
2024 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
2026 /* Add an endpoint to a new possible bandwidth configuration for this device.
2027 * Only one call to this function is allowed per endpoint before
2028 * check_bandwidth() or reset_bandwidth() must be called.
2029 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
2030 * add the endpoint to the schedule with possibly new parameters denoted by a
2031 * different endpoint descriptor in usb_host_endpoint.
2032 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
2035 * The USB core will not allow URBs to be queued to an endpoint until the
2036 * configuration or alt setting is installed in the device, so there's no need
2037 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2039 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2040 struct usb_host_endpoint *ep)
2042 struct xhci_hcd *xhci;
2043 struct xhci_container_ctx *in_ctx;
2044 unsigned int ep_index;
2045 struct xhci_input_control_ctx *ctrl_ctx;
2046 struct xhci_ep_ctx *ep_ctx;
2048 u32 new_add_flags, new_drop_flags;
2049 struct xhci_virt_device *virt_dev;
2052 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2054 /* So we won't queue a reset ep command for a root hub */
2058 xhci = hcd_to_xhci(hcd);
2059 if (xhci->xhc_state & XHCI_STATE_DYING)
2062 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2063 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2064 /* FIXME when we have to issue an evaluate endpoint command to
2065 * deal with ep0 max packet size changing once we get the
2068 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2069 __func__, added_ctxs);
2073 virt_dev = xhci->devs[udev->slot_id];
2074 in_ctx = virt_dev->in_ctx;
2075 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2077 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2082 ep_index = xhci_get_endpoint_index(&ep->desc);
2083 /* If this endpoint is already in use, and the upper layers are trying
2084 * to add it again without dropping it, reject the addition.
2086 if (virt_dev->eps[ep_index].ring &&
2087 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2088 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2089 "without dropping it.\n",
2090 (unsigned int) ep->desc.bEndpointAddress);
2094 /* If the HCD has already noted the endpoint is enabled,
2095 * ignore this request.
2097 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2098 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2104 * Configuration and alternate setting changes must be done in
2105 * process context, not interrupt context (or so documenation
2106 * for usb_set_interface() and usb_set_configuration() claim).
2108 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2109 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2110 __func__, ep->desc.bEndpointAddress);
2114 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2115 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2117 /* If xhci_endpoint_disable() was called for this endpoint, but the
2118 * xHC hasn't been notified yet through the check_bandwidth() call,
2119 * this re-adds a new state for the endpoint from the new endpoint
2120 * descriptors. We must drop and re-add this endpoint, so we leave the
2123 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2125 /* Store the usb_device pointer for later use */
2128 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2129 trace_xhci_add_endpoint(ep_ctx);
2131 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2132 (unsigned int) ep->desc.bEndpointAddress,
2134 (unsigned int) new_drop_flags,
2135 (unsigned int) new_add_flags);
2138 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2140 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2142 struct xhci_input_control_ctx *ctrl_ctx;
2143 struct xhci_ep_ctx *ep_ctx;
2144 struct xhci_slot_ctx *slot_ctx;
2147 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2149 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2154 /* When a device's add flag and drop flag are zero, any subsequent
2155 * configure endpoint command will leave that endpoint's state
2156 * untouched. Make sure we don't leave any old state in the input
2157 * endpoint contexts.
2159 ctrl_ctx->drop_flags = 0;
2160 ctrl_ctx->add_flags = 0;
2161 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2162 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2163 /* Endpoint 0 is always valid */
2164 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2165 for (i = 1; i < 31; i++) {
2166 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2167 ep_ctx->ep_info = 0;
2168 ep_ctx->ep_info2 = 0;
2170 ep_ctx->tx_info = 0;
2174 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2175 struct usb_device *udev, u32 *cmd_status)
2179 switch (*cmd_status) {
2180 case COMP_COMMAND_ABORTED:
2181 case COMP_COMMAND_RING_STOPPED:
2182 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2185 case COMP_RESOURCE_ERROR:
2186 dev_warn(&udev->dev,
2187 "Not enough host controller resources for new device state.\n");
2189 /* FIXME: can we allocate more resources for the HC? */
2191 case COMP_BANDWIDTH_ERROR:
2192 case COMP_SECONDARY_BANDWIDTH_ERROR:
2193 dev_warn(&udev->dev,
2194 "Not enough bandwidth for new device state.\n");
2196 /* FIXME: can we go back to the old state? */
2198 case COMP_TRB_ERROR:
2199 /* the HCD set up something wrong */
2200 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2202 "and endpoint is not disabled.\n");
2205 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2206 dev_warn(&udev->dev,
2207 "ERROR: Incompatible device for endpoint configure command.\n");
2211 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2212 "Successful Endpoint Configure command");
2216 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2224 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2225 struct usb_device *udev, u32 *cmd_status)
2229 switch (*cmd_status) {
2230 case COMP_COMMAND_ABORTED:
2231 case COMP_COMMAND_RING_STOPPED:
2232 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2235 case COMP_PARAMETER_ERROR:
2236 dev_warn(&udev->dev,
2237 "WARN: xHCI driver setup invalid evaluate context command.\n");
2240 case COMP_SLOT_NOT_ENABLED_ERROR:
2241 dev_warn(&udev->dev,
2242 "WARN: slot not enabled for evaluate context command.\n");
2245 case COMP_CONTEXT_STATE_ERROR:
2246 dev_warn(&udev->dev,
2247 "WARN: invalid context state for evaluate context command.\n");
2250 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2251 dev_warn(&udev->dev,
2252 "ERROR: Incompatible device for evaluate context command.\n");
2255 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2256 /* Max Exit Latency too large error */
2257 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2261 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2262 "Successful evaluate context command");
2266 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2274 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2275 struct xhci_input_control_ctx *ctrl_ctx)
2277 u32 valid_add_flags;
2278 u32 valid_drop_flags;
2280 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2281 * (bit 1). The default control endpoint is added during the Address
2282 * Device command and is never removed until the slot is disabled.
2284 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2285 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2287 /* Use hweight32 to count the number of ones in the add flags, or
2288 * number of endpoints added. Don't count endpoints that are changed
2289 * (both added and dropped).
2291 return hweight32(valid_add_flags) -
2292 hweight32(valid_add_flags & valid_drop_flags);
2295 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2296 struct xhci_input_control_ctx *ctrl_ctx)
2298 u32 valid_add_flags;
2299 u32 valid_drop_flags;
2301 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2302 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2304 return hweight32(valid_drop_flags) -
2305 hweight32(valid_add_flags & valid_drop_flags);
2309 * We need to reserve the new number of endpoints before the configure endpoint
2310 * command completes. We can't subtract the dropped endpoints from the number
2311 * of active endpoints until the command completes because we can oversubscribe
2312 * the host in this case:
2314 * - the first configure endpoint command drops more endpoints than it adds
2315 * - a second configure endpoint command that adds more endpoints is queued
2316 * - the first configure endpoint command fails, so the config is unchanged
2317 * - the second command may succeed, even though there isn't enough resources
2319 * Must be called with xhci->lock held.
2321 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2322 struct xhci_input_control_ctx *ctrl_ctx)
2326 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2327 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2328 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2329 "Not enough ep ctxs: "
2330 "%u active, need to add %u, limit is %u.",
2331 xhci->num_active_eps, added_eps,
2332 xhci->limit_active_eps);
2335 xhci->num_active_eps += added_eps;
2336 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2337 "Adding %u ep ctxs, %u now active.", added_eps,
2338 xhci->num_active_eps);
2343 * The configure endpoint was failed by the xHC for some other reason, so we
2344 * need to revert the resources that failed configuration would have used.
2346 * Must be called with xhci->lock held.
2348 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2349 struct xhci_input_control_ctx *ctrl_ctx)
2353 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2354 xhci->num_active_eps -= num_failed_eps;
2355 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2356 "Removing %u failed ep ctxs, %u now active.",
2358 xhci->num_active_eps);
2362 * Now that the command has completed, clean up the active endpoint count by
2363 * subtracting out the endpoints that were dropped (but not changed).
2365 * Must be called with xhci->lock held.
2367 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2368 struct xhci_input_control_ctx *ctrl_ctx)
2370 u32 num_dropped_eps;
2372 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2373 xhci->num_active_eps -= num_dropped_eps;
2374 if (num_dropped_eps)
2375 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2376 "Removing %u dropped ep ctxs, %u now active.",
2378 xhci->num_active_eps);
2381 static unsigned int xhci_get_block_size(struct usb_device *udev)
2383 switch (udev->speed) {
2385 case USB_SPEED_FULL:
2387 case USB_SPEED_HIGH:
2389 case USB_SPEED_SUPER:
2390 case USB_SPEED_SUPER_PLUS:
2392 case USB_SPEED_UNKNOWN:
2393 case USB_SPEED_WIRELESS:
2395 /* Should never happen */
2401 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2403 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2405 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2410 /* If we are changing a LS/FS device under a HS hub,
2411 * make sure (if we are activating a new TT) that the HS bus has enough
2412 * bandwidth for this new TT.
2414 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2415 struct xhci_virt_device *virt_dev,
2418 struct xhci_interval_bw_table *bw_table;
2419 struct xhci_tt_bw_info *tt_info;
2421 /* Find the bandwidth table for the root port this TT is attached to. */
2422 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2423 tt_info = virt_dev->tt_info;
2424 /* If this TT already had active endpoints, the bandwidth for this TT
2425 * has already been added. Removing all periodic endpoints (and thus
2426 * making the TT enactive) will only decrease the bandwidth used.
2430 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2431 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2435 /* Not sure why we would have no new active endpoints...
2437 * Maybe because of an Evaluate Context change for a hub update or a
2438 * control endpoint 0 max packet size change?
2439 * FIXME: skip the bandwidth calculation in that case.
2444 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2445 struct xhci_virt_device *virt_dev)
2447 unsigned int bw_reserved;
2449 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2450 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2453 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2454 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2461 * This algorithm is a very conservative estimate of the worst-case scheduling
2462 * scenario for any one interval. The hardware dynamically schedules the
2463 * packets, so we can't tell which microframe could be the limiting factor in
2464 * the bandwidth scheduling. This only takes into account periodic endpoints.
2466 * Obviously, we can't solve an NP complete problem to find the minimum worst
2467 * case scenario. Instead, we come up with an estimate that is no less than
2468 * the worst case bandwidth used for any one microframe, but may be an
2471 * We walk the requirements for each endpoint by interval, starting with the
2472 * smallest interval, and place packets in the schedule where there is only one
2473 * possible way to schedule packets for that interval. In order to simplify
2474 * this algorithm, we record the largest max packet size for each interval, and
2475 * assume all packets will be that size.
2477 * For interval 0, we obviously must schedule all packets for each interval.
2478 * The bandwidth for interval 0 is just the amount of data to be transmitted
2479 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2480 * the number of packets).
2482 * For interval 1, we have two possible microframes to schedule those packets
2483 * in. For this algorithm, if we can schedule the same number of packets for
2484 * each possible scheduling opportunity (each microframe), we will do so. The
2485 * remaining number of packets will be saved to be transmitted in the gaps in
2486 * the next interval's scheduling sequence.
2488 * As we move those remaining packets to be scheduled with interval 2 packets,
2489 * we have to double the number of remaining packets to transmit. This is
2490 * because the intervals are actually powers of 2, and we would be transmitting
2491 * the previous interval's packets twice in this interval. We also have to be
2492 * sure that when we look at the largest max packet size for this interval, we
2493 * also look at the largest max packet size for the remaining packets and take
2494 * the greater of the two.
2496 * The algorithm continues to evenly distribute packets in each scheduling
2497 * opportunity, and push the remaining packets out, until we get to the last
2498 * interval. Then those packets and their associated overhead are just added
2499 * to the bandwidth used.
2501 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2502 struct xhci_virt_device *virt_dev,
2505 unsigned int bw_reserved;
2506 unsigned int max_bandwidth;
2507 unsigned int bw_used;
2508 unsigned int block_size;
2509 struct xhci_interval_bw_table *bw_table;
2510 unsigned int packet_size = 0;
2511 unsigned int overhead = 0;
2512 unsigned int packets_transmitted = 0;
2513 unsigned int packets_remaining = 0;
2516 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2517 return xhci_check_ss_bw(xhci, virt_dev);
2519 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2520 max_bandwidth = HS_BW_LIMIT;
2521 /* Convert percent of bus BW reserved to blocks reserved */
2522 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2524 max_bandwidth = FS_BW_LIMIT;
2525 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2528 bw_table = virt_dev->bw_table;
2529 /* We need to translate the max packet size and max ESIT payloads into
2530 * the units the hardware uses.
2532 block_size = xhci_get_block_size(virt_dev->udev);
2534 /* If we are manipulating a LS/FS device under a HS hub, double check
2535 * that the HS bus has enough bandwidth if we are activing a new TT.
2537 if (virt_dev->tt_info) {
2538 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2539 "Recalculating BW for rootport %u",
2540 virt_dev->real_port);
2541 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2542 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2543 "newly activated TT.\n");
2546 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2547 "Recalculating BW for TT slot %u port %u",
2548 virt_dev->tt_info->slot_id,
2549 virt_dev->tt_info->ttport);
2551 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2552 "Recalculating BW for rootport %u",
2553 virt_dev->real_port);
2556 /* Add in how much bandwidth will be used for interval zero, or the
2557 * rounded max ESIT payload + number of packets * largest overhead.
2559 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2560 bw_table->interval_bw[0].num_packets *
2561 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2563 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2564 unsigned int bw_added;
2565 unsigned int largest_mps;
2566 unsigned int interval_overhead;
2569 * How many packets could we transmit in this interval?
2570 * If packets didn't fit in the previous interval, we will need
2571 * to transmit that many packets twice within this interval.
2573 packets_remaining = 2 * packets_remaining +
2574 bw_table->interval_bw[i].num_packets;
2576 /* Find the largest max packet size of this or the previous
2579 if (list_empty(&bw_table->interval_bw[i].endpoints))
2582 struct xhci_virt_ep *virt_ep;
2583 struct list_head *ep_entry;
2585 ep_entry = bw_table->interval_bw[i].endpoints.next;
2586 virt_ep = list_entry(ep_entry,
2587 struct xhci_virt_ep, bw_endpoint_list);
2588 /* Convert to blocks, rounding up */
2589 largest_mps = DIV_ROUND_UP(
2590 virt_ep->bw_info.max_packet_size,
2593 if (largest_mps > packet_size)
2594 packet_size = largest_mps;
2596 /* Use the larger overhead of this or the previous interval. */
2597 interval_overhead = xhci_get_largest_overhead(
2598 &bw_table->interval_bw[i]);
2599 if (interval_overhead > overhead)
2600 overhead = interval_overhead;
2602 /* How many packets can we evenly distribute across
2603 * (1 << (i + 1)) possible scheduling opportunities?
2605 packets_transmitted = packets_remaining >> (i + 1);
2607 /* Add in the bandwidth used for those scheduled packets */
2608 bw_added = packets_transmitted * (overhead + packet_size);
2610 /* How many packets do we have remaining to transmit? */
2611 packets_remaining = packets_remaining % (1 << (i + 1));
2613 /* What largest max packet size should those packets have? */
2614 /* If we've transmitted all packets, don't carry over the
2615 * largest packet size.
2617 if (packets_remaining == 0) {
2620 } else if (packets_transmitted > 0) {
2621 /* Otherwise if we do have remaining packets, and we've
2622 * scheduled some packets in this interval, take the
2623 * largest max packet size from endpoints with this
2626 packet_size = largest_mps;
2627 overhead = interval_overhead;
2629 /* Otherwise carry over packet_size and overhead from the last
2630 * time we had a remainder.
2632 bw_used += bw_added;
2633 if (bw_used > max_bandwidth) {
2634 xhci_warn(xhci, "Not enough bandwidth. "
2635 "Proposed: %u, Max: %u\n",
2636 bw_used, max_bandwidth);
2641 * Ok, we know we have some packets left over after even-handedly
2642 * scheduling interval 15. We don't know which microframes they will
2643 * fit into, so we over-schedule and say they will be scheduled every
2646 if (packets_remaining > 0)
2647 bw_used += overhead + packet_size;
2649 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2650 unsigned int port_index = virt_dev->real_port - 1;
2652 /* OK, we're manipulating a HS device attached to a
2653 * root port bandwidth domain. Include the number of active TTs
2654 * in the bandwidth used.
2656 bw_used += TT_HS_OVERHEAD *
2657 xhci->rh_bw[port_index].num_active_tts;
2660 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2661 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2662 "Available: %u " "percent",
2663 bw_used, max_bandwidth, bw_reserved,
2664 (max_bandwidth - bw_used - bw_reserved) * 100 /
2667 bw_used += bw_reserved;
2668 if (bw_used > max_bandwidth) {
2669 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2670 bw_used, max_bandwidth);
2674 bw_table->bw_used = bw_used;
2678 static bool xhci_is_async_ep(unsigned int ep_type)
2680 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2681 ep_type != ISOC_IN_EP &&
2682 ep_type != INT_IN_EP);
2685 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2687 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2690 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2692 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2694 if (ep_bw->ep_interval == 0)
2695 return SS_OVERHEAD_BURST +
2696 (ep_bw->mult * ep_bw->num_packets *
2697 (SS_OVERHEAD + mps));
2698 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2699 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2700 1 << ep_bw->ep_interval);
2704 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2705 struct xhci_bw_info *ep_bw,
2706 struct xhci_interval_bw_table *bw_table,
2707 struct usb_device *udev,
2708 struct xhci_virt_ep *virt_ep,
2709 struct xhci_tt_bw_info *tt_info)
2711 struct xhci_interval_bw *interval_bw;
2712 int normalized_interval;
2714 if (xhci_is_async_ep(ep_bw->type))
2717 if (udev->speed >= USB_SPEED_SUPER) {
2718 if (xhci_is_sync_in_ep(ep_bw->type))
2719 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2720 xhci_get_ss_bw_consumed(ep_bw);
2722 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2723 xhci_get_ss_bw_consumed(ep_bw);
2727 /* SuperSpeed endpoints never get added to intervals in the table, so
2728 * this check is only valid for HS/FS/LS devices.
2730 if (list_empty(&virt_ep->bw_endpoint_list))
2732 /* For LS/FS devices, we need to translate the interval expressed in
2733 * microframes to frames.
2735 if (udev->speed == USB_SPEED_HIGH)
2736 normalized_interval = ep_bw->ep_interval;
2738 normalized_interval = ep_bw->ep_interval - 3;
2740 if (normalized_interval == 0)
2741 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2742 interval_bw = &bw_table->interval_bw[normalized_interval];
2743 interval_bw->num_packets -= ep_bw->num_packets;
2744 switch (udev->speed) {
2746 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2748 case USB_SPEED_FULL:
2749 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2751 case USB_SPEED_HIGH:
2752 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2754 case USB_SPEED_SUPER:
2755 case USB_SPEED_SUPER_PLUS:
2756 case USB_SPEED_UNKNOWN:
2757 case USB_SPEED_WIRELESS:
2758 /* Should never happen because only LS/FS/HS endpoints will get
2759 * added to the endpoint list.
2764 tt_info->active_eps -= 1;
2765 list_del_init(&virt_ep->bw_endpoint_list);
2768 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2769 struct xhci_bw_info *ep_bw,
2770 struct xhci_interval_bw_table *bw_table,
2771 struct usb_device *udev,
2772 struct xhci_virt_ep *virt_ep,
2773 struct xhci_tt_bw_info *tt_info)
2775 struct xhci_interval_bw *interval_bw;
2776 struct xhci_virt_ep *smaller_ep;
2777 int normalized_interval;
2779 if (xhci_is_async_ep(ep_bw->type))
2782 if (udev->speed == USB_SPEED_SUPER) {
2783 if (xhci_is_sync_in_ep(ep_bw->type))
2784 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2785 xhci_get_ss_bw_consumed(ep_bw);
2787 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2788 xhci_get_ss_bw_consumed(ep_bw);
2792 /* For LS/FS devices, we need to translate the interval expressed in
2793 * microframes to frames.
2795 if (udev->speed == USB_SPEED_HIGH)
2796 normalized_interval = ep_bw->ep_interval;
2798 normalized_interval = ep_bw->ep_interval - 3;
2800 if (normalized_interval == 0)
2801 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2802 interval_bw = &bw_table->interval_bw[normalized_interval];
2803 interval_bw->num_packets += ep_bw->num_packets;
2804 switch (udev->speed) {
2806 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2808 case USB_SPEED_FULL:
2809 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2811 case USB_SPEED_HIGH:
2812 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2814 case USB_SPEED_SUPER:
2815 case USB_SPEED_SUPER_PLUS:
2816 case USB_SPEED_UNKNOWN:
2817 case USB_SPEED_WIRELESS:
2818 /* Should never happen because only LS/FS/HS endpoints will get
2819 * added to the endpoint list.
2825 tt_info->active_eps += 1;
2826 /* Insert the endpoint into the list, largest max packet size first. */
2827 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2829 if (ep_bw->max_packet_size >=
2830 smaller_ep->bw_info.max_packet_size) {
2831 /* Add the new ep before the smaller endpoint */
2832 list_add_tail(&virt_ep->bw_endpoint_list,
2833 &smaller_ep->bw_endpoint_list);
2837 /* Add the new endpoint at the end of the list. */
2838 list_add_tail(&virt_ep->bw_endpoint_list,
2839 &interval_bw->endpoints);
2842 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2843 struct xhci_virt_device *virt_dev,
2846 struct xhci_root_port_bw_info *rh_bw_info;
2847 if (!virt_dev->tt_info)
2850 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2851 if (old_active_eps == 0 &&
2852 virt_dev->tt_info->active_eps != 0) {
2853 rh_bw_info->num_active_tts += 1;
2854 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2855 } else if (old_active_eps != 0 &&
2856 virt_dev->tt_info->active_eps == 0) {
2857 rh_bw_info->num_active_tts -= 1;
2858 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2862 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2863 struct xhci_virt_device *virt_dev,
2864 struct xhci_container_ctx *in_ctx)
2866 struct xhci_bw_info ep_bw_info[31];
2868 struct xhci_input_control_ctx *ctrl_ctx;
2869 int old_active_eps = 0;
2871 if (virt_dev->tt_info)
2872 old_active_eps = virt_dev->tt_info->active_eps;
2874 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2876 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2881 for (i = 0; i < 31; i++) {
2882 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2885 /* Make a copy of the BW info in case we need to revert this */
2886 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2887 sizeof(ep_bw_info[i]));
2888 /* Drop the endpoint from the interval table if the endpoint is
2889 * being dropped or changed.
2891 if (EP_IS_DROPPED(ctrl_ctx, i))
2892 xhci_drop_ep_from_interval_table(xhci,
2893 &virt_dev->eps[i].bw_info,
2899 /* Overwrite the information stored in the endpoints' bw_info */
2900 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2901 for (i = 0; i < 31; i++) {
2902 /* Add any changed or added endpoints to the interval table */
2903 if (EP_IS_ADDED(ctrl_ctx, i))
2904 xhci_add_ep_to_interval_table(xhci,
2905 &virt_dev->eps[i].bw_info,
2912 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2913 /* Ok, this fits in the bandwidth we have.
2914 * Update the number of active TTs.
2916 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2920 /* We don't have enough bandwidth for this, revert the stored info. */
2921 for (i = 0; i < 31; i++) {
2922 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2925 /* Drop the new copies of any added or changed endpoints from
2926 * the interval table.
2928 if (EP_IS_ADDED(ctrl_ctx, i)) {
2929 xhci_drop_ep_from_interval_table(xhci,
2930 &virt_dev->eps[i].bw_info,
2936 /* Revert the endpoint back to its old information */
2937 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2938 sizeof(ep_bw_info[i]));
2939 /* Add any changed or dropped endpoints back into the table */
2940 if (EP_IS_DROPPED(ctrl_ctx, i))
2941 xhci_add_ep_to_interval_table(xhci,
2942 &virt_dev->eps[i].bw_info,
2952 /* Issue a configure endpoint command or evaluate context command
2953 * and wait for it to finish.
2955 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2956 struct usb_device *udev,
2957 struct xhci_command *command,
2958 bool ctx_change, bool must_succeed)
2961 unsigned long flags;
2962 struct xhci_input_control_ctx *ctrl_ctx;
2963 struct xhci_virt_device *virt_dev;
2964 struct xhci_slot_ctx *slot_ctx;
2969 spin_lock_irqsave(&xhci->lock, flags);
2971 if (xhci->xhc_state & XHCI_STATE_DYING) {
2972 spin_unlock_irqrestore(&xhci->lock, flags);
2976 virt_dev = xhci->devs[udev->slot_id];
2978 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2980 spin_unlock_irqrestore(&xhci->lock, flags);
2981 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2986 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2987 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2988 spin_unlock_irqrestore(&xhci->lock, flags);
2989 xhci_warn(xhci, "Not enough host resources, "
2990 "active endpoint contexts = %u\n",
2991 xhci->num_active_eps);
2994 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2995 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2996 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2997 xhci_free_host_resources(xhci, ctrl_ctx);
2998 spin_unlock_irqrestore(&xhci->lock, flags);
2999 xhci_warn(xhci, "Not enough bandwidth\n");
3003 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3005 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
3006 trace_xhci_configure_endpoint(slot_ctx);
3009 ret = xhci_queue_configure_endpoint(xhci, command,
3010 command->in_ctx->dma,
3011 udev->slot_id, must_succeed);
3013 ret = xhci_queue_evaluate_context(xhci, command,
3014 command->in_ctx->dma,
3015 udev->slot_id, must_succeed);
3017 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
3018 xhci_free_host_resources(xhci, ctrl_ctx);
3019 spin_unlock_irqrestore(&xhci->lock, flags);
3020 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
3021 "FIXME allocate a new ring segment");
3024 xhci_ring_cmd_db(xhci);
3025 spin_unlock_irqrestore(&xhci->lock, flags);
3027 /* Wait for the configure endpoint command to complete */
3028 wait_for_completion(command->completion);
3031 ret = xhci_configure_endpoint_result(xhci, udev,
3034 ret = xhci_evaluate_context_result(xhci, udev,
3037 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3038 spin_lock_irqsave(&xhci->lock, flags);
3039 /* If the command failed, remove the reserved resources.
3040 * Otherwise, clean up the estimate to include dropped eps.
3043 xhci_free_host_resources(xhci, ctrl_ctx);
3045 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3046 spin_unlock_irqrestore(&xhci->lock, flags);
3051 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3052 struct xhci_virt_device *vdev, int i)
3054 struct xhci_virt_ep *ep = &vdev->eps[i];
3056 if (ep->ep_state & EP_HAS_STREAMS) {
3057 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3058 xhci_get_endpoint_address(i));
3059 xhci_free_stream_info(xhci, ep->stream_info);
3060 ep->stream_info = NULL;
3061 ep->ep_state &= ~EP_HAS_STREAMS;
3065 /* Called after one or more calls to xhci_add_endpoint() or
3066 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3067 * to call xhci_reset_bandwidth().
3069 * Since we are in the middle of changing either configuration or
3070 * installing a new alt setting, the USB core won't allow URBs to be
3071 * enqueued for any endpoint on the old config or interface. Nothing
3072 * else should be touching the xhci->devs[slot_id] structure, so we
3073 * don't need to take the xhci->lock for manipulating that.
3075 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3079 struct xhci_hcd *xhci;
3080 struct xhci_virt_device *virt_dev;
3081 struct xhci_input_control_ctx *ctrl_ctx;
3082 struct xhci_slot_ctx *slot_ctx;
3083 struct xhci_command *command;
3085 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3088 xhci = hcd_to_xhci(hcd);
3089 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3090 (xhci->xhc_state & XHCI_STATE_REMOVING))
3093 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3094 virt_dev = xhci->devs[udev->slot_id];
3096 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3100 command->in_ctx = virt_dev->in_ctx;
3102 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3103 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3105 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3108 goto command_cleanup;
3110 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3111 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3112 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3114 /* Don't issue the command if there's no endpoints to update. */
3115 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3116 ctrl_ctx->drop_flags == 0) {
3118 goto command_cleanup;
3120 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3121 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3122 for (i = 31; i >= 1; i--) {
3123 __le32 le32 = cpu_to_le32(BIT(i));
3125 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3126 || (ctrl_ctx->add_flags & le32) || i == 1) {
3127 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3128 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3133 ret = xhci_configure_endpoint(xhci, udev, command,
3136 /* Callee should call reset_bandwidth() */
3137 goto command_cleanup;
3139 /* Free any rings that were dropped, but not changed. */
3140 for (i = 1; i < 31; i++) {
3141 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3142 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3143 xhci_free_endpoint_ring(xhci, virt_dev, i);
3144 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3147 xhci_zero_in_ctx(xhci, virt_dev);
3149 * Install any rings for completely new endpoints or changed endpoints,
3150 * and free any old rings from changed endpoints.
3152 for (i = 1; i < 31; i++) {
3153 if (!virt_dev->eps[i].new_ring)
3155 /* Only free the old ring if it exists.
3156 * It may not if this is the first add of an endpoint.
3158 if (virt_dev->eps[i].ring) {
3159 xhci_free_endpoint_ring(xhci, virt_dev, i);
3161 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3162 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3163 virt_dev->eps[i].new_ring = NULL;
3164 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3167 kfree(command->completion);
3172 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3174 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3176 struct xhci_hcd *xhci;
3177 struct xhci_virt_device *virt_dev;
3180 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3183 xhci = hcd_to_xhci(hcd);
3185 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3186 virt_dev = xhci->devs[udev->slot_id];
3187 /* Free any rings allocated for added endpoints */
3188 for (i = 0; i < 31; i++) {
3189 if (virt_dev->eps[i].new_ring) {
3190 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3191 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3192 virt_dev->eps[i].new_ring = NULL;
3195 xhci_zero_in_ctx(xhci, virt_dev);
3197 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3199 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3200 struct xhci_container_ctx *in_ctx,
3201 struct xhci_container_ctx *out_ctx,
3202 struct xhci_input_control_ctx *ctrl_ctx,
3203 u32 add_flags, u32 drop_flags)
3205 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3206 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3207 xhci_slot_copy(xhci, in_ctx, out_ctx);
3208 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3211 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3212 struct usb_host_endpoint *host_ep)
3214 struct xhci_hcd *xhci;
3215 struct xhci_virt_device *vdev;
3216 struct xhci_virt_ep *ep;
3217 struct usb_device *udev;
3218 unsigned long flags;
3219 unsigned int ep_index;
3221 xhci = hcd_to_xhci(hcd);
3223 spin_lock_irqsave(&xhci->lock, flags);
3225 udev = (struct usb_device *)host_ep->hcpriv;
3226 if (!udev || !udev->slot_id)
3229 vdev = xhci->devs[udev->slot_id];
3233 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3234 ep = &vdev->eps[ep_index];
3236 /* wait for hub_tt_work to finish clearing hub TT */
3237 if (ep->ep_state & EP_CLEARING_TT) {
3238 spin_unlock_irqrestore(&xhci->lock, flags);
3239 schedule_timeout_uninterruptible(1);
3244 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3247 host_ep->hcpriv = NULL;
3248 spin_unlock_irqrestore(&xhci->lock, flags);
3252 * Called after usb core issues a clear halt control message.
3253 * The host side of the halt should already be cleared by a reset endpoint
3254 * command issued when the STALL event was received.
3256 * The reset endpoint command may only be issued to endpoints in the halted
3257 * state. For software that wishes to reset the data toggle or sequence number
3258 * of an endpoint that isn't in the halted state this function will issue a
3259 * configure endpoint command with the Drop and Add bits set for the target
3260 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3263 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3264 struct usb_host_endpoint *host_ep)
3266 struct xhci_hcd *xhci;
3267 struct usb_device *udev;
3268 struct xhci_virt_device *vdev;
3269 struct xhci_virt_ep *ep;
3270 struct xhci_input_control_ctx *ctrl_ctx;
3271 struct xhci_command *stop_cmd, *cfg_cmd;
3272 unsigned int ep_index;
3273 unsigned long flags;
3277 xhci = hcd_to_xhci(hcd);
3278 if (!host_ep->hcpriv)
3280 udev = (struct usb_device *) host_ep->hcpriv;
3281 vdev = xhci->devs[udev->slot_id];
3284 * vdev may be lost due to xHC restore error and re-initialization
3285 * during S3/S4 resume. A new vdev will be allocated later by
3286 * xhci_discover_or_reset_device()
3288 if (!udev->slot_id || !vdev)
3290 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3291 ep = &vdev->eps[ep_index];
3293 /* Bail out if toggle is already being cleared by a endpoint reset */
3294 spin_lock_irqsave(&xhci->lock, flags);
3295 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3296 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3297 spin_unlock_irqrestore(&xhci->lock, flags);
3300 spin_unlock_irqrestore(&xhci->lock, flags);
3301 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3302 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3303 usb_endpoint_xfer_isoc(&host_ep->desc))
3306 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3308 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3311 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3315 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3319 spin_lock_irqsave(&xhci->lock, flags);
3321 /* block queuing new trbs and ringing ep doorbell */
3322 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3325 * Make sure endpoint ring is empty before resetting the toggle/seq.
3326 * Driver is required to synchronously cancel all transfer request.
3327 * Stop the endpoint to force xHC to update the output context
3330 if (!list_empty(&ep->ring->td_list)) {
3331 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3332 spin_unlock_irqrestore(&xhci->lock, flags);
3333 xhci_free_command(xhci, cfg_cmd);
3337 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3340 spin_unlock_irqrestore(&xhci->lock, flags);
3341 xhci_free_command(xhci, cfg_cmd);
3342 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3347 xhci_ring_cmd_db(xhci);
3348 spin_unlock_irqrestore(&xhci->lock, flags);
3350 wait_for_completion(stop_cmd->completion);
3352 spin_lock_irqsave(&xhci->lock, flags);
3354 /* config ep command clears toggle if add and drop ep flags are set */
3355 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3357 spin_unlock_irqrestore(&xhci->lock, flags);
3358 xhci_free_command(xhci, cfg_cmd);
3359 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3364 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3365 ctrl_ctx, ep_flag, ep_flag);
3366 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3368 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3369 udev->slot_id, false);
3371 spin_unlock_irqrestore(&xhci->lock, flags);
3372 xhci_free_command(xhci, cfg_cmd);
3373 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3378 xhci_ring_cmd_db(xhci);
3379 spin_unlock_irqrestore(&xhci->lock, flags);
3381 wait_for_completion(cfg_cmd->completion);
3383 xhci_free_command(xhci, cfg_cmd);
3385 xhci_free_command(xhci, stop_cmd);
3386 spin_lock_irqsave(&xhci->lock, flags);
3387 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3388 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3389 spin_unlock_irqrestore(&xhci->lock, flags);
3392 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3393 struct usb_device *udev, struct usb_host_endpoint *ep,
3394 unsigned int slot_id)
3397 unsigned int ep_index;
3398 unsigned int ep_state;
3402 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3404 return ret ? ret : -EINVAL;
3405 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3406 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3407 " descriptor for ep 0x%x does not support streams\n",
3408 ep->desc.bEndpointAddress);
3412 ep_index = xhci_get_endpoint_index(&ep->desc);
3413 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3414 if (ep_state & EP_HAS_STREAMS ||
3415 ep_state & EP_GETTING_STREAMS) {
3416 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3417 "already has streams set up.\n",
3418 ep->desc.bEndpointAddress);
3419 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3420 "dynamic stream context array reallocation.\n");
3423 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3424 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3425 "endpoint 0x%x; URBs are pending.\n",
3426 ep->desc.bEndpointAddress);
3432 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3433 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3435 unsigned int max_streams;
3437 /* The stream context array size must be a power of two */
3438 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3440 * Find out how many primary stream array entries the host controller
3441 * supports. Later we may use secondary stream arrays (similar to 2nd
3442 * level page entries), but that's an optional feature for xHCI host
3443 * controllers. xHCs must support at least 4 stream IDs.
3445 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3446 if (*num_stream_ctxs > max_streams) {
3447 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3449 *num_stream_ctxs = max_streams;
3450 *num_streams = max_streams;
3454 /* Returns an error code if one of the endpoint already has streams.
3455 * This does not change any data structures, it only checks and gathers
3458 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3459 struct usb_device *udev,
3460 struct usb_host_endpoint **eps, unsigned int num_eps,
3461 unsigned int *num_streams, u32 *changed_ep_bitmask)
3463 unsigned int max_streams;
3464 unsigned int endpoint_flag;
3468 for (i = 0; i < num_eps; i++) {
3469 ret = xhci_check_streams_endpoint(xhci, udev,
3470 eps[i], udev->slot_id);
3474 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3475 if (max_streams < (*num_streams - 1)) {
3476 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3477 eps[i]->desc.bEndpointAddress,
3479 *num_streams = max_streams+1;
3482 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3483 if (*changed_ep_bitmask & endpoint_flag)
3485 *changed_ep_bitmask |= endpoint_flag;
3490 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3491 struct usb_device *udev,
3492 struct usb_host_endpoint **eps, unsigned int num_eps)
3494 u32 changed_ep_bitmask = 0;
3495 unsigned int slot_id;
3496 unsigned int ep_index;
3497 unsigned int ep_state;
3500 slot_id = udev->slot_id;
3501 if (!xhci->devs[slot_id])
3504 for (i = 0; i < num_eps; i++) {
3505 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3506 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3507 /* Are streams already being freed for the endpoint? */
3508 if (ep_state & EP_GETTING_NO_STREAMS) {
3509 xhci_warn(xhci, "WARN Can't disable streams for "
3511 "streams are being disabled already\n",
3512 eps[i]->desc.bEndpointAddress);
3515 /* Are there actually any streams to free? */
3516 if (!(ep_state & EP_HAS_STREAMS) &&
3517 !(ep_state & EP_GETTING_STREAMS)) {
3518 xhci_warn(xhci, "WARN Can't disable streams for "
3520 "streams are already disabled!\n",
3521 eps[i]->desc.bEndpointAddress);
3522 xhci_warn(xhci, "WARN xhci_free_streams() called "
3523 "with non-streams endpoint\n");
3526 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3528 return changed_ep_bitmask;
3532 * The USB device drivers use this function (through the HCD interface in USB
3533 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3534 * coordinate mass storage command queueing across multiple endpoints (basically
3535 * a stream ID == a task ID).
3537 * Setting up streams involves allocating the same size stream context array
3538 * for each endpoint and issuing a configure endpoint command for all endpoints.
3540 * Don't allow the call to succeed if one endpoint only supports one stream
3541 * (which means it doesn't support streams at all).
3543 * Drivers may get less stream IDs than they asked for, if the host controller
3544 * hardware or endpoints claim they can't support the number of requested
3547 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3548 struct usb_host_endpoint **eps, unsigned int num_eps,
3549 unsigned int num_streams, gfp_t mem_flags)
3552 struct xhci_hcd *xhci;
3553 struct xhci_virt_device *vdev;
3554 struct xhci_command *config_cmd;
3555 struct xhci_input_control_ctx *ctrl_ctx;
3556 unsigned int ep_index;
3557 unsigned int num_stream_ctxs;
3558 unsigned int max_packet;
3559 unsigned long flags;
3560 u32 changed_ep_bitmask = 0;
3565 /* Add one to the number of streams requested to account for
3566 * stream 0 that is reserved for xHCI usage.
3569 xhci = hcd_to_xhci(hcd);
3570 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3573 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3574 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3575 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3576 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3580 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3584 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3586 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3588 xhci_free_command(xhci, config_cmd);
3592 /* Check to make sure all endpoints are not already configured for
3593 * streams. While we're at it, find the maximum number of streams that
3594 * all the endpoints will support and check for duplicate endpoints.
3596 spin_lock_irqsave(&xhci->lock, flags);
3597 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3598 num_eps, &num_streams, &changed_ep_bitmask);
3600 xhci_free_command(xhci, config_cmd);
3601 spin_unlock_irqrestore(&xhci->lock, flags);
3604 if (num_streams <= 1) {
3605 xhci_warn(xhci, "WARN: endpoints can't handle "
3606 "more than one stream.\n");
3607 xhci_free_command(xhci, config_cmd);
3608 spin_unlock_irqrestore(&xhci->lock, flags);
3611 vdev = xhci->devs[udev->slot_id];
3612 /* Mark each endpoint as being in transition, so
3613 * xhci_urb_enqueue() will reject all URBs.
3615 for (i = 0; i < num_eps; i++) {
3616 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3617 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3619 spin_unlock_irqrestore(&xhci->lock, flags);
3621 /* Setup internal data structures and allocate HW data structures for
3622 * streams (but don't install the HW structures in the input context
3623 * until we're sure all memory allocation succeeded).
3625 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3626 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3627 num_stream_ctxs, num_streams);
3629 for (i = 0; i < num_eps; i++) {
3630 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3631 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3632 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3635 max_packet, mem_flags);
3636 if (!vdev->eps[ep_index].stream_info)
3638 /* Set maxPstreams in endpoint context and update deq ptr to
3639 * point to stream context array. FIXME
3643 /* Set up the input context for a configure endpoint command. */
3644 for (i = 0; i < num_eps; i++) {
3645 struct xhci_ep_ctx *ep_ctx;
3647 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3648 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3650 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3651 vdev->out_ctx, ep_index);
3652 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3653 vdev->eps[ep_index].stream_info);
3655 /* Tell the HW to drop its old copy of the endpoint context info
3656 * and add the updated copy from the input context.
3658 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3659 vdev->out_ctx, ctrl_ctx,
3660 changed_ep_bitmask, changed_ep_bitmask);
3662 /* Issue and wait for the configure endpoint command */
3663 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3666 /* xHC rejected the configure endpoint command for some reason, so we
3667 * leave the old ring intact and free our internal streams data
3673 spin_lock_irqsave(&xhci->lock, flags);
3674 for (i = 0; i < num_eps; i++) {
3675 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3676 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3677 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3678 udev->slot_id, ep_index);
3679 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3681 xhci_free_command(xhci, config_cmd);
3682 spin_unlock_irqrestore(&xhci->lock, flags);
3684 for (i = 0; i < num_eps; i++) {
3685 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3686 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3688 /* Subtract 1 for stream 0, which drivers can't use */
3689 return num_streams - 1;
3692 /* If it didn't work, free the streams! */
3693 for (i = 0; i < num_eps; i++) {
3694 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3695 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3696 vdev->eps[ep_index].stream_info = NULL;
3697 /* FIXME Unset maxPstreams in endpoint context and
3698 * update deq ptr to point to normal string ring.
3700 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3701 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3702 xhci_endpoint_zero(xhci, vdev, eps[i]);
3704 xhci_free_command(xhci, config_cmd);
3708 /* Transition the endpoint from using streams to being a "normal" endpoint
3711 * Modify the endpoint context state, submit a configure endpoint command,
3712 * and free all endpoint rings for streams if that completes successfully.
3714 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3715 struct usb_host_endpoint **eps, unsigned int num_eps,
3719 struct xhci_hcd *xhci;
3720 struct xhci_virt_device *vdev;
3721 struct xhci_command *command;
3722 struct xhci_input_control_ctx *ctrl_ctx;
3723 unsigned int ep_index;
3724 unsigned long flags;
3725 u32 changed_ep_bitmask;
3727 xhci = hcd_to_xhci(hcd);
3728 vdev = xhci->devs[udev->slot_id];
3730 /* Set up a configure endpoint command to remove the streams rings */
3731 spin_lock_irqsave(&xhci->lock, flags);
3732 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3733 udev, eps, num_eps);
3734 if (changed_ep_bitmask == 0) {
3735 spin_unlock_irqrestore(&xhci->lock, flags);
3739 /* Use the xhci_command structure from the first endpoint. We may have
3740 * allocated too many, but the driver may call xhci_free_streams() for
3741 * each endpoint it grouped into one call to xhci_alloc_streams().
3743 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3744 command = vdev->eps[ep_index].stream_info->free_streams_command;
3745 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3747 spin_unlock_irqrestore(&xhci->lock, flags);
3748 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3753 for (i = 0; i < num_eps; i++) {
3754 struct xhci_ep_ctx *ep_ctx;
3756 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3757 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3758 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3759 EP_GETTING_NO_STREAMS;
3761 xhci_endpoint_copy(xhci, command->in_ctx,
3762 vdev->out_ctx, ep_index);
3763 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3764 &vdev->eps[ep_index]);
3766 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3767 vdev->out_ctx, ctrl_ctx,
3768 changed_ep_bitmask, changed_ep_bitmask);
3769 spin_unlock_irqrestore(&xhci->lock, flags);
3771 /* Issue and wait for the configure endpoint command,
3772 * which must succeed.
3774 ret = xhci_configure_endpoint(xhci, udev, command,
3777 /* xHC rejected the configure endpoint command for some reason, so we
3778 * leave the streams rings intact.
3783 spin_lock_irqsave(&xhci->lock, flags);
3784 for (i = 0; i < num_eps; i++) {
3785 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3786 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3787 vdev->eps[ep_index].stream_info = NULL;
3788 /* FIXME Unset maxPstreams in endpoint context and
3789 * update deq ptr to point to normal string ring.
3791 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3792 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3794 spin_unlock_irqrestore(&xhci->lock, flags);
3800 * Deletes endpoint resources for endpoints that were active before a Reset
3801 * Device command, or a Disable Slot command. The Reset Device command leaves
3802 * the control endpoint intact, whereas the Disable Slot command deletes it.
3804 * Must be called with xhci->lock held.
3806 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3807 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3810 unsigned int num_dropped_eps = 0;
3811 unsigned int drop_flags = 0;
3813 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3814 if (virt_dev->eps[i].ring) {
3815 drop_flags |= 1 << i;
3819 xhci->num_active_eps -= num_dropped_eps;
3820 if (num_dropped_eps)
3821 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3822 "Dropped %u ep ctxs, flags = 0x%x, "
3824 num_dropped_eps, drop_flags,
3825 xhci->num_active_eps);
3829 * This submits a Reset Device Command, which will set the device state to 0,
3830 * set the device address to 0, and disable all the endpoints except the default
3831 * control endpoint. The USB core should come back and call
3832 * xhci_address_device(), and then re-set up the configuration. If this is
3833 * called because of a usb_reset_and_verify_device(), then the old alternate
3834 * settings will be re-installed through the normal bandwidth allocation
3837 * Wait for the Reset Device command to finish. Remove all structures
3838 * associated with the endpoints that were disabled. Clear the input device
3839 * structure? Reset the control endpoint 0 max packet size?
3841 * If the virt_dev to be reset does not exist or does not match the udev,
3842 * it means the device is lost, possibly due to the xHC restore error and
3843 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3844 * re-allocate the device.
3846 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3847 struct usb_device *udev)
3850 unsigned long flags;
3851 struct xhci_hcd *xhci;
3852 unsigned int slot_id;
3853 struct xhci_virt_device *virt_dev;
3854 struct xhci_command *reset_device_cmd;
3855 struct xhci_slot_ctx *slot_ctx;
3856 int old_active_eps = 0;
3858 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3861 xhci = hcd_to_xhci(hcd);
3862 slot_id = udev->slot_id;
3863 virt_dev = xhci->devs[slot_id];
3865 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3866 "not exist. Re-allocate the device\n", slot_id);
3867 ret = xhci_alloc_dev(hcd, udev);
3874 if (virt_dev->tt_info)
3875 old_active_eps = virt_dev->tt_info->active_eps;
3877 if (virt_dev->udev != udev) {
3878 /* If the virt_dev and the udev does not match, this virt_dev
3879 * may belong to another udev.
3880 * Re-allocate the device.
3882 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3883 "not match the udev. Re-allocate the device\n",
3885 ret = xhci_alloc_dev(hcd, udev);
3892 /* If device is not setup, there is no point in resetting it */
3893 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3894 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3895 SLOT_STATE_DISABLED)
3898 trace_xhci_discover_or_reset_device(slot_ctx);
3900 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3901 /* Allocate the command structure that holds the struct completion.
3902 * Assume we're in process context, since the normal device reset
3903 * process has to wait for the device anyway. Storage devices are
3904 * reset as part of error handling, so use GFP_NOIO instead of
3907 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3908 if (!reset_device_cmd) {
3909 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3913 /* Attempt to submit the Reset Device command to the command ring */
3914 spin_lock_irqsave(&xhci->lock, flags);
3916 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3918 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3919 spin_unlock_irqrestore(&xhci->lock, flags);
3920 goto command_cleanup;
3922 xhci_ring_cmd_db(xhci);
3923 spin_unlock_irqrestore(&xhci->lock, flags);
3925 /* Wait for the Reset Device command to finish */
3926 wait_for_completion(reset_device_cmd->completion);
3928 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3929 * unless we tried to reset a slot ID that wasn't enabled,
3930 * or the device wasn't in the addressed or configured state.
3932 ret = reset_device_cmd->status;
3934 case COMP_COMMAND_ABORTED:
3935 case COMP_COMMAND_RING_STOPPED:
3936 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3938 goto command_cleanup;
3939 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3940 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3941 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3943 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3944 xhci_dbg(xhci, "Not freeing device rings.\n");
3945 /* Don't treat this as an error. May change my mind later. */
3947 goto command_cleanup;
3949 xhci_dbg(xhci, "Successful reset device command.\n");
3952 if (xhci_is_vendor_info_code(xhci, ret))
3954 xhci_warn(xhci, "Unknown completion code %u for "
3955 "reset device command.\n", ret);
3957 goto command_cleanup;
3960 /* Free up host controller endpoint resources */
3961 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3962 spin_lock_irqsave(&xhci->lock, flags);
3963 /* Don't delete the default control endpoint resources */
3964 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3965 spin_unlock_irqrestore(&xhci->lock, flags);
3968 /* Everything but endpoint 0 is disabled, so free the rings. */
3969 for (i = 1; i < 31; i++) {
3970 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3972 if (ep->ep_state & EP_HAS_STREAMS) {
3973 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3974 xhci_get_endpoint_address(i));
3975 xhci_free_stream_info(xhci, ep->stream_info);
3976 ep->stream_info = NULL;
3977 ep->ep_state &= ~EP_HAS_STREAMS;
3981 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3982 xhci_free_endpoint_ring(xhci, virt_dev, i);
3984 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3985 xhci_drop_ep_from_interval_table(xhci,
3986 &virt_dev->eps[i].bw_info,
3991 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3993 /* If necessary, update the number of active TTs on this root port */
3994 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3995 virt_dev->flags = 0;
3999 xhci_free_command(xhci, reset_device_cmd);
4004 * At this point, the struct usb_device is about to go away, the device has
4005 * disconnected, and all traffic has been stopped and the endpoints have been
4006 * disabled. Free any HC data structures associated with that device.
4008 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4010 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4011 struct xhci_virt_device *virt_dev;
4012 struct xhci_slot_ctx *slot_ctx;
4013 unsigned long flags;
4017 * We called pm_runtime_get_noresume when the device was attached.
4018 * Decrement the counter here to allow controller to runtime suspend
4019 * if no devices remain.
4021 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4022 pm_runtime_put_noidle(hcd->self.controller);
4024 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
4025 /* If the host is halted due to driver unload, we still need to free the
4028 if (ret <= 0 && ret != -ENODEV)
4031 virt_dev = xhci->devs[udev->slot_id];
4032 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4033 trace_xhci_free_dev(slot_ctx);
4035 /* Stop any wayward timer functions (which may grab the lock) */
4036 for (i = 0; i < 31; i++)
4037 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4038 virt_dev->udev = NULL;
4039 xhci_disable_slot(xhci, udev->slot_id);
4041 spin_lock_irqsave(&xhci->lock, flags);
4042 xhci_free_virt_device(xhci, udev->slot_id);
4043 spin_unlock_irqrestore(&xhci->lock, flags);
4047 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4049 struct xhci_command *command;
4050 unsigned long flags;
4054 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4058 xhci_debugfs_remove_slot(xhci, slot_id);
4060 spin_lock_irqsave(&xhci->lock, flags);
4061 /* Don't disable the slot if the host controller is dead. */
4062 state = readl(&xhci->op_regs->status);
4063 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4064 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4065 spin_unlock_irqrestore(&xhci->lock, flags);
4070 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4073 spin_unlock_irqrestore(&xhci->lock, flags);
4077 xhci_ring_cmd_db(xhci);
4078 spin_unlock_irqrestore(&xhci->lock, flags);
4080 wait_for_completion(command->completion);
4082 if (command->status != COMP_SUCCESS)
4083 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4084 slot_id, command->status);
4086 xhci_free_command(xhci, command);
4092 * Checks if we have enough host controller resources for the default control
4095 * Must be called with xhci->lock held.
4097 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4099 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4100 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4101 "Not enough ep ctxs: "
4102 "%u active, need to add 1, limit is %u.",
4103 xhci->num_active_eps, xhci->limit_active_eps);
4106 xhci->num_active_eps += 1;
4107 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4108 "Adding 1 ep ctx, %u now active.",
4109 xhci->num_active_eps);
4115 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4116 * timed out, or allocating memory failed. Returns 1 on success.
4118 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4120 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4121 struct xhci_virt_device *vdev;
4122 struct xhci_slot_ctx *slot_ctx;
4123 unsigned long flags;
4125 struct xhci_command *command;
4127 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4131 spin_lock_irqsave(&xhci->lock, flags);
4132 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4134 spin_unlock_irqrestore(&xhci->lock, flags);
4135 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4136 xhci_free_command(xhci, command);
4139 xhci_ring_cmd_db(xhci);
4140 spin_unlock_irqrestore(&xhci->lock, flags);
4142 wait_for_completion(command->completion);
4143 slot_id = command->slot_id;
4145 if (!slot_id || command->status != COMP_SUCCESS) {
4146 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4147 xhci_trb_comp_code_string(command->status));
4148 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4150 readl(&xhci->cap_regs->hcs_params1)));
4151 xhci_free_command(xhci, command);
4155 xhci_free_command(xhci, command);
4157 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4158 spin_lock_irqsave(&xhci->lock, flags);
4159 ret = xhci_reserve_host_control_ep_resources(xhci);
4161 spin_unlock_irqrestore(&xhci->lock, flags);
4162 xhci_warn(xhci, "Not enough host resources, "
4163 "active endpoint contexts = %u\n",
4164 xhci->num_active_eps);
4167 spin_unlock_irqrestore(&xhci->lock, flags);
4169 /* Use GFP_NOIO, since this function can be called from
4170 * xhci_discover_or_reset_device(), which may be called as part of
4171 * mass storage driver error handling.
4173 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4174 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4177 vdev = xhci->devs[slot_id];
4178 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4179 trace_xhci_alloc_dev(slot_ctx);
4181 udev->slot_id = slot_id;
4183 xhci_debugfs_create_slot(xhci, slot_id);
4186 * If resetting upon resume, we can't put the controller into runtime
4187 * suspend if there is a device attached.
4189 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4190 pm_runtime_get_noresume(hcd->self.controller);
4192 /* Is this a LS or FS device under a HS hub? */
4193 /* Hub or peripherial? */
4197 xhci_disable_slot(xhci, udev->slot_id);
4198 xhci_free_virt_device(xhci, udev->slot_id);
4204 * Issue an Address Device command and optionally send a corresponding
4205 * SetAddress request to the device.
4207 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4208 enum xhci_setup_dev setup)
4210 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4211 unsigned long flags;
4212 struct xhci_virt_device *virt_dev;
4214 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4215 struct xhci_slot_ctx *slot_ctx;
4216 struct xhci_input_control_ctx *ctrl_ctx;
4218 struct xhci_command *command = NULL;
4220 mutex_lock(&xhci->mutex);
4222 if (xhci->xhc_state) { /* dying, removing or halted */
4227 if (!udev->slot_id) {
4228 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4229 "Bad Slot ID %d", udev->slot_id);
4234 virt_dev = xhci->devs[udev->slot_id];
4236 if (WARN_ON(!virt_dev)) {
4238 * In plug/unplug torture test with an NEC controller,
4239 * a zero-dereference was observed once due to virt_dev = 0.
4240 * Print useful debug rather than crash if it is observed again!
4242 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4247 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4248 trace_xhci_setup_device_slot(slot_ctx);
4250 if (setup == SETUP_CONTEXT_ONLY) {
4251 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4252 SLOT_STATE_DEFAULT) {
4253 xhci_dbg(xhci, "Slot already in default state\n");
4258 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4264 command->in_ctx = virt_dev->in_ctx;
4266 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4267 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4269 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4275 * If this is the first Set Address since device plug-in or
4276 * virt_device realloaction after a resume with an xHCI power loss,
4277 * then set up the slot context.
4279 if (!slot_ctx->dev_info)
4280 xhci_setup_addressable_virt_dev(xhci, udev);
4281 /* Otherwise, update the control endpoint ring enqueue pointer. */
4283 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4284 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4285 ctrl_ctx->drop_flags = 0;
4287 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4288 le32_to_cpu(slot_ctx->dev_info) >> 27);
4290 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4291 spin_lock_irqsave(&xhci->lock, flags);
4292 trace_xhci_setup_device(virt_dev);
4293 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4294 udev->slot_id, setup);
4296 spin_unlock_irqrestore(&xhci->lock, flags);
4297 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4298 "FIXME: allocate a command ring segment");
4301 xhci_ring_cmd_db(xhci);
4302 spin_unlock_irqrestore(&xhci->lock, flags);
4304 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4305 wait_for_completion(command->completion);
4307 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4308 * the SetAddress() "recovery interval" required by USB and aborting the
4309 * command on a timeout.
4311 switch (command->status) {
4312 case COMP_COMMAND_ABORTED:
4313 case COMP_COMMAND_RING_STOPPED:
4314 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4317 case COMP_CONTEXT_STATE_ERROR:
4318 case COMP_SLOT_NOT_ENABLED_ERROR:
4319 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4320 act, udev->slot_id);
4323 case COMP_USB_TRANSACTION_ERROR:
4324 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4326 mutex_unlock(&xhci->mutex);
4327 ret = xhci_disable_slot(xhci, udev->slot_id);
4328 xhci_free_virt_device(xhci, udev->slot_id);
4330 xhci_alloc_dev(hcd, udev);
4331 kfree(command->completion);
4334 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4335 dev_warn(&udev->dev,
4336 "ERROR: Incompatible device for setup %s command\n", act);
4340 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4341 "Successful setup %s command", act);
4345 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4346 act, command->status);
4347 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4353 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4354 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4355 "Op regs DCBAA ptr = %#016llx", temp_64);
4356 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4357 "Slot ID %d dcbaa entry @%p = %#016llx",
4359 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4360 (unsigned long long)
4361 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4362 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4363 "Output Context DMA address = %#08llx",
4364 (unsigned long long)virt_dev->out_ctx->dma);
4365 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4366 le32_to_cpu(slot_ctx->dev_info) >> 27);
4368 * USB core uses address 1 for the roothubs, so we add one to the
4369 * address given back to us by the HC.
4371 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4372 le32_to_cpu(slot_ctx->dev_info) >> 27);
4373 /* Zero the input context control for later use */
4374 ctrl_ctx->add_flags = 0;
4375 ctrl_ctx->drop_flags = 0;
4376 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4377 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4379 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4380 "Internal device address = %d",
4381 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4383 mutex_unlock(&xhci->mutex);
4385 kfree(command->completion);
4391 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4393 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4396 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4398 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4402 * Transfer the port index into real index in the HW port status
4403 * registers. Caculate offset between the port's PORTSC register
4404 * and port status base. Divide the number of per port register
4405 * to get the real index. The raw port number bases 1.
4407 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4409 struct xhci_hub *rhub;
4411 rhub = xhci_get_rhub(hcd);
4412 return rhub->ports[port1 - 1]->hw_portnum + 1;
4416 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4417 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4419 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4420 struct usb_device *udev, u16 max_exit_latency)
4422 struct xhci_virt_device *virt_dev;
4423 struct xhci_command *command;
4424 struct xhci_input_control_ctx *ctrl_ctx;
4425 struct xhci_slot_ctx *slot_ctx;
4426 unsigned long flags;
4429 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4433 spin_lock_irqsave(&xhci->lock, flags);
4435 virt_dev = xhci->devs[udev->slot_id];
4438 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4439 * xHC was re-initialized. Exit latency will be set later after
4440 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4443 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4444 spin_unlock_irqrestore(&xhci->lock, flags);
4448 /* Attempt to issue an Evaluate Context command to change the MEL. */
4449 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4451 spin_unlock_irqrestore(&xhci->lock, flags);
4452 xhci_free_command(xhci, command);
4453 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4458 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4459 spin_unlock_irqrestore(&xhci->lock, flags);
4461 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4462 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4463 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4464 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4465 slot_ctx->dev_state = 0;
4467 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4468 "Set up evaluate context for LPM MEL change.");
4470 /* Issue and wait for the evaluate context command. */
4471 ret = xhci_configure_endpoint(xhci, udev, command,
4475 spin_lock_irqsave(&xhci->lock, flags);
4476 virt_dev->current_mel = max_exit_latency;
4477 spin_unlock_irqrestore(&xhci->lock, flags);
4480 xhci_free_command(xhci, command);
4487 /* BESL to HIRD Encoding array for USB2 LPM */
4488 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4489 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4491 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4492 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4493 struct usb_device *udev)
4495 int u2del, besl, besl_host;
4496 int besl_device = 0;
4499 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4500 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4502 if (field & USB_BESL_SUPPORT) {
4503 for (besl_host = 0; besl_host < 16; besl_host++) {
4504 if (xhci_besl_encoding[besl_host] >= u2del)
4507 /* Use baseline BESL value as default */
4508 if (field & USB_BESL_BASELINE_VALID)
4509 besl_device = USB_GET_BESL_BASELINE(field);
4510 else if (field & USB_BESL_DEEP_VALID)
4511 besl_device = USB_GET_BESL_DEEP(field);
4516 besl_host = (u2del - 51) / 75 + 1;
4519 besl = besl_host + besl_device;
4526 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4527 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4534 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4536 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4537 l1 = udev->l1_params.timeout / 256;
4539 /* device has preferred BESLD */
4540 if (field & USB_BESL_DEEP_VALID) {
4541 besld = USB_GET_BESL_DEEP(field);
4545 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4548 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4549 struct usb_device *udev, int enable)
4551 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4552 struct xhci_port **ports;
4553 __le32 __iomem *pm_addr, *hlpm_addr;
4554 u32 pm_val, hlpm_val, field;
4555 unsigned int port_num;
4556 unsigned long flags;
4557 int hird, exit_latency;
4560 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4563 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4567 if (!udev->parent || udev->parent->parent ||
4568 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4571 if (udev->usb2_hw_lpm_capable != 1)
4574 spin_lock_irqsave(&xhci->lock, flags);
4576 ports = xhci->usb2_rhub.ports;
4577 port_num = udev->portnum - 1;
4578 pm_addr = ports[port_num]->addr + PORTPMSC;
4579 pm_val = readl(pm_addr);
4580 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4582 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4583 enable ? "enable" : "disable", port_num + 1);
4586 /* Host supports BESL timeout instead of HIRD */
4587 if (udev->usb2_hw_lpm_besl_capable) {
4588 /* if device doesn't have a preferred BESL value use a
4589 * default one which works with mixed HIRD and BESL
4590 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4592 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4593 if ((field & USB_BESL_SUPPORT) &&
4594 (field & USB_BESL_BASELINE_VALID))
4595 hird = USB_GET_BESL_BASELINE(field);
4597 hird = udev->l1_params.besl;
4599 exit_latency = xhci_besl_encoding[hird];
4600 spin_unlock_irqrestore(&xhci->lock, flags);
4602 ret = xhci_change_max_exit_latency(xhci, udev,
4606 spin_lock_irqsave(&xhci->lock, flags);
4608 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4609 writel(hlpm_val, hlpm_addr);
4613 hird = xhci_calculate_hird_besl(xhci, udev);
4616 pm_val &= ~PORT_HIRD_MASK;
4617 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4618 writel(pm_val, pm_addr);
4619 pm_val = readl(pm_addr);
4621 writel(pm_val, pm_addr);
4625 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4626 writel(pm_val, pm_addr);
4629 if (udev->usb2_hw_lpm_besl_capable) {
4630 spin_unlock_irqrestore(&xhci->lock, flags);
4631 xhci_change_max_exit_latency(xhci, udev, 0);
4632 readl_poll_timeout(ports[port_num]->addr, pm_val,
4633 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4639 spin_unlock_irqrestore(&xhci->lock, flags);
4643 /* check if a usb2 port supports a given extened capability protocol
4644 * only USB2 ports extended protocol capability values are cached.
4645 * Return 1 if capability is supported
4647 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4648 unsigned capability)
4650 u32 port_offset, port_count;
4653 for (i = 0; i < xhci->num_ext_caps; i++) {
4654 if (xhci->ext_caps[i] & capability) {
4655 /* port offsets starts at 1 */
4656 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4657 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4658 if (port >= port_offset &&
4659 port < port_offset + port_count)
4666 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4668 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4669 int portnum = udev->portnum - 1;
4671 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4674 /* we only support lpm for non-hub device connected to root hub yet */
4675 if (!udev->parent || udev->parent->parent ||
4676 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4679 if (xhci->hw_lpm_support == 1 &&
4680 xhci_check_usb2_port_capability(
4681 xhci, portnum, XHCI_HLC)) {
4682 udev->usb2_hw_lpm_capable = 1;
4683 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4684 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4685 if (xhci_check_usb2_port_capability(xhci, portnum,
4687 udev->usb2_hw_lpm_besl_capable = 1;
4693 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4695 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4696 static unsigned long long xhci_service_interval_to_ns(
4697 struct usb_endpoint_descriptor *desc)
4699 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4702 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4703 enum usb3_link_state state)
4705 unsigned long long sel;
4706 unsigned long long pel;
4707 unsigned int max_sel_pel;
4712 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4713 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4714 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4715 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4719 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4720 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4721 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4725 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4727 return USB3_LPM_DISABLED;
4730 if (sel <= max_sel_pel && pel <= max_sel_pel)
4731 return USB3_LPM_DEVICE_INITIATED;
4733 if (sel > max_sel_pel)
4734 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4735 "due to long SEL %llu ms\n",
4738 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4739 "due to long PEL %llu ms\n",
4741 return USB3_LPM_DISABLED;
4744 /* The U1 timeout should be the maximum of the following values:
4745 * - For control endpoints, U1 system exit latency (SEL) * 3
4746 * - For bulk endpoints, U1 SEL * 5
4747 * - For interrupt endpoints:
4748 * - Notification EPs, U1 SEL * 3
4749 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4750 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4752 static unsigned long long xhci_calculate_intel_u1_timeout(
4753 struct usb_device *udev,
4754 struct usb_endpoint_descriptor *desc)
4756 unsigned long long timeout_ns;
4760 ep_type = usb_endpoint_type(desc);
4762 case USB_ENDPOINT_XFER_CONTROL:
4763 timeout_ns = udev->u1_params.sel * 3;
4765 case USB_ENDPOINT_XFER_BULK:
4766 timeout_ns = udev->u1_params.sel * 5;
4768 case USB_ENDPOINT_XFER_INT:
4769 intr_type = usb_endpoint_interrupt_type(desc);
4770 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4771 timeout_ns = udev->u1_params.sel * 3;
4774 /* Otherwise the calculation is the same as isoc eps */
4776 case USB_ENDPOINT_XFER_ISOC:
4777 timeout_ns = xhci_service_interval_to_ns(desc);
4778 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4779 if (timeout_ns < udev->u1_params.sel * 2)
4780 timeout_ns = udev->u1_params.sel * 2;
4789 /* Returns the hub-encoded U1 timeout value. */
4790 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4791 struct usb_device *udev,
4792 struct usb_endpoint_descriptor *desc)
4794 unsigned long long timeout_ns;
4796 /* Prevent U1 if service interval is shorter than U1 exit latency */
4797 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4798 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4799 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4800 return USB3_LPM_DISABLED;
4804 if (xhci->quirks & XHCI_INTEL_HOST)
4805 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4807 timeout_ns = udev->u1_params.sel;
4809 /* The U1 timeout is encoded in 1us intervals.
4810 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4812 if (timeout_ns == USB3_LPM_DISABLED)
4815 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4817 /* If the necessary timeout value is bigger than what we can set in the
4818 * USB 3.0 hub, we have to disable hub-initiated U1.
4820 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4822 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4823 "due to long timeout %llu ms\n", timeout_ns);
4824 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4827 /* The U2 timeout should be the maximum of:
4828 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4829 * - largest bInterval of any active periodic endpoint (to avoid going
4830 * into lower power link states between intervals).
4831 * - the U2 Exit Latency of the device
4833 static unsigned long long xhci_calculate_intel_u2_timeout(
4834 struct usb_device *udev,
4835 struct usb_endpoint_descriptor *desc)
4837 unsigned long long timeout_ns;
4838 unsigned long long u2_del_ns;
4840 timeout_ns = 10 * 1000 * 1000;
4842 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4843 (xhci_service_interval_to_ns(desc) > timeout_ns))
4844 timeout_ns = xhci_service_interval_to_ns(desc);
4846 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4847 if (u2_del_ns > timeout_ns)
4848 timeout_ns = u2_del_ns;
4853 /* Returns the hub-encoded U2 timeout value. */
4854 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4855 struct usb_device *udev,
4856 struct usb_endpoint_descriptor *desc)
4858 unsigned long long timeout_ns;
4860 /* Prevent U2 if service interval is shorter than U2 exit latency */
4861 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4862 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4863 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4864 return USB3_LPM_DISABLED;
4868 if (xhci->quirks & XHCI_INTEL_HOST)
4869 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4871 timeout_ns = udev->u2_params.sel;
4873 /* The U2 timeout is encoded in 256us intervals */
4874 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4875 /* If the necessary timeout value is bigger than what we can set in the
4876 * USB 3.0 hub, we have to disable hub-initiated U2.
4878 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4880 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4881 "due to long timeout %llu ms\n", timeout_ns);
4882 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4885 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4886 struct usb_device *udev,
4887 struct usb_endpoint_descriptor *desc,
4888 enum usb3_link_state state,
4891 if (state == USB3_LPM_U1)
4892 return xhci_calculate_u1_timeout(xhci, udev, desc);
4893 else if (state == USB3_LPM_U2)
4894 return xhci_calculate_u2_timeout(xhci, udev, desc);
4896 return USB3_LPM_DISABLED;
4899 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4900 struct usb_device *udev,
4901 struct usb_endpoint_descriptor *desc,
4902 enum usb3_link_state state,
4907 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4908 desc, state, timeout);
4910 /* If we found we can't enable hub-initiated LPM, and
4911 * the U1 or U2 exit latency was too high to allow
4912 * device-initiated LPM as well, then we will disable LPM
4913 * for this device, so stop searching any further.
4915 if (alt_timeout == USB3_LPM_DISABLED) {
4916 *timeout = alt_timeout;
4919 if (alt_timeout > *timeout)
4920 *timeout = alt_timeout;
4924 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4925 struct usb_device *udev,
4926 struct usb_host_interface *alt,
4927 enum usb3_link_state state,
4932 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4933 if (xhci_update_timeout_for_endpoint(xhci, udev,
4934 &alt->endpoint[j].desc, state, timeout))
4940 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4941 enum usb3_link_state state)
4943 struct usb_device *parent;
4944 unsigned int num_hubs;
4946 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4947 for (parent = udev->parent, num_hubs = 0; parent->parent;
4948 parent = parent->parent)
4954 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4955 " below second-tier hub.\n");
4956 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4957 "to decrease power consumption.\n");
4961 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4962 struct usb_device *udev,
4963 enum usb3_link_state state)
4965 if (xhci->quirks & XHCI_INTEL_HOST)
4966 return xhci_check_intel_tier_policy(udev, state);
4971 /* Returns the U1 or U2 timeout that should be enabled.
4972 * If the tier check or timeout setting functions return with a non-zero exit
4973 * code, that means the timeout value has been finalized and we shouldn't look
4974 * at any more endpoints.
4976 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4977 struct usb_device *udev, enum usb3_link_state state)
4979 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4980 struct usb_host_config *config;
4983 u16 timeout = USB3_LPM_DISABLED;
4985 if (state == USB3_LPM_U1)
4987 else if (state == USB3_LPM_U2)
4990 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4995 /* Gather some information about the currently installed configuration
4996 * and alternate interface settings.
4998 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
5002 config = udev->actconfig;
5006 for (i = 0; i < config->desc.bNumInterfaces; i++) {
5007 struct usb_driver *driver;
5008 struct usb_interface *intf = config->interface[i];
5013 /* Check if any currently bound drivers want hub-initiated LPM
5016 if (intf->dev.driver) {
5017 driver = to_usb_driver(intf->dev.driver);
5018 if (driver && driver->disable_hub_initiated_lpm) {
5019 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
5020 state_name, driver->name);
5021 timeout = xhci_get_timeout_no_hub_lpm(udev,
5023 if (timeout == USB3_LPM_DISABLED)
5028 /* Not sure how this could happen... */
5029 if (!intf->cur_altsetting)
5032 if (xhci_update_timeout_for_interface(xhci, udev,
5033 intf->cur_altsetting,
5040 static int calculate_max_exit_latency(struct usb_device *udev,
5041 enum usb3_link_state state_changed,
5042 u16 hub_encoded_timeout)
5044 unsigned long long u1_mel_us = 0;
5045 unsigned long long u2_mel_us = 0;
5046 unsigned long long mel_us = 0;
5052 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5053 hub_encoded_timeout == USB3_LPM_DISABLED);
5054 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5055 hub_encoded_timeout == USB3_LPM_DISABLED);
5057 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5058 hub_encoded_timeout != USB3_LPM_DISABLED);
5059 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5060 hub_encoded_timeout != USB3_LPM_DISABLED);
5062 /* If U1 was already enabled and we're not disabling it,
5063 * or we're going to enable U1, account for the U1 max exit latency.
5065 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5067 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5068 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5070 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5072 mel_us = max(u1_mel_us, u2_mel_us);
5074 /* xHCI host controller max exit latency field is only 16 bits wide. */
5075 if (mel_us > MAX_EXIT) {
5076 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5077 "is too big.\n", mel_us);
5083 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5084 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5085 struct usb_device *udev, enum usb3_link_state state)
5087 struct xhci_hcd *xhci;
5088 struct xhci_port *port;
5089 u16 hub_encoded_timeout;
5093 xhci = hcd_to_xhci(hcd);
5094 /* The LPM timeout values are pretty host-controller specific, so don't
5095 * enable hub-initiated timeouts unless the vendor has provided
5096 * information about their timeout algorithm.
5098 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5099 !xhci->devs[udev->slot_id])
5100 return USB3_LPM_DISABLED;
5102 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5103 return USB3_LPM_DISABLED;
5105 /* If connected to root port then check port can handle lpm */
5106 if (udev->parent && !udev->parent->parent) {
5107 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5108 if (port->lpm_incapable)
5109 return USB3_LPM_DISABLED;
5112 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5113 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5115 /* Max Exit Latency is too big, disable LPM. */
5116 hub_encoded_timeout = USB3_LPM_DISABLED;
5120 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5123 return hub_encoded_timeout;
5126 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5127 struct usb_device *udev, enum usb3_link_state state)
5129 struct xhci_hcd *xhci;
5132 xhci = hcd_to_xhci(hcd);
5133 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5134 !xhci->devs[udev->slot_id])
5137 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5138 return xhci_change_max_exit_latency(xhci, udev, mel);
5140 #else /* CONFIG_PM */
5142 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5143 struct usb_device *udev, int enable)
5148 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5153 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5154 struct usb_device *udev, enum usb3_link_state state)
5156 return USB3_LPM_DISABLED;
5159 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5160 struct usb_device *udev, enum usb3_link_state state)
5164 #endif /* CONFIG_PM */
5166 /*-------------------------------------------------------------------------*/
5168 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5169 * internal data structures for the device.
5171 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5172 struct usb_tt *tt, gfp_t mem_flags)
5174 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5175 struct xhci_virt_device *vdev;
5176 struct xhci_command *config_cmd;
5177 struct xhci_input_control_ctx *ctrl_ctx;
5178 struct xhci_slot_ctx *slot_ctx;
5179 unsigned long flags;
5180 unsigned think_time;
5183 /* Ignore root hubs */
5187 vdev = xhci->devs[hdev->slot_id];
5189 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5193 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5197 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5199 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5201 xhci_free_command(xhci, config_cmd);
5205 spin_lock_irqsave(&xhci->lock, flags);
5206 if (hdev->speed == USB_SPEED_HIGH &&
5207 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5208 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5209 xhci_free_command(xhci, config_cmd);
5210 spin_unlock_irqrestore(&xhci->lock, flags);
5214 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5215 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5216 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5217 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5219 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5220 * but it may be already set to 1 when setup an xHCI virtual
5221 * device, so clear it anyway.
5224 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5225 else if (hdev->speed == USB_SPEED_FULL)
5226 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5228 if (xhci->hci_version > 0x95) {
5229 xhci_dbg(xhci, "xHCI version %x needs hub "
5230 "TT think time and number of ports\n",
5231 (unsigned int) xhci->hci_version);
5232 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5233 /* Set TT think time - convert from ns to FS bit times.
5234 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5235 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5237 * xHCI 1.0: this field shall be 0 if the device is not a
5240 think_time = tt->think_time;
5241 if (think_time != 0)
5242 think_time = (think_time / 666) - 1;
5243 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5244 slot_ctx->tt_info |=
5245 cpu_to_le32(TT_THINK_TIME(think_time));
5247 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5248 "TT think time or number of ports\n",
5249 (unsigned int) xhci->hci_version);
5251 slot_ctx->dev_state = 0;
5252 spin_unlock_irqrestore(&xhci->lock, flags);
5254 xhci_dbg(xhci, "Set up %s for hub device.\n",
5255 (xhci->hci_version > 0x95) ?
5256 "configure endpoint" : "evaluate context");
5258 /* Issue and wait for the configure endpoint or
5259 * evaluate context command.
5261 if (xhci->hci_version > 0x95)
5262 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5265 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5268 xhci_free_command(xhci, config_cmd);
5271 EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5273 static int xhci_get_frame(struct usb_hcd *hcd)
5275 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5276 /* EHCI mods by the periodic size. Why? */
5277 return readl(&xhci->run_regs->microframe_index) >> 3;
5280 static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5282 xhci->usb2_rhub.hcd = hcd;
5283 hcd->speed = HCD_USB2;
5284 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5286 * USB 2.0 roothub under xHCI has an integrated TT,
5287 * (rate matching hub) as opposed to having an OHCI/UHCI
5288 * companion controller.
5293 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5295 unsigned int minor_rev;
5298 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5299 * should return 0x31 for sbrn, or that the minor revision
5300 * is a two digit BCD containig minor and sub-minor numbers.
5301 * This was later clarified in xHCI 1.2.
5303 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5304 * minor revision set to 0x1 instead of 0x10.
5306 if (xhci->usb3_rhub.min_rev == 0x1)
5309 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5311 switch (minor_rev) {
5313 hcd->speed = HCD_USB32;
5314 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5315 hcd->self.root_hub->rx_lanes = 2;
5316 hcd->self.root_hub->tx_lanes = 2;
5317 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5320 hcd->speed = HCD_USB31;
5321 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5322 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5325 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5326 minor_rev, minor_rev ? "Enhanced " : "");
5328 xhci->usb3_rhub.hcd = hcd;
5331 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5333 struct xhci_hcd *xhci;
5335 * TODO: Check with DWC3 clients for sysdev according to
5338 struct device *dev = hcd->self.sysdev;
5341 /* Accept arbitrarily long scatter-gather lists */
5342 hcd->self.sg_tablesize = ~0;
5344 /* support to build packet from discontinuous buffers */
5345 hcd->self.no_sg_constraint = 1;
5347 /* XHCI controllers don't stop the ep queue on short packets :| */
5348 hcd->self.no_stop_on_short = 1;
5350 xhci = hcd_to_xhci(hcd);
5352 if (!usb_hcd_is_primary_hcd(hcd)) {
5353 xhci_hcd_init_usb3_data(xhci, hcd);
5357 mutex_init(&xhci->mutex);
5358 xhci->main_hcd = hcd;
5359 xhci->cap_regs = hcd->regs;
5360 xhci->op_regs = hcd->regs +
5361 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5362 xhci->run_regs = hcd->regs +
5363 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5364 /* Cache read-only capability registers */
5365 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5366 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5367 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5368 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5369 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5370 if (xhci->hci_version > 0x100)
5371 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5373 /* xhci-plat or xhci-pci might have set max_interrupters already */
5374 if ((!xhci->max_interrupters) ||
5375 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5376 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5378 xhci->quirks |= quirks;
5380 get_quirks(dev, xhci);
5382 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5383 * success event after a short transfer. This quirk will ignore such
5386 if (xhci->hci_version > 0x96)
5387 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5389 /* Make sure the HC is halted. */
5390 retval = xhci_halt(xhci);
5394 xhci_zero_64b_regs(xhci);
5396 xhci_dbg(xhci, "Resetting HCD\n");
5397 /* Reset the internal HC memory state and registers. */
5398 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5401 xhci_dbg(xhci, "Reset complete\n");
5404 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5405 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5406 * address memory pointers actually. So, this driver clears the AC64
5407 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5408 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5410 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5411 xhci->hcc_params &= ~BIT(0);
5413 /* Set dma_mask and coherent_dma_mask to 64-bits,
5414 * if xHC supports 64-bit addressing */
5415 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5416 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5417 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5418 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5421 * This is to avoid error in cases where a 32-bit USB
5422 * controller is used on a 64-bit capable system.
5424 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5427 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5428 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5431 xhci_dbg(xhci, "Calling HCD init\n");
5432 /* Initialize HCD and host controller data structures. */
5433 retval = xhci_init(hcd);
5436 xhci_dbg(xhci, "Called HCD init\n");
5438 if (xhci_hcd_is_usb3(hcd))
5439 xhci_hcd_init_usb3_data(xhci, hcd);
5441 xhci_hcd_init_usb2_data(xhci, hcd);
5443 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5444 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5448 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5450 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5451 struct usb_host_endpoint *ep)
5453 struct xhci_hcd *xhci;
5454 struct usb_device *udev;
5455 unsigned int slot_id;
5456 unsigned int ep_index;
5457 unsigned long flags;
5459 xhci = hcd_to_xhci(hcd);
5461 spin_lock_irqsave(&xhci->lock, flags);
5462 udev = (struct usb_device *)ep->hcpriv;
5463 slot_id = udev->slot_id;
5464 ep_index = xhci_get_endpoint_index(&ep->desc);
5466 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5467 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5468 spin_unlock_irqrestore(&xhci->lock, flags);
5471 static const struct hc_driver xhci_hc_driver = {
5472 .description = "xhci-hcd",
5473 .product_desc = "xHCI Host Controller",
5474 .hcd_priv_size = sizeof(struct xhci_hcd),
5477 * generic hardware linkage
5480 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5484 * basic lifecycle operations
5486 .reset = NULL, /* set in xhci_init_driver() */
5489 .shutdown = xhci_shutdown,
5492 * managing i/o requests and associated device resources
5494 .map_urb_for_dma = xhci_map_urb_for_dma,
5495 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5496 .urb_enqueue = xhci_urb_enqueue,
5497 .urb_dequeue = xhci_urb_dequeue,
5498 .alloc_dev = xhci_alloc_dev,
5499 .free_dev = xhci_free_dev,
5500 .alloc_streams = xhci_alloc_streams,
5501 .free_streams = xhci_free_streams,
5502 .add_endpoint = xhci_add_endpoint,
5503 .drop_endpoint = xhci_drop_endpoint,
5504 .endpoint_disable = xhci_endpoint_disable,
5505 .endpoint_reset = xhci_endpoint_reset,
5506 .check_bandwidth = xhci_check_bandwidth,
5507 .reset_bandwidth = xhci_reset_bandwidth,
5508 .address_device = xhci_address_device,
5509 .enable_device = xhci_enable_device,
5510 .update_hub_device = xhci_update_hub_device,
5511 .reset_device = xhci_discover_or_reset_device,
5514 * scheduling support
5516 .get_frame_number = xhci_get_frame,
5521 .hub_control = xhci_hub_control,
5522 .hub_status_data = xhci_hub_status_data,
5523 .bus_suspend = xhci_bus_suspend,
5524 .bus_resume = xhci_bus_resume,
5525 .get_resuming_ports = xhci_get_resuming_ports,
5528 * call back when device connected and addressed
5530 .update_device = xhci_update_device,
5531 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5532 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5533 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5534 .find_raw_port_number = xhci_find_raw_port_number,
5535 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5538 void xhci_init_driver(struct hc_driver *drv,
5539 const struct xhci_driver_overrides *over)
5543 /* Copy the generic table to drv then apply the overrides */
5544 *drv = xhci_hc_driver;
5547 drv->hcd_priv_size += over->extra_priv_size;
5549 drv->reset = over->reset;
5551 drv->start = over->start;
5552 if (over->add_endpoint)
5553 drv->add_endpoint = over->add_endpoint;
5554 if (over->drop_endpoint)
5555 drv->drop_endpoint = over->drop_endpoint;
5556 if (over->check_bandwidth)
5557 drv->check_bandwidth = over->check_bandwidth;
5558 if (over->reset_bandwidth)
5559 drv->reset_bandwidth = over->reset_bandwidth;
5560 if (over->update_hub_device)
5561 drv->update_hub_device = over->update_hub_device;
5562 if (over->hub_control)
5563 drv->hub_control = over->hub_control;
5566 EXPORT_SYMBOL_GPL(xhci_init_driver);
5568 MODULE_DESCRIPTION(DRIVER_DESC);
5569 MODULE_AUTHOR(DRIVER_AUTHOR);
5570 MODULE_LICENSE("GPL");
5572 static int __init xhci_hcd_init(void)
5575 * Check the compiler generated sizes of structures that must be laid
5576 * out in specific ways for hardware access.
5578 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5579 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5580 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5581 /* xhci_device_control has eight fields, and also
5582 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5584 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5585 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5586 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5587 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5588 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5589 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5590 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5595 xhci_debugfs_create_root();
5602 * If an init function is provided, an exit function must also be provided
5603 * to allow module unload.
5605 static void __exit xhci_hcd_fini(void)
5607 xhci_debugfs_remove_root();
5611 module_init(xhci_hcd_init);
5612 module_exit(xhci_hcd_fini);