1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
113 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
116 ret = xhci_handshake(&xhci->op_regs->status,
117 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 xhci_warn(xhci, "Host halt failed, %d\n", ret);
122 xhci->xhc_state |= XHCI_STATE_HALTED;
123 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
128 * Set the run bit and wait for the host to be running.
130 int xhci_start(struct xhci_hcd *xhci)
135 temp = readl(&xhci->op_regs->command);
137 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 writel(temp, &xhci->op_regs->command);
142 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 ret = xhci_handshake(&xhci->op_regs->status,
146 STS_HALT, 0, XHCI_MAX_HALT_USEC);
147 if (ret == -ETIMEDOUT)
148 xhci_err(xhci, "Host took too long to start, "
149 "waited %u microseconds.\n",
152 /* clear state flags. Including dying, halted or removing */
161 * This resets pipelines, timers, counters, state machines, etc.
162 * Transactions will be terminated immediately, and operational registers
163 * will be set to their defaults.
165 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
171 state = readl(&xhci->op_regs->status);
173 if (state == ~(u32)0) {
174 xhci_warn(xhci, "Host not accessible, reset failed.\n");
178 if ((state & STS_HALT) == 0) {
179 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
183 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
184 command = readl(&xhci->op_regs->command);
185 command |= CMD_RESET;
186 writel(command, &xhci->op_regs->command);
188 /* Existing Intel xHCI controllers require a delay of 1 mS,
189 * after setting the CMD_RESET bit, and before accessing any
190 * HC registers. This allows the HC to complete the
191 * reset operation and be ready for HC register access.
192 * Without this delay, the subsequent HC register access,
193 * may result in a system hang very rarely.
195 if (xhci->quirks & XHCI_INTEL_HOST)
198 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
202 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
203 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
205 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
206 "Wait for controller to be ready for doorbell rings");
208 * xHCI cannot write to any doorbells or operational registers other
209 * than status until the "Controller Not Ready" flag is cleared.
211 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
213 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
214 xhci->usb2_rhub.bus_state.suspended_ports = 0;
215 xhci->usb2_rhub.bus_state.resuming_ports = 0;
216 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb3_rhub.bus_state.suspended_ports = 0;
218 xhci->usb3_rhub.bus_state.resuming_ports = 0;
223 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
225 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
231 * Some Renesas controllers get into a weird state if they are
232 * reset while programmed with 64bit addresses (they will preserve
233 * the top half of the address in internal, non visible
234 * registers). You end up with half the address coming from the
235 * kernel, and the other half coming from the firmware. Also,
236 * changing the programming leads to extra accesses even if the
237 * controller is supposed to be halted. The controller ends up with
238 * a fatal fault, and is then ripe for being properly reset.
240 * Special care is taken to only apply this if the device is behind
241 * an iommu. Doing anything when there is no iommu is definitely
244 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
247 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
249 /* Clear HSEIE so that faults do not get signaled */
250 val = readl(&xhci->op_regs->command);
252 writel(val, &xhci->op_regs->command);
254 /* Clear HSE (aka FATAL) */
255 val = readl(&xhci->op_regs->status);
257 writel(val, &xhci->op_regs->status);
259 /* Now zero the registers, and brace for impact */
260 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
261 if (upper_32_bits(val))
262 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
263 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
264 if (upper_32_bits(val))
265 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
267 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
268 ARRAY_SIZE(xhci->run_regs->ir_set));
270 for (i = 0; i < intrs; i++) {
271 struct xhci_intr_reg __iomem *ir;
273 ir = &xhci->run_regs->ir_set[i];
274 val = xhci_read_64(xhci, &ir->erst_base);
275 if (upper_32_bits(val))
276 xhci_write_64(xhci, 0, &ir->erst_base);
277 val= xhci_read_64(xhci, &ir->erst_dequeue);
278 if (upper_32_bits(val))
279 xhci_write_64(xhci, 0, &ir->erst_dequeue);
282 /* Wait for the fault to appear. It will be cleared on reset */
283 err = xhci_handshake(&xhci->op_regs->status,
284 STS_FATAL, STS_FATAL,
287 xhci_info(xhci, "Fault detected\n");
290 #ifdef CONFIG_USB_PCI
294 static int xhci_setup_msi(struct xhci_hcd *xhci)
298 * TODO:Check with MSI Soc for sysdev
300 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
302 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
304 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
305 "failed to allocate MSI entry");
309 ret = request_irq(pdev->irq, xhci_msi_irq,
310 0, "xhci_hcd", xhci_to_hcd(xhci));
312 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
313 "disable MSI interrupt");
314 pci_free_irq_vectors(pdev);
323 static int xhci_setup_msix(struct xhci_hcd *xhci)
326 struct usb_hcd *hcd = xhci_to_hcd(xhci);
327 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
330 * calculate number of msi-x vectors supported.
331 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
332 * with max number of interrupters based on the xhci HCSPARAMS1.
333 * - num_online_cpus: maximum msi-x vectors per CPUs core.
334 * Add additional 1 vector to ensure always available interrupt.
336 xhci->msix_count = min(num_online_cpus() + 1,
337 HCS_MAX_INTRS(xhci->hcs_params1));
339 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
342 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
343 "Failed to enable MSI-X");
347 for (i = 0; i < xhci->msix_count; i++) {
348 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
349 "xhci_hcd", xhci_to_hcd(xhci));
354 hcd->msix_enabled = 1;
358 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
360 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
361 pci_free_irq_vectors(pdev);
365 /* Free any IRQs and disable MSI-X */
366 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
368 struct usb_hcd *hcd = xhci_to_hcd(xhci);
369 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
371 if (xhci->quirks & XHCI_PLAT)
374 /* return if using legacy interrupt */
378 if (hcd->msix_enabled) {
381 for (i = 0; i < xhci->msix_count; i++)
382 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
384 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
387 pci_free_irq_vectors(pdev);
388 hcd->msix_enabled = 0;
391 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
393 struct usb_hcd *hcd = xhci_to_hcd(xhci);
395 if (hcd->msix_enabled) {
396 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
399 for (i = 0; i < xhci->msix_count; i++)
400 synchronize_irq(pci_irq_vector(pdev, i));
404 static int xhci_try_enable_msi(struct usb_hcd *hcd)
406 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
407 struct pci_dev *pdev;
410 /* The xhci platform device has set up IRQs through usb_add_hcd. */
411 if (xhci->quirks & XHCI_PLAT)
414 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
416 * Some Fresco Logic host controllers advertise MSI, but fail to
417 * generate interrupts. Don't even try to enable MSI.
419 if (xhci->quirks & XHCI_BROKEN_MSI)
422 /* unregister the legacy interrupt */
424 free_irq(hcd->irq, hcd);
427 ret = xhci_setup_msix(xhci);
429 /* fall back to msi*/
430 ret = xhci_setup_msi(xhci);
433 hcd->msi_enabled = 1;
438 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
443 if (!strlen(hcd->irq_descr))
444 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
445 hcd->driver->description, hcd->self.busnum);
447 /* fall back to legacy interrupt*/
448 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
449 hcd->irq_descr, hcd);
451 xhci_err(xhci, "request interrupt %d failed\n",
455 hcd->irq = pdev->irq;
461 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
466 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
470 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
476 static void compliance_mode_recovery(struct timer_list *t)
478 struct xhci_hcd *xhci;
480 struct xhci_hub *rhub;
484 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
485 rhub = &xhci->usb3_rhub;
487 for (i = 0; i < rhub->num_ports; i++) {
488 temp = readl(rhub->ports[i]->addr);
489 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
491 * Compliance Mode Detected. Letting USB Core
492 * handle the Warm Reset
494 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
495 "Compliance mode detected->port %d",
497 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
498 "Attempting compliance mode recovery");
499 hcd = xhci->shared_hcd;
501 if (hcd->state == HC_STATE_SUSPENDED)
502 usb_hcd_resume_root_hub(hcd);
504 usb_hcd_poll_rh_status(hcd);
508 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
509 mod_timer(&xhci->comp_mode_recovery_timer,
510 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
514 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
515 * that causes ports behind that hardware to enter compliance mode sometimes.
516 * The quirk creates a timer that polls every 2 seconds the link state of
517 * each host controller's port and recovers it by issuing a Warm reset
518 * if Compliance mode is detected, otherwise the port will become "dead" (no
519 * device connections or disconnections will be detected anymore). Becasue no
520 * status event is generated when entering compliance mode (per xhci spec),
521 * this quirk is needed on systems that have the failing hardware installed.
523 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
525 xhci->port_status_u0 = 0;
526 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
528 xhci->comp_mode_recovery_timer.expires = jiffies +
529 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
531 add_timer(&xhci->comp_mode_recovery_timer);
532 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
533 "Compliance mode recovery timer initialized");
537 * This function identifies the systems that have installed the SN65LVPE502CP
538 * USB3.0 re-driver and that need the Compliance Mode Quirk.
540 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
542 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
544 const char *dmi_product_name, *dmi_sys_vendor;
546 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
547 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
548 if (!dmi_product_name || !dmi_sys_vendor)
551 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
554 if (strstr(dmi_product_name, "Z420") ||
555 strstr(dmi_product_name, "Z620") ||
556 strstr(dmi_product_name, "Z820") ||
557 strstr(dmi_product_name, "Z1 Workstation"))
563 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
565 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
570 * Initialize memory for HCD and xHC (one-time init).
572 * Program the PAGESIZE register, initialize the device context array, create
573 * device contexts (?), set up a command ring segment (or two?), create event
574 * ring (one for now).
576 static int xhci_init(struct usb_hcd *hcd)
578 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
582 spin_lock_init(&xhci->lock);
583 if (xhci->hci_version == 0x95 && link_quirk) {
584 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
585 "QUIRK: Not clearing Link TRB chain bits.");
586 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
588 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
589 "xHCI doesn't need link TRB QUIRK");
591 retval = xhci_mem_init(xhci, GFP_KERNEL);
592 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
594 /* Initializing Compliance Mode Recovery Data If Needed */
595 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
596 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
597 compliance_mode_recovery_timer_init(xhci);
603 /*-------------------------------------------------------------------------*/
606 static int xhci_run_finished(struct xhci_hcd *xhci)
608 if (xhci_start(xhci)) {
612 xhci->shared_hcd->state = HC_STATE_RUNNING;
613 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
615 if (xhci->quirks & XHCI_NEC_HOST)
616 xhci_ring_cmd_db(xhci);
618 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
619 "Finished xhci_run for USB3 roothub");
624 * Start the HC after it was halted.
626 * This function is called by the USB core when the HC driver is added.
627 * Its opposite is xhci_stop().
629 * xhci_init() must be called once before this function can be called.
630 * Reset the HC, enable device slot contexts, program DCBAAP, and
631 * set command ring pointer and event ring pointer.
633 * Setup MSI-X vectors and enable interrupts.
635 int xhci_run(struct usb_hcd *hcd)
640 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
642 /* Start the xHCI host controller running only after the USB 2.0 roothub
646 hcd->uses_new_polling = 1;
647 if (!usb_hcd_is_primary_hcd(hcd))
648 return xhci_run_finished(xhci);
650 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
652 ret = xhci_try_enable_msi(hcd);
656 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
657 temp_64 &= ~ERST_PTR_MASK;
658 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
659 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
661 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
662 "// Set the interrupt modulation register");
663 temp = readl(&xhci->ir_set->irq_control);
664 temp &= ~ER_IRQ_INTERVAL_MASK;
665 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
666 writel(temp, &xhci->ir_set->irq_control);
668 /* Set the HCD state before we enable the irqs */
669 temp = readl(&xhci->op_regs->command);
671 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
672 "// Enable interrupts, cmd = 0x%x.", temp);
673 writel(temp, &xhci->op_regs->command);
675 temp = readl(&xhci->ir_set->irq_pending);
676 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
677 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
678 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
679 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
681 if (xhci->quirks & XHCI_NEC_HOST) {
682 struct xhci_command *command;
684 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
688 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
689 TRB_TYPE(TRB_NEC_GET_FW));
691 xhci_free_command(xhci, command);
693 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
694 "Finished xhci_run for USB2 roothub");
698 xhci_debugfs_init(xhci);
702 EXPORT_SYMBOL_GPL(xhci_run);
707 * This function is called by the USB core when the HC driver is removed.
708 * Its opposite is xhci_run().
710 * Disable device contexts, disable IRQs, and quiesce the HC.
711 * Reset the HC, finish any completed transactions, and cleanup memory.
713 static void xhci_stop(struct usb_hcd *hcd)
716 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
718 mutex_lock(&xhci->mutex);
720 /* Only halt host and free memory after both hcds are removed */
721 if (!usb_hcd_is_primary_hcd(hcd)) {
722 mutex_unlock(&xhci->mutex);
728 spin_lock_irq(&xhci->lock);
729 xhci->xhc_state |= XHCI_STATE_HALTED;
730 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
732 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
733 spin_unlock_irq(&xhci->lock);
735 xhci_cleanup_msix(xhci);
737 /* Deleting Compliance Mode Recovery Timer */
738 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
739 (!(xhci_all_ports_seen_u0(xhci)))) {
740 del_timer_sync(&xhci->comp_mode_recovery_timer);
741 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
742 "%s: compliance mode recovery timer deleted",
746 if (xhci->quirks & XHCI_AMD_PLL_FIX)
749 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
750 "// Disabling event ring interrupts");
751 temp = readl(&xhci->op_regs->status);
752 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
753 temp = readl(&xhci->ir_set->irq_pending);
754 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
756 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
757 xhci_mem_cleanup(xhci);
758 xhci_debugfs_exit(xhci);
759 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
760 "xhci_stop completed - status = %x",
761 readl(&xhci->op_regs->status));
762 mutex_unlock(&xhci->mutex);
766 * Shutdown HC (not bus-specific)
768 * This is called when the machine is rebooting or halting. We assume that the
769 * machine will be powered off, and the HC's internal state will be reset.
770 * Don't bother to free memory.
772 * This will only ever be called with the main usb_hcd (the USB3 roothub).
774 void xhci_shutdown(struct usb_hcd *hcd)
776 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
780 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
781 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
783 /* Don't poll the roothubs after shutdown. */
784 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
785 __func__, hcd->self.busnum);
786 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
787 del_timer_sync(&hcd->rh_timer);
789 if (xhci->shared_hcd) {
790 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
791 del_timer_sync(&xhci->shared_hcd->rh_timer);
794 spin_lock_irqsave(&xhci->lock, flags);
797 /* Power off USB2 ports*/
798 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
799 xhci_set_port_power(xhci, xhci->main_hcd, i, false, &flags);
801 /* Power off USB3 ports*/
802 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
803 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, &flags);
805 /* Workaround for spurious wakeups at shutdown with HSW */
806 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
807 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
808 spin_unlock_irqrestore(&xhci->lock, flags);
810 xhci_cleanup_msix(xhci);
812 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
813 "xhci_shutdown completed - status = %x",
814 readl(&xhci->op_regs->status));
816 EXPORT_SYMBOL_GPL(xhci_shutdown);
819 static void xhci_save_registers(struct xhci_hcd *xhci)
821 xhci->s3.command = readl(&xhci->op_regs->command);
822 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
823 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
824 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
825 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
826 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
827 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
828 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
829 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
832 static void xhci_restore_registers(struct xhci_hcd *xhci)
834 writel(xhci->s3.command, &xhci->op_regs->command);
835 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
836 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
837 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
838 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
839 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
840 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
841 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
842 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
845 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
849 /* step 2: initialize command ring buffer */
850 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
851 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
852 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
853 xhci->cmd_ring->dequeue) &
854 (u64) ~CMD_RING_RSVD_BITS) |
855 xhci->cmd_ring->cycle_state;
856 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
857 "// Setting command ring address to 0x%llx",
858 (long unsigned long) val_64);
859 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
863 * The whole command ring must be cleared to zero when we suspend the host.
865 * The host doesn't save the command ring pointer in the suspend well, so we
866 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
867 * aligned, because of the reserved bits in the command ring dequeue pointer
868 * register. Therefore, we can't just set the dequeue pointer back in the
869 * middle of the ring (TRBs are 16-byte aligned).
871 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
873 struct xhci_ring *ring;
874 struct xhci_segment *seg;
876 ring = xhci->cmd_ring;
880 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
881 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
882 cpu_to_le32(~TRB_CYCLE);
884 } while (seg != ring->deq_seg);
886 /* Reset the software enqueue and dequeue pointers */
887 ring->deq_seg = ring->first_seg;
888 ring->dequeue = ring->first_seg->trbs;
889 ring->enq_seg = ring->deq_seg;
890 ring->enqueue = ring->dequeue;
892 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
894 * Ring is now zeroed, so the HW should look for change of ownership
895 * when the cycle bit is set to 1.
897 ring->cycle_state = 1;
900 * Reset the hardware dequeue pointer.
901 * Yes, this will need to be re-written after resume, but we're paranoid
902 * and want to make sure the hardware doesn't access bogus memory
903 * because, say, the BIOS or an SMI started the host without changing
904 * the command ring pointers.
906 xhci_set_cmd_ring_deq(xhci);
910 * Disable port wake bits if do_wakeup is not set.
912 * Also clear a possible internal port wake state left hanging for ports that
913 * detected termination but never successfully enumerated (trained to 0U).
914 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
915 * at enumeration clears this wake, force one here as well for unconnected ports
918 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
919 struct xhci_hub *rhub,
926 spin_lock_irqsave(&xhci->lock, flags);
928 for (i = 0; i < rhub->num_ports; i++) {
929 portsc = readl(rhub->ports[i]->addr);
930 t1 = xhci_port_state_to_neutral(portsc);
933 /* clear wake bits if do_wake is not set */
935 t2 &= ~PORT_WAKE_BITS;
937 /* Don't touch csc bit if connected or connect change is set */
938 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
942 writel(t2, rhub->ports[i]->addr);
943 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
944 rhub->hcd->self.busnum, i + 1, portsc, t2);
947 spin_unlock_irqrestore(&xhci->lock, flags);
950 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
952 struct xhci_port **ports;
957 status = readl(&xhci->op_regs->status);
958 if (status & STS_EINT)
961 * Checking STS_EINT is not enough as there is a lag between a change
962 * bit being set and the Port Status Change Event that it generated
963 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
966 port_index = xhci->usb2_rhub.num_ports;
967 ports = xhci->usb2_rhub.ports;
968 while (port_index--) {
969 portsc = readl(ports[port_index]->addr);
970 if (portsc & PORT_CHANGE_MASK ||
971 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
974 port_index = xhci->usb3_rhub.num_ports;
975 ports = xhci->usb3_rhub.ports;
976 while (port_index--) {
977 portsc = readl(ports[port_index]->addr);
978 if (portsc & PORT_CHANGE_MASK ||
979 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
986 * Stop HC (not bus-specific)
988 * This is called when the machine transition into S3/S4 mode.
991 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
994 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
995 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1002 if (hcd->state != HC_STATE_SUSPENDED ||
1003 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
1006 /* Clear root port wake on bits if wakeup not allowed. */
1007 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1008 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1010 if (!HCD_HW_ACCESSIBLE(hcd))
1013 xhci_dbc_suspend(xhci);
1015 /* Don't poll the roothubs on bus suspend. */
1016 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1017 __func__, hcd->self.busnum);
1018 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1019 del_timer_sync(&hcd->rh_timer);
1020 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1021 del_timer_sync(&xhci->shared_hcd->rh_timer);
1023 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1024 usleep_range(1000, 1500);
1026 spin_lock_irq(&xhci->lock);
1027 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1028 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1029 /* step 1: stop endpoint */
1030 /* skipped assuming that port suspend has done */
1032 /* step 2: clear Run/Stop bit */
1033 command = readl(&xhci->op_regs->command);
1034 command &= ~CMD_RUN;
1035 writel(command, &xhci->op_regs->command);
1037 /* Some chips from Fresco Logic need an extraordinary delay */
1038 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1040 if (xhci_handshake(&xhci->op_regs->status,
1041 STS_HALT, STS_HALT, delay)) {
1042 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1043 spin_unlock_irq(&xhci->lock);
1046 xhci_clear_command_ring(xhci);
1048 /* step 3: save registers */
1049 xhci_save_registers(xhci);
1051 /* step 4: set CSS flag */
1052 command = readl(&xhci->op_regs->command);
1054 writel(command, &xhci->op_regs->command);
1055 xhci->broken_suspend = 0;
1056 if (xhci_handshake(&xhci->op_regs->status,
1057 STS_SAVE, 0, 20 * 1000)) {
1059 * AMD SNPS xHC 3.0 occasionally does not clear the
1060 * SSS bit of USBSTS and when driver tries to poll
1061 * to see if the xHC clears BIT(8) which never happens
1062 * and driver assumes that controller is not responding
1063 * and times out. To workaround this, its good to check
1064 * if SRE and HCE bits are not set (as per xhci
1065 * Section 5.4.2) and bypass the timeout.
1067 res = readl(&xhci->op_regs->status);
1068 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1069 (((res & STS_SRE) == 0) &&
1070 ((res & STS_HCE) == 0))) {
1071 xhci->broken_suspend = 1;
1073 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1074 spin_unlock_irq(&xhci->lock);
1078 spin_unlock_irq(&xhci->lock);
1081 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1082 * is about to be suspended.
1084 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1085 (!(xhci_all_ports_seen_u0(xhci)))) {
1086 del_timer_sync(&xhci->comp_mode_recovery_timer);
1087 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1088 "%s: compliance mode recovery timer deleted",
1092 /* step 5: remove core well power */
1093 /* synchronize irq when using MSI-X */
1094 xhci_msix_sync_irqs(xhci);
1098 EXPORT_SYMBOL_GPL(xhci_suspend);
1101 * start xHC (not bus-specific)
1103 * This is called when the machine transition from S3/S4 mode.
1106 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1108 u32 command, temp = 0;
1109 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1110 struct usb_hcd *secondary_hcd;
1112 bool comp_timer_running = false;
1113 bool pending_portevent = false;
1114 bool reinit_xhc = false;
1119 /* Wait a bit if either of the roothubs need to settle from the
1120 * transition into bus suspend.
1123 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1124 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1127 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1128 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1130 spin_lock_irq(&xhci->lock);
1132 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1137 * Some controllers might lose power during suspend, so wait
1138 * for controller not ready bit to clear, just as in xHC init.
1140 retval = xhci_handshake(&xhci->op_regs->status,
1141 STS_CNR, 0, 10 * 1000 * 1000);
1143 xhci_warn(xhci, "Controller not ready at resume %d\n",
1145 spin_unlock_irq(&xhci->lock);
1148 /* step 1: restore register */
1149 xhci_restore_registers(xhci);
1150 /* step 2: initialize command ring buffer */
1151 xhci_set_cmd_ring_deq(xhci);
1152 /* step 3: restore state and start state*/
1153 /* step 3: set CRS flag */
1154 command = readl(&xhci->op_regs->command);
1156 writel(command, &xhci->op_regs->command);
1158 * Some controllers take up to 55+ ms to complete the controller
1159 * restore so setting the timeout to 100ms. Xhci specification
1160 * doesn't mention any timeout value.
1162 if (xhci_handshake(&xhci->op_regs->status,
1163 STS_RESTORE, 0, 100 * 1000)) {
1164 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1165 spin_unlock_irq(&xhci->lock);
1170 temp = readl(&xhci->op_regs->status);
1172 /* re-initialize the HC on Restore Error, or Host Controller Error */
1173 if (temp & (STS_SRE | STS_HCE)) {
1175 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1179 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1180 !(xhci_all_ports_seen_u0(xhci))) {
1181 del_timer_sync(&xhci->comp_mode_recovery_timer);
1182 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1183 "Compliance Mode Recovery Timer deleted!");
1186 /* Let the USB core know _both_ roothubs lost power. */
1187 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1188 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1190 xhci_dbg(xhci, "Stop HCD\n");
1192 xhci_zero_64b_regs(xhci);
1193 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1194 spin_unlock_irq(&xhci->lock);
1197 xhci_cleanup_msix(xhci);
1199 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1200 temp = readl(&xhci->op_regs->status);
1201 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1202 temp = readl(&xhci->ir_set->irq_pending);
1203 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1205 xhci_dbg(xhci, "cleaning up memory\n");
1206 xhci_mem_cleanup(xhci);
1207 xhci_debugfs_exit(xhci);
1208 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1209 readl(&xhci->op_regs->status));
1211 /* USB core calls the PCI reinit and start functions twice:
1212 * first with the primary HCD, and then with the secondary HCD.
1213 * If we don't do the same, the host will never be started.
1215 if (!usb_hcd_is_primary_hcd(hcd))
1216 secondary_hcd = hcd;
1218 secondary_hcd = xhci->shared_hcd;
1220 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1221 retval = xhci_init(hcd->primary_hcd);
1224 comp_timer_running = true;
1226 xhci_dbg(xhci, "Start the primary HCD\n");
1227 retval = xhci_run(hcd->primary_hcd);
1229 xhci_dbg(xhci, "Start the secondary HCD\n");
1230 retval = xhci_run(secondary_hcd);
1232 hcd->state = HC_STATE_SUSPENDED;
1233 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1237 /* step 4: set Run/Stop bit */
1238 command = readl(&xhci->op_regs->command);
1240 writel(command, &xhci->op_regs->command);
1241 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1244 /* step 5: walk topology and initialize portsc,
1245 * portpmsc and portli
1247 /* this is done in bus_resume */
1249 /* step 6: restart each of the previously
1250 * Running endpoints by ringing their doorbells
1253 spin_unlock_irq(&xhci->lock);
1255 xhci_dbc_resume(xhci);
1260 * Resume roothubs only if there are pending events.
1261 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1262 * the first wake signalling failed, give it that chance.
1264 pending_portevent = xhci_pending_portevent(xhci);
1265 if (!pending_portevent) {
1267 pending_portevent = xhci_pending_portevent(xhci);
1270 if (pending_portevent) {
1271 usb_hcd_resume_root_hub(xhci->shared_hcd);
1272 usb_hcd_resume_root_hub(hcd);
1276 * If system is subject to the Quirk, Compliance Mode Timer needs to
1277 * be re-initialized Always after a system resume. Ports are subject
1278 * to suffer the Compliance Mode issue again. It doesn't matter if
1279 * ports have entered previously to U0 before system's suspension.
1281 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1282 compliance_mode_recovery_timer_init(xhci);
1284 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1285 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1287 /* Re-enable port polling. */
1288 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1289 __func__, hcd->self.busnum);
1290 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1291 usb_hcd_poll_rh_status(xhci->shared_hcd);
1292 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1293 usb_hcd_poll_rh_status(hcd);
1297 EXPORT_SYMBOL_GPL(xhci_resume);
1298 #endif /* CONFIG_PM */
1300 /*-------------------------------------------------------------------------*/
1302 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1306 unsigned int buf_len;
1307 enum dma_data_direction dir;
1309 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1310 buf_len = urb->transfer_buffer_length;
1312 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1313 dev_to_node(hcd->self.sysdev));
1315 if (usb_urb_dir_out(urb))
1316 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1319 urb->transfer_buffer = temp;
1320 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1321 urb->transfer_buffer,
1322 urb->transfer_buffer_length,
1325 if (dma_mapping_error(hcd->self.sysdev,
1326 urb->transfer_dma)) {
1330 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1336 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1341 unsigned int len = 0;
1342 unsigned int trb_size;
1343 unsigned int max_pkt;
1344 struct scatterlist *sg;
1345 struct scatterlist *tail_sg;
1348 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1353 if (urb->dev->speed >= USB_SPEED_SUPER)
1354 trb_size = TRB_CACHE_SIZE_SS;
1356 trb_size = TRB_CACHE_SIZE_HS;
1358 if (urb->transfer_buffer_length != 0 &&
1359 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1360 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1361 len = len + sg->length;
1362 if (i > trb_size - 2) {
1363 len = len - tail_sg->length;
1364 if (len < max_pkt) {
1369 tail_sg = sg_next(tail_sg);
1376 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1379 unsigned int buf_len;
1380 enum dma_data_direction dir;
1382 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1384 buf_len = urb->transfer_buffer_length;
1386 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1387 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1388 dma_unmap_single(hcd->self.sysdev,
1390 urb->transfer_buffer_length,
1393 if (usb_urb_dir_in(urb)) {
1394 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1395 urb->transfer_buffer,
1398 if (len != buf_len) {
1399 xhci_dbg(hcd_to_xhci(hcd),
1400 "Copy from tmp buf to urb sg list failed\n");
1401 urb->actual_length = len;
1404 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1405 kfree(urb->transfer_buffer);
1406 urb->transfer_buffer = NULL;
1410 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1411 * we'll copy the actual data into the TRB address register. This is limited to
1412 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1413 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1415 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1418 struct xhci_hcd *xhci;
1420 xhci = hcd_to_xhci(hcd);
1422 if (xhci_urb_suitable_for_idt(urb))
1425 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1426 if (xhci_urb_temp_buffer_required(hcd, urb))
1427 return xhci_map_temp_buffer(hcd, urb);
1429 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1432 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1434 struct xhci_hcd *xhci;
1435 bool unmap_temp_buf = false;
1437 xhci = hcd_to_xhci(hcd);
1439 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1440 unmap_temp_buf = true;
1442 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1443 xhci_unmap_temp_buf(hcd, urb);
1445 usb_hcd_unmap_urb_for_dma(hcd, urb);
1449 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1450 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1451 * value to right shift 1 for the bitmask.
1453 * Index = (epnum * 2) + direction - 1,
1454 * where direction = 0 for OUT, 1 for IN.
1455 * For control endpoints, the IN index is used (OUT index is unused), so
1456 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1458 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1461 if (usb_endpoint_xfer_control(desc))
1462 index = (unsigned int) (usb_endpoint_num(desc)*2);
1464 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1465 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1468 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1470 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1471 * address from the XHCI endpoint index.
1473 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1475 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1476 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1477 return direction | number;
1480 /* Find the flag for this endpoint (for use in the control context). Use the
1481 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1484 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1486 return 1 << (xhci_get_endpoint_index(desc) + 1);
1489 /* Compute the last valid endpoint context index. Basically, this is the
1490 * endpoint index plus one. For slot contexts with more than valid endpoint,
1491 * we find the most significant bit set in the added contexts flags.
1492 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1493 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1495 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1497 return fls(added_ctxs) - 1;
1500 /* Returns 1 if the arguments are OK;
1501 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1503 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1504 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1506 struct xhci_hcd *xhci;
1507 struct xhci_virt_device *virt_dev;
1509 if (!hcd || (check_ep && !ep) || !udev) {
1510 pr_debug("xHCI %s called with invalid args\n", func);
1513 if (!udev->parent) {
1514 pr_debug("xHCI %s called for root hub\n", func);
1518 xhci = hcd_to_xhci(hcd);
1519 if (check_virt_dev) {
1520 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1521 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1526 virt_dev = xhci->devs[udev->slot_id];
1527 if (virt_dev->udev != udev) {
1528 xhci_dbg(xhci, "xHCI %s called with udev and "
1529 "virt_dev does not match\n", func);
1534 if (xhci->xhc_state & XHCI_STATE_HALTED)
1540 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1541 struct usb_device *udev, struct xhci_command *command,
1542 bool ctx_change, bool must_succeed);
1545 * Full speed devices may have a max packet size greater than 8 bytes, but the
1546 * USB core doesn't know that until it reads the first 8 bytes of the
1547 * descriptor. If the usb_device's max packet size changes after that point,
1548 * we need to issue an evaluate context command and wait on it.
1550 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1551 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1553 struct xhci_container_ctx *out_ctx;
1554 struct xhci_input_control_ctx *ctrl_ctx;
1555 struct xhci_ep_ctx *ep_ctx;
1556 struct xhci_command *command;
1557 int max_packet_size;
1558 int hw_max_packet_size;
1561 out_ctx = xhci->devs[slot_id]->out_ctx;
1562 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1563 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1564 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1565 if (hw_max_packet_size != max_packet_size) {
1566 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1567 "Max Packet Size for ep 0 changed.");
1568 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1569 "Max packet size in usb_device = %d",
1571 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1572 "Max packet size in xHCI HW = %d",
1573 hw_max_packet_size);
1574 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1575 "Issuing evaluate context command.");
1577 /* Set up the input context flags for the command */
1578 /* FIXME: This won't work if a non-default control endpoint
1579 * changes max packet sizes.
1582 command = xhci_alloc_command(xhci, true, mem_flags);
1586 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1587 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1589 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1592 goto command_cleanup;
1594 /* Set up the modified control endpoint 0 */
1595 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1596 xhci->devs[slot_id]->out_ctx, ep_index);
1598 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1599 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1600 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1601 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1603 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1604 ctrl_ctx->drop_flags = 0;
1606 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1609 /* Clean up the input context for later use by bandwidth
1612 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1614 kfree(command->completion);
1621 * non-error returns are a promise to giveback() the urb later
1622 * we drop ownership so next owner (or urb unlink) can get it
1624 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1626 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1627 unsigned long flags;
1629 unsigned int slot_id, ep_index;
1630 unsigned int *ep_state;
1631 struct urb_priv *urb_priv;
1636 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1637 true, true, __func__);
1639 return ret ? ret : -EINVAL;
1641 slot_id = urb->dev->slot_id;
1642 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1643 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1645 if (!HCD_HW_ACCESSIBLE(hcd))
1648 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1649 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1653 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1654 num_tds = urb->number_of_packets;
1655 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1656 urb->transfer_buffer_length > 0 &&
1657 urb->transfer_flags & URB_ZERO_PACKET &&
1658 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1663 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1667 urb_priv->num_tds = num_tds;
1668 urb_priv->num_tds_done = 0;
1669 urb->hcpriv = urb_priv;
1671 trace_xhci_urb_enqueue(urb);
1673 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1674 /* Check to see if the max packet size for the default control
1675 * endpoint changed during FS device enumeration
1677 if (urb->dev->speed == USB_SPEED_FULL) {
1678 ret = xhci_check_maxpacket(xhci, slot_id,
1679 ep_index, urb, mem_flags);
1681 xhci_urb_free_priv(urb_priv);
1688 spin_lock_irqsave(&xhci->lock, flags);
1690 if (xhci->xhc_state & XHCI_STATE_DYING) {
1691 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1692 urb->ep->desc.bEndpointAddress, urb);
1696 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1697 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1702 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1703 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1708 switch (usb_endpoint_type(&urb->ep->desc)) {
1710 case USB_ENDPOINT_XFER_CONTROL:
1711 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1714 case USB_ENDPOINT_XFER_BULK:
1715 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1718 case USB_ENDPOINT_XFER_INT:
1719 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1722 case USB_ENDPOINT_XFER_ISOC:
1723 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1729 xhci_urb_free_priv(urb_priv);
1732 spin_unlock_irqrestore(&xhci->lock, flags);
1737 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1738 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1739 * should pick up where it left off in the TD, unless a Set Transfer Ring
1740 * Dequeue Pointer is issued.
1742 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1743 * the ring. Since the ring is a contiguous structure, they can't be physically
1744 * removed. Instead, there are two options:
1746 * 1) If the HC is in the middle of processing the URB to be canceled, we
1747 * simply move the ring's dequeue pointer past those TRBs using the Set
1748 * Transfer Ring Dequeue Pointer command. This will be the common case,
1749 * when drivers timeout on the last submitted URB and attempt to cancel.
1751 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1752 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1753 * HC will need to invalidate the any TRBs it has cached after the stop
1754 * endpoint command, as noted in the xHCI 0.95 errata.
1756 * 3) The TD may have completed by the time the Stop Endpoint Command
1757 * completes, so software needs to handle that case too.
1759 * This function should protect against the TD enqueueing code ringing the
1760 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1761 * It also needs to account for multiple cancellations on happening at the same
1762 * time for the same endpoint.
1764 * Note that this function can be called in any context, or so says
1765 * usb_hcd_unlink_urb()
1767 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1769 unsigned long flags;
1772 struct xhci_hcd *xhci;
1773 struct urb_priv *urb_priv;
1775 unsigned int ep_index;
1776 struct xhci_ring *ep_ring;
1777 struct xhci_virt_ep *ep;
1778 struct xhci_command *command;
1779 struct xhci_virt_device *vdev;
1781 xhci = hcd_to_xhci(hcd);
1782 spin_lock_irqsave(&xhci->lock, flags);
1784 trace_xhci_urb_dequeue(urb);
1786 /* Make sure the URB hasn't completed or been unlinked already */
1787 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1791 /* give back URB now if we can't queue it for cancel */
1792 vdev = xhci->devs[urb->dev->slot_id];
1793 urb_priv = urb->hcpriv;
1794 if (!vdev || !urb_priv)
1797 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1798 ep = &vdev->eps[ep_index];
1799 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1800 if (!ep || !ep_ring)
1803 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1804 temp = readl(&xhci->op_regs->status);
1805 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1811 * check ring is not re-allocated since URB was enqueued. If it is, then
1812 * make sure none of the ring related pointers in this URB private data
1813 * are touched, such as td_list, otherwise we overwrite freed data
1815 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1816 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1817 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1818 td = &urb_priv->td[i];
1819 if (!list_empty(&td->cancelled_td_list))
1820 list_del_init(&td->cancelled_td_list);
1825 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1826 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1827 "HC halted, freeing TD manually.");
1828 for (i = urb_priv->num_tds_done;
1829 i < urb_priv->num_tds;
1831 td = &urb_priv->td[i];
1832 if (!list_empty(&td->td_list))
1833 list_del_init(&td->td_list);
1834 if (!list_empty(&td->cancelled_td_list))
1835 list_del_init(&td->cancelled_td_list);
1840 i = urb_priv->num_tds_done;
1841 if (i < urb_priv->num_tds)
1842 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1843 "Cancel URB %p, dev %s, ep 0x%x, "
1844 "starting at offset 0x%llx",
1845 urb, urb->dev->devpath,
1846 urb->ep->desc.bEndpointAddress,
1847 (unsigned long long) xhci_trb_virt_to_dma(
1848 urb_priv->td[i].start_seg,
1849 urb_priv->td[i].first_trb));
1851 for (; i < urb_priv->num_tds; i++) {
1852 td = &urb_priv->td[i];
1853 /* TD can already be on cancelled list if ep halted on it */
1854 if (list_empty(&td->cancelled_td_list)) {
1855 td->cancel_status = TD_DIRTY;
1856 list_add_tail(&td->cancelled_td_list,
1857 &ep->cancelled_td_list);
1861 /* Queue a stop endpoint command, but only if this is
1862 * the first cancellation to be handled.
1864 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1865 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1870 ep->ep_state |= EP_STOP_CMD_PENDING;
1871 ep->stop_cmd_timer.expires = jiffies +
1872 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1873 add_timer(&ep->stop_cmd_timer);
1874 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1876 xhci_ring_cmd_db(xhci);
1879 spin_unlock_irqrestore(&xhci->lock, flags);
1884 xhci_urb_free_priv(urb_priv);
1885 usb_hcd_unlink_urb_from_ep(hcd, urb);
1886 spin_unlock_irqrestore(&xhci->lock, flags);
1887 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1891 /* Drop an endpoint from a new bandwidth configuration for this device.
1892 * Only one call to this function is allowed per endpoint before
1893 * check_bandwidth() or reset_bandwidth() must be called.
1894 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1895 * add the endpoint to the schedule with possibly new parameters denoted by a
1896 * different endpoint descriptor in usb_host_endpoint.
1897 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1900 * The USB core will not allow URBs to be queued to an endpoint that is being
1901 * disabled, so there's no need for mutual exclusion to protect
1902 * the xhci->devs[slot_id] structure.
1904 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1905 struct usb_host_endpoint *ep)
1907 struct xhci_hcd *xhci;
1908 struct xhci_container_ctx *in_ctx, *out_ctx;
1909 struct xhci_input_control_ctx *ctrl_ctx;
1910 unsigned int ep_index;
1911 struct xhci_ep_ctx *ep_ctx;
1913 u32 new_add_flags, new_drop_flags;
1916 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1919 xhci = hcd_to_xhci(hcd);
1920 if (xhci->xhc_state & XHCI_STATE_DYING)
1923 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1924 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1925 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1926 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1927 __func__, drop_flag);
1931 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1932 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1933 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1935 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1940 ep_index = xhci_get_endpoint_index(&ep->desc);
1941 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1942 /* If the HC already knows the endpoint is disabled,
1943 * or the HCD has noted it is disabled, ignore this request
1945 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1946 le32_to_cpu(ctrl_ctx->drop_flags) &
1947 xhci_get_endpoint_flag(&ep->desc)) {
1948 /* Do not warn when called after a usb_device_reset */
1949 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1950 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1955 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1956 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1958 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1959 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1961 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1963 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1965 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1966 (unsigned int) ep->desc.bEndpointAddress,
1968 (unsigned int) new_drop_flags,
1969 (unsigned int) new_add_flags);
1972 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1974 /* Add an endpoint to a new possible bandwidth configuration for this device.
1975 * Only one call to this function is allowed per endpoint before
1976 * check_bandwidth() or reset_bandwidth() must be called.
1977 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1978 * add the endpoint to the schedule with possibly new parameters denoted by a
1979 * different endpoint descriptor in usb_host_endpoint.
1980 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1983 * The USB core will not allow URBs to be queued to an endpoint until the
1984 * configuration or alt setting is installed in the device, so there's no need
1985 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1987 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1988 struct usb_host_endpoint *ep)
1990 struct xhci_hcd *xhci;
1991 struct xhci_container_ctx *in_ctx;
1992 unsigned int ep_index;
1993 struct xhci_input_control_ctx *ctrl_ctx;
1994 struct xhci_ep_ctx *ep_ctx;
1996 u32 new_add_flags, new_drop_flags;
1997 struct xhci_virt_device *virt_dev;
2000 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2002 /* So we won't queue a reset ep command for a root hub */
2006 xhci = hcd_to_xhci(hcd);
2007 if (xhci->xhc_state & XHCI_STATE_DYING)
2010 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2011 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2012 /* FIXME when we have to issue an evaluate endpoint command to
2013 * deal with ep0 max packet size changing once we get the
2016 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2017 __func__, added_ctxs);
2021 virt_dev = xhci->devs[udev->slot_id];
2022 in_ctx = virt_dev->in_ctx;
2023 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2025 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2030 ep_index = xhci_get_endpoint_index(&ep->desc);
2031 /* If this endpoint is already in use, and the upper layers are trying
2032 * to add it again without dropping it, reject the addition.
2034 if (virt_dev->eps[ep_index].ring &&
2035 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2036 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2037 "without dropping it.\n",
2038 (unsigned int) ep->desc.bEndpointAddress);
2042 /* If the HCD has already noted the endpoint is enabled,
2043 * ignore this request.
2045 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2046 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2052 * Configuration and alternate setting changes must be done in
2053 * process context, not interrupt context (or so documenation
2054 * for usb_set_interface() and usb_set_configuration() claim).
2056 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2057 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2058 __func__, ep->desc.bEndpointAddress);
2062 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2063 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2065 /* If xhci_endpoint_disable() was called for this endpoint, but the
2066 * xHC hasn't been notified yet through the check_bandwidth() call,
2067 * this re-adds a new state for the endpoint from the new endpoint
2068 * descriptors. We must drop and re-add this endpoint, so we leave the
2071 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2073 /* Store the usb_device pointer for later use */
2076 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2077 trace_xhci_add_endpoint(ep_ctx);
2079 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2080 (unsigned int) ep->desc.bEndpointAddress,
2082 (unsigned int) new_drop_flags,
2083 (unsigned int) new_add_flags);
2086 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2088 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2090 struct xhci_input_control_ctx *ctrl_ctx;
2091 struct xhci_ep_ctx *ep_ctx;
2092 struct xhci_slot_ctx *slot_ctx;
2095 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2097 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2102 /* When a device's add flag and drop flag are zero, any subsequent
2103 * configure endpoint command will leave that endpoint's state
2104 * untouched. Make sure we don't leave any old state in the input
2105 * endpoint contexts.
2107 ctrl_ctx->drop_flags = 0;
2108 ctrl_ctx->add_flags = 0;
2109 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2110 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2111 /* Endpoint 0 is always valid */
2112 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2113 for (i = 1; i < 31; i++) {
2114 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2115 ep_ctx->ep_info = 0;
2116 ep_ctx->ep_info2 = 0;
2118 ep_ctx->tx_info = 0;
2122 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2123 struct usb_device *udev, u32 *cmd_status)
2127 switch (*cmd_status) {
2128 case COMP_COMMAND_ABORTED:
2129 case COMP_COMMAND_RING_STOPPED:
2130 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2133 case COMP_RESOURCE_ERROR:
2134 dev_warn(&udev->dev,
2135 "Not enough host controller resources for new device state.\n");
2137 /* FIXME: can we allocate more resources for the HC? */
2139 case COMP_BANDWIDTH_ERROR:
2140 case COMP_SECONDARY_BANDWIDTH_ERROR:
2141 dev_warn(&udev->dev,
2142 "Not enough bandwidth for new device state.\n");
2144 /* FIXME: can we go back to the old state? */
2146 case COMP_TRB_ERROR:
2147 /* the HCD set up something wrong */
2148 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2150 "and endpoint is not disabled.\n");
2153 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2154 dev_warn(&udev->dev,
2155 "ERROR: Incompatible device for endpoint configure command.\n");
2159 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2160 "Successful Endpoint Configure command");
2164 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2172 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2173 struct usb_device *udev, u32 *cmd_status)
2177 switch (*cmd_status) {
2178 case COMP_COMMAND_ABORTED:
2179 case COMP_COMMAND_RING_STOPPED:
2180 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2183 case COMP_PARAMETER_ERROR:
2184 dev_warn(&udev->dev,
2185 "WARN: xHCI driver setup invalid evaluate context command.\n");
2188 case COMP_SLOT_NOT_ENABLED_ERROR:
2189 dev_warn(&udev->dev,
2190 "WARN: slot not enabled for evaluate context command.\n");
2193 case COMP_CONTEXT_STATE_ERROR:
2194 dev_warn(&udev->dev,
2195 "WARN: invalid context state for evaluate context command.\n");
2198 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2199 dev_warn(&udev->dev,
2200 "ERROR: Incompatible device for evaluate context command.\n");
2203 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2204 /* Max Exit Latency too large error */
2205 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2209 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2210 "Successful evaluate context command");
2214 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2222 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2223 struct xhci_input_control_ctx *ctrl_ctx)
2225 u32 valid_add_flags;
2226 u32 valid_drop_flags;
2228 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2229 * (bit 1). The default control endpoint is added during the Address
2230 * Device command and is never removed until the slot is disabled.
2232 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2233 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2235 /* Use hweight32 to count the number of ones in the add flags, or
2236 * number of endpoints added. Don't count endpoints that are changed
2237 * (both added and dropped).
2239 return hweight32(valid_add_flags) -
2240 hweight32(valid_add_flags & valid_drop_flags);
2243 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2244 struct xhci_input_control_ctx *ctrl_ctx)
2246 u32 valid_add_flags;
2247 u32 valid_drop_flags;
2249 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2250 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2252 return hweight32(valid_drop_flags) -
2253 hweight32(valid_add_flags & valid_drop_flags);
2257 * We need to reserve the new number of endpoints before the configure endpoint
2258 * command completes. We can't subtract the dropped endpoints from the number
2259 * of active endpoints until the command completes because we can oversubscribe
2260 * the host in this case:
2262 * - the first configure endpoint command drops more endpoints than it adds
2263 * - a second configure endpoint command that adds more endpoints is queued
2264 * - the first configure endpoint command fails, so the config is unchanged
2265 * - the second command may succeed, even though there isn't enough resources
2267 * Must be called with xhci->lock held.
2269 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2270 struct xhci_input_control_ctx *ctrl_ctx)
2274 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2275 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2276 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2277 "Not enough ep ctxs: "
2278 "%u active, need to add %u, limit is %u.",
2279 xhci->num_active_eps, added_eps,
2280 xhci->limit_active_eps);
2283 xhci->num_active_eps += added_eps;
2284 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2285 "Adding %u ep ctxs, %u now active.", added_eps,
2286 xhci->num_active_eps);
2291 * The configure endpoint was failed by the xHC for some other reason, so we
2292 * need to revert the resources that failed configuration would have used.
2294 * Must be called with xhci->lock held.
2296 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2297 struct xhci_input_control_ctx *ctrl_ctx)
2301 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2302 xhci->num_active_eps -= num_failed_eps;
2303 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2304 "Removing %u failed ep ctxs, %u now active.",
2306 xhci->num_active_eps);
2310 * Now that the command has completed, clean up the active endpoint count by
2311 * subtracting out the endpoints that were dropped (but not changed).
2313 * Must be called with xhci->lock held.
2315 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2316 struct xhci_input_control_ctx *ctrl_ctx)
2318 u32 num_dropped_eps;
2320 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2321 xhci->num_active_eps -= num_dropped_eps;
2322 if (num_dropped_eps)
2323 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2324 "Removing %u dropped ep ctxs, %u now active.",
2326 xhci->num_active_eps);
2329 static unsigned int xhci_get_block_size(struct usb_device *udev)
2331 switch (udev->speed) {
2333 case USB_SPEED_FULL:
2335 case USB_SPEED_HIGH:
2337 case USB_SPEED_SUPER:
2338 case USB_SPEED_SUPER_PLUS:
2340 case USB_SPEED_UNKNOWN:
2341 case USB_SPEED_WIRELESS:
2343 /* Should never happen */
2349 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2351 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2353 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2358 /* If we are changing a LS/FS device under a HS hub,
2359 * make sure (if we are activating a new TT) that the HS bus has enough
2360 * bandwidth for this new TT.
2362 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2363 struct xhci_virt_device *virt_dev,
2366 struct xhci_interval_bw_table *bw_table;
2367 struct xhci_tt_bw_info *tt_info;
2369 /* Find the bandwidth table for the root port this TT is attached to. */
2370 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2371 tt_info = virt_dev->tt_info;
2372 /* If this TT already had active endpoints, the bandwidth for this TT
2373 * has already been added. Removing all periodic endpoints (and thus
2374 * making the TT enactive) will only decrease the bandwidth used.
2378 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2379 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2383 /* Not sure why we would have no new active endpoints...
2385 * Maybe because of an Evaluate Context change for a hub update or a
2386 * control endpoint 0 max packet size change?
2387 * FIXME: skip the bandwidth calculation in that case.
2392 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2393 struct xhci_virt_device *virt_dev)
2395 unsigned int bw_reserved;
2397 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2398 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2401 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2402 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2409 * This algorithm is a very conservative estimate of the worst-case scheduling
2410 * scenario for any one interval. The hardware dynamically schedules the
2411 * packets, so we can't tell which microframe could be the limiting factor in
2412 * the bandwidth scheduling. This only takes into account periodic endpoints.
2414 * Obviously, we can't solve an NP complete problem to find the minimum worst
2415 * case scenario. Instead, we come up with an estimate that is no less than
2416 * the worst case bandwidth used for any one microframe, but may be an
2419 * We walk the requirements for each endpoint by interval, starting with the
2420 * smallest interval, and place packets in the schedule where there is only one
2421 * possible way to schedule packets for that interval. In order to simplify
2422 * this algorithm, we record the largest max packet size for each interval, and
2423 * assume all packets will be that size.
2425 * For interval 0, we obviously must schedule all packets for each interval.
2426 * The bandwidth for interval 0 is just the amount of data to be transmitted
2427 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2428 * the number of packets).
2430 * For interval 1, we have two possible microframes to schedule those packets
2431 * in. For this algorithm, if we can schedule the same number of packets for
2432 * each possible scheduling opportunity (each microframe), we will do so. The
2433 * remaining number of packets will be saved to be transmitted in the gaps in
2434 * the next interval's scheduling sequence.
2436 * As we move those remaining packets to be scheduled with interval 2 packets,
2437 * we have to double the number of remaining packets to transmit. This is
2438 * because the intervals are actually powers of 2, and we would be transmitting
2439 * the previous interval's packets twice in this interval. We also have to be
2440 * sure that when we look at the largest max packet size for this interval, we
2441 * also look at the largest max packet size for the remaining packets and take
2442 * the greater of the two.
2444 * The algorithm continues to evenly distribute packets in each scheduling
2445 * opportunity, and push the remaining packets out, until we get to the last
2446 * interval. Then those packets and their associated overhead are just added
2447 * to the bandwidth used.
2449 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2450 struct xhci_virt_device *virt_dev,
2453 unsigned int bw_reserved;
2454 unsigned int max_bandwidth;
2455 unsigned int bw_used;
2456 unsigned int block_size;
2457 struct xhci_interval_bw_table *bw_table;
2458 unsigned int packet_size = 0;
2459 unsigned int overhead = 0;
2460 unsigned int packets_transmitted = 0;
2461 unsigned int packets_remaining = 0;
2464 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2465 return xhci_check_ss_bw(xhci, virt_dev);
2467 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2468 max_bandwidth = HS_BW_LIMIT;
2469 /* Convert percent of bus BW reserved to blocks reserved */
2470 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2472 max_bandwidth = FS_BW_LIMIT;
2473 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2476 bw_table = virt_dev->bw_table;
2477 /* We need to translate the max packet size and max ESIT payloads into
2478 * the units the hardware uses.
2480 block_size = xhci_get_block_size(virt_dev->udev);
2482 /* If we are manipulating a LS/FS device under a HS hub, double check
2483 * that the HS bus has enough bandwidth if we are activing a new TT.
2485 if (virt_dev->tt_info) {
2486 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2487 "Recalculating BW for rootport %u",
2488 virt_dev->real_port);
2489 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2490 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2491 "newly activated TT.\n");
2494 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2495 "Recalculating BW for TT slot %u port %u",
2496 virt_dev->tt_info->slot_id,
2497 virt_dev->tt_info->ttport);
2499 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2500 "Recalculating BW for rootport %u",
2501 virt_dev->real_port);
2504 /* Add in how much bandwidth will be used for interval zero, or the
2505 * rounded max ESIT payload + number of packets * largest overhead.
2507 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2508 bw_table->interval_bw[0].num_packets *
2509 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2511 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2512 unsigned int bw_added;
2513 unsigned int largest_mps;
2514 unsigned int interval_overhead;
2517 * How many packets could we transmit in this interval?
2518 * If packets didn't fit in the previous interval, we will need
2519 * to transmit that many packets twice within this interval.
2521 packets_remaining = 2 * packets_remaining +
2522 bw_table->interval_bw[i].num_packets;
2524 /* Find the largest max packet size of this or the previous
2527 if (list_empty(&bw_table->interval_bw[i].endpoints))
2530 struct xhci_virt_ep *virt_ep;
2531 struct list_head *ep_entry;
2533 ep_entry = bw_table->interval_bw[i].endpoints.next;
2534 virt_ep = list_entry(ep_entry,
2535 struct xhci_virt_ep, bw_endpoint_list);
2536 /* Convert to blocks, rounding up */
2537 largest_mps = DIV_ROUND_UP(
2538 virt_ep->bw_info.max_packet_size,
2541 if (largest_mps > packet_size)
2542 packet_size = largest_mps;
2544 /* Use the larger overhead of this or the previous interval. */
2545 interval_overhead = xhci_get_largest_overhead(
2546 &bw_table->interval_bw[i]);
2547 if (interval_overhead > overhead)
2548 overhead = interval_overhead;
2550 /* How many packets can we evenly distribute across
2551 * (1 << (i + 1)) possible scheduling opportunities?
2553 packets_transmitted = packets_remaining >> (i + 1);
2555 /* Add in the bandwidth used for those scheduled packets */
2556 bw_added = packets_transmitted * (overhead + packet_size);
2558 /* How many packets do we have remaining to transmit? */
2559 packets_remaining = packets_remaining % (1 << (i + 1));
2561 /* What largest max packet size should those packets have? */
2562 /* If we've transmitted all packets, don't carry over the
2563 * largest packet size.
2565 if (packets_remaining == 0) {
2568 } else if (packets_transmitted > 0) {
2569 /* Otherwise if we do have remaining packets, and we've
2570 * scheduled some packets in this interval, take the
2571 * largest max packet size from endpoints with this
2574 packet_size = largest_mps;
2575 overhead = interval_overhead;
2577 /* Otherwise carry over packet_size and overhead from the last
2578 * time we had a remainder.
2580 bw_used += bw_added;
2581 if (bw_used > max_bandwidth) {
2582 xhci_warn(xhci, "Not enough bandwidth. "
2583 "Proposed: %u, Max: %u\n",
2584 bw_used, max_bandwidth);
2589 * Ok, we know we have some packets left over after even-handedly
2590 * scheduling interval 15. We don't know which microframes they will
2591 * fit into, so we over-schedule and say they will be scheduled every
2594 if (packets_remaining > 0)
2595 bw_used += overhead + packet_size;
2597 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2598 unsigned int port_index = virt_dev->real_port - 1;
2600 /* OK, we're manipulating a HS device attached to a
2601 * root port bandwidth domain. Include the number of active TTs
2602 * in the bandwidth used.
2604 bw_used += TT_HS_OVERHEAD *
2605 xhci->rh_bw[port_index].num_active_tts;
2608 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2609 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2610 "Available: %u " "percent",
2611 bw_used, max_bandwidth, bw_reserved,
2612 (max_bandwidth - bw_used - bw_reserved) * 100 /
2615 bw_used += bw_reserved;
2616 if (bw_used > max_bandwidth) {
2617 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2618 bw_used, max_bandwidth);
2622 bw_table->bw_used = bw_used;
2626 static bool xhci_is_async_ep(unsigned int ep_type)
2628 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2629 ep_type != ISOC_IN_EP &&
2630 ep_type != INT_IN_EP);
2633 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2635 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2638 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2640 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2642 if (ep_bw->ep_interval == 0)
2643 return SS_OVERHEAD_BURST +
2644 (ep_bw->mult * ep_bw->num_packets *
2645 (SS_OVERHEAD + mps));
2646 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2647 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2648 1 << ep_bw->ep_interval);
2652 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2653 struct xhci_bw_info *ep_bw,
2654 struct xhci_interval_bw_table *bw_table,
2655 struct usb_device *udev,
2656 struct xhci_virt_ep *virt_ep,
2657 struct xhci_tt_bw_info *tt_info)
2659 struct xhci_interval_bw *interval_bw;
2660 int normalized_interval;
2662 if (xhci_is_async_ep(ep_bw->type))
2665 if (udev->speed >= USB_SPEED_SUPER) {
2666 if (xhci_is_sync_in_ep(ep_bw->type))
2667 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2668 xhci_get_ss_bw_consumed(ep_bw);
2670 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2671 xhci_get_ss_bw_consumed(ep_bw);
2675 /* SuperSpeed endpoints never get added to intervals in the table, so
2676 * this check is only valid for HS/FS/LS devices.
2678 if (list_empty(&virt_ep->bw_endpoint_list))
2680 /* For LS/FS devices, we need to translate the interval expressed in
2681 * microframes to frames.
2683 if (udev->speed == USB_SPEED_HIGH)
2684 normalized_interval = ep_bw->ep_interval;
2686 normalized_interval = ep_bw->ep_interval - 3;
2688 if (normalized_interval == 0)
2689 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2690 interval_bw = &bw_table->interval_bw[normalized_interval];
2691 interval_bw->num_packets -= ep_bw->num_packets;
2692 switch (udev->speed) {
2694 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2696 case USB_SPEED_FULL:
2697 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2699 case USB_SPEED_HIGH:
2700 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2702 case USB_SPEED_SUPER:
2703 case USB_SPEED_SUPER_PLUS:
2704 case USB_SPEED_UNKNOWN:
2705 case USB_SPEED_WIRELESS:
2706 /* Should never happen because only LS/FS/HS endpoints will get
2707 * added to the endpoint list.
2712 tt_info->active_eps -= 1;
2713 list_del_init(&virt_ep->bw_endpoint_list);
2716 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2717 struct xhci_bw_info *ep_bw,
2718 struct xhci_interval_bw_table *bw_table,
2719 struct usb_device *udev,
2720 struct xhci_virt_ep *virt_ep,
2721 struct xhci_tt_bw_info *tt_info)
2723 struct xhci_interval_bw *interval_bw;
2724 struct xhci_virt_ep *smaller_ep;
2725 int normalized_interval;
2727 if (xhci_is_async_ep(ep_bw->type))
2730 if (udev->speed == USB_SPEED_SUPER) {
2731 if (xhci_is_sync_in_ep(ep_bw->type))
2732 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2733 xhci_get_ss_bw_consumed(ep_bw);
2735 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2736 xhci_get_ss_bw_consumed(ep_bw);
2740 /* For LS/FS devices, we need to translate the interval expressed in
2741 * microframes to frames.
2743 if (udev->speed == USB_SPEED_HIGH)
2744 normalized_interval = ep_bw->ep_interval;
2746 normalized_interval = ep_bw->ep_interval - 3;
2748 if (normalized_interval == 0)
2749 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2750 interval_bw = &bw_table->interval_bw[normalized_interval];
2751 interval_bw->num_packets += ep_bw->num_packets;
2752 switch (udev->speed) {
2754 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2756 case USB_SPEED_FULL:
2757 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2759 case USB_SPEED_HIGH:
2760 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2762 case USB_SPEED_SUPER:
2763 case USB_SPEED_SUPER_PLUS:
2764 case USB_SPEED_UNKNOWN:
2765 case USB_SPEED_WIRELESS:
2766 /* Should never happen because only LS/FS/HS endpoints will get
2767 * added to the endpoint list.
2773 tt_info->active_eps += 1;
2774 /* Insert the endpoint into the list, largest max packet size first. */
2775 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2777 if (ep_bw->max_packet_size >=
2778 smaller_ep->bw_info.max_packet_size) {
2779 /* Add the new ep before the smaller endpoint */
2780 list_add_tail(&virt_ep->bw_endpoint_list,
2781 &smaller_ep->bw_endpoint_list);
2785 /* Add the new endpoint at the end of the list. */
2786 list_add_tail(&virt_ep->bw_endpoint_list,
2787 &interval_bw->endpoints);
2790 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2791 struct xhci_virt_device *virt_dev,
2794 struct xhci_root_port_bw_info *rh_bw_info;
2795 if (!virt_dev->tt_info)
2798 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2799 if (old_active_eps == 0 &&
2800 virt_dev->tt_info->active_eps != 0) {
2801 rh_bw_info->num_active_tts += 1;
2802 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2803 } else if (old_active_eps != 0 &&
2804 virt_dev->tt_info->active_eps == 0) {
2805 rh_bw_info->num_active_tts -= 1;
2806 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2810 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2811 struct xhci_virt_device *virt_dev,
2812 struct xhci_container_ctx *in_ctx)
2814 struct xhci_bw_info ep_bw_info[31];
2816 struct xhci_input_control_ctx *ctrl_ctx;
2817 int old_active_eps = 0;
2819 if (virt_dev->tt_info)
2820 old_active_eps = virt_dev->tt_info->active_eps;
2822 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2824 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2829 for (i = 0; i < 31; i++) {
2830 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2833 /* Make a copy of the BW info in case we need to revert this */
2834 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2835 sizeof(ep_bw_info[i]));
2836 /* Drop the endpoint from the interval table if the endpoint is
2837 * being dropped or changed.
2839 if (EP_IS_DROPPED(ctrl_ctx, i))
2840 xhci_drop_ep_from_interval_table(xhci,
2841 &virt_dev->eps[i].bw_info,
2847 /* Overwrite the information stored in the endpoints' bw_info */
2848 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2849 for (i = 0; i < 31; i++) {
2850 /* Add any changed or added endpoints to the interval table */
2851 if (EP_IS_ADDED(ctrl_ctx, i))
2852 xhci_add_ep_to_interval_table(xhci,
2853 &virt_dev->eps[i].bw_info,
2860 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2861 /* Ok, this fits in the bandwidth we have.
2862 * Update the number of active TTs.
2864 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2868 /* We don't have enough bandwidth for this, revert the stored info. */
2869 for (i = 0; i < 31; i++) {
2870 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2873 /* Drop the new copies of any added or changed endpoints from
2874 * the interval table.
2876 if (EP_IS_ADDED(ctrl_ctx, i)) {
2877 xhci_drop_ep_from_interval_table(xhci,
2878 &virt_dev->eps[i].bw_info,
2884 /* Revert the endpoint back to its old information */
2885 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2886 sizeof(ep_bw_info[i]));
2887 /* Add any changed or dropped endpoints back into the table */
2888 if (EP_IS_DROPPED(ctrl_ctx, i))
2889 xhci_add_ep_to_interval_table(xhci,
2890 &virt_dev->eps[i].bw_info,
2900 /* Issue a configure endpoint command or evaluate context command
2901 * and wait for it to finish.
2903 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2904 struct usb_device *udev,
2905 struct xhci_command *command,
2906 bool ctx_change, bool must_succeed)
2909 unsigned long flags;
2910 struct xhci_input_control_ctx *ctrl_ctx;
2911 struct xhci_virt_device *virt_dev;
2912 struct xhci_slot_ctx *slot_ctx;
2917 spin_lock_irqsave(&xhci->lock, flags);
2919 if (xhci->xhc_state & XHCI_STATE_DYING) {
2920 spin_unlock_irqrestore(&xhci->lock, flags);
2924 virt_dev = xhci->devs[udev->slot_id];
2926 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2928 spin_unlock_irqrestore(&xhci->lock, flags);
2929 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2934 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2935 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2936 spin_unlock_irqrestore(&xhci->lock, flags);
2937 xhci_warn(xhci, "Not enough host resources, "
2938 "active endpoint contexts = %u\n",
2939 xhci->num_active_eps);
2942 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2943 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2944 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2945 xhci_free_host_resources(xhci, ctrl_ctx);
2946 spin_unlock_irqrestore(&xhci->lock, flags);
2947 xhci_warn(xhci, "Not enough bandwidth\n");
2951 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2953 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2954 trace_xhci_configure_endpoint(slot_ctx);
2957 ret = xhci_queue_configure_endpoint(xhci, command,
2958 command->in_ctx->dma,
2959 udev->slot_id, must_succeed);
2961 ret = xhci_queue_evaluate_context(xhci, command,
2962 command->in_ctx->dma,
2963 udev->slot_id, must_succeed);
2965 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2966 xhci_free_host_resources(xhci, ctrl_ctx);
2967 spin_unlock_irqrestore(&xhci->lock, flags);
2968 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2969 "FIXME allocate a new ring segment");
2972 xhci_ring_cmd_db(xhci);
2973 spin_unlock_irqrestore(&xhci->lock, flags);
2975 /* Wait for the configure endpoint command to complete */
2976 wait_for_completion(command->completion);
2979 ret = xhci_configure_endpoint_result(xhci, udev,
2982 ret = xhci_evaluate_context_result(xhci, udev,
2985 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2986 spin_lock_irqsave(&xhci->lock, flags);
2987 /* If the command failed, remove the reserved resources.
2988 * Otherwise, clean up the estimate to include dropped eps.
2991 xhci_free_host_resources(xhci, ctrl_ctx);
2993 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2994 spin_unlock_irqrestore(&xhci->lock, flags);
2999 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3000 struct xhci_virt_device *vdev, int i)
3002 struct xhci_virt_ep *ep = &vdev->eps[i];
3004 if (ep->ep_state & EP_HAS_STREAMS) {
3005 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3006 xhci_get_endpoint_address(i));
3007 xhci_free_stream_info(xhci, ep->stream_info);
3008 ep->stream_info = NULL;
3009 ep->ep_state &= ~EP_HAS_STREAMS;
3013 /* Called after one or more calls to xhci_add_endpoint() or
3014 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3015 * to call xhci_reset_bandwidth().
3017 * Since we are in the middle of changing either configuration or
3018 * installing a new alt setting, the USB core won't allow URBs to be
3019 * enqueued for any endpoint on the old config or interface. Nothing
3020 * else should be touching the xhci->devs[slot_id] structure, so we
3021 * don't need to take the xhci->lock for manipulating that.
3023 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3027 struct xhci_hcd *xhci;
3028 struct xhci_virt_device *virt_dev;
3029 struct xhci_input_control_ctx *ctrl_ctx;
3030 struct xhci_slot_ctx *slot_ctx;
3031 struct xhci_command *command;
3033 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3036 xhci = hcd_to_xhci(hcd);
3037 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3038 (xhci->xhc_state & XHCI_STATE_REMOVING))
3041 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3042 virt_dev = xhci->devs[udev->slot_id];
3044 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3048 command->in_ctx = virt_dev->in_ctx;
3050 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3051 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3053 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3056 goto command_cleanup;
3058 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3059 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3060 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3062 /* Don't issue the command if there's no endpoints to update. */
3063 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3064 ctrl_ctx->drop_flags == 0) {
3066 goto command_cleanup;
3068 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3069 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3070 for (i = 31; i >= 1; i--) {
3071 __le32 le32 = cpu_to_le32(BIT(i));
3073 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3074 || (ctrl_ctx->add_flags & le32) || i == 1) {
3075 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3076 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3081 ret = xhci_configure_endpoint(xhci, udev, command,
3084 /* Callee should call reset_bandwidth() */
3085 goto command_cleanup;
3087 /* Free any rings that were dropped, but not changed. */
3088 for (i = 1; i < 31; i++) {
3089 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3090 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3091 xhci_free_endpoint_ring(xhci, virt_dev, i);
3092 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3095 xhci_zero_in_ctx(xhci, virt_dev);
3097 * Install any rings for completely new endpoints or changed endpoints,
3098 * and free any old rings from changed endpoints.
3100 for (i = 1; i < 31; i++) {
3101 if (!virt_dev->eps[i].new_ring)
3103 /* Only free the old ring if it exists.
3104 * It may not if this is the first add of an endpoint.
3106 if (virt_dev->eps[i].ring) {
3107 xhci_free_endpoint_ring(xhci, virt_dev, i);
3109 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3110 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3111 virt_dev->eps[i].new_ring = NULL;
3112 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3115 kfree(command->completion);
3120 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3122 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3124 struct xhci_hcd *xhci;
3125 struct xhci_virt_device *virt_dev;
3128 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3131 xhci = hcd_to_xhci(hcd);
3133 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3134 virt_dev = xhci->devs[udev->slot_id];
3135 /* Free any rings allocated for added endpoints */
3136 for (i = 0; i < 31; i++) {
3137 if (virt_dev->eps[i].new_ring) {
3138 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3139 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3140 virt_dev->eps[i].new_ring = NULL;
3143 xhci_zero_in_ctx(xhci, virt_dev);
3145 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3147 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3148 struct xhci_container_ctx *in_ctx,
3149 struct xhci_container_ctx *out_ctx,
3150 struct xhci_input_control_ctx *ctrl_ctx,
3151 u32 add_flags, u32 drop_flags)
3153 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3154 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3155 xhci_slot_copy(xhci, in_ctx, out_ctx);
3156 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3159 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3160 struct usb_host_endpoint *host_ep)
3162 struct xhci_hcd *xhci;
3163 struct xhci_virt_device *vdev;
3164 struct xhci_virt_ep *ep;
3165 struct usb_device *udev;
3166 unsigned long flags;
3167 unsigned int ep_index;
3169 xhci = hcd_to_xhci(hcd);
3171 spin_lock_irqsave(&xhci->lock, flags);
3173 udev = (struct usb_device *)host_ep->hcpriv;
3174 if (!udev || !udev->slot_id)
3177 vdev = xhci->devs[udev->slot_id];
3181 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3182 ep = &vdev->eps[ep_index];
3186 /* wait for hub_tt_work to finish clearing hub TT */
3187 if (ep->ep_state & EP_CLEARING_TT) {
3188 spin_unlock_irqrestore(&xhci->lock, flags);
3189 schedule_timeout_uninterruptible(1);
3194 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3197 host_ep->hcpriv = NULL;
3198 spin_unlock_irqrestore(&xhci->lock, flags);
3202 * Called after usb core issues a clear halt control message.
3203 * The host side of the halt should already be cleared by a reset endpoint
3204 * command issued when the STALL event was received.
3206 * The reset endpoint command may only be issued to endpoints in the halted
3207 * state. For software that wishes to reset the data toggle or sequence number
3208 * of an endpoint that isn't in the halted state this function will issue a
3209 * configure endpoint command with the Drop and Add bits set for the target
3210 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3213 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3214 struct usb_host_endpoint *host_ep)
3216 struct xhci_hcd *xhci;
3217 struct usb_device *udev;
3218 struct xhci_virt_device *vdev;
3219 struct xhci_virt_ep *ep;
3220 struct xhci_input_control_ctx *ctrl_ctx;
3221 struct xhci_command *stop_cmd, *cfg_cmd;
3222 unsigned int ep_index;
3223 unsigned long flags;
3227 xhci = hcd_to_xhci(hcd);
3228 if (!host_ep->hcpriv)
3230 udev = (struct usb_device *) host_ep->hcpriv;
3231 vdev = xhci->devs[udev->slot_id];
3234 * vdev may be lost due to xHC restore error and re-initialization
3235 * during S3/S4 resume. A new vdev will be allocated later by
3236 * xhci_discover_or_reset_device()
3238 if (!udev->slot_id || !vdev)
3240 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3241 ep = &vdev->eps[ep_index];
3245 /* Bail out if toggle is already being cleared by a endpoint reset */
3246 spin_lock_irqsave(&xhci->lock, flags);
3247 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3248 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3249 spin_unlock_irqrestore(&xhci->lock, flags);
3252 spin_unlock_irqrestore(&xhci->lock, flags);
3253 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3254 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3255 usb_endpoint_xfer_isoc(&host_ep->desc))
3258 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3260 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3263 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3267 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3271 spin_lock_irqsave(&xhci->lock, flags);
3273 /* block queuing new trbs and ringing ep doorbell */
3274 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3277 * Make sure endpoint ring is empty before resetting the toggle/seq.
3278 * Driver is required to synchronously cancel all transfer request.
3279 * Stop the endpoint to force xHC to update the output context
3282 if (!list_empty(&ep->ring->td_list)) {
3283 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3284 spin_unlock_irqrestore(&xhci->lock, flags);
3285 xhci_free_command(xhci, cfg_cmd);
3289 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3292 spin_unlock_irqrestore(&xhci->lock, flags);
3293 xhci_free_command(xhci, cfg_cmd);
3294 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3299 xhci_ring_cmd_db(xhci);
3300 spin_unlock_irqrestore(&xhci->lock, flags);
3302 wait_for_completion(stop_cmd->completion);
3304 spin_lock_irqsave(&xhci->lock, flags);
3306 /* config ep command clears toggle if add and drop ep flags are set */
3307 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3309 spin_unlock_irqrestore(&xhci->lock, flags);
3310 xhci_free_command(xhci, cfg_cmd);
3311 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3316 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3317 ctrl_ctx, ep_flag, ep_flag);
3318 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3320 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3321 udev->slot_id, false);
3323 spin_unlock_irqrestore(&xhci->lock, flags);
3324 xhci_free_command(xhci, cfg_cmd);
3325 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3330 xhci_ring_cmd_db(xhci);
3331 spin_unlock_irqrestore(&xhci->lock, flags);
3333 wait_for_completion(cfg_cmd->completion);
3335 xhci_free_command(xhci, cfg_cmd);
3337 xhci_free_command(xhci, stop_cmd);
3338 spin_lock_irqsave(&xhci->lock, flags);
3339 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3340 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3341 spin_unlock_irqrestore(&xhci->lock, flags);
3344 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3345 struct usb_device *udev, struct usb_host_endpoint *ep,
3346 unsigned int slot_id)
3349 unsigned int ep_index;
3350 unsigned int ep_state;
3354 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3356 return ret ? ret : -EINVAL;
3357 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3358 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3359 " descriptor for ep 0x%x does not support streams\n",
3360 ep->desc.bEndpointAddress);
3364 ep_index = xhci_get_endpoint_index(&ep->desc);
3365 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3366 if (ep_state & EP_HAS_STREAMS ||
3367 ep_state & EP_GETTING_STREAMS) {
3368 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3369 "already has streams set up.\n",
3370 ep->desc.bEndpointAddress);
3371 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3372 "dynamic stream context array reallocation.\n");
3375 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3376 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3377 "endpoint 0x%x; URBs are pending.\n",
3378 ep->desc.bEndpointAddress);
3384 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3385 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3387 unsigned int max_streams;
3389 /* The stream context array size must be a power of two */
3390 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3392 * Find out how many primary stream array entries the host controller
3393 * supports. Later we may use secondary stream arrays (similar to 2nd
3394 * level page entries), but that's an optional feature for xHCI host
3395 * controllers. xHCs must support at least 4 stream IDs.
3397 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3398 if (*num_stream_ctxs > max_streams) {
3399 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3401 *num_stream_ctxs = max_streams;
3402 *num_streams = max_streams;
3406 /* Returns an error code if one of the endpoint already has streams.
3407 * This does not change any data structures, it only checks and gathers
3410 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3411 struct usb_device *udev,
3412 struct usb_host_endpoint **eps, unsigned int num_eps,
3413 unsigned int *num_streams, u32 *changed_ep_bitmask)
3415 unsigned int max_streams;
3416 unsigned int endpoint_flag;
3420 for (i = 0; i < num_eps; i++) {
3421 ret = xhci_check_streams_endpoint(xhci, udev,
3422 eps[i], udev->slot_id);
3426 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3427 if (max_streams < (*num_streams - 1)) {
3428 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3429 eps[i]->desc.bEndpointAddress,
3431 *num_streams = max_streams+1;
3434 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3435 if (*changed_ep_bitmask & endpoint_flag)
3437 *changed_ep_bitmask |= endpoint_flag;
3442 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3443 struct usb_device *udev,
3444 struct usb_host_endpoint **eps, unsigned int num_eps)
3446 u32 changed_ep_bitmask = 0;
3447 unsigned int slot_id;
3448 unsigned int ep_index;
3449 unsigned int ep_state;
3452 slot_id = udev->slot_id;
3453 if (!xhci->devs[slot_id])
3456 for (i = 0; i < num_eps; i++) {
3457 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3458 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3459 /* Are streams already being freed for the endpoint? */
3460 if (ep_state & EP_GETTING_NO_STREAMS) {
3461 xhci_warn(xhci, "WARN Can't disable streams for "
3463 "streams are being disabled already\n",
3464 eps[i]->desc.bEndpointAddress);
3467 /* Are there actually any streams to free? */
3468 if (!(ep_state & EP_HAS_STREAMS) &&
3469 !(ep_state & EP_GETTING_STREAMS)) {
3470 xhci_warn(xhci, "WARN Can't disable streams for "
3472 "streams are already disabled!\n",
3473 eps[i]->desc.bEndpointAddress);
3474 xhci_warn(xhci, "WARN xhci_free_streams() called "
3475 "with non-streams endpoint\n");
3478 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3480 return changed_ep_bitmask;
3484 * The USB device drivers use this function (through the HCD interface in USB
3485 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3486 * coordinate mass storage command queueing across multiple endpoints (basically
3487 * a stream ID == a task ID).
3489 * Setting up streams involves allocating the same size stream context array
3490 * for each endpoint and issuing a configure endpoint command for all endpoints.
3492 * Don't allow the call to succeed if one endpoint only supports one stream
3493 * (which means it doesn't support streams at all).
3495 * Drivers may get less stream IDs than they asked for, if the host controller
3496 * hardware or endpoints claim they can't support the number of requested
3499 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3500 struct usb_host_endpoint **eps, unsigned int num_eps,
3501 unsigned int num_streams, gfp_t mem_flags)
3504 struct xhci_hcd *xhci;
3505 struct xhci_virt_device *vdev;
3506 struct xhci_command *config_cmd;
3507 struct xhci_input_control_ctx *ctrl_ctx;
3508 unsigned int ep_index;
3509 unsigned int num_stream_ctxs;
3510 unsigned int max_packet;
3511 unsigned long flags;
3512 u32 changed_ep_bitmask = 0;
3517 /* Add one to the number of streams requested to account for
3518 * stream 0 that is reserved for xHCI usage.
3521 xhci = hcd_to_xhci(hcd);
3522 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3525 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3526 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3527 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3528 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3532 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3536 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3538 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3540 xhci_free_command(xhci, config_cmd);
3544 /* Check to make sure all endpoints are not already configured for
3545 * streams. While we're at it, find the maximum number of streams that
3546 * all the endpoints will support and check for duplicate endpoints.
3548 spin_lock_irqsave(&xhci->lock, flags);
3549 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3550 num_eps, &num_streams, &changed_ep_bitmask);
3552 xhci_free_command(xhci, config_cmd);
3553 spin_unlock_irqrestore(&xhci->lock, flags);
3556 if (num_streams <= 1) {
3557 xhci_warn(xhci, "WARN: endpoints can't handle "
3558 "more than one stream.\n");
3559 xhci_free_command(xhci, config_cmd);
3560 spin_unlock_irqrestore(&xhci->lock, flags);
3563 vdev = xhci->devs[udev->slot_id];
3564 /* Mark each endpoint as being in transition, so
3565 * xhci_urb_enqueue() will reject all URBs.
3567 for (i = 0; i < num_eps; i++) {
3568 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3569 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3571 spin_unlock_irqrestore(&xhci->lock, flags);
3573 /* Setup internal data structures and allocate HW data structures for
3574 * streams (but don't install the HW structures in the input context
3575 * until we're sure all memory allocation succeeded).
3577 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3578 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3579 num_stream_ctxs, num_streams);
3581 for (i = 0; i < num_eps; i++) {
3582 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3583 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3584 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3587 max_packet, mem_flags);
3588 if (!vdev->eps[ep_index].stream_info)
3590 /* Set maxPstreams in endpoint context and update deq ptr to
3591 * point to stream context array. FIXME
3595 /* Set up the input context for a configure endpoint command. */
3596 for (i = 0; i < num_eps; i++) {
3597 struct xhci_ep_ctx *ep_ctx;
3599 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3600 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3602 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3603 vdev->out_ctx, ep_index);
3604 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3605 vdev->eps[ep_index].stream_info);
3607 /* Tell the HW to drop its old copy of the endpoint context info
3608 * and add the updated copy from the input context.
3610 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3611 vdev->out_ctx, ctrl_ctx,
3612 changed_ep_bitmask, changed_ep_bitmask);
3614 /* Issue and wait for the configure endpoint command */
3615 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3618 /* xHC rejected the configure endpoint command for some reason, so we
3619 * leave the old ring intact and free our internal streams data
3625 spin_lock_irqsave(&xhci->lock, flags);
3626 for (i = 0; i < num_eps; i++) {
3627 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3628 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3629 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3630 udev->slot_id, ep_index);
3631 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3633 xhci_free_command(xhci, config_cmd);
3634 spin_unlock_irqrestore(&xhci->lock, flags);
3636 for (i = 0; i < num_eps; i++) {
3637 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3638 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3640 /* Subtract 1 for stream 0, which drivers can't use */
3641 return num_streams - 1;
3644 /* If it didn't work, free the streams! */
3645 for (i = 0; i < num_eps; i++) {
3646 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3647 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3648 vdev->eps[ep_index].stream_info = NULL;
3649 /* FIXME Unset maxPstreams in endpoint context and
3650 * update deq ptr to point to normal string ring.
3652 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3653 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3654 xhci_endpoint_zero(xhci, vdev, eps[i]);
3656 xhci_free_command(xhci, config_cmd);
3660 /* Transition the endpoint from using streams to being a "normal" endpoint
3663 * Modify the endpoint context state, submit a configure endpoint command,
3664 * and free all endpoint rings for streams if that completes successfully.
3666 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3667 struct usb_host_endpoint **eps, unsigned int num_eps,
3671 struct xhci_hcd *xhci;
3672 struct xhci_virt_device *vdev;
3673 struct xhci_command *command;
3674 struct xhci_input_control_ctx *ctrl_ctx;
3675 unsigned int ep_index;
3676 unsigned long flags;
3677 u32 changed_ep_bitmask;
3679 xhci = hcd_to_xhci(hcd);
3680 vdev = xhci->devs[udev->slot_id];
3682 /* Set up a configure endpoint command to remove the streams rings */
3683 spin_lock_irqsave(&xhci->lock, flags);
3684 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3685 udev, eps, num_eps);
3686 if (changed_ep_bitmask == 0) {
3687 spin_unlock_irqrestore(&xhci->lock, flags);
3691 /* Use the xhci_command structure from the first endpoint. We may have
3692 * allocated too many, but the driver may call xhci_free_streams() for
3693 * each endpoint it grouped into one call to xhci_alloc_streams().
3695 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3696 command = vdev->eps[ep_index].stream_info->free_streams_command;
3697 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3700 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3705 for (i = 0; i < num_eps; i++) {
3706 struct xhci_ep_ctx *ep_ctx;
3708 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3709 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3710 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3711 EP_GETTING_NO_STREAMS;
3713 xhci_endpoint_copy(xhci, command->in_ctx,
3714 vdev->out_ctx, ep_index);
3715 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3716 &vdev->eps[ep_index]);
3718 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3719 vdev->out_ctx, ctrl_ctx,
3720 changed_ep_bitmask, changed_ep_bitmask);
3721 spin_unlock_irqrestore(&xhci->lock, flags);
3723 /* Issue and wait for the configure endpoint command,
3724 * which must succeed.
3726 ret = xhci_configure_endpoint(xhci, udev, command,
3729 /* xHC rejected the configure endpoint command for some reason, so we
3730 * leave the streams rings intact.
3735 spin_lock_irqsave(&xhci->lock, flags);
3736 for (i = 0; i < num_eps; i++) {
3737 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3738 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3739 vdev->eps[ep_index].stream_info = NULL;
3740 /* FIXME Unset maxPstreams in endpoint context and
3741 * update deq ptr to point to normal string ring.
3743 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3744 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3746 spin_unlock_irqrestore(&xhci->lock, flags);
3752 * Deletes endpoint resources for endpoints that were active before a Reset
3753 * Device command, or a Disable Slot command. The Reset Device command leaves
3754 * the control endpoint intact, whereas the Disable Slot command deletes it.
3756 * Must be called with xhci->lock held.
3758 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3759 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3762 unsigned int num_dropped_eps = 0;
3763 unsigned int drop_flags = 0;
3765 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3766 if (virt_dev->eps[i].ring) {
3767 drop_flags |= 1 << i;
3771 xhci->num_active_eps -= num_dropped_eps;
3772 if (num_dropped_eps)
3773 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3774 "Dropped %u ep ctxs, flags = 0x%x, "
3776 num_dropped_eps, drop_flags,
3777 xhci->num_active_eps);
3781 * This submits a Reset Device Command, which will set the device state to 0,
3782 * set the device address to 0, and disable all the endpoints except the default
3783 * control endpoint. The USB core should come back and call
3784 * xhci_address_device(), and then re-set up the configuration. If this is
3785 * called because of a usb_reset_and_verify_device(), then the old alternate
3786 * settings will be re-installed through the normal bandwidth allocation
3789 * Wait for the Reset Device command to finish. Remove all structures
3790 * associated with the endpoints that were disabled. Clear the input device
3791 * structure? Reset the control endpoint 0 max packet size?
3793 * If the virt_dev to be reset does not exist or does not match the udev,
3794 * it means the device is lost, possibly due to the xHC restore error and
3795 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3796 * re-allocate the device.
3798 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3799 struct usb_device *udev)
3802 unsigned long flags;
3803 struct xhci_hcd *xhci;
3804 unsigned int slot_id;
3805 struct xhci_virt_device *virt_dev;
3806 struct xhci_command *reset_device_cmd;
3807 struct xhci_slot_ctx *slot_ctx;
3808 int old_active_eps = 0;
3810 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3813 xhci = hcd_to_xhci(hcd);
3814 slot_id = udev->slot_id;
3815 virt_dev = xhci->devs[slot_id];
3817 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3818 "not exist. Re-allocate the device\n", slot_id);
3819 ret = xhci_alloc_dev(hcd, udev);
3826 if (virt_dev->tt_info)
3827 old_active_eps = virt_dev->tt_info->active_eps;
3829 if (virt_dev->udev != udev) {
3830 /* If the virt_dev and the udev does not match, this virt_dev
3831 * may belong to another udev.
3832 * Re-allocate the device.
3834 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3835 "not match the udev. Re-allocate the device\n",
3837 ret = xhci_alloc_dev(hcd, udev);
3844 /* If device is not setup, there is no point in resetting it */
3845 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3846 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3847 SLOT_STATE_DISABLED)
3850 trace_xhci_discover_or_reset_device(slot_ctx);
3852 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3853 /* Allocate the command structure that holds the struct completion.
3854 * Assume we're in process context, since the normal device reset
3855 * process has to wait for the device anyway. Storage devices are
3856 * reset as part of error handling, so use GFP_NOIO instead of
3859 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3860 if (!reset_device_cmd) {
3861 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3865 /* Attempt to submit the Reset Device command to the command ring */
3866 spin_lock_irqsave(&xhci->lock, flags);
3868 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3870 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3871 spin_unlock_irqrestore(&xhci->lock, flags);
3872 goto command_cleanup;
3874 xhci_ring_cmd_db(xhci);
3875 spin_unlock_irqrestore(&xhci->lock, flags);
3877 /* Wait for the Reset Device command to finish */
3878 wait_for_completion(reset_device_cmd->completion);
3880 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3881 * unless we tried to reset a slot ID that wasn't enabled,
3882 * or the device wasn't in the addressed or configured state.
3884 ret = reset_device_cmd->status;
3886 case COMP_COMMAND_ABORTED:
3887 case COMP_COMMAND_RING_STOPPED:
3888 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3890 goto command_cleanup;
3891 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3892 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3893 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3895 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3896 xhci_dbg(xhci, "Not freeing device rings.\n");
3897 /* Don't treat this as an error. May change my mind later. */
3899 goto command_cleanup;
3901 xhci_dbg(xhci, "Successful reset device command.\n");
3904 if (xhci_is_vendor_info_code(xhci, ret))
3906 xhci_warn(xhci, "Unknown completion code %u for "
3907 "reset device command.\n", ret);
3909 goto command_cleanup;
3912 /* Free up host controller endpoint resources */
3913 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3914 spin_lock_irqsave(&xhci->lock, flags);
3915 /* Don't delete the default control endpoint resources */
3916 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3917 spin_unlock_irqrestore(&xhci->lock, flags);
3920 /* Everything but endpoint 0 is disabled, so free the rings. */
3921 for (i = 1; i < 31; i++) {
3922 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3924 if (ep->ep_state & EP_HAS_STREAMS) {
3925 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3926 xhci_get_endpoint_address(i));
3927 xhci_free_stream_info(xhci, ep->stream_info);
3928 ep->stream_info = NULL;
3929 ep->ep_state &= ~EP_HAS_STREAMS;
3933 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3934 xhci_free_endpoint_ring(xhci, virt_dev, i);
3936 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3937 xhci_drop_ep_from_interval_table(xhci,
3938 &virt_dev->eps[i].bw_info,
3943 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3945 /* If necessary, update the number of active TTs on this root port */
3946 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3947 virt_dev->flags = 0;
3951 xhci_free_command(xhci, reset_device_cmd);
3956 * At this point, the struct usb_device is about to go away, the device has
3957 * disconnected, and all traffic has been stopped and the endpoints have been
3958 * disabled. Free any HC data structures associated with that device.
3960 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3962 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3963 struct xhci_virt_device *virt_dev;
3964 struct xhci_slot_ctx *slot_ctx;
3968 * We called pm_runtime_get_noresume when the device was attached.
3969 * Decrement the counter here to allow controller to runtime suspend
3970 * if no devices remain.
3972 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3973 pm_runtime_put_noidle(hcd->self.controller);
3975 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3976 /* If the host is halted due to driver unload, we still need to free the
3979 if (ret <= 0 && ret != -ENODEV)
3982 virt_dev = xhci->devs[udev->slot_id];
3983 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3984 trace_xhci_free_dev(slot_ctx);
3986 /* Stop any wayward timer functions (which may grab the lock) */
3987 for (i = 0; i < 31; i++) {
3988 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3989 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3991 virt_dev->udev = NULL;
3992 xhci_disable_slot(xhci, udev->slot_id);
3993 xhci_free_virt_device(xhci, udev->slot_id);
3996 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3998 struct xhci_command *command;
3999 unsigned long flags;
4003 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4007 xhci_debugfs_remove_slot(xhci, slot_id);
4009 spin_lock_irqsave(&xhci->lock, flags);
4010 /* Don't disable the slot if the host controller is dead. */
4011 state = readl(&xhci->op_regs->status);
4012 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4013 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4014 spin_unlock_irqrestore(&xhci->lock, flags);
4019 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4022 spin_unlock_irqrestore(&xhci->lock, flags);
4026 xhci_ring_cmd_db(xhci);
4027 spin_unlock_irqrestore(&xhci->lock, flags);
4029 wait_for_completion(command->completion);
4031 if (command->status != COMP_SUCCESS)
4032 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4033 slot_id, command->status);
4035 xhci_free_command(xhci, command);
4041 * Checks if we have enough host controller resources for the default control
4044 * Must be called with xhci->lock held.
4046 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4048 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4049 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4050 "Not enough ep ctxs: "
4051 "%u active, need to add 1, limit is %u.",
4052 xhci->num_active_eps, xhci->limit_active_eps);
4055 xhci->num_active_eps += 1;
4056 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4057 "Adding 1 ep ctx, %u now active.",
4058 xhci->num_active_eps);
4064 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4065 * timed out, or allocating memory failed. Returns 1 on success.
4067 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4069 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4070 struct xhci_virt_device *vdev;
4071 struct xhci_slot_ctx *slot_ctx;
4072 unsigned long flags;
4074 struct xhci_command *command;
4076 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4080 spin_lock_irqsave(&xhci->lock, flags);
4081 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4083 spin_unlock_irqrestore(&xhci->lock, flags);
4084 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4085 xhci_free_command(xhci, command);
4088 xhci_ring_cmd_db(xhci);
4089 spin_unlock_irqrestore(&xhci->lock, flags);
4091 wait_for_completion(command->completion);
4092 slot_id = command->slot_id;
4094 if (!slot_id || command->status != COMP_SUCCESS) {
4095 xhci_err(xhci, "Error while assigning device slot ID\n");
4096 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4098 readl(&xhci->cap_regs->hcs_params1)));
4099 xhci_free_command(xhci, command);
4103 xhci_free_command(xhci, command);
4105 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4106 spin_lock_irqsave(&xhci->lock, flags);
4107 ret = xhci_reserve_host_control_ep_resources(xhci);
4109 spin_unlock_irqrestore(&xhci->lock, flags);
4110 xhci_warn(xhci, "Not enough host resources, "
4111 "active endpoint contexts = %u\n",
4112 xhci->num_active_eps);
4115 spin_unlock_irqrestore(&xhci->lock, flags);
4117 /* Use GFP_NOIO, since this function can be called from
4118 * xhci_discover_or_reset_device(), which may be called as part of
4119 * mass storage driver error handling.
4121 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4122 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4125 vdev = xhci->devs[slot_id];
4126 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4127 trace_xhci_alloc_dev(slot_ctx);
4129 udev->slot_id = slot_id;
4131 xhci_debugfs_create_slot(xhci, slot_id);
4134 * If resetting upon resume, we can't put the controller into runtime
4135 * suspend if there is a device attached.
4137 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4138 pm_runtime_get_noresume(hcd->self.controller);
4140 /* Is this a LS or FS device under a HS hub? */
4141 /* Hub or peripherial? */
4145 xhci_disable_slot(xhci, udev->slot_id);
4146 xhci_free_virt_device(xhci, udev->slot_id);
4152 * Issue an Address Device command and optionally send a corresponding
4153 * SetAddress request to the device.
4155 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4156 enum xhci_setup_dev setup)
4158 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4159 unsigned long flags;
4160 struct xhci_virt_device *virt_dev;
4162 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4163 struct xhci_slot_ctx *slot_ctx;
4164 struct xhci_input_control_ctx *ctrl_ctx;
4166 struct xhci_command *command = NULL;
4168 mutex_lock(&xhci->mutex);
4170 if (xhci->xhc_state) { /* dying, removing or halted */
4175 if (!udev->slot_id) {
4176 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4177 "Bad Slot ID %d", udev->slot_id);
4182 virt_dev = xhci->devs[udev->slot_id];
4184 if (WARN_ON(!virt_dev)) {
4186 * In plug/unplug torture test with an NEC controller,
4187 * a zero-dereference was observed once due to virt_dev = 0.
4188 * Print useful debug rather than crash if it is observed again!
4190 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4195 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4196 trace_xhci_setup_device_slot(slot_ctx);
4198 if (setup == SETUP_CONTEXT_ONLY) {
4199 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4200 SLOT_STATE_DEFAULT) {
4201 xhci_dbg(xhci, "Slot already in default state\n");
4206 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4212 command->in_ctx = virt_dev->in_ctx;
4214 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4215 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4217 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4223 * If this is the first Set Address since device plug-in or
4224 * virt_device realloaction after a resume with an xHCI power loss,
4225 * then set up the slot context.
4227 if (!slot_ctx->dev_info)
4228 xhci_setup_addressable_virt_dev(xhci, udev);
4229 /* Otherwise, update the control endpoint ring enqueue pointer. */
4231 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4232 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4233 ctrl_ctx->drop_flags = 0;
4235 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4236 le32_to_cpu(slot_ctx->dev_info) >> 27);
4238 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4239 spin_lock_irqsave(&xhci->lock, flags);
4240 trace_xhci_setup_device(virt_dev);
4241 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4242 udev->slot_id, setup);
4244 spin_unlock_irqrestore(&xhci->lock, flags);
4245 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4246 "FIXME: allocate a command ring segment");
4249 xhci_ring_cmd_db(xhci);
4250 spin_unlock_irqrestore(&xhci->lock, flags);
4252 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4253 wait_for_completion(command->completion);
4255 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4256 * the SetAddress() "recovery interval" required by USB and aborting the
4257 * command on a timeout.
4259 switch (command->status) {
4260 case COMP_COMMAND_ABORTED:
4261 case COMP_COMMAND_RING_STOPPED:
4262 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4265 case COMP_CONTEXT_STATE_ERROR:
4266 case COMP_SLOT_NOT_ENABLED_ERROR:
4267 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4268 act, udev->slot_id);
4271 case COMP_USB_TRANSACTION_ERROR:
4272 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4274 mutex_unlock(&xhci->mutex);
4275 ret = xhci_disable_slot(xhci, udev->slot_id);
4276 xhci_free_virt_device(xhci, udev->slot_id);
4278 xhci_alloc_dev(hcd, udev);
4279 kfree(command->completion);
4282 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4283 dev_warn(&udev->dev,
4284 "ERROR: Incompatible device for setup %s command\n", act);
4288 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4289 "Successful setup %s command", act);
4293 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4294 act, command->status);
4295 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4301 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4302 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4303 "Op regs DCBAA ptr = %#016llx", temp_64);
4304 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4305 "Slot ID %d dcbaa entry @%p = %#016llx",
4307 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4308 (unsigned long long)
4309 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4310 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4311 "Output Context DMA address = %#08llx",
4312 (unsigned long long)virt_dev->out_ctx->dma);
4313 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4314 le32_to_cpu(slot_ctx->dev_info) >> 27);
4316 * USB core uses address 1 for the roothubs, so we add one to the
4317 * address given back to us by the HC.
4319 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4320 le32_to_cpu(slot_ctx->dev_info) >> 27);
4321 /* Zero the input context control for later use */
4322 ctrl_ctx->add_flags = 0;
4323 ctrl_ctx->drop_flags = 0;
4324 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4325 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4327 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4328 "Internal device address = %d",
4329 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4331 mutex_unlock(&xhci->mutex);
4333 kfree(command->completion);
4339 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4341 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4344 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4346 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4350 * Transfer the port index into real index in the HW port status
4351 * registers. Caculate offset between the port's PORTSC register
4352 * and port status base. Divide the number of per port register
4353 * to get the real index. The raw port number bases 1.
4355 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4357 struct xhci_hub *rhub;
4359 rhub = xhci_get_rhub(hcd);
4360 return rhub->ports[port1 - 1]->hw_portnum + 1;
4364 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4365 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4367 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4368 struct usb_device *udev, u16 max_exit_latency)
4370 struct xhci_virt_device *virt_dev;
4371 struct xhci_command *command;
4372 struct xhci_input_control_ctx *ctrl_ctx;
4373 struct xhci_slot_ctx *slot_ctx;
4374 unsigned long flags;
4377 spin_lock_irqsave(&xhci->lock, flags);
4379 virt_dev = xhci->devs[udev->slot_id];
4382 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4383 * xHC was re-initialized. Exit latency will be set later after
4384 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4387 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4388 spin_unlock_irqrestore(&xhci->lock, flags);
4392 /* Attempt to issue an Evaluate Context command to change the MEL. */
4393 command = xhci->lpm_command;
4394 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4396 spin_unlock_irqrestore(&xhci->lock, flags);
4397 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4402 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4403 spin_unlock_irqrestore(&xhci->lock, flags);
4405 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4406 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4407 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4408 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4409 slot_ctx->dev_state = 0;
4411 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4412 "Set up evaluate context for LPM MEL change.");
4414 /* Issue and wait for the evaluate context command. */
4415 ret = xhci_configure_endpoint(xhci, udev, command,
4419 spin_lock_irqsave(&xhci->lock, flags);
4420 virt_dev->current_mel = max_exit_latency;
4421 spin_unlock_irqrestore(&xhci->lock, flags);
4428 /* BESL to HIRD Encoding array for USB2 LPM */
4429 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4430 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4432 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4433 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4434 struct usb_device *udev)
4436 int u2del, besl, besl_host;
4437 int besl_device = 0;
4440 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4441 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4443 if (field & USB_BESL_SUPPORT) {
4444 for (besl_host = 0; besl_host < 16; besl_host++) {
4445 if (xhci_besl_encoding[besl_host] >= u2del)
4448 /* Use baseline BESL value as default */
4449 if (field & USB_BESL_BASELINE_VALID)
4450 besl_device = USB_GET_BESL_BASELINE(field);
4451 else if (field & USB_BESL_DEEP_VALID)
4452 besl_device = USB_GET_BESL_DEEP(field);
4457 besl_host = (u2del - 51) / 75 + 1;
4460 besl = besl_host + besl_device;
4467 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4468 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4475 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4477 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4478 l1 = udev->l1_params.timeout / 256;
4480 /* device has preferred BESLD */
4481 if (field & USB_BESL_DEEP_VALID) {
4482 besld = USB_GET_BESL_DEEP(field);
4486 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4489 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4490 struct usb_device *udev, int enable)
4492 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4493 struct xhci_port **ports;
4494 __le32 __iomem *pm_addr, *hlpm_addr;
4495 u32 pm_val, hlpm_val, field;
4496 unsigned int port_num;
4497 unsigned long flags;
4498 int hird, exit_latency;
4501 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4504 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4508 if (!udev->parent || udev->parent->parent ||
4509 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4512 if (udev->usb2_hw_lpm_capable != 1)
4515 spin_lock_irqsave(&xhci->lock, flags);
4517 ports = xhci->usb2_rhub.ports;
4518 port_num = udev->portnum - 1;
4519 pm_addr = ports[port_num]->addr + PORTPMSC;
4520 pm_val = readl(pm_addr);
4521 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4523 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4524 enable ? "enable" : "disable", port_num + 1);
4527 /* Host supports BESL timeout instead of HIRD */
4528 if (udev->usb2_hw_lpm_besl_capable) {
4529 /* if device doesn't have a preferred BESL value use a
4530 * default one which works with mixed HIRD and BESL
4531 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4533 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4534 if ((field & USB_BESL_SUPPORT) &&
4535 (field & USB_BESL_BASELINE_VALID))
4536 hird = USB_GET_BESL_BASELINE(field);
4538 hird = udev->l1_params.besl;
4540 exit_latency = xhci_besl_encoding[hird];
4541 spin_unlock_irqrestore(&xhci->lock, flags);
4543 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4544 * input context for link powermanagement evaluate
4545 * context commands. It is protected by hcd->bandwidth
4546 * mutex and is shared by all devices. We need to set
4547 * the max ext latency in USB 2 BESL LPM as well, so
4548 * use the same mutex and xhci_change_max_exit_latency()
4550 mutex_lock(hcd->bandwidth_mutex);
4551 ret = xhci_change_max_exit_latency(xhci, udev,
4553 mutex_unlock(hcd->bandwidth_mutex);
4557 spin_lock_irqsave(&xhci->lock, flags);
4559 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4560 writel(hlpm_val, hlpm_addr);
4564 hird = xhci_calculate_hird_besl(xhci, udev);
4567 pm_val &= ~PORT_HIRD_MASK;
4568 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4569 writel(pm_val, pm_addr);
4570 pm_val = readl(pm_addr);
4572 writel(pm_val, pm_addr);
4576 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4577 writel(pm_val, pm_addr);
4580 if (udev->usb2_hw_lpm_besl_capable) {
4581 spin_unlock_irqrestore(&xhci->lock, flags);
4582 mutex_lock(hcd->bandwidth_mutex);
4583 xhci_change_max_exit_latency(xhci, udev, 0);
4584 mutex_unlock(hcd->bandwidth_mutex);
4585 readl_poll_timeout(ports[port_num]->addr, pm_val,
4586 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4592 spin_unlock_irqrestore(&xhci->lock, flags);
4596 /* check if a usb2 port supports a given extened capability protocol
4597 * only USB2 ports extended protocol capability values are cached.
4598 * Return 1 if capability is supported
4600 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4601 unsigned capability)
4603 u32 port_offset, port_count;
4606 for (i = 0; i < xhci->num_ext_caps; i++) {
4607 if (xhci->ext_caps[i] & capability) {
4608 /* port offsets starts at 1 */
4609 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4610 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4611 if (port >= port_offset &&
4612 port < port_offset + port_count)
4619 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4621 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4622 int portnum = udev->portnum - 1;
4624 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4627 /* we only support lpm for non-hub device connected to root hub yet */
4628 if (!udev->parent || udev->parent->parent ||
4629 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4632 if (xhci->hw_lpm_support == 1 &&
4633 xhci_check_usb2_port_capability(
4634 xhci, portnum, XHCI_HLC)) {
4635 udev->usb2_hw_lpm_capable = 1;
4636 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4637 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4638 if (xhci_check_usb2_port_capability(xhci, portnum,
4640 udev->usb2_hw_lpm_besl_capable = 1;
4646 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4648 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4649 static unsigned long long xhci_service_interval_to_ns(
4650 struct usb_endpoint_descriptor *desc)
4652 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4655 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4656 enum usb3_link_state state)
4658 unsigned long long sel;
4659 unsigned long long pel;
4660 unsigned int max_sel_pel;
4665 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4666 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4667 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4668 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4672 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4673 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4674 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4678 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4680 return USB3_LPM_DISABLED;
4683 if (sel <= max_sel_pel && pel <= max_sel_pel)
4684 return USB3_LPM_DEVICE_INITIATED;
4686 if (sel > max_sel_pel)
4687 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4688 "due to long SEL %llu ms\n",
4691 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4692 "due to long PEL %llu ms\n",
4694 return USB3_LPM_DISABLED;
4697 /* The U1 timeout should be the maximum of the following values:
4698 * - For control endpoints, U1 system exit latency (SEL) * 3
4699 * - For bulk endpoints, U1 SEL * 5
4700 * - For interrupt endpoints:
4701 * - Notification EPs, U1 SEL * 3
4702 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4703 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4705 static unsigned long long xhci_calculate_intel_u1_timeout(
4706 struct usb_device *udev,
4707 struct usb_endpoint_descriptor *desc)
4709 unsigned long long timeout_ns;
4713 ep_type = usb_endpoint_type(desc);
4715 case USB_ENDPOINT_XFER_CONTROL:
4716 timeout_ns = udev->u1_params.sel * 3;
4718 case USB_ENDPOINT_XFER_BULK:
4719 timeout_ns = udev->u1_params.sel * 5;
4721 case USB_ENDPOINT_XFER_INT:
4722 intr_type = usb_endpoint_interrupt_type(desc);
4723 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4724 timeout_ns = udev->u1_params.sel * 3;
4727 /* Otherwise the calculation is the same as isoc eps */
4729 case USB_ENDPOINT_XFER_ISOC:
4730 timeout_ns = xhci_service_interval_to_ns(desc);
4731 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4732 if (timeout_ns < udev->u1_params.sel * 2)
4733 timeout_ns = udev->u1_params.sel * 2;
4742 /* Returns the hub-encoded U1 timeout value. */
4743 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4744 struct usb_device *udev,
4745 struct usb_endpoint_descriptor *desc)
4747 unsigned long long timeout_ns;
4749 /* Prevent U1 if service interval is shorter than U1 exit latency */
4750 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4751 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4752 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4753 return USB3_LPM_DISABLED;
4757 if (xhci->quirks & XHCI_INTEL_HOST)
4758 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4760 timeout_ns = udev->u1_params.sel;
4762 /* The U1 timeout is encoded in 1us intervals.
4763 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4765 if (timeout_ns == USB3_LPM_DISABLED)
4768 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4770 /* If the necessary timeout value is bigger than what we can set in the
4771 * USB 3.0 hub, we have to disable hub-initiated U1.
4773 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4775 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4776 "due to long timeout %llu ms\n", timeout_ns);
4777 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4780 /* The U2 timeout should be the maximum of:
4781 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4782 * - largest bInterval of any active periodic endpoint (to avoid going
4783 * into lower power link states between intervals).
4784 * - the U2 Exit Latency of the device
4786 static unsigned long long xhci_calculate_intel_u2_timeout(
4787 struct usb_device *udev,
4788 struct usb_endpoint_descriptor *desc)
4790 unsigned long long timeout_ns;
4791 unsigned long long u2_del_ns;
4793 timeout_ns = 10 * 1000 * 1000;
4795 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4796 (xhci_service_interval_to_ns(desc) > timeout_ns))
4797 timeout_ns = xhci_service_interval_to_ns(desc);
4799 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4800 if (u2_del_ns > timeout_ns)
4801 timeout_ns = u2_del_ns;
4806 /* Returns the hub-encoded U2 timeout value. */
4807 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4808 struct usb_device *udev,
4809 struct usb_endpoint_descriptor *desc)
4811 unsigned long long timeout_ns;
4813 /* Prevent U2 if service interval is shorter than U2 exit latency */
4814 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4815 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4816 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4817 return USB3_LPM_DISABLED;
4821 if (xhci->quirks & XHCI_INTEL_HOST)
4822 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4824 timeout_ns = udev->u2_params.sel;
4826 /* The U2 timeout is encoded in 256us intervals */
4827 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4828 /* If the necessary timeout value is bigger than what we can set in the
4829 * USB 3.0 hub, we have to disable hub-initiated U2.
4831 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4833 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4834 "due to long timeout %llu ms\n", timeout_ns);
4835 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4838 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4839 struct usb_device *udev,
4840 struct usb_endpoint_descriptor *desc,
4841 enum usb3_link_state state,
4844 if (state == USB3_LPM_U1)
4845 return xhci_calculate_u1_timeout(xhci, udev, desc);
4846 else if (state == USB3_LPM_U2)
4847 return xhci_calculate_u2_timeout(xhci, udev, desc);
4849 return USB3_LPM_DISABLED;
4852 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4853 struct usb_device *udev,
4854 struct usb_endpoint_descriptor *desc,
4855 enum usb3_link_state state,
4860 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4861 desc, state, timeout);
4863 /* If we found we can't enable hub-initiated LPM, and
4864 * the U1 or U2 exit latency was too high to allow
4865 * device-initiated LPM as well, then we will disable LPM
4866 * for this device, so stop searching any further.
4868 if (alt_timeout == USB3_LPM_DISABLED) {
4869 *timeout = alt_timeout;
4872 if (alt_timeout > *timeout)
4873 *timeout = alt_timeout;
4877 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4878 struct usb_device *udev,
4879 struct usb_host_interface *alt,
4880 enum usb3_link_state state,
4885 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4886 if (xhci_update_timeout_for_endpoint(xhci, udev,
4887 &alt->endpoint[j].desc, state, timeout))
4893 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4894 enum usb3_link_state state)
4896 struct usb_device *parent;
4897 unsigned int num_hubs;
4899 if (state == USB3_LPM_U2)
4902 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4903 for (parent = udev->parent, num_hubs = 0; parent->parent;
4904 parent = parent->parent)
4910 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4911 " below second-tier hub.\n");
4912 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4913 "to decrease power consumption.\n");
4917 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4918 struct usb_device *udev,
4919 enum usb3_link_state state)
4921 if (xhci->quirks & XHCI_INTEL_HOST)
4922 return xhci_check_intel_tier_policy(udev, state);
4927 /* Returns the U1 or U2 timeout that should be enabled.
4928 * If the tier check or timeout setting functions return with a non-zero exit
4929 * code, that means the timeout value has been finalized and we shouldn't look
4930 * at any more endpoints.
4932 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4933 struct usb_device *udev, enum usb3_link_state state)
4935 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4936 struct usb_host_config *config;
4939 u16 timeout = USB3_LPM_DISABLED;
4941 if (state == USB3_LPM_U1)
4943 else if (state == USB3_LPM_U2)
4946 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4951 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4954 /* Gather some information about the currently installed configuration
4955 * and alternate interface settings.
4957 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4961 config = udev->actconfig;
4965 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4966 struct usb_driver *driver;
4967 struct usb_interface *intf = config->interface[i];
4972 /* Check if any currently bound drivers want hub-initiated LPM
4975 if (intf->dev.driver) {
4976 driver = to_usb_driver(intf->dev.driver);
4977 if (driver && driver->disable_hub_initiated_lpm) {
4978 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4979 state_name, driver->name);
4980 timeout = xhci_get_timeout_no_hub_lpm(udev,
4982 if (timeout == USB3_LPM_DISABLED)
4987 /* Not sure how this could happen... */
4988 if (!intf->cur_altsetting)
4991 if (xhci_update_timeout_for_interface(xhci, udev,
4992 intf->cur_altsetting,
4999 static int calculate_max_exit_latency(struct usb_device *udev,
5000 enum usb3_link_state state_changed,
5001 u16 hub_encoded_timeout)
5003 unsigned long long u1_mel_us = 0;
5004 unsigned long long u2_mel_us = 0;
5005 unsigned long long mel_us = 0;
5011 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5012 hub_encoded_timeout == USB3_LPM_DISABLED);
5013 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5014 hub_encoded_timeout == USB3_LPM_DISABLED);
5016 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5017 hub_encoded_timeout != USB3_LPM_DISABLED);
5018 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5019 hub_encoded_timeout != USB3_LPM_DISABLED);
5021 /* If U1 was already enabled and we're not disabling it,
5022 * or we're going to enable U1, account for the U1 max exit latency.
5024 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5026 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5027 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5029 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5031 if (u1_mel_us > u2_mel_us)
5035 /* xHCI host controller max exit latency field is only 16 bits wide. */
5036 if (mel_us > MAX_EXIT) {
5037 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5038 "is too big.\n", mel_us);
5044 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5045 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5046 struct usb_device *udev, enum usb3_link_state state)
5048 struct xhci_hcd *xhci;
5049 u16 hub_encoded_timeout;
5053 xhci = hcd_to_xhci(hcd);
5054 /* The LPM timeout values are pretty host-controller specific, so don't
5055 * enable hub-initiated timeouts unless the vendor has provided
5056 * information about their timeout algorithm.
5058 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5059 !xhci->devs[udev->slot_id])
5060 return USB3_LPM_DISABLED;
5062 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5063 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5065 /* Max Exit Latency is too big, disable LPM. */
5066 hub_encoded_timeout = USB3_LPM_DISABLED;
5070 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5073 return hub_encoded_timeout;
5076 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5077 struct usb_device *udev, enum usb3_link_state state)
5079 struct xhci_hcd *xhci;
5082 xhci = hcd_to_xhci(hcd);
5083 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5084 !xhci->devs[udev->slot_id])
5087 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5088 return xhci_change_max_exit_latency(xhci, udev, mel);
5090 #else /* CONFIG_PM */
5092 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5093 struct usb_device *udev, int enable)
5098 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5103 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5104 struct usb_device *udev, enum usb3_link_state state)
5106 return USB3_LPM_DISABLED;
5109 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5110 struct usb_device *udev, enum usb3_link_state state)
5114 #endif /* CONFIG_PM */
5116 /*-------------------------------------------------------------------------*/
5118 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5119 * internal data structures for the device.
5121 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5122 struct usb_tt *tt, gfp_t mem_flags)
5124 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5125 struct xhci_virt_device *vdev;
5126 struct xhci_command *config_cmd;
5127 struct xhci_input_control_ctx *ctrl_ctx;
5128 struct xhci_slot_ctx *slot_ctx;
5129 unsigned long flags;
5130 unsigned think_time;
5133 /* Ignore root hubs */
5137 vdev = xhci->devs[hdev->slot_id];
5139 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5143 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5147 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5149 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5151 xhci_free_command(xhci, config_cmd);
5155 spin_lock_irqsave(&xhci->lock, flags);
5156 if (hdev->speed == USB_SPEED_HIGH &&
5157 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5158 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5159 xhci_free_command(xhci, config_cmd);
5160 spin_unlock_irqrestore(&xhci->lock, flags);
5164 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5165 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5166 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5167 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5169 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5170 * but it may be already set to 1 when setup an xHCI virtual
5171 * device, so clear it anyway.
5174 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5175 else if (hdev->speed == USB_SPEED_FULL)
5176 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5178 if (xhci->hci_version > 0x95) {
5179 xhci_dbg(xhci, "xHCI version %x needs hub "
5180 "TT think time and number of ports\n",
5181 (unsigned int) xhci->hci_version);
5182 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5183 /* Set TT think time - convert from ns to FS bit times.
5184 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5185 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5187 * xHCI 1.0: this field shall be 0 if the device is not a
5190 think_time = tt->think_time;
5191 if (think_time != 0)
5192 think_time = (think_time / 666) - 1;
5193 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5194 slot_ctx->tt_info |=
5195 cpu_to_le32(TT_THINK_TIME(think_time));
5197 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5198 "TT think time or number of ports\n",
5199 (unsigned int) xhci->hci_version);
5201 slot_ctx->dev_state = 0;
5202 spin_unlock_irqrestore(&xhci->lock, flags);
5204 xhci_dbg(xhci, "Set up %s for hub device.\n",
5205 (xhci->hci_version > 0x95) ?
5206 "configure endpoint" : "evaluate context");
5208 /* Issue and wait for the configure endpoint or
5209 * evaluate context command.
5211 if (xhci->hci_version > 0x95)
5212 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5215 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5218 xhci_free_command(xhci, config_cmd);
5222 static int xhci_get_frame(struct usb_hcd *hcd)
5224 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5225 /* EHCI mods by the periodic size. Why? */
5226 return readl(&xhci->run_regs->microframe_index) >> 3;
5229 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5231 struct xhci_hcd *xhci;
5233 * TODO: Check with DWC3 clients for sysdev according to
5236 struct device *dev = hcd->self.sysdev;
5237 unsigned int minor_rev;
5240 /* Accept arbitrarily long scatter-gather lists */
5241 hcd->self.sg_tablesize = ~0;
5243 /* support to build packet from discontinuous buffers */
5244 hcd->self.no_sg_constraint = 1;
5246 /* XHCI controllers don't stop the ep queue on short packets :| */
5247 hcd->self.no_stop_on_short = 1;
5249 xhci = hcd_to_xhci(hcd);
5251 if (usb_hcd_is_primary_hcd(hcd)) {
5252 xhci->main_hcd = hcd;
5253 xhci->usb2_rhub.hcd = hcd;
5254 /* Mark the first roothub as being USB 2.0.
5255 * The xHCI driver will register the USB 3.0 roothub.
5257 hcd->speed = HCD_USB2;
5258 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5260 * USB 2.0 roothub under xHCI has an integrated TT,
5261 * (rate matching hub) as opposed to having an OHCI/UHCI
5262 * companion controller.
5267 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5268 * should return 0x31 for sbrn, or that the minor revision
5269 * is a two digit BCD containig minor and sub-minor numbers.
5270 * This was later clarified in xHCI 1.2.
5272 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5273 * minor revision set to 0x1 instead of 0x10.
5275 if (xhci->usb3_rhub.min_rev == 0x1)
5278 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5280 switch (minor_rev) {
5282 hcd->speed = HCD_USB32;
5283 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5284 hcd->self.root_hub->rx_lanes = 2;
5285 hcd->self.root_hub->tx_lanes = 2;
5286 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5289 hcd->speed = HCD_USB31;
5290 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5291 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5294 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5296 minor_rev ? "Enhanced " : "");
5298 xhci->usb3_rhub.hcd = hcd;
5299 /* xHCI private pointer was set in xhci_pci_probe for the second
5300 * registered roothub.
5305 mutex_init(&xhci->mutex);
5306 xhci->cap_regs = hcd->regs;
5307 xhci->op_regs = hcd->regs +
5308 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5309 xhci->run_regs = hcd->regs +
5310 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5311 /* Cache read-only capability registers */
5312 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5313 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5314 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5315 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5316 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5317 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5318 if (xhci->hci_version > 0x100)
5319 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5321 xhci->quirks |= quirks;
5323 get_quirks(dev, xhci);
5325 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5326 * success event after a short transfer. This quirk will ignore such
5329 if (xhci->hci_version > 0x96)
5330 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5332 /* Make sure the HC is halted. */
5333 retval = xhci_halt(xhci);
5337 xhci_zero_64b_regs(xhci);
5339 xhci_dbg(xhci, "Resetting HCD\n");
5340 /* Reset the internal HC memory state and registers. */
5341 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5344 xhci_dbg(xhci, "Reset complete\n");
5347 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5348 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5349 * address memory pointers actually. So, this driver clears the AC64
5350 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5351 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5353 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5354 xhci->hcc_params &= ~BIT(0);
5356 /* Set dma_mask and coherent_dma_mask to 64-bits,
5357 * if xHC supports 64-bit addressing */
5358 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5359 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5360 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5361 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5364 * This is to avoid error in cases where a 32-bit USB
5365 * controller is used on a 64-bit capable system.
5367 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5370 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5371 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5374 xhci_dbg(xhci, "Calling HCD init\n");
5375 /* Initialize HCD and host controller data structures. */
5376 retval = xhci_init(hcd);
5379 xhci_dbg(xhci, "Called HCD init\n");
5381 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5382 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5386 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5388 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5389 struct usb_host_endpoint *ep)
5391 struct xhci_hcd *xhci;
5392 struct usb_device *udev;
5393 unsigned int slot_id;
5394 unsigned int ep_index;
5395 unsigned long flags;
5397 xhci = hcd_to_xhci(hcd);
5399 spin_lock_irqsave(&xhci->lock, flags);
5400 udev = (struct usb_device *)ep->hcpriv;
5401 slot_id = udev->slot_id;
5402 ep_index = xhci_get_endpoint_index(&ep->desc);
5404 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5405 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5406 spin_unlock_irqrestore(&xhci->lock, flags);
5409 static const struct hc_driver xhci_hc_driver = {
5410 .description = "xhci-hcd",
5411 .product_desc = "xHCI Host Controller",
5412 .hcd_priv_size = sizeof(struct xhci_hcd),
5415 * generic hardware linkage
5418 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5422 * basic lifecycle operations
5424 .reset = NULL, /* set in xhci_init_driver() */
5427 .shutdown = xhci_shutdown,
5430 * managing i/o requests and associated device resources
5432 .map_urb_for_dma = xhci_map_urb_for_dma,
5433 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5434 .urb_enqueue = xhci_urb_enqueue,
5435 .urb_dequeue = xhci_urb_dequeue,
5436 .alloc_dev = xhci_alloc_dev,
5437 .free_dev = xhci_free_dev,
5438 .alloc_streams = xhci_alloc_streams,
5439 .free_streams = xhci_free_streams,
5440 .add_endpoint = xhci_add_endpoint,
5441 .drop_endpoint = xhci_drop_endpoint,
5442 .endpoint_disable = xhci_endpoint_disable,
5443 .endpoint_reset = xhci_endpoint_reset,
5444 .check_bandwidth = xhci_check_bandwidth,
5445 .reset_bandwidth = xhci_reset_bandwidth,
5446 .address_device = xhci_address_device,
5447 .enable_device = xhci_enable_device,
5448 .update_hub_device = xhci_update_hub_device,
5449 .reset_device = xhci_discover_or_reset_device,
5452 * scheduling support
5454 .get_frame_number = xhci_get_frame,
5459 .hub_control = xhci_hub_control,
5460 .hub_status_data = xhci_hub_status_data,
5461 .bus_suspend = xhci_bus_suspend,
5462 .bus_resume = xhci_bus_resume,
5463 .get_resuming_ports = xhci_get_resuming_ports,
5466 * call back when device connected and addressed
5468 .update_device = xhci_update_device,
5469 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5470 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5471 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5472 .find_raw_port_number = xhci_find_raw_port_number,
5473 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5476 void xhci_init_driver(struct hc_driver *drv,
5477 const struct xhci_driver_overrides *over)
5481 /* Copy the generic table to drv then apply the overrides */
5482 *drv = xhci_hc_driver;
5485 drv->hcd_priv_size += over->extra_priv_size;
5487 drv->reset = over->reset;
5489 drv->start = over->start;
5490 if (over->add_endpoint)
5491 drv->add_endpoint = over->add_endpoint;
5492 if (over->drop_endpoint)
5493 drv->drop_endpoint = over->drop_endpoint;
5494 if (over->check_bandwidth)
5495 drv->check_bandwidth = over->check_bandwidth;
5496 if (over->reset_bandwidth)
5497 drv->reset_bandwidth = over->reset_bandwidth;
5500 EXPORT_SYMBOL_GPL(xhci_init_driver);
5502 MODULE_DESCRIPTION(DRIVER_DESC);
5503 MODULE_AUTHOR(DRIVER_AUTHOR);
5504 MODULE_LICENSE("GPL");
5506 static int __init xhci_hcd_init(void)
5509 * Check the compiler generated sizes of structures that must be laid
5510 * out in specific ways for hardware access.
5512 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5513 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5514 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5515 /* xhci_device_control has eight fields, and also
5516 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5518 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5519 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5520 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5521 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5522 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5523 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5524 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5529 xhci_debugfs_create_root();
5535 * If an init function is provided, an exit function must also be provided
5536 * to allow module unload.
5538 static void __exit xhci_hcd_fini(void)
5540 xhci_debugfs_remove_root();
5543 module_init(xhci_hcd_init);
5544 module_exit(xhci_hcd_fini);