1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
113 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
116 ret = xhci_handshake(&xhci->op_regs->status,
117 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 xhci_warn(xhci, "Host halt failed, %d\n", ret);
122 xhci->xhc_state |= XHCI_STATE_HALTED;
123 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
128 * Set the run bit and wait for the host to be running.
130 int xhci_start(struct xhci_hcd *xhci)
135 temp = readl(&xhci->op_regs->command);
137 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 writel(temp, &xhci->op_regs->command);
142 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 ret = xhci_handshake(&xhci->op_regs->status,
146 STS_HALT, 0, XHCI_MAX_HALT_USEC);
147 if (ret == -ETIMEDOUT)
148 xhci_err(xhci, "Host took too long to start, "
149 "waited %u microseconds.\n",
152 /* clear state flags. Including dying, halted or removing */
161 * This resets pipelines, timers, counters, state machines, etc.
162 * Transactions will be terminated immediately, and operational registers
163 * will be set to their defaults.
165 int xhci_reset(struct xhci_hcd *xhci)
171 state = readl(&xhci->op_regs->status);
173 if (state == ~(u32)0) {
174 xhci_warn(xhci, "Host not accessible, reset failed.\n");
178 if ((state & STS_HALT) == 0) {
179 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
183 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
184 command = readl(&xhci->op_regs->command);
185 command |= CMD_RESET;
186 writel(command, &xhci->op_regs->command);
188 /* Existing Intel xHCI controllers require a delay of 1 mS,
189 * after setting the CMD_RESET bit, and before accessing any
190 * HC registers. This allows the HC to complete the
191 * reset operation and be ready for HC register access.
192 * Without this delay, the subsequent HC register access,
193 * may result in a system hang very rarely.
195 if (xhci->quirks & XHCI_INTEL_HOST)
198 ret = xhci_handshake(&xhci->op_regs->command,
199 CMD_RESET, 0, 10 * 1000 * 1000);
203 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
204 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
206 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
207 "Wait for controller to be ready for doorbell rings");
209 * xHCI cannot write to any doorbells or operational registers other
210 * than status until the "Controller Not Ready" flag is cleared.
212 ret = xhci_handshake(&xhci->op_regs->status,
213 STS_CNR, 0, 10 * 1000 * 1000);
215 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
216 xhci->usb2_rhub.bus_state.suspended_ports = 0;
217 xhci->usb2_rhub.bus_state.resuming_ports = 0;
218 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb3_rhub.bus_state.suspended_ports = 0;
220 xhci->usb3_rhub.bus_state.resuming_ports = 0;
225 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
227 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
270 ARRAY_SIZE(xhci->run_regs->ir_set));
272 for (i = 0; i < intrs; i++) {
273 struct xhci_intr_reg __iomem *ir;
275 ir = &xhci->run_regs->ir_set[i];
276 val = xhci_read_64(xhci, &ir->erst_base);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_base);
279 val= xhci_read_64(xhci, &ir->erst_dequeue);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_dequeue);
284 /* Wait for the fault to appear. It will be cleared on reset */
285 err = xhci_handshake(&xhci->op_regs->status,
286 STS_FATAL, STS_FATAL,
289 xhci_info(xhci, "Fault detected\n");
292 #ifdef CONFIG_USB_PCI
296 static int xhci_setup_msi(struct xhci_hcd *xhci)
300 * TODO:Check with MSI Soc for sysdev
302 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
304 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
306 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
307 "failed to allocate MSI entry");
311 ret = request_irq(pdev->irq, xhci_msi_irq,
312 0, "xhci_hcd", xhci_to_hcd(xhci));
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "disable MSI interrupt");
316 pci_free_irq_vectors(pdev);
325 static int xhci_setup_msix(struct xhci_hcd *xhci)
328 struct usb_hcd *hcd = xhci_to_hcd(xhci);
329 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
332 * calculate number of msi-x vectors supported.
333 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
334 * with max number of interrupters based on the xhci HCSPARAMS1.
335 * - num_online_cpus: maximum msi-x vectors per CPUs core.
336 * Add additional 1 vector to ensure always available interrupt.
338 xhci->msix_count = min(num_online_cpus() + 1,
339 HCS_MAX_INTRS(xhci->hcs_params1));
341 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
344 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
345 "Failed to enable MSI-X");
349 for (i = 0; i < xhci->msix_count; i++) {
350 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
351 "xhci_hcd", xhci_to_hcd(xhci));
356 hcd->msix_enabled = 1;
360 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
362 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
363 pci_free_irq_vectors(pdev);
367 /* Free any IRQs and disable MSI-X */
368 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
370 struct usb_hcd *hcd = xhci_to_hcd(xhci);
371 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
373 if (xhci->quirks & XHCI_PLAT)
376 /* return if using legacy interrupt */
380 if (hcd->msix_enabled) {
383 for (i = 0; i < xhci->msix_count; i++)
384 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
386 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
389 pci_free_irq_vectors(pdev);
390 hcd->msix_enabled = 0;
393 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
395 struct usb_hcd *hcd = xhci_to_hcd(xhci);
397 if (hcd->msix_enabled) {
398 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
401 for (i = 0; i < xhci->msix_count; i++)
402 synchronize_irq(pci_irq_vector(pdev, i));
406 static int xhci_try_enable_msi(struct usb_hcd *hcd)
408 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
409 struct pci_dev *pdev;
412 /* The xhci platform device has set up IRQs through usb_add_hcd. */
413 if (xhci->quirks & XHCI_PLAT)
416 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
418 * Some Fresco Logic host controllers advertise MSI, but fail to
419 * generate interrupts. Don't even try to enable MSI.
421 if (xhci->quirks & XHCI_BROKEN_MSI)
424 /* unregister the legacy interrupt */
426 free_irq(hcd->irq, hcd);
429 ret = xhci_setup_msix(xhci);
431 /* fall back to msi*/
432 ret = xhci_setup_msi(xhci);
435 hcd->msi_enabled = 1;
440 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
445 if (!strlen(hcd->irq_descr))
446 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
447 hcd->driver->description, hcd->self.busnum);
449 /* fall back to legacy interrupt*/
450 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
451 hcd->irq_descr, hcd);
453 xhci_err(xhci, "request interrupt %d failed\n",
457 hcd->irq = pdev->irq;
463 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
468 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
472 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
478 static void compliance_mode_recovery(struct timer_list *t)
480 struct xhci_hcd *xhci;
482 struct xhci_hub *rhub;
486 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
487 rhub = &xhci->usb3_rhub;
489 for (i = 0; i < rhub->num_ports; i++) {
490 temp = readl(rhub->ports[i]->addr);
491 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
493 * Compliance Mode Detected. Letting USB Core
494 * handle the Warm Reset
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode detected->port %d",
499 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
500 "Attempting compliance mode recovery");
501 hcd = xhci->shared_hcd;
503 if (hcd->state == HC_STATE_SUSPENDED)
504 usb_hcd_resume_root_hub(hcd);
506 usb_hcd_poll_rh_status(hcd);
510 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
511 mod_timer(&xhci->comp_mode_recovery_timer,
512 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
516 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
517 * that causes ports behind that hardware to enter compliance mode sometimes.
518 * The quirk creates a timer that polls every 2 seconds the link state of
519 * each host controller's port and recovers it by issuing a Warm reset
520 * if Compliance mode is detected, otherwise the port will become "dead" (no
521 * device connections or disconnections will be detected anymore). Becasue no
522 * status event is generated when entering compliance mode (per xhci spec),
523 * this quirk is needed on systems that have the failing hardware installed.
525 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
527 xhci->port_status_u0 = 0;
528 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
530 xhci->comp_mode_recovery_timer.expires = jiffies +
531 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
533 add_timer(&xhci->comp_mode_recovery_timer);
534 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
535 "Compliance mode recovery timer initialized");
539 * This function identifies the systems that have installed the SN65LVPE502CP
540 * USB3.0 re-driver and that need the Compliance Mode Quirk.
542 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
544 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
546 const char *dmi_product_name, *dmi_sys_vendor;
548 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
549 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
550 if (!dmi_product_name || !dmi_sys_vendor)
553 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
556 if (strstr(dmi_product_name, "Z420") ||
557 strstr(dmi_product_name, "Z620") ||
558 strstr(dmi_product_name, "Z820") ||
559 strstr(dmi_product_name, "Z1 Workstation"))
565 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
567 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
572 * Initialize memory for HCD and xHC (one-time init).
574 * Program the PAGESIZE register, initialize the device context array, create
575 * device contexts (?), set up a command ring segment (or two?), create event
576 * ring (one for now).
578 static int xhci_init(struct usb_hcd *hcd)
580 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
583 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
584 spin_lock_init(&xhci->lock);
585 if (xhci->hci_version == 0x95 && link_quirk) {
586 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
587 "QUIRK: Not clearing Link TRB chain bits.");
588 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
590 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
591 "xHCI doesn't need link TRB QUIRK");
593 retval = xhci_mem_init(xhci, GFP_KERNEL);
594 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
596 /* Initializing Compliance Mode Recovery Data If Needed */
597 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
598 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
599 compliance_mode_recovery_timer_init(xhci);
605 /*-------------------------------------------------------------------------*/
608 static int xhci_run_finished(struct xhci_hcd *xhci)
610 if (xhci_start(xhci)) {
614 xhci->shared_hcd->state = HC_STATE_RUNNING;
615 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
617 if (xhci->quirks & XHCI_NEC_HOST)
618 xhci_ring_cmd_db(xhci);
620 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
621 "Finished xhci_run for USB3 roothub");
626 * Start the HC after it was halted.
628 * This function is called by the USB core when the HC driver is added.
629 * Its opposite is xhci_stop().
631 * xhci_init() must be called once before this function can be called.
632 * Reset the HC, enable device slot contexts, program DCBAAP, and
633 * set command ring pointer and event ring pointer.
635 * Setup MSI-X vectors and enable interrupts.
637 int xhci_run(struct usb_hcd *hcd)
642 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
644 /* Start the xHCI host controller running only after the USB 2.0 roothub
648 hcd->uses_new_polling = 1;
649 if (!usb_hcd_is_primary_hcd(hcd))
650 return xhci_run_finished(xhci);
652 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
654 ret = xhci_try_enable_msi(hcd);
658 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
659 temp_64 &= ~ERST_PTR_MASK;
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
663 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
664 "// Set the interrupt modulation register");
665 temp = readl(&xhci->ir_set->irq_control);
666 temp &= ~ER_IRQ_INTERVAL_MASK;
667 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
668 writel(temp, &xhci->ir_set->irq_control);
670 /* Set the HCD state before we enable the irqs */
671 temp = readl(&xhci->op_regs->command);
673 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
674 "// Enable interrupts, cmd = 0x%x.", temp);
675 writel(temp, &xhci->op_regs->command);
677 temp = readl(&xhci->ir_set->irq_pending);
678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
679 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
680 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
681 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
683 if (xhci->quirks & XHCI_NEC_HOST) {
684 struct xhci_command *command;
686 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
690 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
691 TRB_TYPE(TRB_NEC_GET_FW));
693 xhci_free_command(xhci, command);
695 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
696 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
697 "Finished xhci_run for USB2 roothub");
701 xhci_debugfs_init(xhci);
705 EXPORT_SYMBOL_GPL(xhci_run);
710 * This function is called by the USB core when the HC driver is removed.
711 * Its opposite is xhci_run().
713 * Disable device contexts, disable IRQs, and quiesce the HC.
714 * Reset the HC, finish any completed transactions, and cleanup memory.
716 static void xhci_stop(struct usb_hcd *hcd)
719 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
721 mutex_lock(&xhci->mutex);
723 /* Only halt host and free memory after both hcds are removed */
724 if (!usb_hcd_is_primary_hcd(hcd)) {
725 mutex_unlock(&xhci->mutex);
731 spin_lock_irq(&xhci->lock);
732 xhci->xhc_state |= XHCI_STATE_HALTED;
733 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
736 spin_unlock_irq(&xhci->lock);
738 xhci_cleanup_msix(xhci);
740 /* Deleting Compliance Mode Recovery Timer */
741 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
742 (!(xhci_all_ports_seen_u0(xhci)))) {
743 del_timer_sync(&xhci->comp_mode_recovery_timer);
744 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
745 "%s: compliance mode recovery timer deleted",
749 if (xhci->quirks & XHCI_AMD_PLL_FIX)
752 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
753 "// Disabling event ring interrupts");
754 temp = readl(&xhci->op_regs->status);
755 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
756 temp = readl(&xhci->ir_set->irq_pending);
757 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
759 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
760 xhci_mem_cleanup(xhci);
761 xhci_debugfs_exit(xhci);
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_stop completed - status = %x",
764 readl(&xhci->op_regs->status));
765 mutex_unlock(&xhci->mutex);
769 * Shutdown HC (not bus-specific)
771 * This is called when the machine is rebooting or halting. We assume that the
772 * machine will be powered off, and the HC's internal state will be reset.
773 * Don't bother to free memory.
775 * This will only ever be called with the main usb_hcd (the USB3 roothub).
777 void xhci_shutdown(struct usb_hcd *hcd)
779 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
781 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
782 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
784 spin_lock_irq(&xhci->lock);
786 /* Workaround for spurious wakeups at shutdown with HSW */
787 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
789 spin_unlock_irq(&xhci->lock);
791 xhci_cleanup_msix(xhci);
793 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
794 "xhci_shutdown completed - status = %x",
795 readl(&xhci->op_regs->status));
797 EXPORT_SYMBOL_GPL(xhci_shutdown);
800 static void xhci_save_registers(struct xhci_hcd *xhci)
802 xhci->s3.command = readl(&xhci->op_regs->command);
803 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
804 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
805 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
806 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
807 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
808 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
809 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
810 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
813 static void xhci_restore_registers(struct xhci_hcd *xhci)
815 writel(xhci->s3.command, &xhci->op_regs->command);
816 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
817 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
818 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
819 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
820 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
821 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
822 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
823 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
826 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
830 /* step 2: initialize command ring buffer */
831 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
832 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
833 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
834 xhci->cmd_ring->dequeue) &
835 (u64) ~CMD_RING_RSVD_BITS) |
836 xhci->cmd_ring->cycle_state;
837 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
838 "// Setting command ring address to 0x%llx",
839 (long unsigned long) val_64);
840 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
844 * The whole command ring must be cleared to zero when we suspend the host.
846 * The host doesn't save the command ring pointer in the suspend well, so we
847 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
848 * aligned, because of the reserved bits in the command ring dequeue pointer
849 * register. Therefore, we can't just set the dequeue pointer back in the
850 * middle of the ring (TRBs are 16-byte aligned).
852 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
854 struct xhci_ring *ring;
855 struct xhci_segment *seg;
857 ring = xhci->cmd_ring;
861 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
862 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
863 cpu_to_le32(~TRB_CYCLE);
865 } while (seg != ring->deq_seg);
867 /* Reset the software enqueue and dequeue pointers */
868 ring->deq_seg = ring->first_seg;
869 ring->dequeue = ring->first_seg->trbs;
870 ring->enq_seg = ring->deq_seg;
871 ring->enqueue = ring->dequeue;
873 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
875 * Ring is now zeroed, so the HW should look for change of ownership
876 * when the cycle bit is set to 1.
878 ring->cycle_state = 1;
881 * Reset the hardware dequeue pointer.
882 * Yes, this will need to be re-written after resume, but we're paranoid
883 * and want to make sure the hardware doesn't access bogus memory
884 * because, say, the BIOS or an SMI started the host without changing
885 * the command ring pointers.
887 xhci_set_cmd_ring_deq(xhci);
891 * Disable port wake bits if do_wakeup is not set.
893 * Also clear a possible internal port wake state left hanging for ports that
894 * detected termination but never successfully enumerated (trained to 0U).
895 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
896 * at enumeration clears this wake, force one here as well for unconnected ports
899 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
900 struct xhci_hub *rhub,
907 spin_lock_irqsave(&xhci->lock, flags);
909 for (i = 0; i < rhub->num_ports; i++) {
910 portsc = readl(rhub->ports[i]->addr);
911 t1 = xhci_port_state_to_neutral(portsc);
914 /* clear wake bits if do_wake is not set */
916 t2 &= ~PORT_WAKE_BITS;
918 /* Don't touch csc bit if connected or connect change is set */
919 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
923 writel(t2, rhub->ports[i]->addr);
924 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
925 rhub->hcd->self.busnum, i + 1, portsc, t2);
928 spin_unlock_irqrestore(&xhci->lock, flags);
931 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
933 struct xhci_port **ports;
938 status = readl(&xhci->op_regs->status);
939 if (status & STS_EINT)
942 * Checking STS_EINT is not enough as there is a lag between a change
943 * bit being set and the Port Status Change Event that it generated
944 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
947 port_index = xhci->usb2_rhub.num_ports;
948 ports = xhci->usb2_rhub.ports;
949 while (port_index--) {
950 portsc = readl(ports[port_index]->addr);
951 if (portsc & PORT_CHANGE_MASK ||
952 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
955 port_index = xhci->usb3_rhub.num_ports;
956 ports = xhci->usb3_rhub.ports;
957 while (port_index--) {
958 portsc = readl(ports[port_index]->addr);
959 if (portsc & PORT_CHANGE_MASK ||
960 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
967 * Stop HC (not bus-specific)
969 * This is called when the machine transition into S3/S4 mode.
972 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
975 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
976 struct usb_hcd *hcd = xhci_to_hcd(xhci);
983 if (hcd->state != HC_STATE_SUSPENDED ||
984 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
987 /* Clear root port wake on bits if wakeup not allowed. */
988 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
989 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
991 if (!HCD_HW_ACCESSIBLE(hcd))
994 xhci_dbc_suspend(xhci);
996 /* Don't poll the roothubs on bus suspend. */
997 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
998 __func__, hcd->self.busnum);
999 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1000 del_timer_sync(&hcd->rh_timer);
1001 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1002 del_timer_sync(&xhci->shared_hcd->rh_timer);
1004 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1005 usleep_range(1000, 1500);
1007 spin_lock_irq(&xhci->lock);
1008 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1009 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1010 /* step 1: stop endpoint */
1011 /* skipped assuming that port suspend has done */
1013 /* step 2: clear Run/Stop bit */
1014 command = readl(&xhci->op_regs->command);
1015 command &= ~CMD_RUN;
1016 writel(command, &xhci->op_regs->command);
1018 /* Some chips from Fresco Logic need an extraordinary delay */
1019 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1021 if (xhci_handshake(&xhci->op_regs->status,
1022 STS_HALT, STS_HALT, delay)) {
1023 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1024 spin_unlock_irq(&xhci->lock);
1027 xhci_clear_command_ring(xhci);
1029 /* step 3: save registers */
1030 xhci_save_registers(xhci);
1032 /* step 4: set CSS flag */
1033 command = readl(&xhci->op_regs->command);
1035 writel(command, &xhci->op_regs->command);
1036 xhci->broken_suspend = 0;
1037 if (xhci_handshake(&xhci->op_regs->status,
1038 STS_SAVE, 0, 20 * 1000)) {
1040 * AMD SNPS xHC 3.0 occasionally does not clear the
1041 * SSS bit of USBSTS and when driver tries to poll
1042 * to see if the xHC clears BIT(8) which never happens
1043 * and driver assumes that controller is not responding
1044 * and times out. To workaround this, its good to check
1045 * if SRE and HCE bits are not set (as per xhci
1046 * Section 5.4.2) and bypass the timeout.
1048 res = readl(&xhci->op_regs->status);
1049 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1050 (((res & STS_SRE) == 0) &&
1051 ((res & STS_HCE) == 0))) {
1052 xhci->broken_suspend = 1;
1054 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1055 spin_unlock_irq(&xhci->lock);
1059 spin_unlock_irq(&xhci->lock);
1062 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1063 * is about to be suspended.
1065 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1066 (!(xhci_all_ports_seen_u0(xhci)))) {
1067 del_timer_sync(&xhci->comp_mode_recovery_timer);
1068 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1069 "%s: compliance mode recovery timer deleted",
1073 /* step 5: remove core well power */
1074 /* synchronize irq when using MSI-X */
1075 xhci_msix_sync_irqs(xhci);
1079 EXPORT_SYMBOL_GPL(xhci_suspend);
1082 * start xHC (not bus-specific)
1084 * This is called when the machine transition from S3/S4 mode.
1087 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1089 u32 command, temp = 0;
1090 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1091 struct usb_hcd *secondary_hcd;
1093 bool comp_timer_running = false;
1094 bool pending_portevent = false;
1099 /* Wait a bit if either of the roothubs need to settle from the
1100 * transition into bus suspend.
1103 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1104 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1107 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1108 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1110 spin_lock_irq(&xhci->lock);
1111 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1116 * Some controllers might lose power during suspend, so wait
1117 * for controller not ready bit to clear, just as in xHC init.
1119 retval = xhci_handshake(&xhci->op_regs->status,
1120 STS_CNR, 0, 10 * 1000 * 1000);
1122 xhci_warn(xhci, "Controller not ready at resume %d\n",
1124 spin_unlock_irq(&xhci->lock);
1127 /* step 1: restore register */
1128 xhci_restore_registers(xhci);
1129 /* step 2: initialize command ring buffer */
1130 xhci_set_cmd_ring_deq(xhci);
1131 /* step 3: restore state and start state*/
1132 /* step 3: set CRS flag */
1133 command = readl(&xhci->op_regs->command);
1135 writel(command, &xhci->op_regs->command);
1137 * Some controllers take up to 55+ ms to complete the controller
1138 * restore so setting the timeout to 100ms. Xhci specification
1139 * doesn't mention any timeout value.
1141 if (xhci_handshake(&xhci->op_regs->status,
1142 STS_RESTORE, 0, 100 * 1000)) {
1143 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1144 spin_unlock_irq(&xhci->lock);
1147 temp = readl(&xhci->op_regs->status);
1150 /* If restore operation fails, re-initialize the HC during resume */
1151 if ((temp & STS_SRE) || hibernated) {
1153 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1154 !(xhci_all_ports_seen_u0(xhci))) {
1155 del_timer_sync(&xhci->comp_mode_recovery_timer);
1156 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1157 "Compliance Mode Recovery Timer deleted!");
1160 /* Let the USB core know _both_ roothubs lost power. */
1161 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1162 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1164 xhci_dbg(xhci, "Stop HCD\n");
1166 xhci_zero_64b_regs(xhci);
1167 retval = xhci_reset(xhci);
1168 spin_unlock_irq(&xhci->lock);
1171 xhci_cleanup_msix(xhci);
1173 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1174 temp = readl(&xhci->op_regs->status);
1175 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1176 temp = readl(&xhci->ir_set->irq_pending);
1177 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1179 xhci_dbg(xhci, "cleaning up memory\n");
1180 xhci_mem_cleanup(xhci);
1181 xhci_debugfs_exit(xhci);
1182 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1183 readl(&xhci->op_regs->status));
1185 /* USB core calls the PCI reinit and start functions twice:
1186 * first with the primary HCD, and then with the secondary HCD.
1187 * If we don't do the same, the host will never be started.
1189 if (!usb_hcd_is_primary_hcd(hcd))
1190 secondary_hcd = hcd;
1192 secondary_hcd = xhci->shared_hcd;
1194 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1195 retval = xhci_init(hcd->primary_hcd);
1198 comp_timer_running = true;
1200 xhci_dbg(xhci, "Start the primary HCD\n");
1201 retval = xhci_run(hcd->primary_hcd);
1203 xhci_dbg(xhci, "Start the secondary HCD\n");
1204 retval = xhci_run(secondary_hcd);
1206 hcd->state = HC_STATE_SUSPENDED;
1207 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1211 /* step 4: set Run/Stop bit */
1212 command = readl(&xhci->op_regs->command);
1214 writel(command, &xhci->op_regs->command);
1215 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1218 /* step 5: walk topology and initialize portsc,
1219 * portpmsc and portli
1221 /* this is done in bus_resume */
1223 /* step 6: restart each of the previously
1224 * Running endpoints by ringing their doorbells
1227 spin_unlock_irq(&xhci->lock);
1229 xhci_dbc_resume(xhci);
1234 * Resume roothubs only if there are pending events.
1235 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1236 * the first wake signalling failed, give it that chance.
1238 pending_portevent = xhci_pending_portevent(xhci);
1239 if (!pending_portevent) {
1241 pending_portevent = xhci_pending_portevent(xhci);
1244 if (pending_portevent) {
1245 usb_hcd_resume_root_hub(xhci->shared_hcd);
1246 usb_hcd_resume_root_hub(hcd);
1250 * If system is subject to the Quirk, Compliance Mode Timer needs to
1251 * be re-initialized Always after a system resume. Ports are subject
1252 * to suffer the Compliance Mode issue again. It doesn't matter if
1253 * ports have entered previously to U0 before system's suspension.
1255 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1256 compliance_mode_recovery_timer_init(xhci);
1258 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1259 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1261 /* Re-enable port polling. */
1262 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1263 __func__, hcd->self.busnum);
1264 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1265 usb_hcd_poll_rh_status(xhci->shared_hcd);
1266 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1267 usb_hcd_poll_rh_status(hcd);
1271 EXPORT_SYMBOL_GPL(xhci_resume);
1272 #endif /* CONFIG_PM */
1274 /*-------------------------------------------------------------------------*/
1276 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1280 unsigned int buf_len;
1281 enum dma_data_direction dir;
1283 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1284 buf_len = urb->transfer_buffer_length;
1286 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1287 dev_to_node(hcd->self.sysdev));
1289 if (usb_urb_dir_out(urb))
1290 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1293 urb->transfer_buffer = temp;
1294 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1295 urb->transfer_buffer,
1296 urb->transfer_buffer_length,
1299 if (dma_mapping_error(hcd->self.sysdev,
1300 urb->transfer_dma)) {
1304 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1310 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1315 unsigned int len = 0;
1316 unsigned int trb_size;
1317 unsigned int max_pkt;
1318 struct scatterlist *sg;
1319 struct scatterlist *tail_sg;
1322 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1327 if (urb->dev->speed >= USB_SPEED_SUPER)
1328 trb_size = TRB_CACHE_SIZE_SS;
1330 trb_size = TRB_CACHE_SIZE_HS;
1332 if (urb->transfer_buffer_length != 0 &&
1333 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1334 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1335 len = len + sg->length;
1336 if (i > trb_size - 2) {
1337 len = len - tail_sg->length;
1338 if (len < max_pkt) {
1343 tail_sg = sg_next(tail_sg);
1350 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1353 unsigned int buf_len;
1354 enum dma_data_direction dir;
1356 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1358 buf_len = urb->transfer_buffer_length;
1360 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1361 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1362 dma_unmap_single(hcd->self.sysdev,
1364 urb->transfer_buffer_length,
1367 if (usb_urb_dir_in(urb)) {
1368 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1369 urb->transfer_buffer,
1372 if (len != buf_len) {
1373 xhci_dbg(hcd_to_xhci(hcd),
1374 "Copy from tmp buf to urb sg list failed\n");
1375 urb->actual_length = len;
1378 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1379 kfree(urb->transfer_buffer);
1380 urb->transfer_buffer = NULL;
1384 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1385 * we'll copy the actual data into the TRB address register. This is limited to
1386 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1387 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1389 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1392 struct xhci_hcd *xhci;
1394 xhci = hcd_to_xhci(hcd);
1396 if (xhci_urb_suitable_for_idt(urb))
1399 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1400 if (xhci_urb_temp_buffer_required(hcd, urb))
1401 return xhci_map_temp_buffer(hcd, urb);
1403 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1406 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1408 struct xhci_hcd *xhci;
1409 bool unmap_temp_buf = false;
1411 xhci = hcd_to_xhci(hcd);
1413 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1414 unmap_temp_buf = true;
1416 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1417 xhci_unmap_temp_buf(hcd, urb);
1419 usb_hcd_unmap_urb_for_dma(hcd, urb);
1423 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1424 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1425 * value to right shift 1 for the bitmask.
1427 * Index = (epnum * 2) + direction - 1,
1428 * where direction = 0 for OUT, 1 for IN.
1429 * For control endpoints, the IN index is used (OUT index is unused), so
1430 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1432 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1435 if (usb_endpoint_xfer_control(desc))
1436 index = (unsigned int) (usb_endpoint_num(desc)*2);
1438 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1439 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1442 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1444 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1445 * address from the XHCI endpoint index.
1447 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1449 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1450 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1451 return direction | number;
1454 /* Find the flag for this endpoint (for use in the control context). Use the
1455 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1458 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1460 return 1 << (xhci_get_endpoint_index(desc) + 1);
1463 /* Compute the last valid endpoint context index. Basically, this is the
1464 * endpoint index plus one. For slot contexts with more than valid endpoint,
1465 * we find the most significant bit set in the added contexts flags.
1466 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1467 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1469 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1471 return fls(added_ctxs) - 1;
1474 /* Returns 1 if the arguments are OK;
1475 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1477 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1478 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1480 struct xhci_hcd *xhci;
1481 struct xhci_virt_device *virt_dev;
1483 if (!hcd || (check_ep && !ep) || !udev) {
1484 pr_debug("xHCI %s called with invalid args\n", func);
1487 if (!udev->parent) {
1488 pr_debug("xHCI %s called for root hub\n", func);
1492 xhci = hcd_to_xhci(hcd);
1493 if (check_virt_dev) {
1494 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1495 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1500 virt_dev = xhci->devs[udev->slot_id];
1501 if (virt_dev->udev != udev) {
1502 xhci_dbg(xhci, "xHCI %s called with udev and "
1503 "virt_dev does not match\n", func);
1508 if (xhci->xhc_state & XHCI_STATE_HALTED)
1514 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1515 struct usb_device *udev, struct xhci_command *command,
1516 bool ctx_change, bool must_succeed);
1519 * Full speed devices may have a max packet size greater than 8 bytes, but the
1520 * USB core doesn't know that until it reads the first 8 bytes of the
1521 * descriptor. If the usb_device's max packet size changes after that point,
1522 * we need to issue an evaluate context command and wait on it.
1524 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1525 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1527 struct xhci_container_ctx *out_ctx;
1528 struct xhci_input_control_ctx *ctrl_ctx;
1529 struct xhci_ep_ctx *ep_ctx;
1530 struct xhci_command *command;
1531 int max_packet_size;
1532 int hw_max_packet_size;
1535 out_ctx = xhci->devs[slot_id]->out_ctx;
1536 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1537 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1538 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1539 if (hw_max_packet_size != max_packet_size) {
1540 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1541 "Max Packet Size for ep 0 changed.");
1542 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1543 "Max packet size in usb_device = %d",
1545 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1546 "Max packet size in xHCI HW = %d",
1547 hw_max_packet_size);
1548 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1549 "Issuing evaluate context command.");
1551 /* Set up the input context flags for the command */
1552 /* FIXME: This won't work if a non-default control endpoint
1553 * changes max packet sizes.
1556 command = xhci_alloc_command(xhci, true, mem_flags);
1560 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1561 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1563 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1566 goto command_cleanup;
1568 /* Set up the modified control endpoint 0 */
1569 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1570 xhci->devs[slot_id]->out_ctx, ep_index);
1572 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1573 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1574 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1575 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1577 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1578 ctrl_ctx->drop_flags = 0;
1580 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1583 /* Clean up the input context for later use by bandwidth
1586 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1588 kfree(command->completion);
1595 * non-error returns are a promise to giveback() the urb later
1596 * we drop ownership so next owner (or urb unlink) can get it
1598 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1600 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1601 unsigned long flags;
1603 unsigned int slot_id, ep_index;
1604 unsigned int *ep_state;
1605 struct urb_priv *urb_priv;
1608 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1609 true, true, __func__) <= 0)
1612 slot_id = urb->dev->slot_id;
1613 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1614 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1616 if (!HCD_HW_ACCESSIBLE(hcd))
1619 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1620 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1624 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1625 num_tds = urb->number_of_packets;
1626 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1627 urb->transfer_buffer_length > 0 &&
1628 urb->transfer_flags & URB_ZERO_PACKET &&
1629 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1634 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1638 urb_priv->num_tds = num_tds;
1639 urb_priv->num_tds_done = 0;
1640 urb->hcpriv = urb_priv;
1642 trace_xhci_urb_enqueue(urb);
1644 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1645 /* Check to see if the max packet size for the default control
1646 * endpoint changed during FS device enumeration
1648 if (urb->dev->speed == USB_SPEED_FULL) {
1649 ret = xhci_check_maxpacket(xhci, slot_id,
1650 ep_index, urb, mem_flags);
1652 xhci_urb_free_priv(urb_priv);
1659 spin_lock_irqsave(&xhci->lock, flags);
1661 if (xhci->xhc_state & XHCI_STATE_DYING) {
1662 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1663 urb->ep->desc.bEndpointAddress, urb);
1667 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1668 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1673 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1674 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1679 switch (usb_endpoint_type(&urb->ep->desc)) {
1681 case USB_ENDPOINT_XFER_CONTROL:
1682 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1685 case USB_ENDPOINT_XFER_BULK:
1686 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1689 case USB_ENDPOINT_XFER_INT:
1690 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1693 case USB_ENDPOINT_XFER_ISOC:
1694 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1700 xhci_urb_free_priv(urb_priv);
1703 spin_unlock_irqrestore(&xhci->lock, flags);
1708 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1709 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1710 * should pick up where it left off in the TD, unless a Set Transfer Ring
1711 * Dequeue Pointer is issued.
1713 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1714 * the ring. Since the ring is a contiguous structure, they can't be physically
1715 * removed. Instead, there are two options:
1717 * 1) If the HC is in the middle of processing the URB to be canceled, we
1718 * simply move the ring's dequeue pointer past those TRBs using the Set
1719 * Transfer Ring Dequeue Pointer command. This will be the common case,
1720 * when drivers timeout on the last submitted URB and attempt to cancel.
1722 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1723 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1724 * HC will need to invalidate the any TRBs it has cached after the stop
1725 * endpoint command, as noted in the xHCI 0.95 errata.
1727 * 3) The TD may have completed by the time the Stop Endpoint Command
1728 * completes, so software needs to handle that case too.
1730 * This function should protect against the TD enqueueing code ringing the
1731 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1732 * It also needs to account for multiple cancellations on happening at the same
1733 * time for the same endpoint.
1735 * Note that this function can be called in any context, or so says
1736 * usb_hcd_unlink_urb()
1738 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1740 unsigned long flags;
1743 struct xhci_hcd *xhci;
1744 struct urb_priv *urb_priv;
1746 unsigned int ep_index;
1747 struct xhci_ring *ep_ring;
1748 struct xhci_virt_ep *ep;
1749 struct xhci_command *command;
1750 struct xhci_virt_device *vdev;
1752 xhci = hcd_to_xhci(hcd);
1753 spin_lock_irqsave(&xhci->lock, flags);
1755 trace_xhci_urb_dequeue(urb);
1757 /* Make sure the URB hasn't completed or been unlinked already */
1758 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1762 /* give back URB now if we can't queue it for cancel */
1763 vdev = xhci->devs[urb->dev->slot_id];
1764 urb_priv = urb->hcpriv;
1765 if (!vdev || !urb_priv)
1768 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1769 ep = &vdev->eps[ep_index];
1770 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1771 if (!ep || !ep_ring)
1774 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1775 temp = readl(&xhci->op_regs->status);
1776 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1782 * check ring is not re-allocated since URB was enqueued. If it is, then
1783 * make sure none of the ring related pointers in this URB private data
1784 * are touched, such as td_list, otherwise we overwrite freed data
1786 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1787 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1788 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1789 td = &urb_priv->td[i];
1790 if (!list_empty(&td->cancelled_td_list))
1791 list_del_init(&td->cancelled_td_list);
1796 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1797 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1798 "HC halted, freeing TD manually.");
1799 for (i = urb_priv->num_tds_done;
1800 i < urb_priv->num_tds;
1802 td = &urb_priv->td[i];
1803 if (!list_empty(&td->td_list))
1804 list_del_init(&td->td_list);
1805 if (!list_empty(&td->cancelled_td_list))
1806 list_del_init(&td->cancelled_td_list);
1811 i = urb_priv->num_tds_done;
1812 if (i < urb_priv->num_tds)
1813 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1814 "Cancel URB %p, dev %s, ep 0x%x, "
1815 "starting at offset 0x%llx",
1816 urb, urb->dev->devpath,
1817 urb->ep->desc.bEndpointAddress,
1818 (unsigned long long) xhci_trb_virt_to_dma(
1819 urb_priv->td[i].start_seg,
1820 urb_priv->td[i].first_trb));
1822 for (; i < urb_priv->num_tds; i++) {
1823 td = &urb_priv->td[i];
1824 /* TD can already be on cancelled list if ep halted on it */
1825 if (list_empty(&td->cancelled_td_list)) {
1826 td->cancel_status = TD_DIRTY;
1827 list_add_tail(&td->cancelled_td_list,
1828 &ep->cancelled_td_list);
1832 /* Queue a stop endpoint command, but only if this is
1833 * the first cancellation to be handled.
1835 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1836 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1841 ep->ep_state |= EP_STOP_CMD_PENDING;
1842 ep->stop_cmd_timer.expires = jiffies +
1843 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1844 add_timer(&ep->stop_cmd_timer);
1845 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1847 xhci_ring_cmd_db(xhci);
1850 spin_unlock_irqrestore(&xhci->lock, flags);
1855 xhci_urb_free_priv(urb_priv);
1856 usb_hcd_unlink_urb_from_ep(hcd, urb);
1857 spin_unlock_irqrestore(&xhci->lock, flags);
1858 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1862 /* Drop an endpoint from a new bandwidth configuration for this device.
1863 * Only one call to this function is allowed per endpoint before
1864 * check_bandwidth() or reset_bandwidth() must be called.
1865 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1866 * add the endpoint to the schedule with possibly new parameters denoted by a
1867 * different endpoint descriptor in usb_host_endpoint.
1868 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1871 * The USB core will not allow URBs to be queued to an endpoint that is being
1872 * disabled, so there's no need for mutual exclusion to protect
1873 * the xhci->devs[slot_id] structure.
1875 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1876 struct usb_host_endpoint *ep)
1878 struct xhci_hcd *xhci;
1879 struct xhci_container_ctx *in_ctx, *out_ctx;
1880 struct xhci_input_control_ctx *ctrl_ctx;
1881 unsigned int ep_index;
1882 struct xhci_ep_ctx *ep_ctx;
1884 u32 new_add_flags, new_drop_flags;
1887 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1890 xhci = hcd_to_xhci(hcd);
1891 if (xhci->xhc_state & XHCI_STATE_DYING)
1894 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1895 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1896 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1897 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1898 __func__, drop_flag);
1902 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1903 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1904 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1906 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1911 ep_index = xhci_get_endpoint_index(&ep->desc);
1912 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1913 /* If the HC already knows the endpoint is disabled,
1914 * or the HCD has noted it is disabled, ignore this request
1916 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1917 le32_to_cpu(ctrl_ctx->drop_flags) &
1918 xhci_get_endpoint_flag(&ep->desc)) {
1919 /* Do not warn when called after a usb_device_reset */
1920 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1921 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1926 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1927 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1929 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1930 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1932 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1934 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1936 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1937 (unsigned int) ep->desc.bEndpointAddress,
1939 (unsigned int) new_drop_flags,
1940 (unsigned int) new_add_flags);
1943 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1945 /* Add an endpoint to a new possible bandwidth configuration for this device.
1946 * Only one call to this function is allowed per endpoint before
1947 * check_bandwidth() or reset_bandwidth() must be called.
1948 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1949 * add the endpoint to the schedule with possibly new parameters denoted by a
1950 * different endpoint descriptor in usb_host_endpoint.
1951 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1954 * The USB core will not allow URBs to be queued to an endpoint until the
1955 * configuration or alt setting is installed in the device, so there's no need
1956 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1958 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1959 struct usb_host_endpoint *ep)
1961 struct xhci_hcd *xhci;
1962 struct xhci_container_ctx *in_ctx;
1963 unsigned int ep_index;
1964 struct xhci_input_control_ctx *ctrl_ctx;
1965 struct xhci_ep_ctx *ep_ctx;
1967 u32 new_add_flags, new_drop_flags;
1968 struct xhci_virt_device *virt_dev;
1971 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1973 /* So we won't queue a reset ep command for a root hub */
1977 xhci = hcd_to_xhci(hcd);
1978 if (xhci->xhc_state & XHCI_STATE_DYING)
1981 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1982 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1983 /* FIXME when we have to issue an evaluate endpoint command to
1984 * deal with ep0 max packet size changing once we get the
1987 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1988 __func__, added_ctxs);
1992 virt_dev = xhci->devs[udev->slot_id];
1993 in_ctx = virt_dev->in_ctx;
1994 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1996 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2001 ep_index = xhci_get_endpoint_index(&ep->desc);
2002 /* If this endpoint is already in use, and the upper layers are trying
2003 * to add it again without dropping it, reject the addition.
2005 if (virt_dev->eps[ep_index].ring &&
2006 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2007 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2008 "without dropping it.\n",
2009 (unsigned int) ep->desc.bEndpointAddress);
2013 /* If the HCD has already noted the endpoint is enabled,
2014 * ignore this request.
2016 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2017 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2023 * Configuration and alternate setting changes must be done in
2024 * process context, not interrupt context (or so documenation
2025 * for usb_set_interface() and usb_set_configuration() claim).
2027 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2028 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2029 __func__, ep->desc.bEndpointAddress);
2033 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2034 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2036 /* If xhci_endpoint_disable() was called for this endpoint, but the
2037 * xHC hasn't been notified yet through the check_bandwidth() call,
2038 * this re-adds a new state for the endpoint from the new endpoint
2039 * descriptors. We must drop and re-add this endpoint, so we leave the
2042 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2044 /* Store the usb_device pointer for later use */
2047 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2048 trace_xhci_add_endpoint(ep_ctx);
2050 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2051 (unsigned int) ep->desc.bEndpointAddress,
2053 (unsigned int) new_drop_flags,
2054 (unsigned int) new_add_flags);
2057 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2059 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2061 struct xhci_input_control_ctx *ctrl_ctx;
2062 struct xhci_ep_ctx *ep_ctx;
2063 struct xhci_slot_ctx *slot_ctx;
2066 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2068 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2073 /* When a device's add flag and drop flag are zero, any subsequent
2074 * configure endpoint command will leave that endpoint's state
2075 * untouched. Make sure we don't leave any old state in the input
2076 * endpoint contexts.
2078 ctrl_ctx->drop_flags = 0;
2079 ctrl_ctx->add_flags = 0;
2080 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2081 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2082 /* Endpoint 0 is always valid */
2083 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2084 for (i = 1; i < 31; i++) {
2085 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2086 ep_ctx->ep_info = 0;
2087 ep_ctx->ep_info2 = 0;
2089 ep_ctx->tx_info = 0;
2093 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2094 struct usb_device *udev, u32 *cmd_status)
2098 switch (*cmd_status) {
2099 case COMP_COMMAND_ABORTED:
2100 case COMP_COMMAND_RING_STOPPED:
2101 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2104 case COMP_RESOURCE_ERROR:
2105 dev_warn(&udev->dev,
2106 "Not enough host controller resources for new device state.\n");
2108 /* FIXME: can we allocate more resources for the HC? */
2110 case COMP_BANDWIDTH_ERROR:
2111 case COMP_SECONDARY_BANDWIDTH_ERROR:
2112 dev_warn(&udev->dev,
2113 "Not enough bandwidth for new device state.\n");
2115 /* FIXME: can we go back to the old state? */
2117 case COMP_TRB_ERROR:
2118 /* the HCD set up something wrong */
2119 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2121 "and endpoint is not disabled.\n");
2124 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2125 dev_warn(&udev->dev,
2126 "ERROR: Incompatible device for endpoint configure command.\n");
2130 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2131 "Successful Endpoint Configure command");
2135 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2143 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2144 struct usb_device *udev, u32 *cmd_status)
2148 switch (*cmd_status) {
2149 case COMP_COMMAND_ABORTED:
2150 case COMP_COMMAND_RING_STOPPED:
2151 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2154 case COMP_PARAMETER_ERROR:
2155 dev_warn(&udev->dev,
2156 "WARN: xHCI driver setup invalid evaluate context command.\n");
2159 case COMP_SLOT_NOT_ENABLED_ERROR:
2160 dev_warn(&udev->dev,
2161 "WARN: slot not enabled for evaluate context command.\n");
2164 case COMP_CONTEXT_STATE_ERROR:
2165 dev_warn(&udev->dev,
2166 "WARN: invalid context state for evaluate context command.\n");
2169 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2170 dev_warn(&udev->dev,
2171 "ERROR: Incompatible device for evaluate context command.\n");
2174 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2175 /* Max Exit Latency too large error */
2176 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2180 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2181 "Successful evaluate context command");
2185 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2193 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2194 struct xhci_input_control_ctx *ctrl_ctx)
2196 u32 valid_add_flags;
2197 u32 valid_drop_flags;
2199 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2200 * (bit 1). The default control endpoint is added during the Address
2201 * Device command and is never removed until the slot is disabled.
2203 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2204 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2206 /* Use hweight32 to count the number of ones in the add flags, or
2207 * number of endpoints added. Don't count endpoints that are changed
2208 * (both added and dropped).
2210 return hweight32(valid_add_flags) -
2211 hweight32(valid_add_flags & valid_drop_flags);
2214 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2215 struct xhci_input_control_ctx *ctrl_ctx)
2217 u32 valid_add_flags;
2218 u32 valid_drop_flags;
2220 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2221 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2223 return hweight32(valid_drop_flags) -
2224 hweight32(valid_add_flags & valid_drop_flags);
2228 * We need to reserve the new number of endpoints before the configure endpoint
2229 * command completes. We can't subtract the dropped endpoints from the number
2230 * of active endpoints until the command completes because we can oversubscribe
2231 * the host in this case:
2233 * - the first configure endpoint command drops more endpoints than it adds
2234 * - a second configure endpoint command that adds more endpoints is queued
2235 * - the first configure endpoint command fails, so the config is unchanged
2236 * - the second command may succeed, even though there isn't enough resources
2238 * Must be called with xhci->lock held.
2240 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2241 struct xhci_input_control_ctx *ctrl_ctx)
2245 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2246 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2247 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2248 "Not enough ep ctxs: "
2249 "%u active, need to add %u, limit is %u.",
2250 xhci->num_active_eps, added_eps,
2251 xhci->limit_active_eps);
2254 xhci->num_active_eps += added_eps;
2255 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2256 "Adding %u ep ctxs, %u now active.", added_eps,
2257 xhci->num_active_eps);
2262 * The configure endpoint was failed by the xHC for some other reason, so we
2263 * need to revert the resources that failed configuration would have used.
2265 * Must be called with xhci->lock held.
2267 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2268 struct xhci_input_control_ctx *ctrl_ctx)
2272 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2273 xhci->num_active_eps -= num_failed_eps;
2274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2275 "Removing %u failed ep ctxs, %u now active.",
2277 xhci->num_active_eps);
2281 * Now that the command has completed, clean up the active endpoint count by
2282 * subtracting out the endpoints that were dropped (but not changed).
2284 * Must be called with xhci->lock held.
2286 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2287 struct xhci_input_control_ctx *ctrl_ctx)
2289 u32 num_dropped_eps;
2291 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2292 xhci->num_active_eps -= num_dropped_eps;
2293 if (num_dropped_eps)
2294 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2295 "Removing %u dropped ep ctxs, %u now active.",
2297 xhci->num_active_eps);
2300 static unsigned int xhci_get_block_size(struct usb_device *udev)
2302 switch (udev->speed) {
2304 case USB_SPEED_FULL:
2306 case USB_SPEED_HIGH:
2308 case USB_SPEED_SUPER:
2309 case USB_SPEED_SUPER_PLUS:
2311 case USB_SPEED_UNKNOWN:
2312 case USB_SPEED_WIRELESS:
2314 /* Should never happen */
2320 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2322 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2324 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2329 /* If we are changing a LS/FS device under a HS hub,
2330 * make sure (if we are activating a new TT) that the HS bus has enough
2331 * bandwidth for this new TT.
2333 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2334 struct xhci_virt_device *virt_dev,
2337 struct xhci_interval_bw_table *bw_table;
2338 struct xhci_tt_bw_info *tt_info;
2340 /* Find the bandwidth table for the root port this TT is attached to. */
2341 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2342 tt_info = virt_dev->tt_info;
2343 /* If this TT already had active endpoints, the bandwidth for this TT
2344 * has already been added. Removing all periodic endpoints (and thus
2345 * making the TT enactive) will only decrease the bandwidth used.
2349 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2350 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2354 /* Not sure why we would have no new active endpoints...
2356 * Maybe because of an Evaluate Context change for a hub update or a
2357 * control endpoint 0 max packet size change?
2358 * FIXME: skip the bandwidth calculation in that case.
2363 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2364 struct xhci_virt_device *virt_dev)
2366 unsigned int bw_reserved;
2368 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2369 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2372 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2373 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2380 * This algorithm is a very conservative estimate of the worst-case scheduling
2381 * scenario for any one interval. The hardware dynamically schedules the
2382 * packets, so we can't tell which microframe could be the limiting factor in
2383 * the bandwidth scheduling. This only takes into account periodic endpoints.
2385 * Obviously, we can't solve an NP complete problem to find the minimum worst
2386 * case scenario. Instead, we come up with an estimate that is no less than
2387 * the worst case bandwidth used for any one microframe, but may be an
2390 * We walk the requirements for each endpoint by interval, starting with the
2391 * smallest interval, and place packets in the schedule where there is only one
2392 * possible way to schedule packets for that interval. In order to simplify
2393 * this algorithm, we record the largest max packet size for each interval, and
2394 * assume all packets will be that size.
2396 * For interval 0, we obviously must schedule all packets for each interval.
2397 * The bandwidth for interval 0 is just the amount of data to be transmitted
2398 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2399 * the number of packets).
2401 * For interval 1, we have two possible microframes to schedule those packets
2402 * in. For this algorithm, if we can schedule the same number of packets for
2403 * each possible scheduling opportunity (each microframe), we will do so. The
2404 * remaining number of packets will be saved to be transmitted in the gaps in
2405 * the next interval's scheduling sequence.
2407 * As we move those remaining packets to be scheduled with interval 2 packets,
2408 * we have to double the number of remaining packets to transmit. This is
2409 * because the intervals are actually powers of 2, and we would be transmitting
2410 * the previous interval's packets twice in this interval. We also have to be
2411 * sure that when we look at the largest max packet size for this interval, we
2412 * also look at the largest max packet size for the remaining packets and take
2413 * the greater of the two.
2415 * The algorithm continues to evenly distribute packets in each scheduling
2416 * opportunity, and push the remaining packets out, until we get to the last
2417 * interval. Then those packets and their associated overhead are just added
2418 * to the bandwidth used.
2420 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2421 struct xhci_virt_device *virt_dev,
2424 unsigned int bw_reserved;
2425 unsigned int max_bandwidth;
2426 unsigned int bw_used;
2427 unsigned int block_size;
2428 struct xhci_interval_bw_table *bw_table;
2429 unsigned int packet_size = 0;
2430 unsigned int overhead = 0;
2431 unsigned int packets_transmitted = 0;
2432 unsigned int packets_remaining = 0;
2435 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2436 return xhci_check_ss_bw(xhci, virt_dev);
2438 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2439 max_bandwidth = HS_BW_LIMIT;
2440 /* Convert percent of bus BW reserved to blocks reserved */
2441 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2443 max_bandwidth = FS_BW_LIMIT;
2444 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2447 bw_table = virt_dev->bw_table;
2448 /* We need to translate the max packet size and max ESIT payloads into
2449 * the units the hardware uses.
2451 block_size = xhci_get_block_size(virt_dev->udev);
2453 /* If we are manipulating a LS/FS device under a HS hub, double check
2454 * that the HS bus has enough bandwidth if we are activing a new TT.
2456 if (virt_dev->tt_info) {
2457 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2458 "Recalculating BW for rootport %u",
2459 virt_dev->real_port);
2460 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2461 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2462 "newly activated TT.\n");
2465 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2466 "Recalculating BW for TT slot %u port %u",
2467 virt_dev->tt_info->slot_id,
2468 virt_dev->tt_info->ttport);
2470 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2471 "Recalculating BW for rootport %u",
2472 virt_dev->real_port);
2475 /* Add in how much bandwidth will be used for interval zero, or the
2476 * rounded max ESIT payload + number of packets * largest overhead.
2478 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2479 bw_table->interval_bw[0].num_packets *
2480 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2482 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2483 unsigned int bw_added;
2484 unsigned int largest_mps;
2485 unsigned int interval_overhead;
2488 * How many packets could we transmit in this interval?
2489 * If packets didn't fit in the previous interval, we will need
2490 * to transmit that many packets twice within this interval.
2492 packets_remaining = 2 * packets_remaining +
2493 bw_table->interval_bw[i].num_packets;
2495 /* Find the largest max packet size of this or the previous
2498 if (list_empty(&bw_table->interval_bw[i].endpoints))
2501 struct xhci_virt_ep *virt_ep;
2502 struct list_head *ep_entry;
2504 ep_entry = bw_table->interval_bw[i].endpoints.next;
2505 virt_ep = list_entry(ep_entry,
2506 struct xhci_virt_ep, bw_endpoint_list);
2507 /* Convert to blocks, rounding up */
2508 largest_mps = DIV_ROUND_UP(
2509 virt_ep->bw_info.max_packet_size,
2512 if (largest_mps > packet_size)
2513 packet_size = largest_mps;
2515 /* Use the larger overhead of this or the previous interval. */
2516 interval_overhead = xhci_get_largest_overhead(
2517 &bw_table->interval_bw[i]);
2518 if (interval_overhead > overhead)
2519 overhead = interval_overhead;
2521 /* How many packets can we evenly distribute across
2522 * (1 << (i + 1)) possible scheduling opportunities?
2524 packets_transmitted = packets_remaining >> (i + 1);
2526 /* Add in the bandwidth used for those scheduled packets */
2527 bw_added = packets_transmitted * (overhead + packet_size);
2529 /* How many packets do we have remaining to transmit? */
2530 packets_remaining = packets_remaining % (1 << (i + 1));
2532 /* What largest max packet size should those packets have? */
2533 /* If we've transmitted all packets, don't carry over the
2534 * largest packet size.
2536 if (packets_remaining == 0) {
2539 } else if (packets_transmitted > 0) {
2540 /* Otherwise if we do have remaining packets, and we've
2541 * scheduled some packets in this interval, take the
2542 * largest max packet size from endpoints with this
2545 packet_size = largest_mps;
2546 overhead = interval_overhead;
2548 /* Otherwise carry over packet_size and overhead from the last
2549 * time we had a remainder.
2551 bw_used += bw_added;
2552 if (bw_used > max_bandwidth) {
2553 xhci_warn(xhci, "Not enough bandwidth. "
2554 "Proposed: %u, Max: %u\n",
2555 bw_used, max_bandwidth);
2560 * Ok, we know we have some packets left over after even-handedly
2561 * scheduling interval 15. We don't know which microframes they will
2562 * fit into, so we over-schedule and say they will be scheduled every
2565 if (packets_remaining > 0)
2566 bw_used += overhead + packet_size;
2568 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2569 unsigned int port_index = virt_dev->real_port - 1;
2571 /* OK, we're manipulating a HS device attached to a
2572 * root port bandwidth domain. Include the number of active TTs
2573 * in the bandwidth used.
2575 bw_used += TT_HS_OVERHEAD *
2576 xhci->rh_bw[port_index].num_active_tts;
2579 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2580 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2581 "Available: %u " "percent",
2582 bw_used, max_bandwidth, bw_reserved,
2583 (max_bandwidth - bw_used - bw_reserved) * 100 /
2586 bw_used += bw_reserved;
2587 if (bw_used > max_bandwidth) {
2588 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2589 bw_used, max_bandwidth);
2593 bw_table->bw_used = bw_used;
2597 static bool xhci_is_async_ep(unsigned int ep_type)
2599 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2600 ep_type != ISOC_IN_EP &&
2601 ep_type != INT_IN_EP);
2604 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2606 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2609 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2611 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2613 if (ep_bw->ep_interval == 0)
2614 return SS_OVERHEAD_BURST +
2615 (ep_bw->mult * ep_bw->num_packets *
2616 (SS_OVERHEAD + mps));
2617 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2618 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2619 1 << ep_bw->ep_interval);
2623 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2624 struct xhci_bw_info *ep_bw,
2625 struct xhci_interval_bw_table *bw_table,
2626 struct usb_device *udev,
2627 struct xhci_virt_ep *virt_ep,
2628 struct xhci_tt_bw_info *tt_info)
2630 struct xhci_interval_bw *interval_bw;
2631 int normalized_interval;
2633 if (xhci_is_async_ep(ep_bw->type))
2636 if (udev->speed >= USB_SPEED_SUPER) {
2637 if (xhci_is_sync_in_ep(ep_bw->type))
2638 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2639 xhci_get_ss_bw_consumed(ep_bw);
2641 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2642 xhci_get_ss_bw_consumed(ep_bw);
2646 /* SuperSpeed endpoints never get added to intervals in the table, so
2647 * this check is only valid for HS/FS/LS devices.
2649 if (list_empty(&virt_ep->bw_endpoint_list))
2651 /* For LS/FS devices, we need to translate the interval expressed in
2652 * microframes to frames.
2654 if (udev->speed == USB_SPEED_HIGH)
2655 normalized_interval = ep_bw->ep_interval;
2657 normalized_interval = ep_bw->ep_interval - 3;
2659 if (normalized_interval == 0)
2660 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2661 interval_bw = &bw_table->interval_bw[normalized_interval];
2662 interval_bw->num_packets -= ep_bw->num_packets;
2663 switch (udev->speed) {
2665 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2667 case USB_SPEED_FULL:
2668 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2670 case USB_SPEED_HIGH:
2671 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2673 case USB_SPEED_SUPER:
2674 case USB_SPEED_SUPER_PLUS:
2675 case USB_SPEED_UNKNOWN:
2676 case USB_SPEED_WIRELESS:
2677 /* Should never happen because only LS/FS/HS endpoints will get
2678 * added to the endpoint list.
2683 tt_info->active_eps -= 1;
2684 list_del_init(&virt_ep->bw_endpoint_list);
2687 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2688 struct xhci_bw_info *ep_bw,
2689 struct xhci_interval_bw_table *bw_table,
2690 struct usb_device *udev,
2691 struct xhci_virt_ep *virt_ep,
2692 struct xhci_tt_bw_info *tt_info)
2694 struct xhci_interval_bw *interval_bw;
2695 struct xhci_virt_ep *smaller_ep;
2696 int normalized_interval;
2698 if (xhci_is_async_ep(ep_bw->type))
2701 if (udev->speed == USB_SPEED_SUPER) {
2702 if (xhci_is_sync_in_ep(ep_bw->type))
2703 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2704 xhci_get_ss_bw_consumed(ep_bw);
2706 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2707 xhci_get_ss_bw_consumed(ep_bw);
2711 /* For LS/FS devices, we need to translate the interval expressed in
2712 * microframes to frames.
2714 if (udev->speed == USB_SPEED_HIGH)
2715 normalized_interval = ep_bw->ep_interval;
2717 normalized_interval = ep_bw->ep_interval - 3;
2719 if (normalized_interval == 0)
2720 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2721 interval_bw = &bw_table->interval_bw[normalized_interval];
2722 interval_bw->num_packets += ep_bw->num_packets;
2723 switch (udev->speed) {
2725 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2727 case USB_SPEED_FULL:
2728 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2730 case USB_SPEED_HIGH:
2731 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2733 case USB_SPEED_SUPER:
2734 case USB_SPEED_SUPER_PLUS:
2735 case USB_SPEED_UNKNOWN:
2736 case USB_SPEED_WIRELESS:
2737 /* Should never happen because only LS/FS/HS endpoints will get
2738 * added to the endpoint list.
2744 tt_info->active_eps += 1;
2745 /* Insert the endpoint into the list, largest max packet size first. */
2746 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2748 if (ep_bw->max_packet_size >=
2749 smaller_ep->bw_info.max_packet_size) {
2750 /* Add the new ep before the smaller endpoint */
2751 list_add_tail(&virt_ep->bw_endpoint_list,
2752 &smaller_ep->bw_endpoint_list);
2756 /* Add the new endpoint at the end of the list. */
2757 list_add_tail(&virt_ep->bw_endpoint_list,
2758 &interval_bw->endpoints);
2761 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2762 struct xhci_virt_device *virt_dev,
2765 struct xhci_root_port_bw_info *rh_bw_info;
2766 if (!virt_dev->tt_info)
2769 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2770 if (old_active_eps == 0 &&
2771 virt_dev->tt_info->active_eps != 0) {
2772 rh_bw_info->num_active_tts += 1;
2773 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2774 } else if (old_active_eps != 0 &&
2775 virt_dev->tt_info->active_eps == 0) {
2776 rh_bw_info->num_active_tts -= 1;
2777 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2781 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2782 struct xhci_virt_device *virt_dev,
2783 struct xhci_container_ctx *in_ctx)
2785 struct xhci_bw_info ep_bw_info[31];
2787 struct xhci_input_control_ctx *ctrl_ctx;
2788 int old_active_eps = 0;
2790 if (virt_dev->tt_info)
2791 old_active_eps = virt_dev->tt_info->active_eps;
2793 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2795 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2800 for (i = 0; i < 31; i++) {
2801 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2804 /* Make a copy of the BW info in case we need to revert this */
2805 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2806 sizeof(ep_bw_info[i]));
2807 /* Drop the endpoint from the interval table if the endpoint is
2808 * being dropped or changed.
2810 if (EP_IS_DROPPED(ctrl_ctx, i))
2811 xhci_drop_ep_from_interval_table(xhci,
2812 &virt_dev->eps[i].bw_info,
2818 /* Overwrite the information stored in the endpoints' bw_info */
2819 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2820 for (i = 0; i < 31; i++) {
2821 /* Add any changed or added endpoints to the interval table */
2822 if (EP_IS_ADDED(ctrl_ctx, i))
2823 xhci_add_ep_to_interval_table(xhci,
2824 &virt_dev->eps[i].bw_info,
2831 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2832 /* Ok, this fits in the bandwidth we have.
2833 * Update the number of active TTs.
2835 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2839 /* We don't have enough bandwidth for this, revert the stored info. */
2840 for (i = 0; i < 31; i++) {
2841 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2844 /* Drop the new copies of any added or changed endpoints from
2845 * the interval table.
2847 if (EP_IS_ADDED(ctrl_ctx, i)) {
2848 xhci_drop_ep_from_interval_table(xhci,
2849 &virt_dev->eps[i].bw_info,
2855 /* Revert the endpoint back to its old information */
2856 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2857 sizeof(ep_bw_info[i]));
2858 /* Add any changed or dropped endpoints back into the table */
2859 if (EP_IS_DROPPED(ctrl_ctx, i))
2860 xhci_add_ep_to_interval_table(xhci,
2861 &virt_dev->eps[i].bw_info,
2871 /* Issue a configure endpoint command or evaluate context command
2872 * and wait for it to finish.
2874 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2875 struct usb_device *udev,
2876 struct xhci_command *command,
2877 bool ctx_change, bool must_succeed)
2880 unsigned long flags;
2881 struct xhci_input_control_ctx *ctrl_ctx;
2882 struct xhci_virt_device *virt_dev;
2883 struct xhci_slot_ctx *slot_ctx;
2888 spin_lock_irqsave(&xhci->lock, flags);
2890 if (xhci->xhc_state & XHCI_STATE_DYING) {
2891 spin_unlock_irqrestore(&xhci->lock, flags);
2895 virt_dev = xhci->devs[udev->slot_id];
2897 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2899 spin_unlock_irqrestore(&xhci->lock, flags);
2900 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2905 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2906 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2907 spin_unlock_irqrestore(&xhci->lock, flags);
2908 xhci_warn(xhci, "Not enough host resources, "
2909 "active endpoint contexts = %u\n",
2910 xhci->num_active_eps);
2913 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2914 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2915 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2916 xhci_free_host_resources(xhci, ctrl_ctx);
2917 spin_unlock_irqrestore(&xhci->lock, flags);
2918 xhci_warn(xhci, "Not enough bandwidth\n");
2922 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2924 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2925 trace_xhci_configure_endpoint(slot_ctx);
2928 ret = xhci_queue_configure_endpoint(xhci, command,
2929 command->in_ctx->dma,
2930 udev->slot_id, must_succeed);
2932 ret = xhci_queue_evaluate_context(xhci, command,
2933 command->in_ctx->dma,
2934 udev->slot_id, must_succeed);
2936 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2937 xhci_free_host_resources(xhci, ctrl_ctx);
2938 spin_unlock_irqrestore(&xhci->lock, flags);
2939 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2940 "FIXME allocate a new ring segment");
2943 xhci_ring_cmd_db(xhci);
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2946 /* Wait for the configure endpoint command to complete */
2947 wait_for_completion(command->completion);
2950 ret = xhci_configure_endpoint_result(xhci, udev,
2953 ret = xhci_evaluate_context_result(xhci, udev,
2956 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2957 spin_lock_irqsave(&xhci->lock, flags);
2958 /* If the command failed, remove the reserved resources.
2959 * Otherwise, clean up the estimate to include dropped eps.
2962 xhci_free_host_resources(xhci, ctrl_ctx);
2964 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2965 spin_unlock_irqrestore(&xhci->lock, flags);
2970 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2971 struct xhci_virt_device *vdev, int i)
2973 struct xhci_virt_ep *ep = &vdev->eps[i];
2975 if (ep->ep_state & EP_HAS_STREAMS) {
2976 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2977 xhci_get_endpoint_address(i));
2978 xhci_free_stream_info(xhci, ep->stream_info);
2979 ep->stream_info = NULL;
2980 ep->ep_state &= ~EP_HAS_STREAMS;
2984 /* Called after one or more calls to xhci_add_endpoint() or
2985 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2986 * to call xhci_reset_bandwidth().
2988 * Since we are in the middle of changing either configuration or
2989 * installing a new alt setting, the USB core won't allow URBs to be
2990 * enqueued for any endpoint on the old config or interface. Nothing
2991 * else should be touching the xhci->devs[slot_id] structure, so we
2992 * don't need to take the xhci->lock for manipulating that.
2994 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2998 struct xhci_hcd *xhci;
2999 struct xhci_virt_device *virt_dev;
3000 struct xhci_input_control_ctx *ctrl_ctx;
3001 struct xhci_slot_ctx *slot_ctx;
3002 struct xhci_command *command;
3004 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3007 xhci = hcd_to_xhci(hcd);
3008 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3009 (xhci->xhc_state & XHCI_STATE_REMOVING))
3012 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3013 virt_dev = xhci->devs[udev->slot_id];
3015 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3019 command->in_ctx = virt_dev->in_ctx;
3021 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3022 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3024 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3027 goto command_cleanup;
3029 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3030 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3031 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3033 /* Don't issue the command if there's no endpoints to update. */
3034 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3035 ctrl_ctx->drop_flags == 0) {
3037 goto command_cleanup;
3039 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3040 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3041 for (i = 31; i >= 1; i--) {
3042 __le32 le32 = cpu_to_le32(BIT(i));
3044 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3045 || (ctrl_ctx->add_flags & le32) || i == 1) {
3046 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3047 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3052 ret = xhci_configure_endpoint(xhci, udev, command,
3055 /* Callee should call reset_bandwidth() */
3056 goto command_cleanup;
3058 /* Free any rings that were dropped, but not changed. */
3059 for (i = 1; i < 31; i++) {
3060 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3061 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3062 xhci_free_endpoint_ring(xhci, virt_dev, i);
3063 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3066 xhci_zero_in_ctx(xhci, virt_dev);
3068 * Install any rings for completely new endpoints or changed endpoints,
3069 * and free any old rings from changed endpoints.
3071 for (i = 1; i < 31; i++) {
3072 if (!virt_dev->eps[i].new_ring)
3074 /* Only free the old ring if it exists.
3075 * It may not if this is the first add of an endpoint.
3077 if (virt_dev->eps[i].ring) {
3078 xhci_free_endpoint_ring(xhci, virt_dev, i);
3080 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3081 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3082 virt_dev->eps[i].new_ring = NULL;
3083 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3086 kfree(command->completion);
3091 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3093 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3095 struct xhci_hcd *xhci;
3096 struct xhci_virt_device *virt_dev;
3099 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3102 xhci = hcd_to_xhci(hcd);
3104 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3105 virt_dev = xhci->devs[udev->slot_id];
3106 /* Free any rings allocated for added endpoints */
3107 for (i = 0; i < 31; i++) {
3108 if (virt_dev->eps[i].new_ring) {
3109 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3110 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3111 virt_dev->eps[i].new_ring = NULL;
3114 xhci_zero_in_ctx(xhci, virt_dev);
3116 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3118 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3119 struct xhci_container_ctx *in_ctx,
3120 struct xhci_container_ctx *out_ctx,
3121 struct xhci_input_control_ctx *ctrl_ctx,
3122 u32 add_flags, u32 drop_flags)
3124 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3125 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3126 xhci_slot_copy(xhci, in_ctx, out_ctx);
3127 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3130 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3131 struct usb_host_endpoint *host_ep)
3133 struct xhci_hcd *xhci;
3134 struct xhci_virt_device *vdev;
3135 struct xhci_virt_ep *ep;
3136 struct usb_device *udev;
3137 unsigned long flags;
3138 unsigned int ep_index;
3140 xhci = hcd_to_xhci(hcd);
3142 spin_lock_irqsave(&xhci->lock, flags);
3144 udev = (struct usb_device *)host_ep->hcpriv;
3145 if (!udev || !udev->slot_id)
3148 vdev = xhci->devs[udev->slot_id];
3152 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3153 ep = &vdev->eps[ep_index];
3157 /* wait for hub_tt_work to finish clearing hub TT */
3158 if (ep->ep_state & EP_CLEARING_TT) {
3159 spin_unlock_irqrestore(&xhci->lock, flags);
3160 schedule_timeout_uninterruptible(1);
3165 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3168 host_ep->hcpriv = NULL;
3169 spin_unlock_irqrestore(&xhci->lock, flags);
3173 * Called after usb core issues a clear halt control message.
3174 * The host side of the halt should already be cleared by a reset endpoint
3175 * command issued when the STALL event was received.
3177 * The reset endpoint command may only be issued to endpoints in the halted
3178 * state. For software that wishes to reset the data toggle or sequence number
3179 * of an endpoint that isn't in the halted state this function will issue a
3180 * configure endpoint command with the Drop and Add bits set for the target
3181 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3184 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3185 struct usb_host_endpoint *host_ep)
3187 struct xhci_hcd *xhci;
3188 struct usb_device *udev;
3189 struct xhci_virt_device *vdev;
3190 struct xhci_virt_ep *ep;
3191 struct xhci_input_control_ctx *ctrl_ctx;
3192 struct xhci_command *stop_cmd, *cfg_cmd;
3193 unsigned int ep_index;
3194 unsigned long flags;
3198 xhci = hcd_to_xhci(hcd);
3199 if (!host_ep->hcpriv)
3201 udev = (struct usb_device *) host_ep->hcpriv;
3202 vdev = xhci->devs[udev->slot_id];
3205 * vdev may be lost due to xHC restore error and re-initialization
3206 * during S3/S4 resume. A new vdev will be allocated later by
3207 * xhci_discover_or_reset_device()
3209 if (!udev->slot_id || !vdev)
3211 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3212 ep = &vdev->eps[ep_index];
3216 /* Bail out if toggle is already being cleared by a endpoint reset */
3217 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3218 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3221 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3222 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3223 usb_endpoint_xfer_isoc(&host_ep->desc))
3226 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3228 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3231 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3235 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3239 spin_lock_irqsave(&xhci->lock, flags);
3241 /* block queuing new trbs and ringing ep doorbell */
3242 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3245 * Make sure endpoint ring is empty before resetting the toggle/seq.
3246 * Driver is required to synchronously cancel all transfer request.
3247 * Stop the endpoint to force xHC to update the output context
3250 if (!list_empty(&ep->ring->td_list)) {
3251 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3252 spin_unlock_irqrestore(&xhci->lock, flags);
3253 xhci_free_command(xhci, cfg_cmd);
3257 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3260 spin_unlock_irqrestore(&xhci->lock, flags);
3261 xhci_free_command(xhci, cfg_cmd);
3262 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3267 xhci_ring_cmd_db(xhci);
3268 spin_unlock_irqrestore(&xhci->lock, flags);
3270 wait_for_completion(stop_cmd->completion);
3272 spin_lock_irqsave(&xhci->lock, flags);
3274 /* config ep command clears toggle if add and drop ep flags are set */
3275 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3277 spin_unlock_irqrestore(&xhci->lock, flags);
3278 xhci_free_command(xhci, cfg_cmd);
3279 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3284 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3285 ctrl_ctx, ep_flag, ep_flag);
3286 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3288 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3289 udev->slot_id, false);
3291 spin_unlock_irqrestore(&xhci->lock, flags);
3292 xhci_free_command(xhci, cfg_cmd);
3293 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3298 xhci_ring_cmd_db(xhci);
3299 spin_unlock_irqrestore(&xhci->lock, flags);
3301 wait_for_completion(cfg_cmd->completion);
3303 xhci_free_command(xhci, cfg_cmd);
3305 xhci_free_command(xhci, stop_cmd);
3306 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3307 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3310 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3311 struct usb_device *udev, struct usb_host_endpoint *ep,
3312 unsigned int slot_id)
3315 unsigned int ep_index;
3316 unsigned int ep_state;
3320 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3323 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3324 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3325 " descriptor for ep 0x%x does not support streams\n",
3326 ep->desc.bEndpointAddress);
3330 ep_index = xhci_get_endpoint_index(&ep->desc);
3331 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3332 if (ep_state & EP_HAS_STREAMS ||
3333 ep_state & EP_GETTING_STREAMS) {
3334 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3335 "already has streams set up.\n",
3336 ep->desc.bEndpointAddress);
3337 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3338 "dynamic stream context array reallocation.\n");
3341 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3342 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3343 "endpoint 0x%x; URBs are pending.\n",
3344 ep->desc.bEndpointAddress);
3350 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3351 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3353 unsigned int max_streams;
3355 /* The stream context array size must be a power of two */
3356 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3358 * Find out how many primary stream array entries the host controller
3359 * supports. Later we may use secondary stream arrays (similar to 2nd
3360 * level page entries), but that's an optional feature for xHCI host
3361 * controllers. xHCs must support at least 4 stream IDs.
3363 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3364 if (*num_stream_ctxs > max_streams) {
3365 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3367 *num_stream_ctxs = max_streams;
3368 *num_streams = max_streams;
3372 /* Returns an error code if one of the endpoint already has streams.
3373 * This does not change any data structures, it only checks and gathers
3376 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3377 struct usb_device *udev,
3378 struct usb_host_endpoint **eps, unsigned int num_eps,
3379 unsigned int *num_streams, u32 *changed_ep_bitmask)
3381 unsigned int max_streams;
3382 unsigned int endpoint_flag;
3386 for (i = 0; i < num_eps; i++) {
3387 ret = xhci_check_streams_endpoint(xhci, udev,
3388 eps[i], udev->slot_id);
3392 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3393 if (max_streams < (*num_streams - 1)) {
3394 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3395 eps[i]->desc.bEndpointAddress,
3397 *num_streams = max_streams+1;
3400 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3401 if (*changed_ep_bitmask & endpoint_flag)
3403 *changed_ep_bitmask |= endpoint_flag;
3408 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3409 struct usb_device *udev,
3410 struct usb_host_endpoint **eps, unsigned int num_eps)
3412 u32 changed_ep_bitmask = 0;
3413 unsigned int slot_id;
3414 unsigned int ep_index;
3415 unsigned int ep_state;
3418 slot_id = udev->slot_id;
3419 if (!xhci->devs[slot_id])
3422 for (i = 0; i < num_eps; i++) {
3423 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3424 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3425 /* Are streams already being freed for the endpoint? */
3426 if (ep_state & EP_GETTING_NO_STREAMS) {
3427 xhci_warn(xhci, "WARN Can't disable streams for "
3429 "streams are being disabled already\n",
3430 eps[i]->desc.bEndpointAddress);
3433 /* Are there actually any streams to free? */
3434 if (!(ep_state & EP_HAS_STREAMS) &&
3435 !(ep_state & EP_GETTING_STREAMS)) {
3436 xhci_warn(xhci, "WARN Can't disable streams for "
3438 "streams are already disabled!\n",
3439 eps[i]->desc.bEndpointAddress);
3440 xhci_warn(xhci, "WARN xhci_free_streams() called "
3441 "with non-streams endpoint\n");
3444 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3446 return changed_ep_bitmask;
3450 * The USB device drivers use this function (through the HCD interface in USB
3451 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3452 * coordinate mass storage command queueing across multiple endpoints (basically
3453 * a stream ID == a task ID).
3455 * Setting up streams involves allocating the same size stream context array
3456 * for each endpoint and issuing a configure endpoint command for all endpoints.
3458 * Don't allow the call to succeed if one endpoint only supports one stream
3459 * (which means it doesn't support streams at all).
3461 * Drivers may get less stream IDs than they asked for, if the host controller
3462 * hardware or endpoints claim they can't support the number of requested
3465 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3466 struct usb_host_endpoint **eps, unsigned int num_eps,
3467 unsigned int num_streams, gfp_t mem_flags)
3470 struct xhci_hcd *xhci;
3471 struct xhci_virt_device *vdev;
3472 struct xhci_command *config_cmd;
3473 struct xhci_input_control_ctx *ctrl_ctx;
3474 unsigned int ep_index;
3475 unsigned int num_stream_ctxs;
3476 unsigned int max_packet;
3477 unsigned long flags;
3478 u32 changed_ep_bitmask = 0;
3483 /* Add one to the number of streams requested to account for
3484 * stream 0 that is reserved for xHCI usage.
3487 xhci = hcd_to_xhci(hcd);
3488 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3491 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3492 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3493 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3494 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3498 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3502 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3504 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3506 xhci_free_command(xhci, config_cmd);
3510 /* Check to make sure all endpoints are not already configured for
3511 * streams. While we're at it, find the maximum number of streams that
3512 * all the endpoints will support and check for duplicate endpoints.
3514 spin_lock_irqsave(&xhci->lock, flags);
3515 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3516 num_eps, &num_streams, &changed_ep_bitmask);
3518 xhci_free_command(xhci, config_cmd);
3519 spin_unlock_irqrestore(&xhci->lock, flags);
3522 if (num_streams <= 1) {
3523 xhci_warn(xhci, "WARN: endpoints can't handle "
3524 "more than one stream.\n");
3525 xhci_free_command(xhci, config_cmd);
3526 spin_unlock_irqrestore(&xhci->lock, flags);
3529 vdev = xhci->devs[udev->slot_id];
3530 /* Mark each endpoint as being in transition, so
3531 * xhci_urb_enqueue() will reject all URBs.
3533 for (i = 0; i < num_eps; i++) {
3534 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3535 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3537 spin_unlock_irqrestore(&xhci->lock, flags);
3539 /* Setup internal data structures and allocate HW data structures for
3540 * streams (but don't install the HW structures in the input context
3541 * until we're sure all memory allocation succeeded).
3543 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3544 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3545 num_stream_ctxs, num_streams);
3547 for (i = 0; i < num_eps; i++) {
3548 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3549 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3550 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3553 max_packet, mem_flags);
3554 if (!vdev->eps[ep_index].stream_info)
3556 /* Set maxPstreams in endpoint context and update deq ptr to
3557 * point to stream context array. FIXME
3561 /* Set up the input context for a configure endpoint command. */
3562 for (i = 0; i < num_eps; i++) {
3563 struct xhci_ep_ctx *ep_ctx;
3565 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3566 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3568 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3569 vdev->out_ctx, ep_index);
3570 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3571 vdev->eps[ep_index].stream_info);
3573 /* Tell the HW to drop its old copy of the endpoint context info
3574 * and add the updated copy from the input context.
3576 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3577 vdev->out_ctx, ctrl_ctx,
3578 changed_ep_bitmask, changed_ep_bitmask);
3580 /* Issue and wait for the configure endpoint command */
3581 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3584 /* xHC rejected the configure endpoint command for some reason, so we
3585 * leave the old ring intact and free our internal streams data
3591 spin_lock_irqsave(&xhci->lock, flags);
3592 for (i = 0; i < num_eps; i++) {
3593 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3594 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3595 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3596 udev->slot_id, ep_index);
3597 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3599 xhci_free_command(xhci, config_cmd);
3600 spin_unlock_irqrestore(&xhci->lock, flags);
3602 for (i = 0; i < num_eps; i++) {
3603 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3604 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3606 /* Subtract 1 for stream 0, which drivers can't use */
3607 return num_streams - 1;
3610 /* If it didn't work, free the streams! */
3611 for (i = 0; i < num_eps; i++) {
3612 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3613 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3614 vdev->eps[ep_index].stream_info = NULL;
3615 /* FIXME Unset maxPstreams in endpoint context and
3616 * update deq ptr to point to normal string ring.
3618 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3619 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3620 xhci_endpoint_zero(xhci, vdev, eps[i]);
3622 xhci_free_command(xhci, config_cmd);
3626 /* Transition the endpoint from using streams to being a "normal" endpoint
3629 * Modify the endpoint context state, submit a configure endpoint command,
3630 * and free all endpoint rings for streams if that completes successfully.
3632 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3633 struct usb_host_endpoint **eps, unsigned int num_eps,
3637 struct xhci_hcd *xhci;
3638 struct xhci_virt_device *vdev;
3639 struct xhci_command *command;
3640 struct xhci_input_control_ctx *ctrl_ctx;
3641 unsigned int ep_index;
3642 unsigned long flags;
3643 u32 changed_ep_bitmask;
3645 xhci = hcd_to_xhci(hcd);
3646 vdev = xhci->devs[udev->slot_id];
3648 /* Set up a configure endpoint command to remove the streams rings */
3649 spin_lock_irqsave(&xhci->lock, flags);
3650 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3651 udev, eps, num_eps);
3652 if (changed_ep_bitmask == 0) {
3653 spin_unlock_irqrestore(&xhci->lock, flags);
3657 /* Use the xhci_command structure from the first endpoint. We may have
3658 * allocated too many, but the driver may call xhci_free_streams() for
3659 * each endpoint it grouped into one call to xhci_alloc_streams().
3661 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3662 command = vdev->eps[ep_index].stream_info->free_streams_command;
3663 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3665 spin_unlock_irqrestore(&xhci->lock, flags);
3666 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3671 for (i = 0; i < num_eps; i++) {
3672 struct xhci_ep_ctx *ep_ctx;
3674 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3675 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3676 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3677 EP_GETTING_NO_STREAMS;
3679 xhci_endpoint_copy(xhci, command->in_ctx,
3680 vdev->out_ctx, ep_index);
3681 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3682 &vdev->eps[ep_index]);
3684 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3685 vdev->out_ctx, ctrl_ctx,
3686 changed_ep_bitmask, changed_ep_bitmask);
3687 spin_unlock_irqrestore(&xhci->lock, flags);
3689 /* Issue and wait for the configure endpoint command,
3690 * which must succeed.
3692 ret = xhci_configure_endpoint(xhci, udev, command,
3695 /* xHC rejected the configure endpoint command for some reason, so we
3696 * leave the streams rings intact.
3701 spin_lock_irqsave(&xhci->lock, flags);
3702 for (i = 0; i < num_eps; i++) {
3703 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3704 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3705 vdev->eps[ep_index].stream_info = NULL;
3706 /* FIXME Unset maxPstreams in endpoint context and
3707 * update deq ptr to point to normal string ring.
3709 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3710 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3712 spin_unlock_irqrestore(&xhci->lock, flags);
3718 * Deletes endpoint resources for endpoints that were active before a Reset
3719 * Device command, or a Disable Slot command. The Reset Device command leaves
3720 * the control endpoint intact, whereas the Disable Slot command deletes it.
3722 * Must be called with xhci->lock held.
3724 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3725 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3728 unsigned int num_dropped_eps = 0;
3729 unsigned int drop_flags = 0;
3731 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3732 if (virt_dev->eps[i].ring) {
3733 drop_flags |= 1 << i;
3737 xhci->num_active_eps -= num_dropped_eps;
3738 if (num_dropped_eps)
3739 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3740 "Dropped %u ep ctxs, flags = 0x%x, "
3742 num_dropped_eps, drop_flags,
3743 xhci->num_active_eps);
3747 * This submits a Reset Device Command, which will set the device state to 0,
3748 * set the device address to 0, and disable all the endpoints except the default
3749 * control endpoint. The USB core should come back and call
3750 * xhci_address_device(), and then re-set up the configuration. If this is
3751 * called because of a usb_reset_and_verify_device(), then the old alternate
3752 * settings will be re-installed through the normal bandwidth allocation
3755 * Wait for the Reset Device command to finish. Remove all structures
3756 * associated with the endpoints that were disabled. Clear the input device
3757 * structure? Reset the control endpoint 0 max packet size?
3759 * If the virt_dev to be reset does not exist or does not match the udev,
3760 * it means the device is lost, possibly due to the xHC restore error and
3761 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3762 * re-allocate the device.
3764 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3765 struct usb_device *udev)
3768 unsigned long flags;
3769 struct xhci_hcd *xhci;
3770 unsigned int slot_id;
3771 struct xhci_virt_device *virt_dev;
3772 struct xhci_command *reset_device_cmd;
3773 struct xhci_slot_ctx *slot_ctx;
3774 int old_active_eps = 0;
3776 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3779 xhci = hcd_to_xhci(hcd);
3780 slot_id = udev->slot_id;
3781 virt_dev = xhci->devs[slot_id];
3783 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3784 "not exist. Re-allocate the device\n", slot_id);
3785 ret = xhci_alloc_dev(hcd, udev);
3792 if (virt_dev->tt_info)
3793 old_active_eps = virt_dev->tt_info->active_eps;
3795 if (virt_dev->udev != udev) {
3796 /* If the virt_dev and the udev does not match, this virt_dev
3797 * may belong to another udev.
3798 * Re-allocate the device.
3800 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3801 "not match the udev. Re-allocate the device\n",
3803 ret = xhci_alloc_dev(hcd, udev);
3810 /* If device is not setup, there is no point in resetting it */
3811 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3812 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3813 SLOT_STATE_DISABLED)
3816 trace_xhci_discover_or_reset_device(slot_ctx);
3818 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3819 /* Allocate the command structure that holds the struct completion.
3820 * Assume we're in process context, since the normal device reset
3821 * process has to wait for the device anyway. Storage devices are
3822 * reset as part of error handling, so use GFP_NOIO instead of
3825 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3826 if (!reset_device_cmd) {
3827 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3831 /* Attempt to submit the Reset Device command to the command ring */
3832 spin_lock_irqsave(&xhci->lock, flags);
3834 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3836 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3837 spin_unlock_irqrestore(&xhci->lock, flags);
3838 goto command_cleanup;
3840 xhci_ring_cmd_db(xhci);
3841 spin_unlock_irqrestore(&xhci->lock, flags);
3843 /* Wait for the Reset Device command to finish */
3844 wait_for_completion(reset_device_cmd->completion);
3846 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3847 * unless we tried to reset a slot ID that wasn't enabled,
3848 * or the device wasn't in the addressed or configured state.
3850 ret = reset_device_cmd->status;
3852 case COMP_COMMAND_ABORTED:
3853 case COMP_COMMAND_RING_STOPPED:
3854 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3856 goto command_cleanup;
3857 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3858 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3859 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3861 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3862 xhci_dbg(xhci, "Not freeing device rings.\n");
3863 /* Don't treat this as an error. May change my mind later. */
3865 goto command_cleanup;
3867 xhci_dbg(xhci, "Successful reset device command.\n");
3870 if (xhci_is_vendor_info_code(xhci, ret))
3872 xhci_warn(xhci, "Unknown completion code %u for "
3873 "reset device command.\n", ret);
3875 goto command_cleanup;
3878 /* Free up host controller endpoint resources */
3879 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3880 spin_lock_irqsave(&xhci->lock, flags);
3881 /* Don't delete the default control endpoint resources */
3882 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3886 /* Everything but endpoint 0 is disabled, so free the rings. */
3887 for (i = 1; i < 31; i++) {
3888 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3890 if (ep->ep_state & EP_HAS_STREAMS) {
3891 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3892 xhci_get_endpoint_address(i));
3893 xhci_free_stream_info(xhci, ep->stream_info);
3894 ep->stream_info = NULL;
3895 ep->ep_state &= ~EP_HAS_STREAMS;
3899 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3900 xhci_free_endpoint_ring(xhci, virt_dev, i);
3902 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3903 xhci_drop_ep_from_interval_table(xhci,
3904 &virt_dev->eps[i].bw_info,
3909 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3911 /* If necessary, update the number of active TTs on this root port */
3912 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3913 virt_dev->flags = 0;
3917 xhci_free_command(xhci, reset_device_cmd);
3922 * At this point, the struct usb_device is about to go away, the device has
3923 * disconnected, and all traffic has been stopped and the endpoints have been
3924 * disabled. Free any HC data structures associated with that device.
3926 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3928 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3929 struct xhci_virt_device *virt_dev;
3930 struct xhci_slot_ctx *slot_ctx;
3933 #ifndef CONFIG_USB_DEFAULT_PERSIST
3935 * We called pm_runtime_get_noresume when the device was attached.
3936 * Decrement the counter here to allow controller to runtime suspend
3937 * if no devices remain.
3939 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3940 pm_runtime_put_noidle(hcd->self.controller);
3943 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3944 /* If the host is halted due to driver unload, we still need to free the
3947 if (ret <= 0 && ret != -ENODEV)
3950 virt_dev = xhci->devs[udev->slot_id];
3951 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3952 trace_xhci_free_dev(slot_ctx);
3954 /* Stop any wayward timer functions (which may grab the lock) */
3955 for (i = 0; i < 31; i++) {
3956 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3957 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3959 virt_dev->udev = NULL;
3960 ret = xhci_disable_slot(xhci, udev->slot_id);
3962 xhci_free_virt_device(xhci, udev->slot_id);
3965 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3967 struct xhci_command *command;
3968 unsigned long flags;
3972 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3976 xhci_debugfs_remove_slot(xhci, slot_id);
3978 spin_lock_irqsave(&xhci->lock, flags);
3979 /* Don't disable the slot if the host controller is dead. */
3980 state = readl(&xhci->op_regs->status);
3981 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3982 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3983 spin_unlock_irqrestore(&xhci->lock, flags);
3988 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3991 spin_unlock_irqrestore(&xhci->lock, flags);
3995 xhci_ring_cmd_db(xhci);
3996 spin_unlock_irqrestore(&xhci->lock, flags);
4001 * Checks if we have enough host controller resources for the default control
4004 * Must be called with xhci->lock held.
4006 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4008 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4009 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4010 "Not enough ep ctxs: "
4011 "%u active, need to add 1, limit is %u.",
4012 xhci->num_active_eps, xhci->limit_active_eps);
4015 xhci->num_active_eps += 1;
4016 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4017 "Adding 1 ep ctx, %u now active.",
4018 xhci->num_active_eps);
4024 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4025 * timed out, or allocating memory failed. Returns 1 on success.
4027 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4029 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4030 struct xhci_virt_device *vdev;
4031 struct xhci_slot_ctx *slot_ctx;
4032 unsigned long flags;
4034 struct xhci_command *command;
4036 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4040 spin_lock_irqsave(&xhci->lock, flags);
4041 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4043 spin_unlock_irqrestore(&xhci->lock, flags);
4044 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4045 xhci_free_command(xhci, command);
4048 xhci_ring_cmd_db(xhci);
4049 spin_unlock_irqrestore(&xhci->lock, flags);
4051 wait_for_completion(command->completion);
4052 slot_id = command->slot_id;
4054 if (!slot_id || command->status != COMP_SUCCESS) {
4055 xhci_err(xhci, "Error while assigning device slot ID\n");
4056 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4058 readl(&xhci->cap_regs->hcs_params1)));
4059 xhci_free_command(xhci, command);
4063 xhci_free_command(xhci, command);
4065 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4066 spin_lock_irqsave(&xhci->lock, flags);
4067 ret = xhci_reserve_host_control_ep_resources(xhci);
4069 spin_unlock_irqrestore(&xhci->lock, flags);
4070 xhci_warn(xhci, "Not enough host resources, "
4071 "active endpoint contexts = %u\n",
4072 xhci->num_active_eps);
4075 spin_unlock_irqrestore(&xhci->lock, flags);
4077 /* Use GFP_NOIO, since this function can be called from
4078 * xhci_discover_or_reset_device(), which may be called as part of
4079 * mass storage driver error handling.
4081 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4082 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4085 vdev = xhci->devs[slot_id];
4086 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4087 trace_xhci_alloc_dev(slot_ctx);
4089 udev->slot_id = slot_id;
4091 xhci_debugfs_create_slot(xhci, slot_id);
4093 #ifndef CONFIG_USB_DEFAULT_PERSIST
4095 * If resetting upon resume, we can't put the controller into runtime
4096 * suspend if there is a device attached.
4098 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4099 pm_runtime_get_noresume(hcd->self.controller);
4102 /* Is this a LS or FS device under a HS hub? */
4103 /* Hub or peripherial? */
4107 ret = xhci_disable_slot(xhci, udev->slot_id);
4109 xhci_free_virt_device(xhci, udev->slot_id);
4115 * Issue an Address Device command and optionally send a corresponding
4116 * SetAddress request to the device.
4118 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4119 enum xhci_setup_dev setup)
4121 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4122 unsigned long flags;
4123 struct xhci_virt_device *virt_dev;
4125 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4126 struct xhci_slot_ctx *slot_ctx;
4127 struct xhci_input_control_ctx *ctrl_ctx;
4129 struct xhci_command *command = NULL;
4131 mutex_lock(&xhci->mutex);
4133 if (xhci->xhc_state) { /* dying, removing or halted */
4138 if (!udev->slot_id) {
4139 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4140 "Bad Slot ID %d", udev->slot_id);
4145 virt_dev = xhci->devs[udev->slot_id];
4147 if (WARN_ON(!virt_dev)) {
4149 * In plug/unplug torture test with an NEC controller,
4150 * a zero-dereference was observed once due to virt_dev = 0.
4151 * Print useful debug rather than crash if it is observed again!
4153 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4158 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4159 trace_xhci_setup_device_slot(slot_ctx);
4161 if (setup == SETUP_CONTEXT_ONLY) {
4162 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4163 SLOT_STATE_DEFAULT) {
4164 xhci_dbg(xhci, "Slot already in default state\n");
4169 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4175 command->in_ctx = virt_dev->in_ctx;
4177 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4178 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4180 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4186 * If this is the first Set Address since device plug-in or
4187 * virt_device realloaction after a resume with an xHCI power loss,
4188 * then set up the slot context.
4190 if (!slot_ctx->dev_info)
4191 xhci_setup_addressable_virt_dev(xhci, udev);
4192 /* Otherwise, update the control endpoint ring enqueue pointer. */
4194 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4195 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4196 ctrl_ctx->drop_flags = 0;
4198 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4199 le32_to_cpu(slot_ctx->dev_info) >> 27);
4201 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4202 spin_lock_irqsave(&xhci->lock, flags);
4203 trace_xhci_setup_device(virt_dev);
4204 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4205 udev->slot_id, setup);
4207 spin_unlock_irqrestore(&xhci->lock, flags);
4208 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4209 "FIXME: allocate a command ring segment");
4212 xhci_ring_cmd_db(xhci);
4213 spin_unlock_irqrestore(&xhci->lock, flags);
4215 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4216 wait_for_completion(command->completion);
4218 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4219 * the SetAddress() "recovery interval" required by USB and aborting the
4220 * command on a timeout.
4222 switch (command->status) {
4223 case COMP_COMMAND_ABORTED:
4224 case COMP_COMMAND_RING_STOPPED:
4225 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4228 case COMP_CONTEXT_STATE_ERROR:
4229 case COMP_SLOT_NOT_ENABLED_ERROR:
4230 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4231 act, udev->slot_id);
4234 case COMP_USB_TRANSACTION_ERROR:
4235 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4237 mutex_unlock(&xhci->mutex);
4238 ret = xhci_disable_slot(xhci, udev->slot_id);
4240 xhci_alloc_dev(hcd, udev);
4241 kfree(command->completion);
4244 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4245 dev_warn(&udev->dev,
4246 "ERROR: Incompatible device for setup %s command\n", act);
4250 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4251 "Successful setup %s command", act);
4255 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4256 act, command->status);
4257 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4263 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4264 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4265 "Op regs DCBAA ptr = %#016llx", temp_64);
4266 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4267 "Slot ID %d dcbaa entry @%p = %#016llx",
4269 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4270 (unsigned long long)
4271 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4272 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4273 "Output Context DMA address = %#08llx",
4274 (unsigned long long)virt_dev->out_ctx->dma);
4275 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4276 le32_to_cpu(slot_ctx->dev_info) >> 27);
4278 * USB core uses address 1 for the roothubs, so we add one to the
4279 * address given back to us by the HC.
4281 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4282 le32_to_cpu(slot_ctx->dev_info) >> 27);
4283 /* Zero the input context control for later use */
4284 ctrl_ctx->add_flags = 0;
4285 ctrl_ctx->drop_flags = 0;
4286 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4287 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4289 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4290 "Internal device address = %d",
4291 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4293 mutex_unlock(&xhci->mutex);
4295 kfree(command->completion);
4301 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4303 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4306 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4308 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4312 * Transfer the port index into real index in the HW port status
4313 * registers. Caculate offset between the port's PORTSC register
4314 * and port status base. Divide the number of per port register
4315 * to get the real index. The raw port number bases 1.
4317 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4319 struct xhci_hub *rhub;
4321 rhub = xhci_get_rhub(hcd);
4322 return rhub->ports[port1 - 1]->hw_portnum + 1;
4326 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4327 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4329 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4330 struct usb_device *udev, u16 max_exit_latency)
4332 struct xhci_virt_device *virt_dev;
4333 struct xhci_command *command;
4334 struct xhci_input_control_ctx *ctrl_ctx;
4335 struct xhci_slot_ctx *slot_ctx;
4336 unsigned long flags;
4339 spin_lock_irqsave(&xhci->lock, flags);
4341 virt_dev = xhci->devs[udev->slot_id];
4344 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4345 * xHC was re-initialized. Exit latency will be set later after
4346 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4349 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4350 spin_unlock_irqrestore(&xhci->lock, flags);
4354 /* Attempt to issue an Evaluate Context command to change the MEL. */
4355 command = xhci->lpm_command;
4356 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4358 spin_unlock_irqrestore(&xhci->lock, flags);
4359 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4364 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4365 spin_unlock_irqrestore(&xhci->lock, flags);
4367 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4368 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4369 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4370 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4371 slot_ctx->dev_state = 0;
4373 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4374 "Set up evaluate context for LPM MEL change.");
4376 /* Issue and wait for the evaluate context command. */
4377 ret = xhci_configure_endpoint(xhci, udev, command,
4381 spin_lock_irqsave(&xhci->lock, flags);
4382 virt_dev->current_mel = max_exit_latency;
4383 spin_unlock_irqrestore(&xhci->lock, flags);
4390 /* BESL to HIRD Encoding array for USB2 LPM */
4391 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4392 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4394 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4395 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4396 struct usb_device *udev)
4398 int u2del, besl, besl_host;
4399 int besl_device = 0;
4402 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4403 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4405 if (field & USB_BESL_SUPPORT) {
4406 for (besl_host = 0; besl_host < 16; besl_host++) {
4407 if (xhci_besl_encoding[besl_host] >= u2del)
4410 /* Use baseline BESL value as default */
4411 if (field & USB_BESL_BASELINE_VALID)
4412 besl_device = USB_GET_BESL_BASELINE(field);
4413 else if (field & USB_BESL_DEEP_VALID)
4414 besl_device = USB_GET_BESL_DEEP(field);
4419 besl_host = (u2del - 51) / 75 + 1;
4422 besl = besl_host + besl_device;
4429 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4430 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4437 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4439 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4440 l1 = udev->l1_params.timeout / 256;
4442 /* device has preferred BESLD */
4443 if (field & USB_BESL_DEEP_VALID) {
4444 besld = USB_GET_BESL_DEEP(field);
4448 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4451 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4452 struct usb_device *udev, int enable)
4454 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4455 struct xhci_port **ports;
4456 __le32 __iomem *pm_addr, *hlpm_addr;
4457 u32 pm_val, hlpm_val, field;
4458 unsigned int port_num;
4459 unsigned long flags;
4460 int hird, exit_latency;
4463 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4466 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4470 if (!udev->parent || udev->parent->parent ||
4471 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4474 if (udev->usb2_hw_lpm_capable != 1)
4477 spin_lock_irqsave(&xhci->lock, flags);
4479 ports = xhci->usb2_rhub.ports;
4480 port_num = udev->portnum - 1;
4481 pm_addr = ports[port_num]->addr + PORTPMSC;
4482 pm_val = readl(pm_addr);
4483 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4485 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4486 enable ? "enable" : "disable", port_num + 1);
4489 /* Host supports BESL timeout instead of HIRD */
4490 if (udev->usb2_hw_lpm_besl_capable) {
4491 /* if device doesn't have a preferred BESL value use a
4492 * default one which works with mixed HIRD and BESL
4493 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4495 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4496 if ((field & USB_BESL_SUPPORT) &&
4497 (field & USB_BESL_BASELINE_VALID))
4498 hird = USB_GET_BESL_BASELINE(field);
4500 hird = udev->l1_params.besl;
4502 exit_latency = xhci_besl_encoding[hird];
4503 spin_unlock_irqrestore(&xhci->lock, flags);
4505 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4506 * input context for link powermanagement evaluate
4507 * context commands. It is protected by hcd->bandwidth
4508 * mutex and is shared by all devices. We need to set
4509 * the max ext latency in USB 2 BESL LPM as well, so
4510 * use the same mutex and xhci_change_max_exit_latency()
4512 mutex_lock(hcd->bandwidth_mutex);
4513 ret = xhci_change_max_exit_latency(xhci, udev,
4515 mutex_unlock(hcd->bandwidth_mutex);
4519 spin_lock_irqsave(&xhci->lock, flags);
4521 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4522 writel(hlpm_val, hlpm_addr);
4526 hird = xhci_calculate_hird_besl(xhci, udev);
4529 pm_val &= ~PORT_HIRD_MASK;
4530 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4531 writel(pm_val, pm_addr);
4532 pm_val = readl(pm_addr);
4534 writel(pm_val, pm_addr);
4538 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4539 writel(pm_val, pm_addr);
4542 if (udev->usb2_hw_lpm_besl_capable) {
4543 spin_unlock_irqrestore(&xhci->lock, flags);
4544 mutex_lock(hcd->bandwidth_mutex);
4545 xhci_change_max_exit_latency(xhci, udev, 0);
4546 mutex_unlock(hcd->bandwidth_mutex);
4547 readl_poll_timeout(ports[port_num]->addr, pm_val,
4548 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4554 spin_unlock_irqrestore(&xhci->lock, flags);
4558 /* check if a usb2 port supports a given extened capability protocol
4559 * only USB2 ports extended protocol capability values are cached.
4560 * Return 1 if capability is supported
4562 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4563 unsigned capability)
4565 u32 port_offset, port_count;
4568 for (i = 0; i < xhci->num_ext_caps; i++) {
4569 if (xhci->ext_caps[i] & capability) {
4570 /* port offsets starts at 1 */
4571 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4572 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4573 if (port >= port_offset &&
4574 port < port_offset + port_count)
4581 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4583 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4584 int portnum = udev->portnum - 1;
4586 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4589 /* we only support lpm for non-hub device connected to root hub yet */
4590 if (!udev->parent || udev->parent->parent ||
4591 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4594 if (xhci->hw_lpm_support == 1 &&
4595 xhci_check_usb2_port_capability(
4596 xhci, portnum, XHCI_HLC)) {
4597 udev->usb2_hw_lpm_capable = 1;
4598 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4599 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4600 if (xhci_check_usb2_port_capability(xhci, portnum,
4602 udev->usb2_hw_lpm_besl_capable = 1;
4608 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4610 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4611 static unsigned long long xhci_service_interval_to_ns(
4612 struct usb_endpoint_descriptor *desc)
4614 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4617 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4618 enum usb3_link_state state)
4620 unsigned long long sel;
4621 unsigned long long pel;
4622 unsigned int max_sel_pel;
4627 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4628 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4629 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4630 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4634 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4635 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4636 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4640 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4642 return USB3_LPM_DISABLED;
4645 if (sel <= max_sel_pel && pel <= max_sel_pel)
4646 return USB3_LPM_DEVICE_INITIATED;
4648 if (sel > max_sel_pel)
4649 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4650 "due to long SEL %llu ms\n",
4653 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4654 "due to long PEL %llu ms\n",
4656 return USB3_LPM_DISABLED;
4659 /* The U1 timeout should be the maximum of the following values:
4660 * - For control endpoints, U1 system exit latency (SEL) * 3
4661 * - For bulk endpoints, U1 SEL * 5
4662 * - For interrupt endpoints:
4663 * - Notification EPs, U1 SEL * 3
4664 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4665 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4667 static unsigned long long xhci_calculate_intel_u1_timeout(
4668 struct usb_device *udev,
4669 struct usb_endpoint_descriptor *desc)
4671 unsigned long long timeout_ns;
4675 ep_type = usb_endpoint_type(desc);
4677 case USB_ENDPOINT_XFER_CONTROL:
4678 timeout_ns = udev->u1_params.sel * 3;
4680 case USB_ENDPOINT_XFER_BULK:
4681 timeout_ns = udev->u1_params.sel * 5;
4683 case USB_ENDPOINT_XFER_INT:
4684 intr_type = usb_endpoint_interrupt_type(desc);
4685 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4686 timeout_ns = udev->u1_params.sel * 3;
4689 /* Otherwise the calculation is the same as isoc eps */
4691 case USB_ENDPOINT_XFER_ISOC:
4692 timeout_ns = xhci_service_interval_to_ns(desc);
4693 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4694 if (timeout_ns < udev->u1_params.sel * 2)
4695 timeout_ns = udev->u1_params.sel * 2;
4704 /* Returns the hub-encoded U1 timeout value. */
4705 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4706 struct usb_device *udev,
4707 struct usb_endpoint_descriptor *desc)
4709 unsigned long long timeout_ns;
4711 /* Prevent U1 if service interval is shorter than U1 exit latency */
4712 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4713 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4714 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4715 return USB3_LPM_DISABLED;
4719 if (xhci->quirks & XHCI_INTEL_HOST)
4720 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4722 timeout_ns = udev->u1_params.sel;
4724 /* The U1 timeout is encoded in 1us intervals.
4725 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4727 if (timeout_ns == USB3_LPM_DISABLED)
4730 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4732 /* If the necessary timeout value is bigger than what we can set in the
4733 * USB 3.0 hub, we have to disable hub-initiated U1.
4735 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4737 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4738 "due to long timeout %llu ms\n", timeout_ns);
4739 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4742 /* The U2 timeout should be the maximum of:
4743 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4744 * - largest bInterval of any active periodic endpoint (to avoid going
4745 * into lower power link states between intervals).
4746 * - the U2 Exit Latency of the device
4748 static unsigned long long xhci_calculate_intel_u2_timeout(
4749 struct usb_device *udev,
4750 struct usb_endpoint_descriptor *desc)
4752 unsigned long long timeout_ns;
4753 unsigned long long u2_del_ns;
4755 timeout_ns = 10 * 1000 * 1000;
4757 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4758 (xhci_service_interval_to_ns(desc) > timeout_ns))
4759 timeout_ns = xhci_service_interval_to_ns(desc);
4761 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4762 if (u2_del_ns > timeout_ns)
4763 timeout_ns = u2_del_ns;
4768 /* Returns the hub-encoded U2 timeout value. */
4769 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4770 struct usb_device *udev,
4771 struct usb_endpoint_descriptor *desc)
4773 unsigned long long timeout_ns;
4775 /* Prevent U2 if service interval is shorter than U2 exit latency */
4776 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4777 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4778 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4779 return USB3_LPM_DISABLED;
4783 if (xhci->quirks & XHCI_INTEL_HOST)
4784 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4786 timeout_ns = udev->u2_params.sel;
4788 /* The U2 timeout is encoded in 256us intervals */
4789 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4790 /* If the necessary timeout value is bigger than what we can set in the
4791 * USB 3.0 hub, we have to disable hub-initiated U2.
4793 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4795 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4796 "due to long timeout %llu ms\n", timeout_ns);
4797 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4800 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4801 struct usb_device *udev,
4802 struct usb_endpoint_descriptor *desc,
4803 enum usb3_link_state state,
4806 if (state == USB3_LPM_U1)
4807 return xhci_calculate_u1_timeout(xhci, udev, desc);
4808 else if (state == USB3_LPM_U2)
4809 return xhci_calculate_u2_timeout(xhci, udev, desc);
4811 return USB3_LPM_DISABLED;
4814 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4815 struct usb_device *udev,
4816 struct usb_endpoint_descriptor *desc,
4817 enum usb3_link_state state,
4822 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4823 desc, state, timeout);
4825 /* If we found we can't enable hub-initiated LPM, and
4826 * the U1 or U2 exit latency was too high to allow
4827 * device-initiated LPM as well, then we will disable LPM
4828 * for this device, so stop searching any further.
4830 if (alt_timeout == USB3_LPM_DISABLED) {
4831 *timeout = alt_timeout;
4834 if (alt_timeout > *timeout)
4835 *timeout = alt_timeout;
4839 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4840 struct usb_device *udev,
4841 struct usb_host_interface *alt,
4842 enum usb3_link_state state,
4847 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4848 if (xhci_update_timeout_for_endpoint(xhci, udev,
4849 &alt->endpoint[j].desc, state, timeout))
4855 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4856 enum usb3_link_state state)
4858 struct usb_device *parent;
4859 unsigned int num_hubs;
4861 if (state == USB3_LPM_U2)
4864 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4865 for (parent = udev->parent, num_hubs = 0; parent->parent;
4866 parent = parent->parent)
4872 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4873 " below second-tier hub.\n");
4874 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4875 "to decrease power consumption.\n");
4879 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4880 struct usb_device *udev,
4881 enum usb3_link_state state)
4883 if (xhci->quirks & XHCI_INTEL_HOST)
4884 return xhci_check_intel_tier_policy(udev, state);
4889 /* Returns the U1 or U2 timeout that should be enabled.
4890 * If the tier check or timeout setting functions return with a non-zero exit
4891 * code, that means the timeout value has been finalized and we shouldn't look
4892 * at any more endpoints.
4894 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4895 struct usb_device *udev, enum usb3_link_state state)
4897 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4898 struct usb_host_config *config;
4901 u16 timeout = USB3_LPM_DISABLED;
4903 if (state == USB3_LPM_U1)
4905 else if (state == USB3_LPM_U2)
4908 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4913 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4916 /* Gather some information about the currently installed configuration
4917 * and alternate interface settings.
4919 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4923 config = udev->actconfig;
4927 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4928 struct usb_driver *driver;
4929 struct usb_interface *intf = config->interface[i];
4934 /* Check if any currently bound drivers want hub-initiated LPM
4937 if (intf->dev.driver) {
4938 driver = to_usb_driver(intf->dev.driver);
4939 if (driver && driver->disable_hub_initiated_lpm) {
4940 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4941 state_name, driver->name);
4942 timeout = xhci_get_timeout_no_hub_lpm(udev,
4944 if (timeout == USB3_LPM_DISABLED)
4949 /* Not sure how this could happen... */
4950 if (!intf->cur_altsetting)
4953 if (xhci_update_timeout_for_interface(xhci, udev,
4954 intf->cur_altsetting,
4961 static int calculate_max_exit_latency(struct usb_device *udev,
4962 enum usb3_link_state state_changed,
4963 u16 hub_encoded_timeout)
4965 unsigned long long u1_mel_us = 0;
4966 unsigned long long u2_mel_us = 0;
4967 unsigned long long mel_us = 0;
4973 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4974 hub_encoded_timeout == USB3_LPM_DISABLED);
4975 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4976 hub_encoded_timeout == USB3_LPM_DISABLED);
4978 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4979 hub_encoded_timeout != USB3_LPM_DISABLED);
4980 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4981 hub_encoded_timeout != USB3_LPM_DISABLED);
4983 /* If U1 was already enabled and we're not disabling it,
4984 * or we're going to enable U1, account for the U1 max exit latency.
4986 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4988 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4989 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4991 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4993 if (u1_mel_us > u2_mel_us)
4997 /* xHCI host controller max exit latency field is only 16 bits wide. */
4998 if (mel_us > MAX_EXIT) {
4999 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5000 "is too big.\n", mel_us);
5006 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5007 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5008 struct usb_device *udev, enum usb3_link_state state)
5010 struct xhci_hcd *xhci;
5011 u16 hub_encoded_timeout;
5015 xhci = hcd_to_xhci(hcd);
5016 /* The LPM timeout values are pretty host-controller specific, so don't
5017 * enable hub-initiated timeouts unless the vendor has provided
5018 * information about their timeout algorithm.
5020 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5021 !xhci->devs[udev->slot_id])
5022 return USB3_LPM_DISABLED;
5024 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5025 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5027 /* Max Exit Latency is too big, disable LPM. */
5028 hub_encoded_timeout = USB3_LPM_DISABLED;
5032 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5035 return hub_encoded_timeout;
5038 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5039 struct usb_device *udev, enum usb3_link_state state)
5041 struct xhci_hcd *xhci;
5044 xhci = hcd_to_xhci(hcd);
5045 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5046 !xhci->devs[udev->slot_id])
5049 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5050 return xhci_change_max_exit_latency(xhci, udev, mel);
5052 #else /* CONFIG_PM */
5054 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5055 struct usb_device *udev, int enable)
5060 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5065 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5066 struct usb_device *udev, enum usb3_link_state state)
5068 return USB3_LPM_DISABLED;
5071 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5072 struct usb_device *udev, enum usb3_link_state state)
5076 #endif /* CONFIG_PM */
5078 /*-------------------------------------------------------------------------*/
5080 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5081 * internal data structures for the device.
5083 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5084 struct usb_tt *tt, gfp_t mem_flags)
5086 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5087 struct xhci_virt_device *vdev;
5088 struct xhci_command *config_cmd;
5089 struct xhci_input_control_ctx *ctrl_ctx;
5090 struct xhci_slot_ctx *slot_ctx;
5091 unsigned long flags;
5092 unsigned think_time;
5095 /* Ignore root hubs */
5099 vdev = xhci->devs[hdev->slot_id];
5101 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5105 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5109 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5111 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5113 xhci_free_command(xhci, config_cmd);
5117 spin_lock_irqsave(&xhci->lock, flags);
5118 if (hdev->speed == USB_SPEED_HIGH &&
5119 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5120 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5121 xhci_free_command(xhci, config_cmd);
5122 spin_unlock_irqrestore(&xhci->lock, flags);
5126 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5127 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5128 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5129 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5131 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5132 * but it may be already set to 1 when setup an xHCI virtual
5133 * device, so clear it anyway.
5136 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5137 else if (hdev->speed == USB_SPEED_FULL)
5138 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5140 if (xhci->hci_version > 0x95) {
5141 xhci_dbg(xhci, "xHCI version %x needs hub "
5142 "TT think time and number of ports\n",
5143 (unsigned int) xhci->hci_version);
5144 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5145 /* Set TT think time - convert from ns to FS bit times.
5146 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5147 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5149 * xHCI 1.0: this field shall be 0 if the device is not a
5152 think_time = tt->think_time;
5153 if (think_time != 0)
5154 think_time = (think_time / 666) - 1;
5155 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5156 slot_ctx->tt_info |=
5157 cpu_to_le32(TT_THINK_TIME(think_time));
5159 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5160 "TT think time or number of ports\n",
5161 (unsigned int) xhci->hci_version);
5163 slot_ctx->dev_state = 0;
5164 spin_unlock_irqrestore(&xhci->lock, flags);
5166 xhci_dbg(xhci, "Set up %s for hub device.\n",
5167 (xhci->hci_version > 0x95) ?
5168 "configure endpoint" : "evaluate context");
5170 /* Issue and wait for the configure endpoint or
5171 * evaluate context command.
5173 if (xhci->hci_version > 0x95)
5174 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5177 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5180 xhci_free_command(xhci, config_cmd);
5184 static int xhci_get_frame(struct usb_hcd *hcd)
5186 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5187 /* EHCI mods by the periodic size. Why? */
5188 return readl(&xhci->run_regs->microframe_index) >> 3;
5191 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5193 struct xhci_hcd *xhci;
5195 * TODO: Check with DWC3 clients for sysdev according to
5198 struct device *dev = hcd->self.sysdev;
5199 unsigned int minor_rev;
5202 /* Accept arbitrarily long scatter-gather lists */
5203 hcd->self.sg_tablesize = ~0;
5205 /* support to build packet from discontinuous buffers */
5206 hcd->self.no_sg_constraint = 1;
5208 /* XHCI controllers don't stop the ep queue on short packets :| */
5209 hcd->self.no_stop_on_short = 1;
5211 xhci = hcd_to_xhci(hcd);
5213 if (usb_hcd_is_primary_hcd(hcd)) {
5214 xhci->main_hcd = hcd;
5215 xhci->usb2_rhub.hcd = hcd;
5216 /* Mark the first roothub as being USB 2.0.
5217 * The xHCI driver will register the USB 3.0 roothub.
5219 hcd->speed = HCD_USB2;
5220 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5222 * USB 2.0 roothub under xHCI has an integrated TT,
5223 * (rate matching hub) as opposed to having an OHCI/UHCI
5224 * companion controller.
5229 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5230 * should return 0x31 for sbrn, or that the minor revision
5231 * is a two digit BCD containig minor and sub-minor numbers.
5232 * This was later clarified in xHCI 1.2.
5234 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5235 * minor revision set to 0x1 instead of 0x10.
5237 if (xhci->usb3_rhub.min_rev == 0x1)
5240 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5242 switch (minor_rev) {
5244 hcd->speed = HCD_USB32;
5245 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5246 hcd->self.root_hub->rx_lanes = 2;
5247 hcd->self.root_hub->tx_lanes = 2;
5248 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5251 hcd->speed = HCD_USB31;
5252 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5253 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5256 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5258 minor_rev ? "Enhanced " : "");
5260 xhci->usb3_rhub.hcd = hcd;
5261 /* xHCI private pointer was set in xhci_pci_probe for the second
5262 * registered roothub.
5267 mutex_init(&xhci->mutex);
5268 xhci->cap_regs = hcd->regs;
5269 xhci->op_regs = hcd->regs +
5270 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5271 xhci->run_regs = hcd->regs +
5272 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5273 /* Cache read-only capability registers */
5274 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5275 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5276 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5277 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5278 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5279 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5280 if (xhci->hci_version > 0x100)
5281 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5283 xhci->quirks |= quirks;
5285 get_quirks(dev, xhci);
5287 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5288 * success event after a short transfer. This quirk will ignore such
5291 if (xhci->hci_version > 0x96)
5292 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5294 /* Make sure the HC is halted. */
5295 retval = xhci_halt(xhci);
5299 xhci_zero_64b_regs(xhci);
5301 xhci_dbg(xhci, "Resetting HCD\n");
5302 /* Reset the internal HC memory state and registers. */
5303 retval = xhci_reset(xhci);
5306 xhci_dbg(xhci, "Reset complete\n");
5309 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5310 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5311 * address memory pointers actually. So, this driver clears the AC64
5312 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5313 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5315 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5316 xhci->hcc_params &= ~BIT(0);
5318 /* Set dma_mask and coherent_dma_mask to 64-bits,
5319 * if xHC supports 64-bit addressing */
5320 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5321 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5322 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5323 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5326 * This is to avoid error in cases where a 32-bit USB
5327 * controller is used on a 64-bit capable system.
5329 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5332 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5333 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5336 xhci_dbg(xhci, "Calling HCD init\n");
5337 /* Initialize HCD and host controller data structures. */
5338 retval = xhci_init(hcd);
5341 xhci_dbg(xhci, "Called HCD init\n");
5343 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5344 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5348 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5350 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5351 struct usb_host_endpoint *ep)
5353 struct xhci_hcd *xhci;
5354 struct usb_device *udev;
5355 unsigned int slot_id;
5356 unsigned int ep_index;
5357 unsigned long flags;
5359 xhci = hcd_to_xhci(hcd);
5361 spin_lock_irqsave(&xhci->lock, flags);
5362 udev = (struct usb_device *)ep->hcpriv;
5363 slot_id = udev->slot_id;
5364 ep_index = xhci_get_endpoint_index(&ep->desc);
5366 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5367 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5368 spin_unlock_irqrestore(&xhci->lock, flags);
5371 static const struct hc_driver xhci_hc_driver = {
5372 .description = "xhci-hcd",
5373 .product_desc = "xHCI Host Controller",
5374 .hcd_priv_size = sizeof(struct xhci_hcd),
5377 * generic hardware linkage
5380 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5384 * basic lifecycle operations
5386 .reset = NULL, /* set in xhci_init_driver() */
5389 .shutdown = xhci_shutdown,
5392 * managing i/o requests and associated device resources
5394 .map_urb_for_dma = xhci_map_urb_for_dma,
5395 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5396 .urb_enqueue = xhci_urb_enqueue,
5397 .urb_dequeue = xhci_urb_dequeue,
5398 .alloc_dev = xhci_alloc_dev,
5399 .free_dev = xhci_free_dev,
5400 .alloc_streams = xhci_alloc_streams,
5401 .free_streams = xhci_free_streams,
5402 .add_endpoint = xhci_add_endpoint,
5403 .drop_endpoint = xhci_drop_endpoint,
5404 .endpoint_disable = xhci_endpoint_disable,
5405 .endpoint_reset = xhci_endpoint_reset,
5406 .check_bandwidth = xhci_check_bandwidth,
5407 .reset_bandwidth = xhci_reset_bandwidth,
5408 .address_device = xhci_address_device,
5409 .enable_device = xhci_enable_device,
5410 .update_hub_device = xhci_update_hub_device,
5411 .reset_device = xhci_discover_or_reset_device,
5414 * scheduling support
5416 .get_frame_number = xhci_get_frame,
5421 .hub_control = xhci_hub_control,
5422 .hub_status_data = xhci_hub_status_data,
5423 .bus_suspend = xhci_bus_suspend,
5424 .bus_resume = xhci_bus_resume,
5425 .get_resuming_ports = xhci_get_resuming_ports,
5428 * call back when device connected and addressed
5430 .update_device = xhci_update_device,
5431 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5432 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5433 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5434 .find_raw_port_number = xhci_find_raw_port_number,
5435 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5438 void xhci_init_driver(struct hc_driver *drv,
5439 const struct xhci_driver_overrides *over)
5443 /* Copy the generic table to drv then apply the overrides */
5444 *drv = xhci_hc_driver;
5447 drv->hcd_priv_size += over->extra_priv_size;
5449 drv->reset = over->reset;
5451 drv->start = over->start;
5452 if (over->add_endpoint)
5453 drv->add_endpoint = over->add_endpoint;
5454 if (over->drop_endpoint)
5455 drv->drop_endpoint = over->drop_endpoint;
5456 if (over->check_bandwidth)
5457 drv->check_bandwidth = over->check_bandwidth;
5458 if (over->reset_bandwidth)
5459 drv->reset_bandwidth = over->reset_bandwidth;
5462 EXPORT_SYMBOL_GPL(xhci_init_driver);
5464 MODULE_DESCRIPTION(DRIVER_DESC);
5465 MODULE_AUTHOR(DRIVER_AUTHOR);
5466 MODULE_LICENSE("GPL");
5468 static int __init xhci_hcd_init(void)
5471 * Check the compiler generated sizes of structures that must be laid
5472 * out in specific ways for hardware access.
5474 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5475 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5476 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5477 /* xhci_device_control has eight fields, and also
5478 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5480 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5481 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5482 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5483 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5484 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5485 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5486 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5491 xhci_debugfs_create_root();
5497 * If an init function is provided, an exit function must also be provided
5498 * to allow module unload.
5500 static void __exit xhci_hcd_fini(void)
5502 xhci_debugfs_remove_root();
5505 module_init(xhci_hcd_init);
5506 module_exit(xhci_hcd_fini);