1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
157 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
166 * This resets pipelines, timers, counters, state machines, etc.
167 * Transactions will be terminated immediately, and operational registers
168 * will be set to their defaults.
170 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
176 state = readl(&xhci->op_regs->status);
178 if (state == ~(u32)0) {
179 xhci_warn(xhci, "Host not accessible, reset failed.\n");
183 if ((state & STS_HALT) == 0) {
184 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
188 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
189 command = readl(&xhci->op_regs->command);
190 command |= CMD_RESET;
191 writel(command, &xhci->op_regs->command);
193 /* Existing Intel xHCI controllers require a delay of 1 mS,
194 * after setting the CMD_RESET bit, and before accessing any
195 * HC registers. This allows the HC to complete the
196 * reset operation and be ready for HC register access.
197 * Without this delay, the subsequent HC register access,
198 * may result in a system hang very rarely.
200 if (xhci->quirks & XHCI_INTEL_HOST)
203 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
207 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
208 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
210 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
211 "Wait for controller to be ready for doorbell rings");
213 * xHCI cannot write to any doorbells or operational registers other
214 * than status until the "Controller Not Ready" flag is cleared.
216 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
228 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
249 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
252 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
254 /* Clear HSEIE so that faults do not get signaled */
255 val = readl(&xhci->op_regs->command);
257 writel(val, &xhci->op_regs->command);
259 /* Clear HSE (aka FATAL) */
260 val = readl(&xhci->op_regs->status);
262 writel(val, &xhci->op_regs->status);
264 /* Now zero the registers, and brace for impact */
265 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
268 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
269 if (upper_32_bits(val))
270 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
272 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
273 ARRAY_SIZE(xhci->run_regs->ir_set));
275 for (i = 0; i < intrs; i++) {
276 struct xhci_intr_reg __iomem *ir;
278 ir = &xhci->run_regs->ir_set[i];
279 val = xhci_read_64(xhci, &ir->erst_base);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_base);
282 val= xhci_read_64(xhci, &ir->erst_dequeue);
283 if (upper_32_bits(val))
284 xhci_write_64(xhci, 0, &ir->erst_dequeue);
287 /* Wait for the fault to appear. It will be cleared on reset */
288 err = xhci_handshake(&xhci->op_regs->status,
289 STS_FATAL, STS_FATAL,
292 xhci_info(xhci, "Fault detected\n");
295 #ifdef CONFIG_USB_PCI
299 static int xhci_setup_msi(struct xhci_hcd *xhci)
303 * TODO:Check with MSI Soc for sysdev
305 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
307 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "failed to allocate MSI entry");
314 ret = request_irq(pdev->irq, xhci_msi_irq,
315 0, "xhci_hcd", xhci_to_hcd(xhci));
317 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
318 "disable MSI interrupt");
319 pci_free_irq_vectors(pdev);
328 static int xhci_setup_msix(struct xhci_hcd *xhci)
331 struct usb_hcd *hcd = xhci_to_hcd(xhci);
332 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
335 * calculate number of msi-x vectors supported.
336 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
337 * with max number of interrupters based on the xhci HCSPARAMS1.
338 * - num_online_cpus: maximum msi-x vectors per CPUs core.
339 * Add additional 1 vector to ensure always available interrupt.
341 xhci->msix_count = min(num_online_cpus() + 1,
342 HCS_MAX_INTRS(xhci->hcs_params1));
344 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
347 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
348 "Failed to enable MSI-X");
352 for (i = 0; i < xhci->msix_count; i++) {
353 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
354 "xhci_hcd", xhci_to_hcd(xhci));
359 hcd->msix_enabled = 1;
363 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
365 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
366 pci_free_irq_vectors(pdev);
370 /* Free any IRQs and disable MSI-X */
371 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
373 struct usb_hcd *hcd = xhci_to_hcd(xhci);
374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
376 if (xhci->quirks & XHCI_PLAT)
379 /* return if using legacy interrupt */
383 if (hcd->msix_enabled) {
386 for (i = 0; i < xhci->msix_count; i++)
387 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
389 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
392 pci_free_irq_vectors(pdev);
393 hcd->msix_enabled = 0;
396 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
398 struct usb_hcd *hcd = xhci_to_hcd(xhci);
400 if (hcd->msix_enabled) {
401 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
404 for (i = 0; i < xhci->msix_count; i++)
405 synchronize_irq(pci_irq_vector(pdev, i));
409 static int xhci_try_enable_msi(struct usb_hcd *hcd)
411 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
412 struct pci_dev *pdev;
415 /* The xhci platform device has set up IRQs through usb_add_hcd. */
416 if (xhci->quirks & XHCI_PLAT)
419 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
421 * Some Fresco Logic host controllers advertise MSI, but fail to
422 * generate interrupts. Don't even try to enable MSI.
424 if (xhci->quirks & XHCI_BROKEN_MSI)
427 /* unregister the legacy interrupt */
429 free_irq(hcd->irq, hcd);
432 ret = xhci_setup_msix(xhci);
434 /* fall back to msi*/
435 ret = xhci_setup_msi(xhci);
438 hcd->msi_enabled = 1;
443 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
448 if (!strlen(hcd->irq_descr))
449 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
450 hcd->driver->description, hcd->self.busnum);
452 /* fall back to legacy interrupt*/
453 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
454 hcd->irq_descr, hcd);
456 xhci_err(xhci, "request interrupt %d failed\n",
460 hcd->irq = pdev->irq;
466 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
471 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
475 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
481 static void compliance_mode_recovery(struct timer_list *t)
483 struct xhci_hcd *xhci;
485 struct xhci_hub *rhub;
489 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
490 rhub = &xhci->usb3_rhub;
496 for (i = 0; i < rhub->num_ports; i++) {
497 temp = readl(rhub->ports[i]->addr);
498 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
500 * Compliance Mode Detected. Letting USB Core
501 * handle the Warm Reset
503 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
504 "Compliance mode detected->port %d",
506 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
507 "Attempting compliance mode recovery");
509 if (hcd->state == HC_STATE_SUSPENDED)
510 usb_hcd_resume_root_hub(hcd);
512 usb_hcd_poll_rh_status(hcd);
516 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
517 mod_timer(&xhci->comp_mode_recovery_timer,
518 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
522 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
523 * that causes ports behind that hardware to enter compliance mode sometimes.
524 * The quirk creates a timer that polls every 2 seconds the link state of
525 * each host controller's port and recovers it by issuing a Warm reset
526 * if Compliance mode is detected, otherwise the port will become "dead" (no
527 * device connections or disconnections will be detected anymore). Becasue no
528 * status event is generated when entering compliance mode (per xhci spec),
529 * this quirk is needed on systems that have the failing hardware installed.
531 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
533 xhci->port_status_u0 = 0;
534 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
536 xhci->comp_mode_recovery_timer.expires = jiffies +
537 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
539 add_timer(&xhci->comp_mode_recovery_timer);
540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
541 "Compliance mode recovery timer initialized");
545 * This function identifies the systems that have installed the SN65LVPE502CP
546 * USB3.0 re-driver and that need the Compliance Mode Quirk.
548 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
550 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
552 const char *dmi_product_name, *dmi_sys_vendor;
554 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
555 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
556 if (!dmi_product_name || !dmi_sys_vendor)
559 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
562 if (strstr(dmi_product_name, "Z420") ||
563 strstr(dmi_product_name, "Z620") ||
564 strstr(dmi_product_name, "Z820") ||
565 strstr(dmi_product_name, "Z1 Workstation"))
571 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
573 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
578 * Initialize memory for HCD and xHC (one-time init).
580 * Program the PAGESIZE register, initialize the device context array, create
581 * device contexts (?), set up a command ring segment (or two?), create event
582 * ring (one for now).
584 static int xhci_init(struct usb_hcd *hcd)
586 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
590 spin_lock_init(&xhci->lock);
591 if (xhci->hci_version == 0x95 && link_quirk) {
592 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
593 "QUIRK: Not clearing Link TRB chain bits.");
594 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
596 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
597 "xHCI doesn't need link TRB QUIRK");
599 retval = xhci_mem_init(xhci, GFP_KERNEL);
600 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
602 /* Initializing Compliance Mode Recovery Data If Needed */
603 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
604 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
605 compliance_mode_recovery_timer_init(xhci);
611 /*-------------------------------------------------------------------------*/
614 static int xhci_run_finished(struct xhci_hcd *xhci)
620 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
621 * Protect the short window before host is running with a lock
623 spin_lock_irqsave(&xhci->lock, flags);
625 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
626 temp = readl(&xhci->op_regs->command);
628 writel(temp, &xhci->op_regs->command);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
631 temp = readl(&xhci->ir_set->irq_pending);
632 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
634 if (xhci_start(xhci)) {
636 spin_unlock_irqrestore(&xhci->lock, flags);
640 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
642 if (xhci->quirks & XHCI_NEC_HOST)
643 xhci_ring_cmd_db(xhci);
645 spin_unlock_irqrestore(&xhci->lock, flags);
651 * Start the HC after it was halted.
653 * This function is called by the USB core when the HC driver is added.
654 * Its opposite is xhci_stop().
656 * xhci_init() must be called once before this function can be called.
657 * Reset the HC, enable device slot contexts, program DCBAAP, and
658 * set command ring pointer and event ring pointer.
660 * Setup MSI-X vectors and enable interrupts.
662 int xhci_run(struct usb_hcd *hcd)
667 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
669 /* Start the xHCI host controller running only after the USB 2.0 roothub
673 hcd->uses_new_polling = 1;
674 if (!usb_hcd_is_primary_hcd(hcd))
675 return xhci_run_finished(xhci);
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
679 ret = xhci_try_enable_msi(hcd);
683 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
684 temp_64 &= ~ERST_PTR_MASK;
685 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
686 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
688 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
689 "// Set the interrupt modulation register");
690 temp = readl(&xhci->ir_set->irq_control);
691 temp &= ~ER_IRQ_INTERVAL_MASK;
692 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
693 writel(temp, &xhci->ir_set->irq_control);
695 if (xhci->quirks & XHCI_NEC_HOST) {
696 struct xhci_command *command;
698 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
702 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
703 TRB_TYPE(TRB_NEC_GET_FW));
705 xhci_free_command(xhci, command);
707 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
708 "Finished %s for main hcd", __func__);
710 xhci_create_dbc_dev(xhci);
712 xhci_debugfs_init(xhci);
714 if (xhci_has_one_roothub(xhci))
715 return xhci_run_finished(xhci);
717 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
721 EXPORT_SYMBOL_GPL(xhci_run);
726 * This function is called by the USB core when the HC driver is removed.
727 * Its opposite is xhci_run().
729 * Disable device contexts, disable IRQs, and quiesce the HC.
730 * Reset the HC, finish any completed transactions, and cleanup memory.
732 static void xhci_stop(struct usb_hcd *hcd)
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
737 mutex_lock(&xhci->mutex);
739 /* Only halt host and free memory after both hcds are removed */
740 if (!usb_hcd_is_primary_hcd(hcd)) {
741 mutex_unlock(&xhci->mutex);
745 xhci_remove_dbc_dev(xhci);
747 spin_lock_irq(&xhci->lock);
748 xhci->xhc_state |= XHCI_STATE_HALTED;
749 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
751 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
752 spin_unlock_irq(&xhci->lock);
754 xhci_cleanup_msix(xhci);
756 /* Deleting Compliance Mode Recovery Timer */
757 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
758 (!(xhci_all_ports_seen_u0(xhci)))) {
759 del_timer_sync(&xhci->comp_mode_recovery_timer);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
761 "%s: compliance mode recovery timer deleted",
765 if (xhci->quirks & XHCI_AMD_PLL_FIX)
768 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
769 "// Disabling event ring interrupts");
770 temp = readl(&xhci->op_regs->status);
771 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
772 temp = readl(&xhci->ir_set->irq_pending);
773 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
775 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
776 xhci_mem_cleanup(xhci);
777 xhci_debugfs_exit(xhci);
778 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
779 "xhci_stop completed - status = %x",
780 readl(&xhci->op_regs->status));
781 mutex_unlock(&xhci->mutex);
785 * Shutdown HC (not bus-specific)
787 * This is called when the machine is rebooting or halting. We assume that the
788 * machine will be powered off, and the HC's internal state will be reset.
789 * Don't bother to free memory.
791 * This will only ever be called with the main usb_hcd (the USB3 roothub).
793 void xhci_shutdown(struct usb_hcd *hcd)
795 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
797 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
798 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
800 /* Don't poll the roothubs after shutdown. */
801 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
802 __func__, hcd->self.busnum);
803 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
804 del_timer_sync(&hcd->rh_timer);
806 if (xhci->shared_hcd) {
807 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
808 del_timer_sync(&xhci->shared_hcd->rh_timer);
811 spin_lock_irq(&xhci->lock);
815 * Workaround for spurious wakeps at shutdown with HSW, and for boot
816 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
818 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
819 xhci->quirks & XHCI_RESET_TO_DEFAULT)
820 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
822 spin_unlock_irq(&xhci->lock);
824 xhci_cleanup_msix(xhci);
826 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
827 "xhci_shutdown completed - status = %x",
828 readl(&xhci->op_regs->status));
830 EXPORT_SYMBOL_GPL(xhci_shutdown);
833 static void xhci_save_registers(struct xhci_hcd *xhci)
835 xhci->s3.command = readl(&xhci->op_regs->command);
836 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
837 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
838 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
839 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
840 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
841 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
842 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
843 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
846 static void xhci_restore_registers(struct xhci_hcd *xhci)
848 writel(xhci->s3.command, &xhci->op_regs->command);
849 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
850 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
851 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
852 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
853 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
854 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
855 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
856 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
859 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
863 /* step 2: initialize command ring buffer */
864 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
865 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
866 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
867 xhci->cmd_ring->dequeue) &
868 (u64) ~CMD_RING_RSVD_BITS) |
869 xhci->cmd_ring->cycle_state;
870 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
871 "// Setting command ring address to 0x%llx",
872 (long unsigned long) val_64);
873 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
877 * The whole command ring must be cleared to zero when we suspend the host.
879 * The host doesn't save the command ring pointer in the suspend well, so we
880 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
881 * aligned, because of the reserved bits in the command ring dequeue pointer
882 * register. Therefore, we can't just set the dequeue pointer back in the
883 * middle of the ring (TRBs are 16-byte aligned).
885 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
887 struct xhci_ring *ring;
888 struct xhci_segment *seg;
890 ring = xhci->cmd_ring;
894 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
895 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
896 cpu_to_le32(~TRB_CYCLE);
898 } while (seg != ring->deq_seg);
900 /* Reset the software enqueue and dequeue pointers */
901 ring->deq_seg = ring->first_seg;
902 ring->dequeue = ring->first_seg->trbs;
903 ring->enq_seg = ring->deq_seg;
904 ring->enqueue = ring->dequeue;
906 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
908 * Ring is now zeroed, so the HW should look for change of ownership
909 * when the cycle bit is set to 1.
911 ring->cycle_state = 1;
914 * Reset the hardware dequeue pointer.
915 * Yes, this will need to be re-written after resume, but we're paranoid
916 * and want to make sure the hardware doesn't access bogus memory
917 * because, say, the BIOS or an SMI started the host without changing
918 * the command ring pointers.
920 xhci_set_cmd_ring_deq(xhci);
924 * Disable port wake bits if do_wakeup is not set.
926 * Also clear a possible internal port wake state left hanging for ports that
927 * detected termination but never successfully enumerated (trained to 0U).
928 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
929 * at enumeration clears this wake, force one here as well for unconnected ports
932 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
933 struct xhci_hub *rhub,
940 spin_lock_irqsave(&xhci->lock, flags);
942 for (i = 0; i < rhub->num_ports; i++) {
943 portsc = readl(rhub->ports[i]->addr);
944 t1 = xhci_port_state_to_neutral(portsc);
947 /* clear wake bits if do_wake is not set */
949 t2 &= ~PORT_WAKE_BITS;
951 /* Don't touch csc bit if connected or connect change is set */
952 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
956 writel(t2, rhub->ports[i]->addr);
957 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
958 rhub->hcd->self.busnum, i + 1, portsc, t2);
961 spin_unlock_irqrestore(&xhci->lock, flags);
964 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
966 struct xhci_port **ports;
971 status = readl(&xhci->op_regs->status);
972 if (status & STS_EINT)
975 * Checking STS_EINT is not enough as there is a lag between a change
976 * bit being set and the Port Status Change Event that it generated
977 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
980 port_index = xhci->usb2_rhub.num_ports;
981 ports = xhci->usb2_rhub.ports;
982 while (port_index--) {
983 portsc = readl(ports[port_index]->addr);
984 if (portsc & PORT_CHANGE_MASK ||
985 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
988 port_index = xhci->usb3_rhub.num_ports;
989 ports = xhci->usb3_rhub.ports;
990 while (port_index--) {
991 portsc = readl(ports[port_index]->addr);
992 if (portsc & PORT_CHANGE_MASK ||
993 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
1000 * Stop HC (not bus-specific)
1002 * This is called when the machine transition into S3/S4 mode.
1005 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1008 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1009 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1016 if (hcd->state != HC_STATE_SUSPENDED ||
1017 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1020 /* Clear root port wake on bits if wakeup not allowed. */
1021 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1022 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1024 if (!HCD_HW_ACCESSIBLE(hcd))
1027 xhci_dbc_suspend(xhci);
1029 /* Don't poll the roothubs on bus suspend. */
1030 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1031 __func__, hcd->self.busnum);
1032 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1033 del_timer_sync(&hcd->rh_timer);
1034 if (xhci->shared_hcd) {
1035 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1036 del_timer_sync(&xhci->shared_hcd->rh_timer);
1039 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1040 usleep_range(1000, 1500);
1042 spin_lock_irq(&xhci->lock);
1043 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1044 if (xhci->shared_hcd)
1045 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1046 /* step 1: stop endpoint */
1047 /* skipped assuming that port suspend has done */
1049 /* step 2: clear Run/Stop bit */
1050 command = readl(&xhci->op_regs->command);
1051 command &= ~CMD_RUN;
1052 writel(command, &xhci->op_regs->command);
1054 /* Some chips from Fresco Logic need an extraordinary delay */
1055 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1057 if (xhci_handshake(&xhci->op_regs->status,
1058 STS_HALT, STS_HALT, delay)) {
1059 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1060 spin_unlock_irq(&xhci->lock);
1063 xhci_clear_command_ring(xhci);
1065 /* step 3: save registers */
1066 xhci_save_registers(xhci);
1068 /* step 4: set CSS flag */
1069 command = readl(&xhci->op_regs->command);
1071 writel(command, &xhci->op_regs->command);
1072 xhci->broken_suspend = 0;
1073 if (xhci_handshake(&xhci->op_regs->status,
1074 STS_SAVE, 0, 20 * 1000)) {
1076 * AMD SNPS xHC 3.0 occasionally does not clear the
1077 * SSS bit of USBSTS and when driver tries to poll
1078 * to see if the xHC clears BIT(8) which never happens
1079 * and driver assumes that controller is not responding
1080 * and times out. To workaround this, its good to check
1081 * if SRE and HCE bits are not set (as per xhci
1082 * Section 5.4.2) and bypass the timeout.
1084 res = readl(&xhci->op_regs->status);
1085 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1086 (((res & STS_SRE) == 0) &&
1087 ((res & STS_HCE) == 0))) {
1088 xhci->broken_suspend = 1;
1090 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1091 spin_unlock_irq(&xhci->lock);
1095 spin_unlock_irq(&xhci->lock);
1098 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1099 * is about to be suspended.
1101 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1102 (!(xhci_all_ports_seen_u0(xhci)))) {
1103 del_timer_sync(&xhci->comp_mode_recovery_timer);
1104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1105 "%s: compliance mode recovery timer deleted",
1109 /* step 5: remove core well power */
1110 /* synchronize irq when using MSI-X */
1111 xhci_msix_sync_irqs(xhci);
1115 EXPORT_SYMBOL_GPL(xhci_suspend);
1118 * start xHC (not bus-specific)
1120 * This is called when the machine transition from S3/S4 mode.
1123 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1125 u32 command, temp = 0;
1126 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1128 bool comp_timer_running = false;
1129 bool pending_portevent = false;
1130 bool reinit_xhc = false;
1135 /* Wait a bit if either of the roothubs need to settle from the
1136 * transition into bus suspend.
1139 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1140 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1143 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1144 if (xhci->shared_hcd)
1145 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1147 spin_lock_irq(&xhci->lock);
1149 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1154 * Some controllers might lose power during suspend, so wait
1155 * for controller not ready bit to clear, just as in xHC init.
1157 retval = xhci_handshake(&xhci->op_regs->status,
1158 STS_CNR, 0, 10 * 1000 * 1000);
1160 xhci_warn(xhci, "Controller not ready at resume %d\n",
1162 spin_unlock_irq(&xhci->lock);
1165 /* step 1: restore register */
1166 xhci_restore_registers(xhci);
1167 /* step 2: initialize command ring buffer */
1168 xhci_set_cmd_ring_deq(xhci);
1169 /* step 3: restore state and start state*/
1170 /* step 3: set CRS flag */
1171 command = readl(&xhci->op_regs->command);
1173 writel(command, &xhci->op_regs->command);
1175 * Some controllers take up to 55+ ms to complete the controller
1176 * restore so setting the timeout to 100ms. Xhci specification
1177 * doesn't mention any timeout value.
1179 if (xhci_handshake(&xhci->op_regs->status,
1180 STS_RESTORE, 0, 100 * 1000)) {
1181 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1182 spin_unlock_irq(&xhci->lock);
1187 temp = readl(&xhci->op_regs->status);
1189 /* re-initialize the HC on Restore Error, or Host Controller Error */
1190 if (temp & (STS_SRE | STS_HCE)) {
1192 if (!xhci->broken_suspend)
1193 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1197 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1198 !(xhci_all_ports_seen_u0(xhci))) {
1199 del_timer_sync(&xhci->comp_mode_recovery_timer);
1200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1201 "Compliance Mode Recovery Timer deleted!");
1204 /* Let the USB core know _both_ roothubs lost power. */
1205 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1206 if (xhci->shared_hcd)
1207 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1209 xhci_dbg(xhci, "Stop HCD\n");
1211 xhci_zero_64b_regs(xhci);
1212 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1213 spin_unlock_irq(&xhci->lock);
1216 xhci_cleanup_msix(xhci);
1218 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1219 temp = readl(&xhci->op_regs->status);
1220 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1221 temp = readl(&xhci->ir_set->irq_pending);
1222 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1224 xhci_dbg(xhci, "cleaning up memory\n");
1225 xhci_mem_cleanup(xhci);
1226 xhci_debugfs_exit(xhci);
1227 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1228 readl(&xhci->op_regs->status));
1230 /* USB core calls the PCI reinit and start functions twice:
1231 * first with the primary HCD, and then with the secondary HCD.
1232 * If we don't do the same, the host will never be started.
1234 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1235 retval = xhci_init(hcd);
1238 comp_timer_running = true;
1240 xhci_dbg(xhci, "Start the primary HCD\n");
1241 retval = xhci_run(hcd);
1242 if (!retval && xhci->shared_hcd) {
1243 xhci_dbg(xhci, "Start the secondary HCD\n");
1244 retval = xhci_run(xhci->shared_hcd);
1247 hcd->state = HC_STATE_SUSPENDED;
1248 if (xhci->shared_hcd)
1249 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1253 /* step 4: set Run/Stop bit */
1254 command = readl(&xhci->op_regs->command);
1256 writel(command, &xhci->op_regs->command);
1257 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1260 /* step 5: walk topology and initialize portsc,
1261 * portpmsc and portli
1263 /* this is done in bus_resume */
1265 /* step 6: restart each of the previously
1266 * Running endpoints by ringing their doorbells
1269 spin_unlock_irq(&xhci->lock);
1271 xhci_dbc_resume(xhci);
1276 * Resume roothubs only if there are pending events.
1277 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1278 * the first wake signalling failed, give it that chance.
1280 pending_portevent = xhci_pending_portevent(xhci);
1281 if (!pending_portevent) {
1283 pending_portevent = xhci_pending_portevent(xhci);
1286 if (pending_portevent) {
1287 if (xhci->shared_hcd)
1288 usb_hcd_resume_root_hub(xhci->shared_hcd);
1289 usb_hcd_resume_root_hub(hcd);
1293 * If system is subject to the Quirk, Compliance Mode Timer needs to
1294 * be re-initialized Always after a system resume. Ports are subject
1295 * to suffer the Compliance Mode issue again. It doesn't matter if
1296 * ports have entered previously to U0 before system's suspension.
1298 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1299 compliance_mode_recovery_timer_init(xhci);
1301 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1302 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1304 /* Re-enable port polling. */
1305 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1306 __func__, hcd->self.busnum);
1307 if (xhci->shared_hcd) {
1308 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1309 usb_hcd_poll_rh_status(xhci->shared_hcd);
1311 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1312 usb_hcd_poll_rh_status(hcd);
1316 EXPORT_SYMBOL_GPL(xhci_resume);
1317 #endif /* CONFIG_PM */
1319 /*-------------------------------------------------------------------------*/
1321 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1325 unsigned int buf_len;
1326 enum dma_data_direction dir;
1328 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1329 buf_len = urb->transfer_buffer_length;
1331 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1332 dev_to_node(hcd->self.sysdev));
1334 if (usb_urb_dir_out(urb))
1335 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1338 urb->transfer_buffer = temp;
1339 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1340 urb->transfer_buffer,
1341 urb->transfer_buffer_length,
1344 if (dma_mapping_error(hcd->self.sysdev,
1345 urb->transfer_dma)) {
1349 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1355 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1360 unsigned int len = 0;
1361 unsigned int trb_size;
1362 unsigned int max_pkt;
1363 struct scatterlist *sg;
1364 struct scatterlist *tail_sg;
1367 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1372 if (urb->dev->speed >= USB_SPEED_SUPER)
1373 trb_size = TRB_CACHE_SIZE_SS;
1375 trb_size = TRB_CACHE_SIZE_HS;
1377 if (urb->transfer_buffer_length != 0 &&
1378 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1379 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1380 len = len + sg->length;
1381 if (i > trb_size - 2) {
1382 len = len - tail_sg->length;
1383 if (len < max_pkt) {
1388 tail_sg = sg_next(tail_sg);
1395 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1398 unsigned int buf_len;
1399 enum dma_data_direction dir;
1401 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1403 buf_len = urb->transfer_buffer_length;
1405 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1406 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1407 dma_unmap_single(hcd->self.sysdev,
1409 urb->transfer_buffer_length,
1412 if (usb_urb_dir_in(urb)) {
1413 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1414 urb->transfer_buffer,
1417 if (len != buf_len) {
1418 xhci_dbg(hcd_to_xhci(hcd),
1419 "Copy from tmp buf to urb sg list failed\n");
1420 urb->actual_length = len;
1423 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1424 kfree(urb->transfer_buffer);
1425 urb->transfer_buffer = NULL;
1429 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1430 * we'll copy the actual data into the TRB address register. This is limited to
1431 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1432 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1434 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1437 struct xhci_hcd *xhci;
1439 xhci = hcd_to_xhci(hcd);
1441 if (xhci_urb_suitable_for_idt(urb))
1444 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1445 if (xhci_urb_temp_buffer_required(hcd, urb))
1446 return xhci_map_temp_buffer(hcd, urb);
1448 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1451 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1453 struct xhci_hcd *xhci;
1454 bool unmap_temp_buf = false;
1456 xhci = hcd_to_xhci(hcd);
1458 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1459 unmap_temp_buf = true;
1461 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1462 xhci_unmap_temp_buf(hcd, urb);
1464 usb_hcd_unmap_urb_for_dma(hcd, urb);
1468 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1469 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1470 * value to right shift 1 for the bitmask.
1472 * Index = (epnum * 2) + direction - 1,
1473 * where direction = 0 for OUT, 1 for IN.
1474 * For control endpoints, the IN index is used (OUT index is unused), so
1475 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1477 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1480 if (usb_endpoint_xfer_control(desc))
1481 index = (unsigned int) (usb_endpoint_num(desc)*2);
1483 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1484 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1487 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1489 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1490 * address from the XHCI endpoint index.
1492 static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1494 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1495 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1496 return direction | number;
1499 /* Find the flag for this endpoint (for use in the control context). Use the
1500 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1503 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1505 return 1 << (xhci_get_endpoint_index(desc) + 1);
1508 /* Compute the last valid endpoint context index. Basically, this is the
1509 * endpoint index plus one. For slot contexts with more than valid endpoint,
1510 * we find the most significant bit set in the added contexts flags.
1511 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1512 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1514 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1516 return fls(added_ctxs) - 1;
1519 /* Returns 1 if the arguments are OK;
1520 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1522 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1523 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1525 struct xhci_hcd *xhci;
1526 struct xhci_virt_device *virt_dev;
1528 if (!hcd || (check_ep && !ep) || !udev) {
1529 pr_debug("xHCI %s called with invalid args\n", func);
1532 if (!udev->parent) {
1533 pr_debug("xHCI %s called for root hub\n", func);
1537 xhci = hcd_to_xhci(hcd);
1538 if (check_virt_dev) {
1539 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1540 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1545 virt_dev = xhci->devs[udev->slot_id];
1546 if (virt_dev->udev != udev) {
1547 xhci_dbg(xhci, "xHCI %s called with udev and "
1548 "virt_dev does not match\n", func);
1553 if (xhci->xhc_state & XHCI_STATE_HALTED)
1559 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1560 struct usb_device *udev, struct xhci_command *command,
1561 bool ctx_change, bool must_succeed);
1564 * Full speed devices may have a max packet size greater than 8 bytes, but the
1565 * USB core doesn't know that until it reads the first 8 bytes of the
1566 * descriptor. If the usb_device's max packet size changes after that point,
1567 * we need to issue an evaluate context command and wait on it.
1569 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1570 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1572 struct xhci_container_ctx *out_ctx;
1573 struct xhci_input_control_ctx *ctrl_ctx;
1574 struct xhci_ep_ctx *ep_ctx;
1575 struct xhci_command *command;
1576 int max_packet_size;
1577 int hw_max_packet_size;
1580 out_ctx = xhci->devs[slot_id]->out_ctx;
1581 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1582 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1583 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1584 if (hw_max_packet_size != max_packet_size) {
1585 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1586 "Max Packet Size for ep 0 changed.");
1587 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1588 "Max packet size in usb_device = %d",
1590 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1591 "Max packet size in xHCI HW = %d",
1592 hw_max_packet_size);
1593 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1594 "Issuing evaluate context command.");
1596 /* Set up the input context flags for the command */
1597 /* FIXME: This won't work if a non-default control endpoint
1598 * changes max packet sizes.
1601 command = xhci_alloc_command(xhci, true, mem_flags);
1605 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1606 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1608 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1611 goto command_cleanup;
1613 /* Set up the modified control endpoint 0 */
1614 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1615 xhci->devs[slot_id]->out_ctx, ep_index);
1617 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1618 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1619 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1620 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1622 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1623 ctrl_ctx->drop_flags = 0;
1625 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1628 /* Clean up the input context for later use by bandwidth
1631 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1633 kfree(command->completion);
1640 * non-error returns are a promise to giveback() the urb later
1641 * we drop ownership so next owner (or urb unlink) can get it
1643 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1646 unsigned long flags;
1648 unsigned int slot_id, ep_index;
1649 unsigned int *ep_state;
1650 struct urb_priv *urb_priv;
1655 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1656 true, true, __func__);
1658 return ret ? ret : -EINVAL;
1660 slot_id = urb->dev->slot_id;
1661 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1662 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1664 if (!HCD_HW_ACCESSIBLE(hcd))
1667 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1668 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1672 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1673 num_tds = urb->number_of_packets;
1674 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1675 urb->transfer_buffer_length > 0 &&
1676 urb->transfer_flags & URB_ZERO_PACKET &&
1677 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1682 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1686 urb_priv->num_tds = num_tds;
1687 urb_priv->num_tds_done = 0;
1688 urb->hcpriv = urb_priv;
1690 trace_xhci_urb_enqueue(urb);
1692 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1693 /* Check to see if the max packet size for the default control
1694 * endpoint changed during FS device enumeration
1696 if (urb->dev->speed == USB_SPEED_FULL) {
1697 ret = xhci_check_maxpacket(xhci, slot_id,
1698 ep_index, urb, mem_flags);
1700 xhci_urb_free_priv(urb_priv);
1707 spin_lock_irqsave(&xhci->lock, flags);
1709 if (xhci->xhc_state & XHCI_STATE_DYING) {
1710 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1711 urb->ep->desc.bEndpointAddress, urb);
1715 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1716 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1721 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1722 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1727 switch (usb_endpoint_type(&urb->ep->desc)) {
1729 case USB_ENDPOINT_XFER_CONTROL:
1730 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1733 case USB_ENDPOINT_XFER_BULK:
1734 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1737 case USB_ENDPOINT_XFER_INT:
1738 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1741 case USB_ENDPOINT_XFER_ISOC:
1742 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1748 xhci_urb_free_priv(urb_priv);
1751 spin_unlock_irqrestore(&xhci->lock, flags);
1756 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1757 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1758 * should pick up where it left off in the TD, unless a Set Transfer Ring
1759 * Dequeue Pointer is issued.
1761 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1762 * the ring. Since the ring is a contiguous structure, they can't be physically
1763 * removed. Instead, there are two options:
1765 * 1) If the HC is in the middle of processing the URB to be canceled, we
1766 * simply move the ring's dequeue pointer past those TRBs using the Set
1767 * Transfer Ring Dequeue Pointer command. This will be the common case,
1768 * when drivers timeout on the last submitted URB and attempt to cancel.
1770 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1771 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1772 * HC will need to invalidate the any TRBs it has cached after the stop
1773 * endpoint command, as noted in the xHCI 0.95 errata.
1775 * 3) The TD may have completed by the time the Stop Endpoint Command
1776 * completes, so software needs to handle that case too.
1778 * This function should protect against the TD enqueueing code ringing the
1779 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1780 * It also needs to account for multiple cancellations on happening at the same
1781 * time for the same endpoint.
1783 * Note that this function can be called in any context, or so says
1784 * usb_hcd_unlink_urb()
1786 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1788 unsigned long flags;
1791 struct xhci_hcd *xhci;
1792 struct urb_priv *urb_priv;
1794 unsigned int ep_index;
1795 struct xhci_ring *ep_ring;
1796 struct xhci_virt_ep *ep;
1797 struct xhci_command *command;
1798 struct xhci_virt_device *vdev;
1800 xhci = hcd_to_xhci(hcd);
1801 spin_lock_irqsave(&xhci->lock, flags);
1803 trace_xhci_urb_dequeue(urb);
1805 /* Make sure the URB hasn't completed or been unlinked already */
1806 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1810 /* give back URB now if we can't queue it for cancel */
1811 vdev = xhci->devs[urb->dev->slot_id];
1812 urb_priv = urb->hcpriv;
1813 if (!vdev || !urb_priv)
1816 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1817 ep = &vdev->eps[ep_index];
1818 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1819 if (!ep || !ep_ring)
1822 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1823 temp = readl(&xhci->op_regs->status);
1824 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1830 * check ring is not re-allocated since URB was enqueued. If it is, then
1831 * make sure none of the ring related pointers in this URB private data
1832 * are touched, such as td_list, otherwise we overwrite freed data
1834 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1835 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1836 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1837 td = &urb_priv->td[i];
1838 if (!list_empty(&td->cancelled_td_list))
1839 list_del_init(&td->cancelled_td_list);
1844 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1845 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1846 "HC halted, freeing TD manually.");
1847 for (i = urb_priv->num_tds_done;
1848 i < urb_priv->num_tds;
1850 td = &urb_priv->td[i];
1851 if (!list_empty(&td->td_list))
1852 list_del_init(&td->td_list);
1853 if (!list_empty(&td->cancelled_td_list))
1854 list_del_init(&td->cancelled_td_list);
1859 i = urb_priv->num_tds_done;
1860 if (i < urb_priv->num_tds)
1861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1862 "Cancel URB %p, dev %s, ep 0x%x, "
1863 "starting at offset 0x%llx",
1864 urb, urb->dev->devpath,
1865 urb->ep->desc.bEndpointAddress,
1866 (unsigned long long) xhci_trb_virt_to_dma(
1867 urb_priv->td[i].start_seg,
1868 urb_priv->td[i].first_trb));
1870 for (; i < urb_priv->num_tds; i++) {
1871 td = &urb_priv->td[i];
1872 /* TD can already be on cancelled list if ep halted on it */
1873 if (list_empty(&td->cancelled_td_list)) {
1874 td->cancel_status = TD_DIRTY;
1875 list_add_tail(&td->cancelled_td_list,
1876 &ep->cancelled_td_list);
1880 /* Queue a stop endpoint command, but only if this is
1881 * the first cancellation to be handled.
1883 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1884 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1889 ep->ep_state |= EP_STOP_CMD_PENDING;
1890 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1892 xhci_ring_cmd_db(xhci);
1895 spin_unlock_irqrestore(&xhci->lock, flags);
1900 xhci_urb_free_priv(urb_priv);
1901 usb_hcd_unlink_urb_from_ep(hcd, urb);
1902 spin_unlock_irqrestore(&xhci->lock, flags);
1903 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1907 /* Drop an endpoint from a new bandwidth configuration for this device.
1908 * Only one call to this function is allowed per endpoint before
1909 * check_bandwidth() or reset_bandwidth() must be called.
1910 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1911 * add the endpoint to the schedule with possibly new parameters denoted by a
1912 * different endpoint descriptor in usb_host_endpoint.
1913 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1916 * The USB core will not allow URBs to be queued to an endpoint that is being
1917 * disabled, so there's no need for mutual exclusion to protect
1918 * the xhci->devs[slot_id] structure.
1920 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1921 struct usb_host_endpoint *ep)
1923 struct xhci_hcd *xhci;
1924 struct xhci_container_ctx *in_ctx, *out_ctx;
1925 struct xhci_input_control_ctx *ctrl_ctx;
1926 unsigned int ep_index;
1927 struct xhci_ep_ctx *ep_ctx;
1929 u32 new_add_flags, new_drop_flags;
1932 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1935 xhci = hcd_to_xhci(hcd);
1936 if (xhci->xhc_state & XHCI_STATE_DYING)
1939 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1940 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1941 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1942 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1943 __func__, drop_flag);
1947 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1948 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1949 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1951 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1956 ep_index = xhci_get_endpoint_index(&ep->desc);
1957 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1958 /* If the HC already knows the endpoint is disabled,
1959 * or the HCD has noted it is disabled, ignore this request
1961 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1962 le32_to_cpu(ctrl_ctx->drop_flags) &
1963 xhci_get_endpoint_flag(&ep->desc)) {
1964 /* Do not warn when called after a usb_device_reset */
1965 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1966 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1971 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1972 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1974 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1975 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1977 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1979 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1981 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1982 (unsigned int) ep->desc.bEndpointAddress,
1984 (unsigned int) new_drop_flags,
1985 (unsigned int) new_add_flags);
1988 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1990 /* Add an endpoint to a new possible bandwidth configuration for this device.
1991 * Only one call to this function is allowed per endpoint before
1992 * check_bandwidth() or reset_bandwidth() must be called.
1993 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1994 * add the endpoint to the schedule with possibly new parameters denoted by a
1995 * different endpoint descriptor in usb_host_endpoint.
1996 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1999 * The USB core will not allow URBs to be queued to an endpoint until the
2000 * configuration or alt setting is installed in the device, so there's no need
2001 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2003 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2004 struct usb_host_endpoint *ep)
2006 struct xhci_hcd *xhci;
2007 struct xhci_container_ctx *in_ctx;
2008 unsigned int ep_index;
2009 struct xhci_input_control_ctx *ctrl_ctx;
2010 struct xhci_ep_ctx *ep_ctx;
2012 u32 new_add_flags, new_drop_flags;
2013 struct xhci_virt_device *virt_dev;
2016 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2018 /* So we won't queue a reset ep command for a root hub */
2022 xhci = hcd_to_xhci(hcd);
2023 if (xhci->xhc_state & XHCI_STATE_DYING)
2026 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2027 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2028 /* FIXME when we have to issue an evaluate endpoint command to
2029 * deal with ep0 max packet size changing once we get the
2032 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2033 __func__, added_ctxs);
2037 virt_dev = xhci->devs[udev->slot_id];
2038 in_ctx = virt_dev->in_ctx;
2039 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2041 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2046 ep_index = xhci_get_endpoint_index(&ep->desc);
2047 /* If this endpoint is already in use, and the upper layers are trying
2048 * to add it again without dropping it, reject the addition.
2050 if (virt_dev->eps[ep_index].ring &&
2051 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2052 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2053 "without dropping it.\n",
2054 (unsigned int) ep->desc.bEndpointAddress);
2058 /* If the HCD has already noted the endpoint is enabled,
2059 * ignore this request.
2061 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2062 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2068 * Configuration and alternate setting changes must be done in
2069 * process context, not interrupt context (or so documenation
2070 * for usb_set_interface() and usb_set_configuration() claim).
2072 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2073 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2074 __func__, ep->desc.bEndpointAddress);
2078 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2079 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2081 /* If xhci_endpoint_disable() was called for this endpoint, but the
2082 * xHC hasn't been notified yet through the check_bandwidth() call,
2083 * this re-adds a new state for the endpoint from the new endpoint
2084 * descriptors. We must drop and re-add this endpoint, so we leave the
2087 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2089 /* Store the usb_device pointer for later use */
2092 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2093 trace_xhci_add_endpoint(ep_ctx);
2095 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2096 (unsigned int) ep->desc.bEndpointAddress,
2098 (unsigned int) new_drop_flags,
2099 (unsigned int) new_add_flags);
2102 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2104 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2106 struct xhci_input_control_ctx *ctrl_ctx;
2107 struct xhci_ep_ctx *ep_ctx;
2108 struct xhci_slot_ctx *slot_ctx;
2111 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2113 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2118 /* When a device's add flag and drop flag are zero, any subsequent
2119 * configure endpoint command will leave that endpoint's state
2120 * untouched. Make sure we don't leave any old state in the input
2121 * endpoint contexts.
2123 ctrl_ctx->drop_flags = 0;
2124 ctrl_ctx->add_flags = 0;
2125 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2126 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2127 /* Endpoint 0 is always valid */
2128 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2129 for (i = 1; i < 31; i++) {
2130 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2131 ep_ctx->ep_info = 0;
2132 ep_ctx->ep_info2 = 0;
2134 ep_ctx->tx_info = 0;
2138 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2139 struct usb_device *udev, u32 *cmd_status)
2143 switch (*cmd_status) {
2144 case COMP_COMMAND_ABORTED:
2145 case COMP_COMMAND_RING_STOPPED:
2146 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2149 case COMP_RESOURCE_ERROR:
2150 dev_warn(&udev->dev,
2151 "Not enough host controller resources for new device state.\n");
2153 /* FIXME: can we allocate more resources for the HC? */
2155 case COMP_BANDWIDTH_ERROR:
2156 case COMP_SECONDARY_BANDWIDTH_ERROR:
2157 dev_warn(&udev->dev,
2158 "Not enough bandwidth for new device state.\n");
2160 /* FIXME: can we go back to the old state? */
2162 case COMP_TRB_ERROR:
2163 /* the HCD set up something wrong */
2164 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2166 "and endpoint is not disabled.\n");
2169 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2170 dev_warn(&udev->dev,
2171 "ERROR: Incompatible device for endpoint configure command.\n");
2175 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2176 "Successful Endpoint Configure command");
2180 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2188 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2189 struct usb_device *udev, u32 *cmd_status)
2193 switch (*cmd_status) {
2194 case COMP_COMMAND_ABORTED:
2195 case COMP_COMMAND_RING_STOPPED:
2196 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2199 case COMP_PARAMETER_ERROR:
2200 dev_warn(&udev->dev,
2201 "WARN: xHCI driver setup invalid evaluate context command.\n");
2204 case COMP_SLOT_NOT_ENABLED_ERROR:
2205 dev_warn(&udev->dev,
2206 "WARN: slot not enabled for evaluate context command.\n");
2209 case COMP_CONTEXT_STATE_ERROR:
2210 dev_warn(&udev->dev,
2211 "WARN: invalid context state for evaluate context command.\n");
2214 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2215 dev_warn(&udev->dev,
2216 "ERROR: Incompatible device for evaluate context command.\n");
2219 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2220 /* Max Exit Latency too large error */
2221 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2225 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2226 "Successful evaluate context command");
2230 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2238 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2239 struct xhci_input_control_ctx *ctrl_ctx)
2241 u32 valid_add_flags;
2242 u32 valid_drop_flags;
2244 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2245 * (bit 1). The default control endpoint is added during the Address
2246 * Device command and is never removed until the slot is disabled.
2248 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2249 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2251 /* Use hweight32 to count the number of ones in the add flags, or
2252 * number of endpoints added. Don't count endpoints that are changed
2253 * (both added and dropped).
2255 return hweight32(valid_add_flags) -
2256 hweight32(valid_add_flags & valid_drop_flags);
2259 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2260 struct xhci_input_control_ctx *ctrl_ctx)
2262 u32 valid_add_flags;
2263 u32 valid_drop_flags;
2265 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2266 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2268 return hweight32(valid_drop_flags) -
2269 hweight32(valid_add_flags & valid_drop_flags);
2273 * We need to reserve the new number of endpoints before the configure endpoint
2274 * command completes. We can't subtract the dropped endpoints from the number
2275 * of active endpoints until the command completes because we can oversubscribe
2276 * the host in this case:
2278 * - the first configure endpoint command drops more endpoints than it adds
2279 * - a second configure endpoint command that adds more endpoints is queued
2280 * - the first configure endpoint command fails, so the config is unchanged
2281 * - the second command may succeed, even though there isn't enough resources
2283 * Must be called with xhci->lock held.
2285 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2286 struct xhci_input_control_ctx *ctrl_ctx)
2290 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2291 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2292 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2293 "Not enough ep ctxs: "
2294 "%u active, need to add %u, limit is %u.",
2295 xhci->num_active_eps, added_eps,
2296 xhci->limit_active_eps);
2299 xhci->num_active_eps += added_eps;
2300 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2301 "Adding %u ep ctxs, %u now active.", added_eps,
2302 xhci->num_active_eps);
2307 * The configure endpoint was failed by the xHC for some other reason, so we
2308 * need to revert the resources that failed configuration would have used.
2310 * Must be called with xhci->lock held.
2312 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2313 struct xhci_input_control_ctx *ctrl_ctx)
2317 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2318 xhci->num_active_eps -= num_failed_eps;
2319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2320 "Removing %u failed ep ctxs, %u now active.",
2322 xhci->num_active_eps);
2326 * Now that the command has completed, clean up the active endpoint count by
2327 * subtracting out the endpoints that were dropped (but not changed).
2329 * Must be called with xhci->lock held.
2331 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2332 struct xhci_input_control_ctx *ctrl_ctx)
2334 u32 num_dropped_eps;
2336 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2337 xhci->num_active_eps -= num_dropped_eps;
2338 if (num_dropped_eps)
2339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2340 "Removing %u dropped ep ctxs, %u now active.",
2342 xhci->num_active_eps);
2345 static unsigned int xhci_get_block_size(struct usb_device *udev)
2347 switch (udev->speed) {
2349 case USB_SPEED_FULL:
2351 case USB_SPEED_HIGH:
2353 case USB_SPEED_SUPER:
2354 case USB_SPEED_SUPER_PLUS:
2356 case USB_SPEED_UNKNOWN:
2357 case USB_SPEED_WIRELESS:
2359 /* Should never happen */
2365 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2367 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2369 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2374 /* If we are changing a LS/FS device under a HS hub,
2375 * make sure (if we are activating a new TT) that the HS bus has enough
2376 * bandwidth for this new TT.
2378 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2379 struct xhci_virt_device *virt_dev,
2382 struct xhci_interval_bw_table *bw_table;
2383 struct xhci_tt_bw_info *tt_info;
2385 /* Find the bandwidth table for the root port this TT is attached to. */
2386 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2387 tt_info = virt_dev->tt_info;
2388 /* If this TT already had active endpoints, the bandwidth for this TT
2389 * has already been added. Removing all periodic endpoints (and thus
2390 * making the TT enactive) will only decrease the bandwidth used.
2394 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2395 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2399 /* Not sure why we would have no new active endpoints...
2401 * Maybe because of an Evaluate Context change for a hub update or a
2402 * control endpoint 0 max packet size change?
2403 * FIXME: skip the bandwidth calculation in that case.
2408 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2409 struct xhci_virt_device *virt_dev)
2411 unsigned int bw_reserved;
2413 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2414 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2417 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2418 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2425 * This algorithm is a very conservative estimate of the worst-case scheduling
2426 * scenario for any one interval. The hardware dynamically schedules the
2427 * packets, so we can't tell which microframe could be the limiting factor in
2428 * the bandwidth scheduling. This only takes into account periodic endpoints.
2430 * Obviously, we can't solve an NP complete problem to find the minimum worst
2431 * case scenario. Instead, we come up with an estimate that is no less than
2432 * the worst case bandwidth used for any one microframe, but may be an
2435 * We walk the requirements for each endpoint by interval, starting with the
2436 * smallest interval, and place packets in the schedule where there is only one
2437 * possible way to schedule packets for that interval. In order to simplify
2438 * this algorithm, we record the largest max packet size for each interval, and
2439 * assume all packets will be that size.
2441 * For interval 0, we obviously must schedule all packets for each interval.
2442 * The bandwidth for interval 0 is just the amount of data to be transmitted
2443 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2444 * the number of packets).
2446 * For interval 1, we have two possible microframes to schedule those packets
2447 * in. For this algorithm, if we can schedule the same number of packets for
2448 * each possible scheduling opportunity (each microframe), we will do so. The
2449 * remaining number of packets will be saved to be transmitted in the gaps in
2450 * the next interval's scheduling sequence.
2452 * As we move those remaining packets to be scheduled with interval 2 packets,
2453 * we have to double the number of remaining packets to transmit. This is
2454 * because the intervals are actually powers of 2, and we would be transmitting
2455 * the previous interval's packets twice in this interval. We also have to be
2456 * sure that when we look at the largest max packet size for this interval, we
2457 * also look at the largest max packet size for the remaining packets and take
2458 * the greater of the two.
2460 * The algorithm continues to evenly distribute packets in each scheduling
2461 * opportunity, and push the remaining packets out, until we get to the last
2462 * interval. Then those packets and their associated overhead are just added
2463 * to the bandwidth used.
2465 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2466 struct xhci_virt_device *virt_dev,
2469 unsigned int bw_reserved;
2470 unsigned int max_bandwidth;
2471 unsigned int bw_used;
2472 unsigned int block_size;
2473 struct xhci_interval_bw_table *bw_table;
2474 unsigned int packet_size = 0;
2475 unsigned int overhead = 0;
2476 unsigned int packets_transmitted = 0;
2477 unsigned int packets_remaining = 0;
2480 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2481 return xhci_check_ss_bw(xhci, virt_dev);
2483 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2484 max_bandwidth = HS_BW_LIMIT;
2485 /* Convert percent of bus BW reserved to blocks reserved */
2486 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2488 max_bandwidth = FS_BW_LIMIT;
2489 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2492 bw_table = virt_dev->bw_table;
2493 /* We need to translate the max packet size and max ESIT payloads into
2494 * the units the hardware uses.
2496 block_size = xhci_get_block_size(virt_dev->udev);
2498 /* If we are manipulating a LS/FS device under a HS hub, double check
2499 * that the HS bus has enough bandwidth if we are activing a new TT.
2501 if (virt_dev->tt_info) {
2502 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2503 "Recalculating BW for rootport %u",
2504 virt_dev->real_port);
2505 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2506 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2507 "newly activated TT.\n");
2510 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2511 "Recalculating BW for TT slot %u port %u",
2512 virt_dev->tt_info->slot_id,
2513 virt_dev->tt_info->ttport);
2515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2516 "Recalculating BW for rootport %u",
2517 virt_dev->real_port);
2520 /* Add in how much bandwidth will be used for interval zero, or the
2521 * rounded max ESIT payload + number of packets * largest overhead.
2523 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2524 bw_table->interval_bw[0].num_packets *
2525 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2527 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2528 unsigned int bw_added;
2529 unsigned int largest_mps;
2530 unsigned int interval_overhead;
2533 * How many packets could we transmit in this interval?
2534 * If packets didn't fit in the previous interval, we will need
2535 * to transmit that many packets twice within this interval.
2537 packets_remaining = 2 * packets_remaining +
2538 bw_table->interval_bw[i].num_packets;
2540 /* Find the largest max packet size of this or the previous
2543 if (list_empty(&bw_table->interval_bw[i].endpoints))
2546 struct xhci_virt_ep *virt_ep;
2547 struct list_head *ep_entry;
2549 ep_entry = bw_table->interval_bw[i].endpoints.next;
2550 virt_ep = list_entry(ep_entry,
2551 struct xhci_virt_ep, bw_endpoint_list);
2552 /* Convert to blocks, rounding up */
2553 largest_mps = DIV_ROUND_UP(
2554 virt_ep->bw_info.max_packet_size,
2557 if (largest_mps > packet_size)
2558 packet_size = largest_mps;
2560 /* Use the larger overhead of this or the previous interval. */
2561 interval_overhead = xhci_get_largest_overhead(
2562 &bw_table->interval_bw[i]);
2563 if (interval_overhead > overhead)
2564 overhead = interval_overhead;
2566 /* How many packets can we evenly distribute across
2567 * (1 << (i + 1)) possible scheduling opportunities?
2569 packets_transmitted = packets_remaining >> (i + 1);
2571 /* Add in the bandwidth used for those scheduled packets */
2572 bw_added = packets_transmitted * (overhead + packet_size);
2574 /* How many packets do we have remaining to transmit? */
2575 packets_remaining = packets_remaining % (1 << (i + 1));
2577 /* What largest max packet size should those packets have? */
2578 /* If we've transmitted all packets, don't carry over the
2579 * largest packet size.
2581 if (packets_remaining == 0) {
2584 } else if (packets_transmitted > 0) {
2585 /* Otherwise if we do have remaining packets, and we've
2586 * scheduled some packets in this interval, take the
2587 * largest max packet size from endpoints with this
2590 packet_size = largest_mps;
2591 overhead = interval_overhead;
2593 /* Otherwise carry over packet_size and overhead from the last
2594 * time we had a remainder.
2596 bw_used += bw_added;
2597 if (bw_used > max_bandwidth) {
2598 xhci_warn(xhci, "Not enough bandwidth. "
2599 "Proposed: %u, Max: %u\n",
2600 bw_used, max_bandwidth);
2605 * Ok, we know we have some packets left over after even-handedly
2606 * scheduling interval 15. We don't know which microframes they will
2607 * fit into, so we over-schedule and say they will be scheduled every
2610 if (packets_remaining > 0)
2611 bw_used += overhead + packet_size;
2613 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2614 unsigned int port_index = virt_dev->real_port - 1;
2616 /* OK, we're manipulating a HS device attached to a
2617 * root port bandwidth domain. Include the number of active TTs
2618 * in the bandwidth used.
2620 bw_used += TT_HS_OVERHEAD *
2621 xhci->rh_bw[port_index].num_active_tts;
2624 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2625 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2626 "Available: %u " "percent",
2627 bw_used, max_bandwidth, bw_reserved,
2628 (max_bandwidth - bw_used - bw_reserved) * 100 /
2631 bw_used += bw_reserved;
2632 if (bw_used > max_bandwidth) {
2633 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2634 bw_used, max_bandwidth);
2638 bw_table->bw_used = bw_used;
2642 static bool xhci_is_async_ep(unsigned int ep_type)
2644 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2645 ep_type != ISOC_IN_EP &&
2646 ep_type != INT_IN_EP);
2649 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2651 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2654 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2656 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2658 if (ep_bw->ep_interval == 0)
2659 return SS_OVERHEAD_BURST +
2660 (ep_bw->mult * ep_bw->num_packets *
2661 (SS_OVERHEAD + mps));
2662 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2663 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2664 1 << ep_bw->ep_interval);
2668 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2669 struct xhci_bw_info *ep_bw,
2670 struct xhci_interval_bw_table *bw_table,
2671 struct usb_device *udev,
2672 struct xhci_virt_ep *virt_ep,
2673 struct xhci_tt_bw_info *tt_info)
2675 struct xhci_interval_bw *interval_bw;
2676 int normalized_interval;
2678 if (xhci_is_async_ep(ep_bw->type))
2681 if (udev->speed >= USB_SPEED_SUPER) {
2682 if (xhci_is_sync_in_ep(ep_bw->type))
2683 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2684 xhci_get_ss_bw_consumed(ep_bw);
2686 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2687 xhci_get_ss_bw_consumed(ep_bw);
2691 /* SuperSpeed endpoints never get added to intervals in the table, so
2692 * this check is only valid for HS/FS/LS devices.
2694 if (list_empty(&virt_ep->bw_endpoint_list))
2696 /* For LS/FS devices, we need to translate the interval expressed in
2697 * microframes to frames.
2699 if (udev->speed == USB_SPEED_HIGH)
2700 normalized_interval = ep_bw->ep_interval;
2702 normalized_interval = ep_bw->ep_interval - 3;
2704 if (normalized_interval == 0)
2705 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2706 interval_bw = &bw_table->interval_bw[normalized_interval];
2707 interval_bw->num_packets -= ep_bw->num_packets;
2708 switch (udev->speed) {
2710 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2712 case USB_SPEED_FULL:
2713 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2715 case USB_SPEED_HIGH:
2716 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2718 case USB_SPEED_SUPER:
2719 case USB_SPEED_SUPER_PLUS:
2720 case USB_SPEED_UNKNOWN:
2721 case USB_SPEED_WIRELESS:
2722 /* Should never happen because only LS/FS/HS endpoints will get
2723 * added to the endpoint list.
2728 tt_info->active_eps -= 1;
2729 list_del_init(&virt_ep->bw_endpoint_list);
2732 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2733 struct xhci_bw_info *ep_bw,
2734 struct xhci_interval_bw_table *bw_table,
2735 struct usb_device *udev,
2736 struct xhci_virt_ep *virt_ep,
2737 struct xhci_tt_bw_info *tt_info)
2739 struct xhci_interval_bw *interval_bw;
2740 struct xhci_virt_ep *smaller_ep;
2741 int normalized_interval;
2743 if (xhci_is_async_ep(ep_bw->type))
2746 if (udev->speed == USB_SPEED_SUPER) {
2747 if (xhci_is_sync_in_ep(ep_bw->type))
2748 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2749 xhci_get_ss_bw_consumed(ep_bw);
2751 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2752 xhci_get_ss_bw_consumed(ep_bw);
2756 /* For LS/FS devices, we need to translate the interval expressed in
2757 * microframes to frames.
2759 if (udev->speed == USB_SPEED_HIGH)
2760 normalized_interval = ep_bw->ep_interval;
2762 normalized_interval = ep_bw->ep_interval - 3;
2764 if (normalized_interval == 0)
2765 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2766 interval_bw = &bw_table->interval_bw[normalized_interval];
2767 interval_bw->num_packets += ep_bw->num_packets;
2768 switch (udev->speed) {
2770 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2772 case USB_SPEED_FULL:
2773 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2775 case USB_SPEED_HIGH:
2776 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2778 case USB_SPEED_SUPER:
2779 case USB_SPEED_SUPER_PLUS:
2780 case USB_SPEED_UNKNOWN:
2781 case USB_SPEED_WIRELESS:
2782 /* Should never happen because only LS/FS/HS endpoints will get
2783 * added to the endpoint list.
2789 tt_info->active_eps += 1;
2790 /* Insert the endpoint into the list, largest max packet size first. */
2791 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2793 if (ep_bw->max_packet_size >=
2794 smaller_ep->bw_info.max_packet_size) {
2795 /* Add the new ep before the smaller endpoint */
2796 list_add_tail(&virt_ep->bw_endpoint_list,
2797 &smaller_ep->bw_endpoint_list);
2801 /* Add the new endpoint at the end of the list. */
2802 list_add_tail(&virt_ep->bw_endpoint_list,
2803 &interval_bw->endpoints);
2806 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2807 struct xhci_virt_device *virt_dev,
2810 struct xhci_root_port_bw_info *rh_bw_info;
2811 if (!virt_dev->tt_info)
2814 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2815 if (old_active_eps == 0 &&
2816 virt_dev->tt_info->active_eps != 0) {
2817 rh_bw_info->num_active_tts += 1;
2818 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2819 } else if (old_active_eps != 0 &&
2820 virt_dev->tt_info->active_eps == 0) {
2821 rh_bw_info->num_active_tts -= 1;
2822 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2826 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2827 struct xhci_virt_device *virt_dev,
2828 struct xhci_container_ctx *in_ctx)
2830 struct xhci_bw_info ep_bw_info[31];
2832 struct xhci_input_control_ctx *ctrl_ctx;
2833 int old_active_eps = 0;
2835 if (virt_dev->tt_info)
2836 old_active_eps = virt_dev->tt_info->active_eps;
2838 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2840 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2845 for (i = 0; i < 31; i++) {
2846 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2849 /* Make a copy of the BW info in case we need to revert this */
2850 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2851 sizeof(ep_bw_info[i]));
2852 /* Drop the endpoint from the interval table if the endpoint is
2853 * being dropped or changed.
2855 if (EP_IS_DROPPED(ctrl_ctx, i))
2856 xhci_drop_ep_from_interval_table(xhci,
2857 &virt_dev->eps[i].bw_info,
2863 /* Overwrite the information stored in the endpoints' bw_info */
2864 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2865 for (i = 0; i < 31; i++) {
2866 /* Add any changed or added endpoints to the interval table */
2867 if (EP_IS_ADDED(ctrl_ctx, i))
2868 xhci_add_ep_to_interval_table(xhci,
2869 &virt_dev->eps[i].bw_info,
2876 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2877 /* Ok, this fits in the bandwidth we have.
2878 * Update the number of active TTs.
2880 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2884 /* We don't have enough bandwidth for this, revert the stored info. */
2885 for (i = 0; i < 31; i++) {
2886 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2889 /* Drop the new copies of any added or changed endpoints from
2890 * the interval table.
2892 if (EP_IS_ADDED(ctrl_ctx, i)) {
2893 xhci_drop_ep_from_interval_table(xhci,
2894 &virt_dev->eps[i].bw_info,
2900 /* Revert the endpoint back to its old information */
2901 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2902 sizeof(ep_bw_info[i]));
2903 /* Add any changed or dropped endpoints back into the table */
2904 if (EP_IS_DROPPED(ctrl_ctx, i))
2905 xhci_add_ep_to_interval_table(xhci,
2906 &virt_dev->eps[i].bw_info,
2916 /* Issue a configure endpoint command or evaluate context command
2917 * and wait for it to finish.
2919 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2920 struct usb_device *udev,
2921 struct xhci_command *command,
2922 bool ctx_change, bool must_succeed)
2925 unsigned long flags;
2926 struct xhci_input_control_ctx *ctrl_ctx;
2927 struct xhci_virt_device *virt_dev;
2928 struct xhci_slot_ctx *slot_ctx;
2933 spin_lock_irqsave(&xhci->lock, flags);
2935 if (xhci->xhc_state & XHCI_STATE_DYING) {
2936 spin_unlock_irqrestore(&xhci->lock, flags);
2940 virt_dev = xhci->devs[udev->slot_id];
2942 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2945 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2950 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2951 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2952 spin_unlock_irqrestore(&xhci->lock, flags);
2953 xhci_warn(xhci, "Not enough host resources, "
2954 "active endpoint contexts = %u\n",
2955 xhci->num_active_eps);
2958 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2959 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2960 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2961 xhci_free_host_resources(xhci, ctrl_ctx);
2962 spin_unlock_irqrestore(&xhci->lock, flags);
2963 xhci_warn(xhci, "Not enough bandwidth\n");
2967 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2969 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2970 trace_xhci_configure_endpoint(slot_ctx);
2973 ret = xhci_queue_configure_endpoint(xhci, command,
2974 command->in_ctx->dma,
2975 udev->slot_id, must_succeed);
2977 ret = xhci_queue_evaluate_context(xhci, command,
2978 command->in_ctx->dma,
2979 udev->slot_id, must_succeed);
2981 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2982 xhci_free_host_resources(xhci, ctrl_ctx);
2983 spin_unlock_irqrestore(&xhci->lock, flags);
2984 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2985 "FIXME allocate a new ring segment");
2988 xhci_ring_cmd_db(xhci);
2989 spin_unlock_irqrestore(&xhci->lock, flags);
2991 /* Wait for the configure endpoint command to complete */
2992 wait_for_completion(command->completion);
2995 ret = xhci_configure_endpoint_result(xhci, udev,
2998 ret = xhci_evaluate_context_result(xhci, udev,
3001 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3002 spin_lock_irqsave(&xhci->lock, flags);
3003 /* If the command failed, remove the reserved resources.
3004 * Otherwise, clean up the estimate to include dropped eps.
3007 xhci_free_host_resources(xhci, ctrl_ctx);
3009 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3010 spin_unlock_irqrestore(&xhci->lock, flags);
3015 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3016 struct xhci_virt_device *vdev, int i)
3018 struct xhci_virt_ep *ep = &vdev->eps[i];
3020 if (ep->ep_state & EP_HAS_STREAMS) {
3021 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3022 xhci_get_endpoint_address(i));
3023 xhci_free_stream_info(xhci, ep->stream_info);
3024 ep->stream_info = NULL;
3025 ep->ep_state &= ~EP_HAS_STREAMS;
3029 /* Called after one or more calls to xhci_add_endpoint() or
3030 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3031 * to call xhci_reset_bandwidth().
3033 * Since we are in the middle of changing either configuration or
3034 * installing a new alt setting, the USB core won't allow URBs to be
3035 * enqueued for any endpoint on the old config or interface. Nothing
3036 * else should be touching the xhci->devs[slot_id] structure, so we
3037 * don't need to take the xhci->lock for manipulating that.
3039 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3043 struct xhci_hcd *xhci;
3044 struct xhci_virt_device *virt_dev;
3045 struct xhci_input_control_ctx *ctrl_ctx;
3046 struct xhci_slot_ctx *slot_ctx;
3047 struct xhci_command *command;
3049 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3052 xhci = hcd_to_xhci(hcd);
3053 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3054 (xhci->xhc_state & XHCI_STATE_REMOVING))
3057 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3058 virt_dev = xhci->devs[udev->slot_id];
3060 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3064 command->in_ctx = virt_dev->in_ctx;
3066 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3067 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3069 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3072 goto command_cleanup;
3074 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3075 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3076 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3078 /* Don't issue the command if there's no endpoints to update. */
3079 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3080 ctrl_ctx->drop_flags == 0) {
3082 goto command_cleanup;
3084 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3085 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3086 for (i = 31; i >= 1; i--) {
3087 __le32 le32 = cpu_to_le32(BIT(i));
3089 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3090 || (ctrl_ctx->add_flags & le32) || i == 1) {
3091 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3092 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3097 ret = xhci_configure_endpoint(xhci, udev, command,
3100 /* Callee should call reset_bandwidth() */
3101 goto command_cleanup;
3103 /* Free any rings that were dropped, but not changed. */
3104 for (i = 1; i < 31; i++) {
3105 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3106 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3107 xhci_free_endpoint_ring(xhci, virt_dev, i);
3108 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3111 xhci_zero_in_ctx(xhci, virt_dev);
3113 * Install any rings for completely new endpoints or changed endpoints,
3114 * and free any old rings from changed endpoints.
3116 for (i = 1; i < 31; i++) {
3117 if (!virt_dev->eps[i].new_ring)
3119 /* Only free the old ring if it exists.
3120 * It may not if this is the first add of an endpoint.
3122 if (virt_dev->eps[i].ring) {
3123 xhci_free_endpoint_ring(xhci, virt_dev, i);
3125 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3126 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3127 virt_dev->eps[i].new_ring = NULL;
3128 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3131 kfree(command->completion);
3136 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3138 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3140 struct xhci_hcd *xhci;
3141 struct xhci_virt_device *virt_dev;
3144 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3147 xhci = hcd_to_xhci(hcd);
3149 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3150 virt_dev = xhci->devs[udev->slot_id];
3151 /* Free any rings allocated for added endpoints */
3152 for (i = 0; i < 31; i++) {
3153 if (virt_dev->eps[i].new_ring) {
3154 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3155 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3156 virt_dev->eps[i].new_ring = NULL;
3159 xhci_zero_in_ctx(xhci, virt_dev);
3161 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3163 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3164 struct xhci_container_ctx *in_ctx,
3165 struct xhci_container_ctx *out_ctx,
3166 struct xhci_input_control_ctx *ctrl_ctx,
3167 u32 add_flags, u32 drop_flags)
3169 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3170 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3171 xhci_slot_copy(xhci, in_ctx, out_ctx);
3172 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3175 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3176 struct usb_host_endpoint *host_ep)
3178 struct xhci_hcd *xhci;
3179 struct xhci_virt_device *vdev;
3180 struct xhci_virt_ep *ep;
3181 struct usb_device *udev;
3182 unsigned long flags;
3183 unsigned int ep_index;
3185 xhci = hcd_to_xhci(hcd);
3187 spin_lock_irqsave(&xhci->lock, flags);
3189 udev = (struct usb_device *)host_ep->hcpriv;
3190 if (!udev || !udev->slot_id)
3193 vdev = xhci->devs[udev->slot_id];
3197 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3198 ep = &vdev->eps[ep_index];
3200 /* wait for hub_tt_work to finish clearing hub TT */
3201 if (ep->ep_state & EP_CLEARING_TT) {
3202 spin_unlock_irqrestore(&xhci->lock, flags);
3203 schedule_timeout_uninterruptible(1);
3208 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3211 host_ep->hcpriv = NULL;
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3216 * Called after usb core issues a clear halt control message.
3217 * The host side of the halt should already be cleared by a reset endpoint
3218 * command issued when the STALL event was received.
3220 * The reset endpoint command may only be issued to endpoints in the halted
3221 * state. For software that wishes to reset the data toggle or sequence number
3222 * of an endpoint that isn't in the halted state this function will issue a
3223 * configure endpoint command with the Drop and Add bits set for the target
3224 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3227 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3228 struct usb_host_endpoint *host_ep)
3230 struct xhci_hcd *xhci;
3231 struct usb_device *udev;
3232 struct xhci_virt_device *vdev;
3233 struct xhci_virt_ep *ep;
3234 struct xhci_input_control_ctx *ctrl_ctx;
3235 struct xhci_command *stop_cmd, *cfg_cmd;
3236 unsigned int ep_index;
3237 unsigned long flags;
3241 xhci = hcd_to_xhci(hcd);
3242 if (!host_ep->hcpriv)
3244 udev = (struct usb_device *) host_ep->hcpriv;
3245 vdev = xhci->devs[udev->slot_id];
3248 * vdev may be lost due to xHC restore error and re-initialization
3249 * during S3/S4 resume. A new vdev will be allocated later by
3250 * xhci_discover_or_reset_device()
3252 if (!udev->slot_id || !vdev)
3254 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3255 ep = &vdev->eps[ep_index];
3257 /* Bail out if toggle is already being cleared by a endpoint reset */
3258 spin_lock_irqsave(&xhci->lock, flags);
3259 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3260 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3261 spin_unlock_irqrestore(&xhci->lock, flags);
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3266 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3267 usb_endpoint_xfer_isoc(&host_ep->desc))
3270 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3272 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3275 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3279 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3283 spin_lock_irqsave(&xhci->lock, flags);
3285 /* block queuing new trbs and ringing ep doorbell */
3286 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3289 * Make sure endpoint ring is empty before resetting the toggle/seq.
3290 * Driver is required to synchronously cancel all transfer request.
3291 * Stop the endpoint to force xHC to update the output context
3294 if (!list_empty(&ep->ring->td_list)) {
3295 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3296 spin_unlock_irqrestore(&xhci->lock, flags);
3297 xhci_free_command(xhci, cfg_cmd);
3301 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3304 spin_unlock_irqrestore(&xhci->lock, flags);
3305 xhci_free_command(xhci, cfg_cmd);
3306 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3311 xhci_ring_cmd_db(xhci);
3312 spin_unlock_irqrestore(&xhci->lock, flags);
3314 wait_for_completion(stop_cmd->completion);
3316 spin_lock_irqsave(&xhci->lock, flags);
3318 /* config ep command clears toggle if add and drop ep flags are set */
3319 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3321 spin_unlock_irqrestore(&xhci->lock, flags);
3322 xhci_free_command(xhci, cfg_cmd);
3323 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3328 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3329 ctrl_ctx, ep_flag, ep_flag);
3330 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3332 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3333 udev->slot_id, false);
3335 spin_unlock_irqrestore(&xhci->lock, flags);
3336 xhci_free_command(xhci, cfg_cmd);
3337 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3342 xhci_ring_cmd_db(xhci);
3343 spin_unlock_irqrestore(&xhci->lock, flags);
3345 wait_for_completion(cfg_cmd->completion);
3347 xhci_free_command(xhci, cfg_cmd);
3349 xhci_free_command(xhci, stop_cmd);
3350 spin_lock_irqsave(&xhci->lock, flags);
3351 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3352 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3353 spin_unlock_irqrestore(&xhci->lock, flags);
3356 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3357 struct usb_device *udev, struct usb_host_endpoint *ep,
3358 unsigned int slot_id)
3361 unsigned int ep_index;
3362 unsigned int ep_state;
3366 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3368 return ret ? ret : -EINVAL;
3369 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3370 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3371 " descriptor for ep 0x%x does not support streams\n",
3372 ep->desc.bEndpointAddress);
3376 ep_index = xhci_get_endpoint_index(&ep->desc);
3377 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3378 if (ep_state & EP_HAS_STREAMS ||
3379 ep_state & EP_GETTING_STREAMS) {
3380 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3381 "already has streams set up.\n",
3382 ep->desc.bEndpointAddress);
3383 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3384 "dynamic stream context array reallocation.\n");
3387 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3388 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3389 "endpoint 0x%x; URBs are pending.\n",
3390 ep->desc.bEndpointAddress);
3396 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3397 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3399 unsigned int max_streams;
3401 /* The stream context array size must be a power of two */
3402 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3404 * Find out how many primary stream array entries the host controller
3405 * supports. Later we may use secondary stream arrays (similar to 2nd
3406 * level page entries), but that's an optional feature for xHCI host
3407 * controllers. xHCs must support at least 4 stream IDs.
3409 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3410 if (*num_stream_ctxs > max_streams) {
3411 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3413 *num_stream_ctxs = max_streams;
3414 *num_streams = max_streams;
3418 /* Returns an error code if one of the endpoint already has streams.
3419 * This does not change any data structures, it only checks and gathers
3422 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3423 struct usb_device *udev,
3424 struct usb_host_endpoint **eps, unsigned int num_eps,
3425 unsigned int *num_streams, u32 *changed_ep_bitmask)
3427 unsigned int max_streams;
3428 unsigned int endpoint_flag;
3432 for (i = 0; i < num_eps; i++) {
3433 ret = xhci_check_streams_endpoint(xhci, udev,
3434 eps[i], udev->slot_id);
3438 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3439 if (max_streams < (*num_streams - 1)) {
3440 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3441 eps[i]->desc.bEndpointAddress,
3443 *num_streams = max_streams+1;
3446 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3447 if (*changed_ep_bitmask & endpoint_flag)
3449 *changed_ep_bitmask |= endpoint_flag;
3454 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3455 struct usb_device *udev,
3456 struct usb_host_endpoint **eps, unsigned int num_eps)
3458 u32 changed_ep_bitmask = 0;
3459 unsigned int slot_id;
3460 unsigned int ep_index;
3461 unsigned int ep_state;
3464 slot_id = udev->slot_id;
3465 if (!xhci->devs[slot_id])
3468 for (i = 0; i < num_eps; i++) {
3469 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3470 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3471 /* Are streams already being freed for the endpoint? */
3472 if (ep_state & EP_GETTING_NO_STREAMS) {
3473 xhci_warn(xhci, "WARN Can't disable streams for "
3475 "streams are being disabled already\n",
3476 eps[i]->desc.bEndpointAddress);
3479 /* Are there actually any streams to free? */
3480 if (!(ep_state & EP_HAS_STREAMS) &&
3481 !(ep_state & EP_GETTING_STREAMS)) {
3482 xhci_warn(xhci, "WARN Can't disable streams for "
3484 "streams are already disabled!\n",
3485 eps[i]->desc.bEndpointAddress);
3486 xhci_warn(xhci, "WARN xhci_free_streams() called "
3487 "with non-streams endpoint\n");
3490 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3492 return changed_ep_bitmask;
3496 * The USB device drivers use this function (through the HCD interface in USB
3497 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3498 * coordinate mass storage command queueing across multiple endpoints (basically
3499 * a stream ID == a task ID).
3501 * Setting up streams involves allocating the same size stream context array
3502 * for each endpoint and issuing a configure endpoint command for all endpoints.
3504 * Don't allow the call to succeed if one endpoint only supports one stream
3505 * (which means it doesn't support streams at all).
3507 * Drivers may get less stream IDs than they asked for, if the host controller
3508 * hardware or endpoints claim they can't support the number of requested
3511 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3512 struct usb_host_endpoint **eps, unsigned int num_eps,
3513 unsigned int num_streams, gfp_t mem_flags)
3516 struct xhci_hcd *xhci;
3517 struct xhci_virt_device *vdev;
3518 struct xhci_command *config_cmd;
3519 struct xhci_input_control_ctx *ctrl_ctx;
3520 unsigned int ep_index;
3521 unsigned int num_stream_ctxs;
3522 unsigned int max_packet;
3523 unsigned long flags;
3524 u32 changed_ep_bitmask = 0;
3529 /* Add one to the number of streams requested to account for
3530 * stream 0 that is reserved for xHCI usage.
3533 xhci = hcd_to_xhci(hcd);
3534 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3537 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3538 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3539 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3540 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3544 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3548 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3550 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3552 xhci_free_command(xhci, config_cmd);
3556 /* Check to make sure all endpoints are not already configured for
3557 * streams. While we're at it, find the maximum number of streams that
3558 * all the endpoints will support and check for duplicate endpoints.
3560 spin_lock_irqsave(&xhci->lock, flags);
3561 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3562 num_eps, &num_streams, &changed_ep_bitmask);
3564 xhci_free_command(xhci, config_cmd);
3565 spin_unlock_irqrestore(&xhci->lock, flags);
3568 if (num_streams <= 1) {
3569 xhci_warn(xhci, "WARN: endpoints can't handle "
3570 "more than one stream.\n");
3571 xhci_free_command(xhci, config_cmd);
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3575 vdev = xhci->devs[udev->slot_id];
3576 /* Mark each endpoint as being in transition, so
3577 * xhci_urb_enqueue() will reject all URBs.
3579 for (i = 0; i < num_eps; i++) {
3580 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3581 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3583 spin_unlock_irqrestore(&xhci->lock, flags);
3585 /* Setup internal data structures and allocate HW data structures for
3586 * streams (but don't install the HW structures in the input context
3587 * until we're sure all memory allocation succeeded).
3589 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3590 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3591 num_stream_ctxs, num_streams);
3593 for (i = 0; i < num_eps; i++) {
3594 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3595 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3596 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3599 max_packet, mem_flags);
3600 if (!vdev->eps[ep_index].stream_info)
3602 /* Set maxPstreams in endpoint context and update deq ptr to
3603 * point to stream context array. FIXME
3607 /* Set up the input context for a configure endpoint command. */
3608 for (i = 0; i < num_eps; i++) {
3609 struct xhci_ep_ctx *ep_ctx;
3611 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3612 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3614 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3615 vdev->out_ctx, ep_index);
3616 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3617 vdev->eps[ep_index].stream_info);
3619 /* Tell the HW to drop its old copy of the endpoint context info
3620 * and add the updated copy from the input context.
3622 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3623 vdev->out_ctx, ctrl_ctx,
3624 changed_ep_bitmask, changed_ep_bitmask);
3626 /* Issue and wait for the configure endpoint command */
3627 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3630 /* xHC rejected the configure endpoint command for some reason, so we
3631 * leave the old ring intact and free our internal streams data
3637 spin_lock_irqsave(&xhci->lock, flags);
3638 for (i = 0; i < num_eps; i++) {
3639 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3640 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3641 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3642 udev->slot_id, ep_index);
3643 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3645 xhci_free_command(xhci, config_cmd);
3646 spin_unlock_irqrestore(&xhci->lock, flags);
3648 for (i = 0; i < num_eps; i++) {
3649 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3650 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3652 /* Subtract 1 for stream 0, which drivers can't use */
3653 return num_streams - 1;
3656 /* If it didn't work, free the streams! */
3657 for (i = 0; i < num_eps; i++) {
3658 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3659 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3660 vdev->eps[ep_index].stream_info = NULL;
3661 /* FIXME Unset maxPstreams in endpoint context and
3662 * update deq ptr to point to normal string ring.
3664 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3665 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3666 xhci_endpoint_zero(xhci, vdev, eps[i]);
3668 xhci_free_command(xhci, config_cmd);
3672 /* Transition the endpoint from using streams to being a "normal" endpoint
3675 * Modify the endpoint context state, submit a configure endpoint command,
3676 * and free all endpoint rings for streams if that completes successfully.
3678 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3679 struct usb_host_endpoint **eps, unsigned int num_eps,
3683 struct xhci_hcd *xhci;
3684 struct xhci_virt_device *vdev;
3685 struct xhci_command *command;
3686 struct xhci_input_control_ctx *ctrl_ctx;
3687 unsigned int ep_index;
3688 unsigned long flags;
3689 u32 changed_ep_bitmask;
3691 xhci = hcd_to_xhci(hcd);
3692 vdev = xhci->devs[udev->slot_id];
3694 /* Set up a configure endpoint command to remove the streams rings */
3695 spin_lock_irqsave(&xhci->lock, flags);
3696 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3697 udev, eps, num_eps);
3698 if (changed_ep_bitmask == 0) {
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3703 /* Use the xhci_command structure from the first endpoint. We may have
3704 * allocated too many, but the driver may call xhci_free_streams() for
3705 * each endpoint it grouped into one call to xhci_alloc_streams().
3707 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3708 command = vdev->eps[ep_index].stream_info->free_streams_command;
3709 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3711 spin_unlock_irqrestore(&xhci->lock, flags);
3712 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3717 for (i = 0; i < num_eps; i++) {
3718 struct xhci_ep_ctx *ep_ctx;
3720 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3721 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3722 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3723 EP_GETTING_NO_STREAMS;
3725 xhci_endpoint_copy(xhci, command->in_ctx,
3726 vdev->out_ctx, ep_index);
3727 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3728 &vdev->eps[ep_index]);
3730 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3731 vdev->out_ctx, ctrl_ctx,
3732 changed_ep_bitmask, changed_ep_bitmask);
3733 spin_unlock_irqrestore(&xhci->lock, flags);
3735 /* Issue and wait for the configure endpoint command,
3736 * which must succeed.
3738 ret = xhci_configure_endpoint(xhci, udev, command,
3741 /* xHC rejected the configure endpoint command for some reason, so we
3742 * leave the streams rings intact.
3747 spin_lock_irqsave(&xhci->lock, flags);
3748 for (i = 0; i < num_eps; i++) {
3749 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3750 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3751 vdev->eps[ep_index].stream_info = NULL;
3752 /* FIXME Unset maxPstreams in endpoint context and
3753 * update deq ptr to point to normal string ring.
3755 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3756 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3758 spin_unlock_irqrestore(&xhci->lock, flags);
3764 * Deletes endpoint resources for endpoints that were active before a Reset
3765 * Device command, or a Disable Slot command. The Reset Device command leaves
3766 * the control endpoint intact, whereas the Disable Slot command deletes it.
3768 * Must be called with xhci->lock held.
3770 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3771 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3774 unsigned int num_dropped_eps = 0;
3775 unsigned int drop_flags = 0;
3777 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3778 if (virt_dev->eps[i].ring) {
3779 drop_flags |= 1 << i;
3783 xhci->num_active_eps -= num_dropped_eps;
3784 if (num_dropped_eps)
3785 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3786 "Dropped %u ep ctxs, flags = 0x%x, "
3788 num_dropped_eps, drop_flags,
3789 xhci->num_active_eps);
3793 * This submits a Reset Device Command, which will set the device state to 0,
3794 * set the device address to 0, and disable all the endpoints except the default
3795 * control endpoint. The USB core should come back and call
3796 * xhci_address_device(), and then re-set up the configuration. If this is
3797 * called because of a usb_reset_and_verify_device(), then the old alternate
3798 * settings will be re-installed through the normal bandwidth allocation
3801 * Wait for the Reset Device command to finish. Remove all structures
3802 * associated with the endpoints that were disabled. Clear the input device
3803 * structure? Reset the control endpoint 0 max packet size?
3805 * If the virt_dev to be reset does not exist or does not match the udev,
3806 * it means the device is lost, possibly due to the xHC restore error and
3807 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3808 * re-allocate the device.
3810 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3811 struct usb_device *udev)
3814 unsigned long flags;
3815 struct xhci_hcd *xhci;
3816 unsigned int slot_id;
3817 struct xhci_virt_device *virt_dev;
3818 struct xhci_command *reset_device_cmd;
3819 struct xhci_slot_ctx *slot_ctx;
3820 int old_active_eps = 0;
3822 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3825 xhci = hcd_to_xhci(hcd);
3826 slot_id = udev->slot_id;
3827 virt_dev = xhci->devs[slot_id];
3829 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3830 "not exist. Re-allocate the device\n", slot_id);
3831 ret = xhci_alloc_dev(hcd, udev);
3838 if (virt_dev->tt_info)
3839 old_active_eps = virt_dev->tt_info->active_eps;
3841 if (virt_dev->udev != udev) {
3842 /* If the virt_dev and the udev does not match, this virt_dev
3843 * may belong to another udev.
3844 * Re-allocate the device.
3846 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3847 "not match the udev. Re-allocate the device\n",
3849 ret = xhci_alloc_dev(hcd, udev);
3856 /* If device is not setup, there is no point in resetting it */
3857 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3858 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3859 SLOT_STATE_DISABLED)
3862 trace_xhci_discover_or_reset_device(slot_ctx);
3864 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3865 /* Allocate the command structure that holds the struct completion.
3866 * Assume we're in process context, since the normal device reset
3867 * process has to wait for the device anyway. Storage devices are
3868 * reset as part of error handling, so use GFP_NOIO instead of
3871 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3872 if (!reset_device_cmd) {
3873 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3877 /* Attempt to submit the Reset Device command to the command ring */
3878 spin_lock_irqsave(&xhci->lock, flags);
3880 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3882 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3884 goto command_cleanup;
3886 xhci_ring_cmd_db(xhci);
3887 spin_unlock_irqrestore(&xhci->lock, flags);
3889 /* Wait for the Reset Device command to finish */
3890 wait_for_completion(reset_device_cmd->completion);
3892 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3893 * unless we tried to reset a slot ID that wasn't enabled,
3894 * or the device wasn't in the addressed or configured state.
3896 ret = reset_device_cmd->status;
3898 case COMP_COMMAND_ABORTED:
3899 case COMP_COMMAND_RING_STOPPED:
3900 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3902 goto command_cleanup;
3903 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3904 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3905 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3907 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3908 xhci_dbg(xhci, "Not freeing device rings.\n");
3909 /* Don't treat this as an error. May change my mind later. */
3911 goto command_cleanup;
3913 xhci_dbg(xhci, "Successful reset device command.\n");
3916 if (xhci_is_vendor_info_code(xhci, ret))
3918 xhci_warn(xhci, "Unknown completion code %u for "
3919 "reset device command.\n", ret);
3921 goto command_cleanup;
3924 /* Free up host controller endpoint resources */
3925 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3926 spin_lock_irqsave(&xhci->lock, flags);
3927 /* Don't delete the default control endpoint resources */
3928 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3929 spin_unlock_irqrestore(&xhci->lock, flags);
3932 /* Everything but endpoint 0 is disabled, so free the rings. */
3933 for (i = 1; i < 31; i++) {
3934 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3936 if (ep->ep_state & EP_HAS_STREAMS) {
3937 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3938 xhci_get_endpoint_address(i));
3939 xhci_free_stream_info(xhci, ep->stream_info);
3940 ep->stream_info = NULL;
3941 ep->ep_state &= ~EP_HAS_STREAMS;
3945 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3946 xhci_free_endpoint_ring(xhci, virt_dev, i);
3948 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3949 xhci_drop_ep_from_interval_table(xhci,
3950 &virt_dev->eps[i].bw_info,
3955 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3957 /* If necessary, update the number of active TTs on this root port */
3958 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3959 virt_dev->flags = 0;
3963 xhci_free_command(xhci, reset_device_cmd);
3968 * At this point, the struct usb_device is about to go away, the device has
3969 * disconnected, and all traffic has been stopped and the endpoints have been
3970 * disabled. Free any HC data structures associated with that device.
3972 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3974 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3975 struct xhci_virt_device *virt_dev;
3976 struct xhci_slot_ctx *slot_ctx;
3980 * We called pm_runtime_get_noresume when the device was attached.
3981 * Decrement the counter here to allow controller to runtime suspend
3982 * if no devices remain.
3984 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3985 pm_runtime_put_noidle(hcd->self.controller);
3987 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3988 /* If the host is halted due to driver unload, we still need to free the
3991 if (ret <= 0 && ret != -ENODEV)
3994 virt_dev = xhci->devs[udev->slot_id];
3995 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3996 trace_xhci_free_dev(slot_ctx);
3998 /* Stop any wayward timer functions (which may grab the lock) */
3999 for (i = 0; i < 31; i++)
4000 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4001 virt_dev->udev = NULL;
4002 xhci_disable_slot(xhci, udev->slot_id);
4003 xhci_free_virt_device(xhci, udev->slot_id);
4006 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4008 struct xhci_command *command;
4009 unsigned long flags;
4013 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4017 xhci_debugfs_remove_slot(xhci, slot_id);
4019 spin_lock_irqsave(&xhci->lock, flags);
4020 /* Don't disable the slot if the host controller is dead. */
4021 state = readl(&xhci->op_regs->status);
4022 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4023 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4024 spin_unlock_irqrestore(&xhci->lock, flags);
4029 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4032 spin_unlock_irqrestore(&xhci->lock, flags);
4036 xhci_ring_cmd_db(xhci);
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4039 wait_for_completion(command->completion);
4041 if (command->status != COMP_SUCCESS)
4042 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4043 slot_id, command->status);
4045 xhci_free_command(xhci, command);
4051 * Checks if we have enough host controller resources for the default control
4054 * Must be called with xhci->lock held.
4056 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4058 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4059 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4060 "Not enough ep ctxs: "
4061 "%u active, need to add 1, limit is %u.",
4062 xhci->num_active_eps, xhci->limit_active_eps);
4065 xhci->num_active_eps += 1;
4066 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4067 "Adding 1 ep ctx, %u now active.",
4068 xhci->num_active_eps);
4074 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4075 * timed out, or allocating memory failed. Returns 1 on success.
4077 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4079 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4080 struct xhci_virt_device *vdev;
4081 struct xhci_slot_ctx *slot_ctx;
4082 unsigned long flags;
4084 struct xhci_command *command;
4086 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4090 spin_lock_irqsave(&xhci->lock, flags);
4091 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4093 spin_unlock_irqrestore(&xhci->lock, flags);
4094 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4095 xhci_free_command(xhci, command);
4098 xhci_ring_cmd_db(xhci);
4099 spin_unlock_irqrestore(&xhci->lock, flags);
4101 wait_for_completion(command->completion);
4102 slot_id = command->slot_id;
4104 if (!slot_id || command->status != COMP_SUCCESS) {
4105 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4106 xhci_trb_comp_code_string(command->status));
4107 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4109 readl(&xhci->cap_regs->hcs_params1)));
4110 xhci_free_command(xhci, command);
4114 xhci_free_command(xhci, command);
4116 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4117 spin_lock_irqsave(&xhci->lock, flags);
4118 ret = xhci_reserve_host_control_ep_resources(xhci);
4120 spin_unlock_irqrestore(&xhci->lock, flags);
4121 xhci_warn(xhci, "Not enough host resources, "
4122 "active endpoint contexts = %u\n",
4123 xhci->num_active_eps);
4126 spin_unlock_irqrestore(&xhci->lock, flags);
4128 /* Use GFP_NOIO, since this function can be called from
4129 * xhci_discover_or_reset_device(), which may be called as part of
4130 * mass storage driver error handling.
4132 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4133 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4136 vdev = xhci->devs[slot_id];
4137 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4138 trace_xhci_alloc_dev(slot_ctx);
4140 udev->slot_id = slot_id;
4142 xhci_debugfs_create_slot(xhci, slot_id);
4145 * If resetting upon resume, we can't put the controller into runtime
4146 * suspend if there is a device attached.
4148 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4149 pm_runtime_get_noresume(hcd->self.controller);
4151 /* Is this a LS or FS device under a HS hub? */
4152 /* Hub or peripherial? */
4156 xhci_disable_slot(xhci, udev->slot_id);
4157 xhci_free_virt_device(xhci, udev->slot_id);
4163 * Issue an Address Device command and optionally send a corresponding
4164 * SetAddress request to the device.
4166 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4167 enum xhci_setup_dev setup)
4169 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4170 unsigned long flags;
4171 struct xhci_virt_device *virt_dev;
4173 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4174 struct xhci_slot_ctx *slot_ctx;
4175 struct xhci_input_control_ctx *ctrl_ctx;
4177 struct xhci_command *command = NULL;
4179 mutex_lock(&xhci->mutex);
4181 if (xhci->xhc_state) { /* dying, removing or halted */
4186 if (!udev->slot_id) {
4187 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4188 "Bad Slot ID %d", udev->slot_id);
4193 virt_dev = xhci->devs[udev->slot_id];
4195 if (WARN_ON(!virt_dev)) {
4197 * In plug/unplug torture test with an NEC controller,
4198 * a zero-dereference was observed once due to virt_dev = 0.
4199 * Print useful debug rather than crash if it is observed again!
4201 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4206 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4207 trace_xhci_setup_device_slot(slot_ctx);
4209 if (setup == SETUP_CONTEXT_ONLY) {
4210 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4211 SLOT_STATE_DEFAULT) {
4212 xhci_dbg(xhci, "Slot already in default state\n");
4217 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4223 command->in_ctx = virt_dev->in_ctx;
4225 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4226 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4228 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4234 * If this is the first Set Address since device plug-in or
4235 * virt_device realloaction after a resume with an xHCI power loss,
4236 * then set up the slot context.
4238 if (!slot_ctx->dev_info)
4239 xhci_setup_addressable_virt_dev(xhci, udev);
4240 /* Otherwise, update the control endpoint ring enqueue pointer. */
4242 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4243 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4244 ctrl_ctx->drop_flags = 0;
4246 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4247 le32_to_cpu(slot_ctx->dev_info) >> 27);
4249 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4250 spin_lock_irqsave(&xhci->lock, flags);
4251 trace_xhci_setup_device(virt_dev);
4252 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4253 udev->slot_id, setup);
4255 spin_unlock_irqrestore(&xhci->lock, flags);
4256 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4257 "FIXME: allocate a command ring segment");
4260 xhci_ring_cmd_db(xhci);
4261 spin_unlock_irqrestore(&xhci->lock, flags);
4263 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4264 wait_for_completion(command->completion);
4266 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4267 * the SetAddress() "recovery interval" required by USB and aborting the
4268 * command on a timeout.
4270 switch (command->status) {
4271 case COMP_COMMAND_ABORTED:
4272 case COMP_COMMAND_RING_STOPPED:
4273 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4276 case COMP_CONTEXT_STATE_ERROR:
4277 case COMP_SLOT_NOT_ENABLED_ERROR:
4278 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4279 act, udev->slot_id);
4282 case COMP_USB_TRANSACTION_ERROR:
4283 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4285 mutex_unlock(&xhci->mutex);
4286 ret = xhci_disable_slot(xhci, udev->slot_id);
4287 xhci_free_virt_device(xhci, udev->slot_id);
4289 xhci_alloc_dev(hcd, udev);
4290 kfree(command->completion);
4293 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4294 dev_warn(&udev->dev,
4295 "ERROR: Incompatible device for setup %s command\n", act);
4299 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4300 "Successful setup %s command", act);
4304 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4305 act, command->status);
4306 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4312 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4313 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4314 "Op regs DCBAA ptr = %#016llx", temp_64);
4315 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4316 "Slot ID %d dcbaa entry @%p = %#016llx",
4318 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4319 (unsigned long long)
4320 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4321 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4322 "Output Context DMA address = %#08llx",
4323 (unsigned long long)virt_dev->out_ctx->dma);
4324 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4325 le32_to_cpu(slot_ctx->dev_info) >> 27);
4327 * USB core uses address 1 for the roothubs, so we add one to the
4328 * address given back to us by the HC.
4330 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4331 le32_to_cpu(slot_ctx->dev_info) >> 27);
4332 /* Zero the input context control for later use */
4333 ctrl_ctx->add_flags = 0;
4334 ctrl_ctx->drop_flags = 0;
4335 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4336 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4338 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4339 "Internal device address = %d",
4340 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4342 mutex_unlock(&xhci->mutex);
4344 kfree(command->completion);
4350 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4352 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4355 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4357 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4361 * Transfer the port index into real index in the HW port status
4362 * registers. Caculate offset between the port's PORTSC register
4363 * and port status base. Divide the number of per port register
4364 * to get the real index. The raw port number bases 1.
4366 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4368 struct xhci_hub *rhub;
4370 rhub = xhci_get_rhub(hcd);
4371 return rhub->ports[port1 - 1]->hw_portnum + 1;
4375 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4376 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4378 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4379 struct usb_device *udev, u16 max_exit_latency)
4381 struct xhci_virt_device *virt_dev;
4382 struct xhci_command *command;
4383 struct xhci_input_control_ctx *ctrl_ctx;
4384 struct xhci_slot_ctx *slot_ctx;
4385 unsigned long flags;
4388 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4392 spin_lock_irqsave(&xhci->lock, flags);
4394 virt_dev = xhci->devs[udev->slot_id];
4397 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4398 * xHC was re-initialized. Exit latency will be set later after
4399 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4402 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4403 spin_unlock_irqrestore(&xhci->lock, flags);
4407 /* Attempt to issue an Evaluate Context command to change the MEL. */
4408 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4410 spin_unlock_irqrestore(&xhci->lock, flags);
4411 xhci_free_command(xhci, command);
4412 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4417 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4418 spin_unlock_irqrestore(&xhci->lock, flags);
4420 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4421 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4422 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4423 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4424 slot_ctx->dev_state = 0;
4426 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4427 "Set up evaluate context for LPM MEL change.");
4429 /* Issue and wait for the evaluate context command. */
4430 ret = xhci_configure_endpoint(xhci, udev, command,
4434 spin_lock_irqsave(&xhci->lock, flags);
4435 virt_dev->current_mel = max_exit_latency;
4436 spin_unlock_irqrestore(&xhci->lock, flags);
4439 xhci_free_command(xhci, command);
4446 /* BESL to HIRD Encoding array for USB2 LPM */
4447 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4448 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4450 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4451 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4452 struct usb_device *udev)
4454 int u2del, besl, besl_host;
4455 int besl_device = 0;
4458 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4459 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4461 if (field & USB_BESL_SUPPORT) {
4462 for (besl_host = 0; besl_host < 16; besl_host++) {
4463 if (xhci_besl_encoding[besl_host] >= u2del)
4466 /* Use baseline BESL value as default */
4467 if (field & USB_BESL_BASELINE_VALID)
4468 besl_device = USB_GET_BESL_BASELINE(field);
4469 else if (field & USB_BESL_DEEP_VALID)
4470 besl_device = USB_GET_BESL_DEEP(field);
4475 besl_host = (u2del - 51) / 75 + 1;
4478 besl = besl_host + besl_device;
4485 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4486 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4493 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4495 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4496 l1 = udev->l1_params.timeout / 256;
4498 /* device has preferred BESLD */
4499 if (field & USB_BESL_DEEP_VALID) {
4500 besld = USB_GET_BESL_DEEP(field);
4504 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4507 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4508 struct usb_device *udev, int enable)
4510 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4511 struct xhci_port **ports;
4512 __le32 __iomem *pm_addr, *hlpm_addr;
4513 u32 pm_val, hlpm_val, field;
4514 unsigned int port_num;
4515 unsigned long flags;
4516 int hird, exit_latency;
4519 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4522 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4526 if (!udev->parent || udev->parent->parent ||
4527 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4530 if (udev->usb2_hw_lpm_capable != 1)
4533 spin_lock_irqsave(&xhci->lock, flags);
4535 ports = xhci->usb2_rhub.ports;
4536 port_num = udev->portnum - 1;
4537 pm_addr = ports[port_num]->addr + PORTPMSC;
4538 pm_val = readl(pm_addr);
4539 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4541 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4542 enable ? "enable" : "disable", port_num + 1);
4545 /* Host supports BESL timeout instead of HIRD */
4546 if (udev->usb2_hw_lpm_besl_capable) {
4547 /* if device doesn't have a preferred BESL value use a
4548 * default one which works with mixed HIRD and BESL
4549 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4551 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4552 if ((field & USB_BESL_SUPPORT) &&
4553 (field & USB_BESL_BASELINE_VALID))
4554 hird = USB_GET_BESL_BASELINE(field);
4556 hird = udev->l1_params.besl;
4558 exit_latency = xhci_besl_encoding[hird];
4559 spin_unlock_irqrestore(&xhci->lock, flags);
4561 ret = xhci_change_max_exit_latency(xhci, udev,
4565 spin_lock_irqsave(&xhci->lock, flags);
4567 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4568 writel(hlpm_val, hlpm_addr);
4572 hird = xhci_calculate_hird_besl(xhci, udev);
4575 pm_val &= ~PORT_HIRD_MASK;
4576 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4577 writel(pm_val, pm_addr);
4578 pm_val = readl(pm_addr);
4580 writel(pm_val, pm_addr);
4584 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4585 writel(pm_val, pm_addr);
4588 if (udev->usb2_hw_lpm_besl_capable) {
4589 spin_unlock_irqrestore(&xhci->lock, flags);
4590 xhci_change_max_exit_latency(xhci, udev, 0);
4591 readl_poll_timeout(ports[port_num]->addr, pm_val,
4592 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4598 spin_unlock_irqrestore(&xhci->lock, flags);
4602 /* check if a usb2 port supports a given extened capability protocol
4603 * only USB2 ports extended protocol capability values are cached.
4604 * Return 1 if capability is supported
4606 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4607 unsigned capability)
4609 u32 port_offset, port_count;
4612 for (i = 0; i < xhci->num_ext_caps; i++) {
4613 if (xhci->ext_caps[i] & capability) {
4614 /* port offsets starts at 1 */
4615 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4616 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4617 if (port >= port_offset &&
4618 port < port_offset + port_count)
4625 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4627 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4628 int portnum = udev->portnum - 1;
4630 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4633 /* we only support lpm for non-hub device connected to root hub yet */
4634 if (!udev->parent || udev->parent->parent ||
4635 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4638 if (xhci->hw_lpm_support == 1 &&
4639 xhci_check_usb2_port_capability(
4640 xhci, portnum, XHCI_HLC)) {
4641 udev->usb2_hw_lpm_capable = 1;
4642 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4643 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4644 if (xhci_check_usb2_port_capability(xhci, portnum,
4646 udev->usb2_hw_lpm_besl_capable = 1;
4652 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4654 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4655 static unsigned long long xhci_service_interval_to_ns(
4656 struct usb_endpoint_descriptor *desc)
4658 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4661 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4662 enum usb3_link_state state)
4664 unsigned long long sel;
4665 unsigned long long pel;
4666 unsigned int max_sel_pel;
4671 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4672 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4673 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4674 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4678 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4679 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4680 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4684 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4686 return USB3_LPM_DISABLED;
4689 if (sel <= max_sel_pel && pel <= max_sel_pel)
4690 return USB3_LPM_DEVICE_INITIATED;
4692 if (sel > max_sel_pel)
4693 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4694 "due to long SEL %llu ms\n",
4697 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4698 "due to long PEL %llu ms\n",
4700 return USB3_LPM_DISABLED;
4703 /* The U1 timeout should be the maximum of the following values:
4704 * - For control endpoints, U1 system exit latency (SEL) * 3
4705 * - For bulk endpoints, U1 SEL * 5
4706 * - For interrupt endpoints:
4707 * - Notification EPs, U1 SEL * 3
4708 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4709 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4711 static unsigned long long xhci_calculate_intel_u1_timeout(
4712 struct usb_device *udev,
4713 struct usb_endpoint_descriptor *desc)
4715 unsigned long long timeout_ns;
4719 ep_type = usb_endpoint_type(desc);
4721 case USB_ENDPOINT_XFER_CONTROL:
4722 timeout_ns = udev->u1_params.sel * 3;
4724 case USB_ENDPOINT_XFER_BULK:
4725 timeout_ns = udev->u1_params.sel * 5;
4727 case USB_ENDPOINT_XFER_INT:
4728 intr_type = usb_endpoint_interrupt_type(desc);
4729 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4730 timeout_ns = udev->u1_params.sel * 3;
4733 /* Otherwise the calculation is the same as isoc eps */
4735 case USB_ENDPOINT_XFER_ISOC:
4736 timeout_ns = xhci_service_interval_to_ns(desc);
4737 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4738 if (timeout_ns < udev->u1_params.sel * 2)
4739 timeout_ns = udev->u1_params.sel * 2;
4748 /* Returns the hub-encoded U1 timeout value. */
4749 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4750 struct usb_device *udev,
4751 struct usb_endpoint_descriptor *desc)
4753 unsigned long long timeout_ns;
4755 /* Prevent U1 if service interval is shorter than U1 exit latency */
4756 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4757 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4758 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4759 return USB3_LPM_DISABLED;
4763 if (xhci->quirks & XHCI_INTEL_HOST)
4764 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4766 timeout_ns = udev->u1_params.sel;
4768 /* The U1 timeout is encoded in 1us intervals.
4769 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4771 if (timeout_ns == USB3_LPM_DISABLED)
4774 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4776 /* If the necessary timeout value is bigger than what we can set in the
4777 * USB 3.0 hub, we have to disable hub-initiated U1.
4779 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4781 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4782 "due to long timeout %llu ms\n", timeout_ns);
4783 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4786 /* The U2 timeout should be the maximum of:
4787 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4788 * - largest bInterval of any active periodic endpoint (to avoid going
4789 * into lower power link states between intervals).
4790 * - the U2 Exit Latency of the device
4792 static unsigned long long xhci_calculate_intel_u2_timeout(
4793 struct usb_device *udev,
4794 struct usb_endpoint_descriptor *desc)
4796 unsigned long long timeout_ns;
4797 unsigned long long u2_del_ns;
4799 timeout_ns = 10 * 1000 * 1000;
4801 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4802 (xhci_service_interval_to_ns(desc) > timeout_ns))
4803 timeout_ns = xhci_service_interval_to_ns(desc);
4805 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4806 if (u2_del_ns > timeout_ns)
4807 timeout_ns = u2_del_ns;
4812 /* Returns the hub-encoded U2 timeout value. */
4813 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4814 struct usb_device *udev,
4815 struct usb_endpoint_descriptor *desc)
4817 unsigned long long timeout_ns;
4819 /* Prevent U2 if service interval is shorter than U2 exit latency */
4820 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4821 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4822 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4823 return USB3_LPM_DISABLED;
4827 if (xhci->quirks & XHCI_INTEL_HOST)
4828 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4830 timeout_ns = udev->u2_params.sel;
4832 /* The U2 timeout is encoded in 256us intervals */
4833 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4834 /* If the necessary timeout value is bigger than what we can set in the
4835 * USB 3.0 hub, we have to disable hub-initiated U2.
4837 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4839 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4840 "due to long timeout %llu ms\n", timeout_ns);
4841 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4844 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4845 struct usb_device *udev,
4846 struct usb_endpoint_descriptor *desc,
4847 enum usb3_link_state state,
4850 if (state == USB3_LPM_U1)
4851 return xhci_calculate_u1_timeout(xhci, udev, desc);
4852 else if (state == USB3_LPM_U2)
4853 return xhci_calculate_u2_timeout(xhci, udev, desc);
4855 return USB3_LPM_DISABLED;
4858 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4859 struct usb_device *udev,
4860 struct usb_endpoint_descriptor *desc,
4861 enum usb3_link_state state,
4866 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4867 desc, state, timeout);
4869 /* If we found we can't enable hub-initiated LPM, and
4870 * the U1 or U2 exit latency was too high to allow
4871 * device-initiated LPM as well, then we will disable LPM
4872 * for this device, so stop searching any further.
4874 if (alt_timeout == USB3_LPM_DISABLED) {
4875 *timeout = alt_timeout;
4878 if (alt_timeout > *timeout)
4879 *timeout = alt_timeout;
4883 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4884 struct usb_device *udev,
4885 struct usb_host_interface *alt,
4886 enum usb3_link_state state,
4891 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4892 if (xhci_update_timeout_for_endpoint(xhci, udev,
4893 &alt->endpoint[j].desc, state, timeout))
4899 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4900 enum usb3_link_state state)
4902 struct usb_device *parent;
4903 unsigned int num_hubs;
4905 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4906 for (parent = udev->parent, num_hubs = 0; parent->parent;
4907 parent = parent->parent)
4913 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4914 " below second-tier hub.\n");
4915 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4916 "to decrease power consumption.\n");
4920 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4921 struct usb_device *udev,
4922 enum usb3_link_state state)
4924 if (xhci->quirks & XHCI_INTEL_HOST)
4925 return xhci_check_intel_tier_policy(udev, state);
4930 /* Returns the U1 or U2 timeout that should be enabled.
4931 * If the tier check or timeout setting functions return with a non-zero exit
4932 * code, that means the timeout value has been finalized and we shouldn't look
4933 * at any more endpoints.
4935 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4936 struct usb_device *udev, enum usb3_link_state state)
4938 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4939 struct usb_host_config *config;
4942 u16 timeout = USB3_LPM_DISABLED;
4944 if (state == USB3_LPM_U1)
4946 else if (state == USB3_LPM_U2)
4949 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4954 /* Gather some information about the currently installed configuration
4955 * and alternate interface settings.
4957 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4961 config = udev->actconfig;
4965 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4966 struct usb_driver *driver;
4967 struct usb_interface *intf = config->interface[i];
4972 /* Check if any currently bound drivers want hub-initiated LPM
4975 if (intf->dev.driver) {
4976 driver = to_usb_driver(intf->dev.driver);
4977 if (driver && driver->disable_hub_initiated_lpm) {
4978 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4979 state_name, driver->name);
4980 timeout = xhci_get_timeout_no_hub_lpm(udev,
4982 if (timeout == USB3_LPM_DISABLED)
4987 /* Not sure how this could happen... */
4988 if (!intf->cur_altsetting)
4991 if (xhci_update_timeout_for_interface(xhci, udev,
4992 intf->cur_altsetting,
4999 static int calculate_max_exit_latency(struct usb_device *udev,
5000 enum usb3_link_state state_changed,
5001 u16 hub_encoded_timeout)
5003 unsigned long long u1_mel_us = 0;
5004 unsigned long long u2_mel_us = 0;
5005 unsigned long long mel_us = 0;
5011 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5012 hub_encoded_timeout == USB3_LPM_DISABLED);
5013 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5014 hub_encoded_timeout == USB3_LPM_DISABLED);
5016 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5017 hub_encoded_timeout != USB3_LPM_DISABLED);
5018 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5019 hub_encoded_timeout != USB3_LPM_DISABLED);
5021 /* If U1 was already enabled and we're not disabling it,
5022 * or we're going to enable U1, account for the U1 max exit latency.
5024 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5026 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5027 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5029 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5031 mel_us = max(u1_mel_us, u2_mel_us);
5033 /* xHCI host controller max exit latency field is only 16 bits wide. */
5034 if (mel_us > MAX_EXIT) {
5035 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5036 "is too big.\n", mel_us);
5042 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5043 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5044 struct usb_device *udev, enum usb3_link_state state)
5046 struct xhci_hcd *xhci;
5047 u16 hub_encoded_timeout;
5051 xhci = hcd_to_xhci(hcd);
5052 /* The LPM timeout values are pretty host-controller specific, so don't
5053 * enable hub-initiated timeouts unless the vendor has provided
5054 * information about their timeout algorithm.
5056 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5057 !xhci->devs[udev->slot_id])
5058 return USB3_LPM_DISABLED;
5060 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5061 return USB3_LPM_DISABLED;
5063 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5064 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5066 /* Max Exit Latency is too big, disable LPM. */
5067 hub_encoded_timeout = USB3_LPM_DISABLED;
5071 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5074 return hub_encoded_timeout;
5077 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5078 struct usb_device *udev, enum usb3_link_state state)
5080 struct xhci_hcd *xhci;
5083 xhci = hcd_to_xhci(hcd);
5084 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5085 !xhci->devs[udev->slot_id])
5088 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5089 return xhci_change_max_exit_latency(xhci, udev, mel);
5091 #else /* CONFIG_PM */
5093 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5094 struct usb_device *udev, int enable)
5099 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5104 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5105 struct usb_device *udev, enum usb3_link_state state)
5107 return USB3_LPM_DISABLED;
5110 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5111 struct usb_device *udev, enum usb3_link_state state)
5115 #endif /* CONFIG_PM */
5117 /*-------------------------------------------------------------------------*/
5119 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5120 * internal data structures for the device.
5122 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5123 struct usb_tt *tt, gfp_t mem_flags)
5125 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5126 struct xhci_virt_device *vdev;
5127 struct xhci_command *config_cmd;
5128 struct xhci_input_control_ctx *ctrl_ctx;
5129 struct xhci_slot_ctx *slot_ctx;
5130 unsigned long flags;
5131 unsigned think_time;
5134 /* Ignore root hubs */
5138 vdev = xhci->devs[hdev->slot_id];
5140 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5144 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5148 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5150 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5152 xhci_free_command(xhci, config_cmd);
5156 spin_lock_irqsave(&xhci->lock, flags);
5157 if (hdev->speed == USB_SPEED_HIGH &&
5158 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5159 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5160 xhci_free_command(xhci, config_cmd);
5161 spin_unlock_irqrestore(&xhci->lock, flags);
5165 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5166 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5167 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5168 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5170 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5171 * but it may be already set to 1 when setup an xHCI virtual
5172 * device, so clear it anyway.
5175 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5176 else if (hdev->speed == USB_SPEED_FULL)
5177 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5179 if (xhci->hci_version > 0x95) {
5180 xhci_dbg(xhci, "xHCI version %x needs hub "
5181 "TT think time and number of ports\n",
5182 (unsigned int) xhci->hci_version);
5183 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5184 /* Set TT think time - convert from ns to FS bit times.
5185 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5186 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5188 * xHCI 1.0: this field shall be 0 if the device is not a
5191 think_time = tt->think_time;
5192 if (think_time != 0)
5193 think_time = (think_time / 666) - 1;
5194 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5195 slot_ctx->tt_info |=
5196 cpu_to_le32(TT_THINK_TIME(think_time));
5198 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5199 "TT think time or number of ports\n",
5200 (unsigned int) xhci->hci_version);
5202 slot_ctx->dev_state = 0;
5203 spin_unlock_irqrestore(&xhci->lock, flags);
5205 xhci_dbg(xhci, "Set up %s for hub device.\n",
5206 (xhci->hci_version > 0x95) ?
5207 "configure endpoint" : "evaluate context");
5209 /* Issue and wait for the configure endpoint or
5210 * evaluate context command.
5212 if (xhci->hci_version > 0x95)
5213 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5216 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5219 xhci_free_command(xhci, config_cmd);
5223 static int xhci_get_frame(struct usb_hcd *hcd)
5225 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5226 /* EHCI mods by the periodic size. Why? */
5227 return readl(&xhci->run_regs->microframe_index) >> 3;
5230 static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5232 xhci->usb2_rhub.hcd = hcd;
5233 hcd->speed = HCD_USB2;
5234 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5236 * USB 2.0 roothub under xHCI has an integrated TT,
5237 * (rate matching hub) as opposed to having an OHCI/UHCI
5238 * companion controller.
5243 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5245 unsigned int minor_rev;
5248 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5249 * should return 0x31 for sbrn, or that the minor revision
5250 * is a two digit BCD containig minor and sub-minor numbers.
5251 * This was later clarified in xHCI 1.2.
5253 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5254 * minor revision set to 0x1 instead of 0x10.
5256 if (xhci->usb3_rhub.min_rev == 0x1)
5259 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5261 switch (minor_rev) {
5263 hcd->speed = HCD_USB32;
5264 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5265 hcd->self.root_hub->rx_lanes = 2;
5266 hcd->self.root_hub->tx_lanes = 2;
5267 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5270 hcd->speed = HCD_USB31;
5271 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5272 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5275 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5276 minor_rev, minor_rev ? "Enhanced " : "");
5278 xhci->usb3_rhub.hcd = hcd;
5281 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5283 struct xhci_hcd *xhci;
5285 * TODO: Check with DWC3 clients for sysdev according to
5288 struct device *dev = hcd->self.sysdev;
5291 /* Accept arbitrarily long scatter-gather lists */
5292 hcd->self.sg_tablesize = ~0;
5294 /* support to build packet from discontinuous buffers */
5295 hcd->self.no_sg_constraint = 1;
5297 /* XHCI controllers don't stop the ep queue on short packets :| */
5298 hcd->self.no_stop_on_short = 1;
5300 xhci = hcd_to_xhci(hcd);
5302 if (!usb_hcd_is_primary_hcd(hcd)) {
5303 xhci_hcd_init_usb3_data(xhci, hcd);
5307 mutex_init(&xhci->mutex);
5308 xhci->main_hcd = hcd;
5309 xhci->cap_regs = hcd->regs;
5310 xhci->op_regs = hcd->regs +
5311 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5312 xhci->run_regs = hcd->regs +
5313 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5314 /* Cache read-only capability registers */
5315 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5316 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5317 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5318 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5319 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5320 if (xhci->hci_version > 0x100)
5321 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5323 xhci->quirks |= quirks;
5325 get_quirks(dev, xhci);
5327 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5328 * success event after a short transfer. This quirk will ignore such
5331 if (xhci->hci_version > 0x96)
5332 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5334 /* Make sure the HC is halted. */
5335 retval = xhci_halt(xhci);
5339 xhci_zero_64b_regs(xhci);
5341 xhci_dbg(xhci, "Resetting HCD\n");
5342 /* Reset the internal HC memory state and registers. */
5343 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5346 xhci_dbg(xhci, "Reset complete\n");
5349 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5350 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5351 * address memory pointers actually. So, this driver clears the AC64
5352 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5353 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5355 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5356 xhci->hcc_params &= ~BIT(0);
5358 /* Set dma_mask and coherent_dma_mask to 64-bits,
5359 * if xHC supports 64-bit addressing */
5360 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5361 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5362 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5363 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5366 * This is to avoid error in cases where a 32-bit USB
5367 * controller is used on a 64-bit capable system.
5369 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5372 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5373 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5376 xhci_dbg(xhci, "Calling HCD init\n");
5377 /* Initialize HCD and host controller data structures. */
5378 retval = xhci_init(hcd);
5381 xhci_dbg(xhci, "Called HCD init\n");
5383 if (xhci_hcd_is_usb3(hcd))
5384 xhci_hcd_init_usb3_data(xhci, hcd);
5386 xhci_hcd_init_usb2_data(xhci, hcd);
5388 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5389 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5393 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5395 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5396 struct usb_host_endpoint *ep)
5398 struct xhci_hcd *xhci;
5399 struct usb_device *udev;
5400 unsigned int slot_id;
5401 unsigned int ep_index;
5402 unsigned long flags;
5404 xhci = hcd_to_xhci(hcd);
5406 spin_lock_irqsave(&xhci->lock, flags);
5407 udev = (struct usb_device *)ep->hcpriv;
5408 slot_id = udev->slot_id;
5409 ep_index = xhci_get_endpoint_index(&ep->desc);
5411 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5412 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5413 spin_unlock_irqrestore(&xhci->lock, flags);
5416 static const struct hc_driver xhci_hc_driver = {
5417 .description = "xhci-hcd",
5418 .product_desc = "xHCI Host Controller",
5419 .hcd_priv_size = sizeof(struct xhci_hcd),
5422 * generic hardware linkage
5425 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5429 * basic lifecycle operations
5431 .reset = NULL, /* set in xhci_init_driver() */
5434 .shutdown = xhci_shutdown,
5437 * managing i/o requests and associated device resources
5439 .map_urb_for_dma = xhci_map_urb_for_dma,
5440 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5441 .urb_enqueue = xhci_urb_enqueue,
5442 .urb_dequeue = xhci_urb_dequeue,
5443 .alloc_dev = xhci_alloc_dev,
5444 .free_dev = xhci_free_dev,
5445 .alloc_streams = xhci_alloc_streams,
5446 .free_streams = xhci_free_streams,
5447 .add_endpoint = xhci_add_endpoint,
5448 .drop_endpoint = xhci_drop_endpoint,
5449 .endpoint_disable = xhci_endpoint_disable,
5450 .endpoint_reset = xhci_endpoint_reset,
5451 .check_bandwidth = xhci_check_bandwidth,
5452 .reset_bandwidth = xhci_reset_bandwidth,
5453 .address_device = xhci_address_device,
5454 .enable_device = xhci_enable_device,
5455 .update_hub_device = xhci_update_hub_device,
5456 .reset_device = xhci_discover_or_reset_device,
5459 * scheduling support
5461 .get_frame_number = xhci_get_frame,
5466 .hub_control = xhci_hub_control,
5467 .hub_status_data = xhci_hub_status_data,
5468 .bus_suspend = xhci_bus_suspend,
5469 .bus_resume = xhci_bus_resume,
5470 .get_resuming_ports = xhci_get_resuming_ports,
5473 * call back when device connected and addressed
5475 .update_device = xhci_update_device,
5476 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5477 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5478 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5479 .find_raw_port_number = xhci_find_raw_port_number,
5480 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5483 void xhci_init_driver(struct hc_driver *drv,
5484 const struct xhci_driver_overrides *over)
5488 /* Copy the generic table to drv then apply the overrides */
5489 *drv = xhci_hc_driver;
5492 drv->hcd_priv_size += over->extra_priv_size;
5494 drv->reset = over->reset;
5496 drv->start = over->start;
5497 if (over->add_endpoint)
5498 drv->add_endpoint = over->add_endpoint;
5499 if (over->drop_endpoint)
5500 drv->drop_endpoint = over->drop_endpoint;
5501 if (over->check_bandwidth)
5502 drv->check_bandwidth = over->check_bandwidth;
5503 if (over->reset_bandwidth)
5504 drv->reset_bandwidth = over->reset_bandwidth;
5505 if (over->hub_control)
5506 drv->hub_control = over->hub_control;
5509 EXPORT_SYMBOL_GPL(xhci_init_driver);
5511 MODULE_DESCRIPTION(DRIVER_DESC);
5512 MODULE_AUTHOR(DRIVER_AUTHOR);
5513 MODULE_LICENSE("GPL");
5515 static int __init xhci_hcd_init(void)
5518 * Check the compiler generated sizes of structures that must be laid
5519 * out in specific ways for hardware access.
5521 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5522 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5523 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5524 /* xhci_device_control has eight fields, and also
5525 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5527 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5528 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5529 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5530 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5531 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5532 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5533 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5538 xhci_debugfs_create_root();
5545 * If an init function is provided, an exit function must also be provided
5546 * to allow module unload.
5548 static void __exit xhci_hcd_fini(void)
5550 xhci_debugfs_remove_root();
5554 module_init(xhci_hcd_init);
5555 module_exit(xhci_hcd_fini);