1 // SPDX-License-Identifier: GPL-2.0+
3 * USB HOST XHCI Controller stack
5 * Based on xHCI host controller driver in linux-kernel
8 * Copyright (C) 2008 Intel Corp.
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
17 * This file gives the xhci stack for usb3.0 looking into
18 * xhci specification Rev1.0 (5/21/10).
19 * The quirk devices support hasn't been given yet.
25 #include <dm/device_compat.h>
31 #include <asm/byteorder.h>
32 #include <asm/cache.h>
33 #include <asm/unaligned.h>
34 #include <linux/bitops.h>
35 #include <linux/bug.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/iopoll.h>
40 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
41 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
44 static struct descriptor {
45 struct usb_hub_descriptor hub;
46 struct usb_device_descriptor device;
47 struct usb_config_descriptor config;
48 struct usb_interface_descriptor interface;
49 struct usb_endpoint_descriptor endpoint;
50 struct usb_ss_ep_comp_descriptor ep_companion;
51 } __attribute__ ((packed)) descriptor = {
53 0xc, /* bDescLength */
54 0x2a, /* bDescriptorType: hub descriptor */
55 2, /* bNrPorts -- runtime modified */
56 cpu_to_le16(0x8), /* wHubCharacteristics */
57 10, /* bPwrOn2PwrGood */
58 0, /* bHubCntrCurrent */
59 { /* Device removable */
60 } /* at most 7 ports! XXX */
64 1, /* bDescriptorType: UDESC_DEVICE */
65 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
66 9, /* bDeviceClass: UDCLASS_HUB */
67 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
68 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
69 9, /* bMaxPacketSize: 512 bytes 2^9 */
70 0x0000, /* idVendor */
71 0x0000, /* idProduct */
72 cpu_to_le16(0x0100), /* bcdDevice */
73 1, /* iManufacturer */
75 0, /* iSerialNumber */
76 1 /* bNumConfigurations: 1 */
80 2, /* bDescriptorType: UDESC_CONFIG */
81 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
82 1, /* bNumInterface */
83 1, /* bConfigurationValue */
84 0, /* iConfiguration */
85 0x40, /* bmAttributes: UC_SELF_POWER */
90 4, /* bDescriptorType: UDESC_INTERFACE */
91 0, /* bInterfaceNumber */
92 0, /* bAlternateSetting */
93 1, /* bNumEndpoints */
94 9, /* bInterfaceClass: UICLASS_HUB */
95 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
96 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
101 5, /* bDescriptorType: UDESC_ENDPOINT */
102 0x81, /* bEndpointAddress: IN endpoint 1 */
103 3, /* bmAttributes: UE_INTERRUPT */
104 8, /* wMaxPacketSize */
108 0x06, /* ss_bLength */
109 0x30, /* ss_bDescriptorType: SS EP Companion */
110 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
111 /* ss_bmAttributes: 1 packet per service interval */
113 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
118 #if !CONFIG_IS_ENABLED(DM_USB)
119 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
122 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
124 #if CONFIG_IS_ENABLED(DM_USB)
127 /* Find the USB controller */
128 for (dev = udev->dev;
129 device_get_uclass_id(dev) != UCLASS_USB;
132 return dev_get_priv(dev);
134 return udev->controller;
139 * Waits for as per specified amount of time
140 * for the "result" to match with "done"
142 * @param ptr pointer to the register to be read
143 * @param mask mask for the value read
144 * @param done value to be campared with result
145 * @param usec time to wait till
146 * @return 0 if handshake is success else < 0 on failure
149 handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec)
154 ret = readx_poll_sleep_timeout(xhci_readl, ptr, result,
155 (result & mask) == done || result == U32_MAX,
157 if (result == U32_MAX) /* card removed */
164 * Set the run bit and wait for the host to be running.
166 * @param hcor pointer to host controller operation registers
167 * @return status of the Handshake
169 static int xhci_start(struct xhci_hcor *hcor)
174 puts("Starting the controller\n");
175 temp = xhci_readl(&hcor->or_usbcmd);
177 xhci_writel(&hcor->or_usbcmd, temp);
180 * Wait for the HCHalted Status bit to be 0 to indicate the host is
183 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
185 debug("Host took too long to start, "
186 "waited %u microseconds.\n",
191 #if CONFIG_IS_ENABLED(DM_USB)
193 * Resets XHCI Hardware
195 * @param ctrl pointer to host controller
196 * @return 0 if OK, or a negative error code.
198 static int xhci_reset_hw(struct xhci_ctrl *ctrl)
202 ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
203 if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
204 dev_err(ctrl->dev, "failed to get reset\n");
208 if (reset_valid(&ctrl->reset)) {
209 ret = reset_assert(&ctrl->reset);
213 ret = reset_deassert(&ctrl->reset);
223 * Resets the XHCI Controller
225 * @param hcor pointer to host controller operation registers
226 * @return -EBUSY if XHCI Controller is not halted else status of handshake
228 static int xhci_reset(struct xhci_hcor *hcor)
234 /* Halting the Host first */
235 debug("// Halt the HC: %p\n", hcor);
236 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
238 cmd = xhci_readl(&hcor->or_usbcmd);
240 xhci_writel(&hcor->or_usbcmd, cmd);
243 ret = handshake(&hcor->or_usbsts,
244 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
246 printf("Host not halted after %u microseconds.\n",
251 debug("// Reset the HC\n");
252 cmd = xhci_readl(&hcor->or_usbcmd);
254 xhci_writel(&hcor->or_usbcmd, cmd);
256 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
261 * xHCI cannot write to any doorbells or operational registers other
262 * than status until the "Controller Not Ready" flag is cleared.
264 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
268 * Used for passing endpoint bitmasks between the core and HCDs.
269 * Find the index for an endpoint given its descriptor.
270 * Use the return value to right shift 1 for the bitmask.
272 * Index = (epnum * 2) + direction - 1,
273 * where direction = 0 for OUT, 1 for IN.
274 * For control endpoints, the IN index is used (OUT index is unused), so
275 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
277 * @param desc USB enpdoint Descriptor
278 * @return index of the Endpoint
280 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
284 if (usb_endpoint_xfer_control(desc))
285 index = (unsigned int)(usb_endpoint_num(desc) * 2);
287 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
288 (usb_endpoint_dir_in(desc) ? 0 : 1));
294 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
295 * microframes, rounded down to nearest power of 2.
297 static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
298 unsigned int min_exponent,
299 unsigned int max_exponent)
301 unsigned int interval;
303 interval = fls(desc_interval) - 1;
304 interval = clamp_val(interval, min_exponent, max_exponent);
305 if ((1 << interval) != desc_interval)
306 debug("rounding interval to %d microframes, "\
307 "ep desc says %d microframes\n",
308 1 << interval, desc_interval);
313 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
314 struct usb_endpoint_descriptor *endpt_desc)
316 if (endpt_desc->bInterval == 0)
319 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
322 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
323 struct usb_endpoint_descriptor *endpt_desc)
325 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
329 * Convert interval expressed as 2^(bInterval - 1) == interval into
330 * straight exponent value 2^n == interval.
332 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
333 struct usb_endpoint_descriptor *endpt_desc)
335 unsigned int interval;
337 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
338 if (interval != endpt_desc->bInterval - 1)
339 debug("ep %#x - rounding interval to %d %sframes\n",
340 endpt_desc->bEndpointAddress, 1 << interval,
341 udev->speed == USB_SPEED_FULL ? "" : "micro");
343 if (udev->speed == USB_SPEED_FULL) {
345 * Full speed isoc endpoints specify interval in frames,
346 * not microframes. We are using microframes everywhere,
347 * so adjust accordingly.
349 interval += 3; /* 1 frame = 2^3 uframes */
356 * Return the polling or NAK interval.
358 * The polling interval is expressed in "microframes". If xHCI's Interval field
359 * is set to N, it will service the endpoint every 2^(Interval)*125us.
361 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
364 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
365 struct usb_endpoint_descriptor *endpt_desc)
367 unsigned int interval = 0;
369 switch (udev->speed) {
372 if (usb_endpoint_xfer_control(endpt_desc) ||
373 usb_endpoint_xfer_bulk(endpt_desc)) {
374 interval = xhci_parse_microframe_interval(udev,
378 /* Fall through - SS and HS isoc/int have same decoding */
380 case USB_SPEED_SUPER:
381 if (usb_endpoint_xfer_int(endpt_desc) ||
382 usb_endpoint_xfer_isoc(endpt_desc)) {
383 interval = xhci_parse_exponent_interval(udev,
389 if (usb_endpoint_xfer_isoc(endpt_desc)) {
390 interval = xhci_parse_exponent_interval(udev,
395 * Fall through for interrupt endpoint interval decoding
396 * since it uses the same rules as low speed interrupt
401 if (usb_endpoint_xfer_int(endpt_desc) ||
402 usb_endpoint_xfer_isoc(endpt_desc)) {
403 interval = xhci_parse_frame_interval(udev, endpt_desc);
415 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
416 * High speed endpoint descriptors can define "the number of additional
417 * transaction opportunities per microframe", but that goes in the Max Burst
418 * endpoint context field.
420 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
421 struct usb_endpoint_descriptor *endpt_desc,
422 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
424 if (udev->speed < USB_SPEED_SUPER ||
425 !usb_endpoint_xfer_isoc(endpt_desc))
428 return ss_ep_comp_desc->bmAttributes;
431 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
432 struct usb_endpoint_descriptor *endpt_desc,
433 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
435 /* Super speed and Plus have max burst in ep companion desc */
436 if (udev->speed >= USB_SPEED_SUPER)
437 return ss_ep_comp_desc->bMaxBurst;
439 if (udev->speed == USB_SPEED_HIGH &&
440 (usb_endpoint_xfer_isoc(endpt_desc) ||
441 usb_endpoint_xfer_int(endpt_desc)))
442 return usb_endpoint_maxp_mult(endpt_desc) - 1;
448 * Return the maximum endpoint service interval time (ESIT) payload.
449 * Basically, this is the maxpacket size, multiplied by the burst size
452 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
453 struct usb_endpoint_descriptor *endpt_desc,
454 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
459 /* Only applies for interrupt or isochronous endpoints */
460 if (usb_endpoint_xfer_control(endpt_desc) ||
461 usb_endpoint_xfer_bulk(endpt_desc))
464 /* SuperSpeed Isoc ep with less than 48k per esit */
465 if (udev->speed >= USB_SPEED_SUPER)
466 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
468 max_packet = usb_endpoint_maxp(endpt_desc);
469 max_burst = usb_endpoint_maxp_mult(endpt_desc);
471 /* A 0 in max burst means 1 transfer per ESIT */
472 return max_packet * max_burst;
476 * Issue a configure endpoint command or evaluate context command
477 * and wait for it to finish.
479 * @param udev pointer to the Device Data Structure
480 * @param ctx_change flag to indicate the Context has changed or NOT
481 * @return 0 on success, -1 on failure
483 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
485 struct xhci_container_ctx *in_ctx;
486 struct xhci_virt_device *virt_dev;
487 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
488 union xhci_trb *event;
490 virt_dev = ctrl->devs[udev->slot_id];
491 in_ctx = virt_dev->in_ctx;
493 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
494 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
495 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
496 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
497 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
500 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
502 debug("Successful %s command\n",
503 ctx_change ? "Evaluate Context" : "Configure Endpoint");
506 printf("ERROR: %s command returned completion code %d.\n",
507 ctx_change ? "Evaluate Context" : "Configure Endpoint",
508 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
512 xhci_acknowledge_event(ctrl);
518 * Configure the endpoint, programming the device contexts.
520 * @param udev pointer to the USB device structure
521 * @return returns the status of the xhci_configure_endpoints
523 static int xhci_set_configuration(struct usb_device *udev)
525 struct xhci_container_ctx *in_ctx;
526 struct xhci_container_ctx *out_ctx;
527 struct xhci_input_control_ctx *ctrl_ctx;
528 struct xhci_slot_ctx *slot_ctx;
529 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
534 unsigned int ep_type;
535 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
539 int slot_id = udev->slot_id;
540 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
541 struct usb_interface *ifdesc;
542 u32 max_esit_payload;
543 unsigned int interval;
545 unsigned int max_burst;
546 unsigned int avg_trb_len;
547 unsigned int err_count = 0;
549 out_ctx = virt_dev->out_ctx;
550 in_ctx = virt_dev->in_ctx;
552 num_of_ep = udev->config.if_desc[0].no_of_ep;
553 ifdesc = &udev->config.if_desc[0];
555 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
556 /* Initialize the input context control */
557 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
558 ctrl_ctx->drop_flags = 0;
560 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
561 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
562 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
563 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
564 if (max_ep_flag < ep_flag)
565 max_ep_flag = ep_flag;
568 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
571 xhci_slot_copy(ctrl, in_ctx, out_ctx);
572 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
573 slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
574 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
576 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
578 /* filling up ep contexts */
579 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
580 struct usb_endpoint_descriptor *endpt_desc = NULL;
581 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
583 endpt_desc = &ifdesc->ep_desc[cur_ep];
584 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
588 * Get values to fill the endpoint context, mostly from ep
589 * descriptor. The average TRB buffer lengt for bulk endpoints
590 * is unclear as we have no clue on scatter gather list entry
591 * size. For Isoc and Int, set it to max available.
592 * See xHCI 1.1 spec 4.14.1.1 for details.
594 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
596 interval = xhci_get_endpoint_interval(udev, endpt_desc);
597 mult = xhci_get_endpoint_mult(udev, endpt_desc,
599 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
601 avg_trb_len = max_esit_payload;
603 ep_index = xhci_get_ep_index(endpt_desc);
604 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
606 /* Allocate the ep rings */
607 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
608 if (!virt_dev->eps[ep_index].ring)
611 /*NOTE: ep_desc[0] actually represents EP1 and so on */
612 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
613 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
615 ep_ctx[ep_index]->ep_info =
616 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
617 EP_INTERVAL(interval) | EP_MULT(mult));
619 ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
620 ep_ctx[ep_index]->ep_info2 |=
621 cpu_to_le32(MAX_PACKET
622 (get_unaligned(&endpt_desc->wMaxPacketSize)));
624 /* Allow 3 retries for everything but isoc, set CErr = 3 */
625 if (!usb_endpoint_xfer_isoc(endpt_desc))
627 ep_ctx[ep_index]->ep_info2 |=
628 cpu_to_le32(MAX_BURST(max_burst) |
629 ERROR_COUNT(err_count));
631 trb_64 = virt_to_phys(virt_dev->eps[ep_index].ring->enqueue);
632 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
633 virt_dev->eps[ep_index].ring->cycle_state);
637 * 'Average TRB Length' should be 8 for control endpoints.
639 if (usb_endpoint_xfer_control(endpt_desc))
641 ep_ctx[ep_index]->tx_info =
642 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
643 EP_AVG_TRB_LENGTH(avg_trb_len));
646 * The MediaTek xHCI defines some extra SW parameters which
647 * are put into reserved DWs in Slot and Endpoint Contexts
648 * for synchronous endpoints.
650 if (ctrl->quirks & XHCI_MTK_HOST) {
651 ep_ctx[ep_index]->reserved[0] =
652 cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
656 return xhci_configure_endpoints(udev, false);
660 * Issue an Address Device command (which will issue a SetAddress request to
663 * @param udev pointer to the Device Data Structure
664 * @return 0 if successful else error code on failure
666 static int xhci_address_device(struct usb_device *udev, int root_portnr)
669 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
670 struct xhci_slot_ctx *slot_ctx;
671 struct xhci_input_control_ctx *ctrl_ctx;
672 struct xhci_virt_device *virt_dev;
673 int slot_id = udev->slot_id;
674 union xhci_trb *event;
676 virt_dev = ctrl->devs[slot_id];
679 * This is the first Set Address since device plug-in
680 * so setting up the slot context.
682 debug("Setting up addressable devices %p\n", ctrl->dcbaa);
683 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
685 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
686 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
687 ctrl_ctx->drop_flags = 0;
689 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
690 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
691 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
693 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
696 printf("Setup ERROR: address device command for slot %d.\n",
701 puts("Device not responding to set address.\n");
705 puts("ERROR: Incompatible device"
706 "for address device command.\n");
710 debug("Successful Address Device command\n");
714 printf("ERROR: unexpected command completion code 0x%x.\n",
715 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
720 xhci_acknowledge_event(ctrl);
724 * TODO: Unsuccessful Address Device command shall leave the
725 * slot in default state. So, issue Disable Slot command now.
729 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
730 virt_dev->out_ctx->size);
731 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
733 debug("xHC internal address is: %d\n",
734 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
740 * Issue Enable slot command to the controller to allocate
741 * device slot and assign the slot id. It fails if the xHC
742 * ran out of device slots, the Enable Slot command timed out,
743 * or allocating memory failed.
745 * @param udev pointer to the Device Data Structure
746 * @return Returns 0 on succes else return error code on failure
748 static int _xhci_alloc_device(struct usb_device *udev)
750 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
751 union xhci_trb *event;
755 * Root hub will be first device to be initailized.
756 * If this device is root-hub, don't do any xHC related
759 if (ctrl->rootdev == 0) {
760 udev->speed = USB_SPEED_SUPER;
764 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
765 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
766 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
769 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
771 xhci_acknowledge_event(ctrl);
773 ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
776 * TODO: Unsuccessful Address Device command shall leave
777 * the slot in default. So, issue Disable Slot command now.
779 puts("Could not allocate xHCI USB device data structures\n");
786 #if !CONFIG_IS_ENABLED(DM_USB)
787 int usb_alloc_device(struct usb_device *udev)
789 return _xhci_alloc_device(udev);
794 * Full speed devices may have a max packet size greater than 8 bytes, but the
795 * USB core doesn't know that until it reads the first 8 bytes of the
796 * descriptor. If the usb_device's max packet size changes after that point,
797 * we need to issue an evaluate context command and wait on it.
799 * @param udev pointer to the Device Data Structure
800 * @return returns the status of the xhci_configure_endpoints
802 int xhci_check_maxpacket(struct usb_device *udev)
804 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
805 unsigned int slot_id = udev->slot_id;
806 int ep_index = 0; /* control endpoint */
807 struct xhci_container_ctx *in_ctx;
808 struct xhci_container_ctx *out_ctx;
809 struct xhci_input_control_ctx *ctrl_ctx;
810 struct xhci_ep_ctx *ep_ctx;
812 int hw_max_packet_size;
815 out_ctx = ctrl->devs[slot_id]->out_ctx;
816 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
818 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
819 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
820 max_packet_size = udev->epmaxpacketin[0];
821 if (hw_max_packet_size != max_packet_size) {
822 debug("Max Packet Size for ep 0 changed.\n");
823 debug("Max packet size in usb_device = %d\n", max_packet_size);
824 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
825 debug("Issuing evaluate context command.\n");
827 /* Set up the modified control endpoint 0 */
828 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
829 ctrl->devs[slot_id]->out_ctx, ep_index);
830 in_ctx = ctrl->devs[slot_id]->in_ctx;
831 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
832 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
833 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
836 * Set up the input context flags for the command
837 * FIXME: This won't work if a non-default control endpoint
838 * changes max packet sizes.
840 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
841 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
842 ctrl_ctx->drop_flags = 0;
844 ret = xhci_configure_endpoints(udev, true);
850 * Clears the Change bits of the Port Status Register
852 * @param wValue request value
853 * @param wIndex request index
854 * @param addr address of posrt status register
855 * @param port_status state of port status register
858 static void xhci_clear_port_change_bit(u16 wValue,
859 u16 wIndex, volatile uint32_t *addr, u32 port_status)
861 char *port_change_bit;
865 case USB_PORT_FEAT_C_RESET:
867 port_change_bit = "reset";
869 case USB_PORT_FEAT_C_CONNECTION:
871 port_change_bit = "connect";
873 case USB_PORT_FEAT_C_OVER_CURRENT:
875 port_change_bit = "over-current";
877 case USB_PORT_FEAT_C_ENABLE:
879 port_change_bit = "enable/disable";
881 case USB_PORT_FEAT_C_SUSPEND:
883 port_change_bit = "suspend/resume";
886 /* Should never happen */
890 /* Change bits are all write 1 to clear */
891 xhci_writel(addr, port_status | status);
893 port_status = xhci_readl(addr);
894 debug("clear port %s change, actual port %d status = 0x%x\n",
895 port_change_bit, wIndex, port_status);
899 * Save Read Only (RO) bits and save read/write bits where
900 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
901 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
903 * @param state state of the Port Status and Control Regsiter
904 * @return a value that would result in the port being in the
905 * same state, if the value was written to the port
906 * status control register.
908 static u32 xhci_port_state_to_neutral(u32 state)
910 /* Save read-only status and port state */
911 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
915 * Submits the Requests to the XHCI Host Controller
917 * @param udev pointer to the USB device structure
918 * @param pipe contains the DIR_IN or OUT , devnum
919 * @param buffer buffer to be read/written based on the request
920 * @return returns 0 if successful else -1 on failure
922 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
923 void *buffer, struct devrequest *req)
930 volatile uint32_t *status_reg;
931 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
932 struct xhci_hccr *hccr = ctrl->hccr;
933 struct xhci_hcor *hcor = ctrl->hcor;
934 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
936 if ((req->requesttype & USB_RT_PORT) &&
937 le16_to_cpu(req->index) > max_ports) {
938 printf("The request port(%d) exceeds maximum port number\n",
939 le16_to_cpu(req->index) - 1);
943 status_reg = (volatile uint32_t *)
944 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
947 typeReq = req->request | req->requesttype << 8;
950 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
951 switch (le16_to_cpu(req->value) >> 8) {
953 debug("USB_DT_DEVICE request\n");
954 srcptr = &descriptor.device;
958 debug("USB_DT_CONFIG config\n");
959 srcptr = &descriptor.config;
963 debug("USB_DT_STRING config\n");
964 switch (le16_to_cpu(req->value) & 0xff) {
965 case 0: /* Language */
966 srcptr = "\4\3\11\4";
969 case 1: /* Vendor String */
970 srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
973 case 2: /* Product Name */
974 srcptr = "\52\3X\0H\0C\0I\0 "
976 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
980 printf("unknown value DT_STRING %x\n",
981 le16_to_cpu(req->value));
986 printf("unknown value %x\n", le16_to_cpu(req->value));
990 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
991 switch (le16_to_cpu(req->value) >> 8) {
994 debug("USB_DT_HUB config\n");
995 srcptr = &descriptor.hub;
999 printf("unknown value %x\n", le16_to_cpu(req->value));
1003 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
1004 debug("USB_REQ_SET_ADDRESS\n");
1005 ctrl->rootdev = le16_to_cpu(req->value);
1007 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
1010 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
1011 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
1016 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
1017 memset(tmpbuf, 0, 4);
1018 reg = xhci_readl(status_reg);
1019 if (reg & PORT_CONNECT) {
1020 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
1021 switch (reg & DEV_SPEED_MASK) {
1023 debug("SPEED = FULLSPEED\n");
1026 debug("SPEED = LOWSPEED\n");
1027 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
1030 debug("SPEED = HIGHSPEED\n");
1031 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
1034 debug("SPEED = SUPERSPEED\n");
1035 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
1040 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
1041 if ((reg & PORT_PLS_MASK) == XDEV_U3)
1042 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
1044 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
1045 if (reg & PORT_RESET)
1046 tmpbuf[0] |= USB_PORT_STAT_RESET;
1047 if (reg & PORT_POWER)
1049 * XXX: This Port power bit (for USB 3.0 hub)
1050 * we are faking in USB 2.0 hub port status;
1051 * since there's a change in bit positions in
1053 * USB 2.0 port status PP is at position[8]
1054 * USB 3.0 port status PP is at position[9]
1055 * So, we are still keeping it at position [8]
1057 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
1059 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
1061 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
1063 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
1065 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
1070 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1071 reg = xhci_readl(status_reg);
1072 reg = xhci_port_state_to_neutral(reg);
1073 switch (le16_to_cpu(req->value)) {
1074 case USB_PORT_FEAT_ENABLE:
1076 xhci_writel(status_reg, reg);
1078 case USB_PORT_FEAT_POWER:
1080 xhci_writel(status_reg, reg);
1082 case USB_PORT_FEAT_RESET:
1084 xhci_writel(status_reg, reg);
1087 printf("unknown feature %x\n", le16_to_cpu(req->value));
1091 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1092 reg = xhci_readl(status_reg);
1093 reg = xhci_port_state_to_neutral(reg);
1094 switch (le16_to_cpu(req->value)) {
1095 case USB_PORT_FEAT_ENABLE:
1098 case USB_PORT_FEAT_POWER:
1101 case USB_PORT_FEAT_C_RESET:
1102 case USB_PORT_FEAT_C_CONNECTION:
1103 case USB_PORT_FEAT_C_OVER_CURRENT:
1104 case USB_PORT_FEAT_C_ENABLE:
1105 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
1106 le16_to_cpu(req->index),
1110 printf("unknown feature %x\n", le16_to_cpu(req->value));
1113 xhci_writel(status_reg, reg);
1116 puts("Unknown request\n");
1120 debug("scrlen = %d\n req->length = %d\n",
1121 srclen, le16_to_cpu(req->length));
1123 len = min(srclen, (int)le16_to_cpu(req->length));
1125 if (srcptr != NULL && len > 0)
1126 memcpy(buffer, srcptr, len);
1128 debug("Len is 0\n");
1130 udev->act_len = len;
1137 udev->status = USB_ST_STALLED;
1143 * Submits the INT request to XHCI Host cotroller
1145 * @param udev pointer to the USB device
1146 * @param pipe contains the DIR_IN or OUT , devnum
1147 * @param buffer buffer to be read/written based on the request
1148 * @param length length of the buffer
1149 * @param interval interval of the interrupt
1152 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
1153 void *buffer, int length, int interval,
1156 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1157 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1162 * xHCI uses normal TRBs for both bulk and interrupt. When the
1163 * interrupt endpoint is to be serviced, the xHC will consume
1164 * (at most) one TD. A TD (comprised of sg list entries) can
1165 * take several service intervals to transmit.
1167 return xhci_bulk_tx(udev, pipe, length, buffer);
1171 * submit the BULK type of request to the USB Device
1173 * @param udev pointer to the USB device
1174 * @param pipe contains the DIR_IN or OUT , devnum
1175 * @param buffer buffer to be read/written based on the request
1176 * @param length length of the buffer
1177 * @return returns 0 if successful else -1 on failure
1179 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
1180 void *buffer, int length)
1182 if (usb_pipetype(pipe) != PIPE_BULK) {
1183 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1187 return xhci_bulk_tx(udev, pipe, length, buffer);
1191 * submit the control type of request to the Root hub/Device based on the devnum
1193 * @param udev pointer to the USB device
1194 * @param pipe contains the DIR_IN or OUT , devnum
1195 * @param buffer buffer to be read/written based on the request
1196 * @param length length of the buffer
1197 * @param setup Request type
1198 * @param root_portnr Root port number that this device is on
1199 * @return returns 0 if successful else -1 on failure
1201 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
1202 void *buffer, int length,
1203 struct devrequest *setup, int root_portnr)
1205 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
1208 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1209 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
1213 if (usb_pipedevice(pipe) == ctrl->rootdev)
1214 return xhci_submit_root(udev, pipe, buffer, setup);
1216 if (setup->request == USB_REQ_SET_ADDRESS &&
1217 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1218 return xhci_address_device(udev, root_portnr);
1220 if (setup->request == USB_REQ_SET_CONFIGURATION &&
1221 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 ret = xhci_set_configuration(udev);
1224 puts("Failed to configure xHCI endpoint\n");
1229 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
1232 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
1234 struct xhci_hccr *hccr;
1235 struct xhci_hcor *hcor;
1243 * Program the Number of Device Slots Enabled field in the CONFIG
1244 * register with the max value of slots the HC can handle.
1246 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
1247 val2 = xhci_readl(&hcor->or_config);
1248 val |= (val2 & ~HCS_SLOTS_MASK);
1249 xhci_writel(&hcor->or_config, val);
1251 /* initializing xhci data structures */
1252 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
1255 reg = xhci_readl(&hccr->cr_hcsparams1);
1256 descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg);
1257 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1259 /* Port Indicators */
1260 reg = xhci_readl(&hccr->cr_hccparams);
1261 if (HCS_INDICATOR(reg))
1262 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1263 | 0x80, &descriptor.hub.wHubCharacteristics);
1265 /* Port Power Control */
1267 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1268 | 0x01, &descriptor.hub.wHubCharacteristics);
1270 if (xhci_start(hcor)) {
1275 /* Zero'ing IRQ control register and IRQ pending register */
1276 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1277 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1279 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1280 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1281 ctrl->hci_version = reg;
1286 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
1290 xhci_reset(ctrl->hcor);
1292 debug("// Disabling event ring interrupts\n");
1293 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1294 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1295 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1296 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1301 #if !CONFIG_IS_ENABLED(DM_USB)
1302 int submit_control_msg(struct usb_device *udev, unsigned long pipe,
1303 void *buffer, int length, struct devrequest *setup)
1305 struct usb_device *hop = udev;
1308 while (hop->parent->parent)
1311 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1315 int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1318 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1321 int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1322 int length, int interval, bool nonblock)
1324 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
1329 * Intialises the XHCI host controller
1330 * and allocates the necessary data structures
1332 * @param index index to the host controller data structure
1333 * @return pointer to the intialised controller
1335 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1337 struct xhci_hccr *hccr;
1338 struct xhci_hcor *hcor;
1339 struct xhci_ctrl *ctrl;
1344 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
1347 if (xhci_reset(hcor) != 0)
1350 ctrl = &xhcic[index];
1355 ret = xhci_lowlevel_init(ctrl);
1361 *controller = &xhcic[index];
1368 * Stops the XHCI host controller
1369 * and cleans up all the related data structures
1371 * @param index index to the host controller data structure
1374 int usb_lowlevel_stop(int index)
1376 struct xhci_ctrl *ctrl = (xhcic + index);
1379 xhci_lowlevel_stop(ctrl);
1380 xhci_hcd_stop(index);
1386 #endif /* CONFIG_IS_ENABLED(DM_USB) */
1388 #if CONFIG_IS_ENABLED(DM_USB)
1390 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1391 unsigned long pipe, void *buffer, int length,
1392 struct devrequest *setup)
1394 struct usb_device *uhop;
1395 struct udevice *hub;
1396 int root_portnr = 0;
1398 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1399 dev->name, udev, udev->dev->name, udev->portnr);
1401 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
1402 /* Figure out our port number on the root hub */
1403 if (usb_hub_is_root_hub(hub)) {
1404 root_portnr = udev->portnr;
1406 while (!usb_hub_is_root_hub(hub->parent))
1408 uhop = dev_get_parent_priv(hub);
1409 root_portnr = uhop->portnr;
1413 struct usb_device *hop = udev;
1416 while (hop->parent->parent)
1419 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1423 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1424 unsigned long pipe, void *buffer, int length)
1426 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1427 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1430 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1431 unsigned long pipe, void *buffer, int length,
1432 int interval, bool nonblock)
1434 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1435 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
1439 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
1441 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1442 return _xhci_alloc_device(udev);
1445 static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
1447 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1448 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
1449 struct xhci_virt_device *virt_dev;
1450 struct xhci_input_control_ctx *ctrl_ctx;
1451 struct xhci_container_ctx *out_ctx;
1452 struct xhci_container_ctx *in_ctx;
1453 struct xhci_slot_ctx *slot_ctx;
1454 int slot_id = udev->slot_id;
1455 unsigned think_time;
1457 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1459 /* Ignore root hubs */
1460 if (usb_hub_is_root_hub(udev->dev))
1463 virt_dev = ctrl->devs[slot_id];
1466 out_ctx = virt_dev->out_ctx;
1467 in_ctx = virt_dev->in_ctx;
1469 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1470 /* Initialize the input context control */
1471 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1472 ctrl_ctx->drop_flags = 0;
1474 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
1477 xhci_slot_copy(ctrl, in_ctx, out_ctx);
1478 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
1480 /* Update hub related fields */
1481 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
1483 * refer to section 6.2.2: MTT should be 0 for full speed hub,
1484 * but it may be already set to 1 when setup an xHCI virtual
1485 * device, so clear it anyway.
1488 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1489 else if (udev->speed == USB_SPEED_FULL)
1490 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
1491 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
1493 * Set TT think time - convert from ns to FS bit times.
1494 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
1496 * 0 = 8 FS bit times, 1 = 16 FS bit times,
1497 * 2 = 24 FS bit times, 3 = 32 FS bit times.
1499 * This field shall be 0 if the device is not a high-spped hub.
1501 think_time = hub->tt.think_time;
1502 if (think_time != 0)
1503 think_time = (think_time / 666) - 1;
1504 if (udev->speed == USB_SPEED_HIGH)
1505 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
1506 slot_ctx->dev_state = 0;
1508 return xhci_configure_endpoints(udev, false);
1511 static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
1514 * xHCD allocates one segment which includes 64 TRBs for each endpoint
1515 * and the last TRB in this segment is configured as a link TRB to form
1516 * a TRB ring. Each TRB can transfer up to 64K bytes, however data
1517 * buffers referenced by transfer TRBs shall not span 64KB boundaries.
1518 * Hence the maximum number of TRBs we can use in one transfer is 62.
1520 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
1525 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
1526 struct xhci_hcor *hcor)
1528 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1529 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1532 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
1537 ret = xhci_reset_hw(ctrl);
1542 * XHCI needs to issue a Address device command to setup
1543 * proper device context structures, before it can interact
1544 * with the device. So a get_descriptor will fail before any
1545 * of that is done for XHCI unlike EHCI.
1547 priv->desc_before_addr = false;
1549 ret = xhci_reset(hcor);
1555 ret = xhci_lowlevel_init(ctrl);
1562 debug("%s: failed, ret=%d\n", __func__, ret);
1566 int xhci_deregister(struct udevice *dev)
1568 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1570 xhci_lowlevel_stop(ctrl);
1576 struct dm_usb_ops xhci_usb_ops = {
1577 .control = xhci_submit_control_msg,
1578 .bulk = xhci_submit_bulk_msg,
1579 .interrupt = xhci_submit_int_msg,
1580 .alloc_device = xhci_alloc_device,
1581 .update_hub_device = xhci_update_hub_device,
1582 .get_max_xfer_size = xhci_get_max_xfer_size,