1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
129 * Set the run bit and wait for the host to be running.
131 int xhci_start(struct xhci_hcd *xhci)
136 temp = readl(&xhci->op_regs->command);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 writel(temp, &xhci->op_regs->command);
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
153 /* clear state flags. Including dying, halted or removing */
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
166 int xhci_reset(struct xhci_hcd *xhci)
172 state = readl(&xhci->op_regs->status);
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
196 if (xhci->quirks & XHCI_INTEL_HOST)
199 // Hack: reduce handshake timeout from 10s 0.5s due to unprogrammed vl805
200 ret = xhci_handshake(&xhci->op_regs->command,
201 CMD_RESET, 0, 500 * 1000);
205 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
206 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
208 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
209 "Wait for controller to be ready for doorbell rings");
211 * xHCI cannot write to any doorbells or operational registers other
212 * than status until the "Controller Not Ready" flag is cleared.
214 ret = xhci_handshake(&xhci->op_regs->status,
215 STS_CNR, 0, 10 * 1000 * 1000);
217 for (i = 0; i < 2; i++) {
218 xhci->bus_state[i].port_c_suspend = 0;
219 xhci->bus_state[i].suspended_ports = 0;
220 xhci->bus_state[i].resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !dev->iommu_group)
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
286 xhci_info(xhci, "Fault detected\n");
289 #ifdef CONFIG_USB_PCI
293 static int xhci_setup_msi(struct xhci_hcd *xhci)
297 * TODO:Check with MSI Soc for sysdev
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
322 static int xhci_setup_msix(struct xhci_hcd *xhci)
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
353 hcd->msix_enabled = 1;
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
364 /* Free any IRQs and disable MSI-X */
365 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
370 if (xhci->quirks & XHCI_PLAT)
373 /* return if using legacy interrupt */
377 if (hcd->msix_enabled) {
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
390 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
403 static int xhci_try_enable_msi(struct usb_hcd *hcd)
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
418 if (xhci->quirks & XHCI_BROKEN_MSI)
421 /* unregister the legacy interrupt */
423 free_irq(hcd->irq, hcd);
426 ret = xhci_setup_msix(xhci);
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
432 hcd->msi_enabled = 1;
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
450 xhci_err(xhci, "request interrupt %d failed\n",
454 hcd->irq = pdev->irq;
460 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
465 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
469 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
475 static void compliance_mode_recovery(struct timer_list *t)
477 struct xhci_hcd *xhci;
479 struct xhci_hub *rhub;
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
503 usb_hcd_poll_rh_status(hcd);
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
522 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
541 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
543 const char *dmi_product_name, *dmi_sys_vendor;
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
562 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
569 * Initialize memory for HCD and xHC (one-time init).
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
575 static int xhci_init(struct usb_hcd *hcd)
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
602 /*-------------------------------------------------------------------------*/
605 static int xhci_run_finished(struct xhci_hcd *xhci)
607 if (xhci_start(xhci)) {
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
623 * Start the HC after it was halted.
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
632 * Setup MSI-X vectors and enable interrupts.
634 int xhci_run(struct usb_hcd *hcd)
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
651 ret = xhci_try_enable_msi(hcd);
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
690 xhci_free_command(xhci, command);
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
697 xhci_debugfs_init(xhci);
701 EXPORT_SYMBOL_GPL(xhci_run);
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
712 static void xhci_stop(struct usb_hcd *hcd)
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
717 mutex_lock(&xhci->mutex);
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
732 spin_unlock_irq(&xhci->lock);
734 xhci_cleanup_msix(xhci);
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
765 * Shutdown HC (not bus-specific)
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
773 void xhci_shutdown(struct usb_hcd *hcd)
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
780 spin_lock_irq(&xhci->lock);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
785 spin_unlock_irq(&xhci->lock);
787 xhci_cleanup_msix(xhci);
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
793 EXPORT_SYMBOL_GPL(xhci_shutdown);
796 static void xhci_save_registers(struct xhci_hcd *xhci)
798 xhci->s3.command = readl(&xhci->op_regs->command);
799 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
800 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
801 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
802 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
803 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
804 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
805 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
806 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
809 static void xhci_restore_registers(struct xhci_hcd *xhci)
811 writel(xhci->s3.command, &xhci->op_regs->command);
812 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
813 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
814 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
815 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
816 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
817 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
818 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
819 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
822 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
826 /* step 2: initialize command ring buffer */
827 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
828 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
829 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
830 xhci->cmd_ring->dequeue) &
831 (u64) ~CMD_RING_RSVD_BITS) |
832 xhci->cmd_ring->cycle_state;
833 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
834 "// Setting command ring address to 0x%llx",
835 (long unsigned long) val_64);
836 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
840 * The whole command ring must be cleared to zero when we suspend the host.
842 * The host doesn't save the command ring pointer in the suspend well, so we
843 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
844 * aligned, because of the reserved bits in the command ring dequeue pointer
845 * register. Therefore, we can't just set the dequeue pointer back in the
846 * middle of the ring (TRBs are 16-byte aligned).
848 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
850 struct xhci_ring *ring;
851 struct xhci_segment *seg;
853 ring = xhci->cmd_ring;
857 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
858 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
859 cpu_to_le32(~TRB_CYCLE);
861 } while (seg != ring->deq_seg);
863 /* Reset the software enqueue and dequeue pointers */
864 ring->deq_seg = ring->first_seg;
865 ring->dequeue = ring->first_seg->trbs;
866 ring->enq_seg = ring->deq_seg;
867 ring->enqueue = ring->dequeue;
869 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
871 * Ring is now zeroed, so the HW should look for change of ownership
872 * when the cycle bit is set to 1.
874 ring->cycle_state = 1;
877 * Reset the hardware dequeue pointer.
878 * Yes, this will need to be re-written after resume, but we're paranoid
879 * and want to make sure the hardware doesn't access bogus memory
880 * because, say, the BIOS or an SMI started the host without changing
881 * the command ring pointers.
883 xhci_set_cmd_ring_deq(xhci);
886 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
888 struct xhci_port **ports;
893 spin_lock_irqsave(&xhci->lock, flags);
895 /* disable usb3 ports Wake bits */
896 port_index = xhci->usb3_rhub.num_ports;
897 ports = xhci->usb3_rhub.ports;
898 while (port_index--) {
899 t1 = readl(ports[port_index]->addr);
900 t1 = xhci_port_state_to_neutral(t1);
901 t2 = t1 & ~PORT_WAKE_BITS;
903 writel(t2, ports[port_index]->addr);
906 /* disable usb2 ports Wake bits */
907 port_index = xhci->usb2_rhub.num_ports;
908 ports = xhci->usb2_rhub.ports;
909 while (port_index--) {
910 t1 = readl(ports[port_index]->addr);
911 t1 = xhci_port_state_to_neutral(t1);
912 t2 = t1 & ~PORT_WAKE_BITS;
914 writel(t2, ports[port_index]->addr);
917 spin_unlock_irqrestore(&xhci->lock, flags);
920 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
922 struct xhci_port **ports;
927 status = readl(&xhci->op_regs->status);
928 if (status & STS_EINT)
931 * Checking STS_EINT is not enough as there is a lag between a change
932 * bit being set and the Port Status Change Event that it generated
933 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
936 port_index = xhci->usb2_rhub.num_ports;
937 ports = xhci->usb2_rhub.ports;
938 while (port_index--) {
939 portsc = readl(ports[port_index]->addr);
940 if (portsc & PORT_CHANGE_MASK ||
941 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
944 port_index = xhci->usb3_rhub.num_ports;
945 ports = xhci->usb3_rhub.ports;
946 while (port_index--) {
947 portsc = readl(ports[port_index]->addr);
948 if (portsc & PORT_CHANGE_MASK ||
949 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
956 * Stop HC (not bus-specific)
958 * This is called when the machine transition into S3/S4 mode.
961 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
964 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
965 struct usb_hcd *hcd = xhci_to_hcd(xhci);
972 if (hcd->state != HC_STATE_SUSPENDED ||
973 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
976 xhci_dbc_suspend(xhci);
978 /* Clear root port wake on bits if wakeup not allowed. */
980 xhci_disable_port_wake_on_bits(xhci);
982 /* Don't poll the roothubs on bus suspend. */
983 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
984 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
985 del_timer_sync(&hcd->rh_timer);
986 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
987 del_timer_sync(&xhci->shared_hcd->rh_timer);
989 if (xhci->quirks & XHCI_SUSPEND_DELAY)
990 usleep_range(1000, 1500);
992 spin_lock_irq(&xhci->lock);
993 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
994 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
995 /* step 1: stop endpoint */
996 /* skipped assuming that port suspend has done */
998 /* step 2: clear Run/Stop bit */
999 command = readl(&xhci->op_regs->command);
1000 command &= ~CMD_RUN;
1001 writel(command, &xhci->op_regs->command);
1003 /* Some chips from Fresco Logic need an extraordinary delay */
1004 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1006 if (xhci_handshake(&xhci->op_regs->status,
1007 STS_HALT, STS_HALT, delay)) {
1008 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1009 spin_unlock_irq(&xhci->lock);
1012 xhci_clear_command_ring(xhci);
1014 /* step 3: save registers */
1015 xhci_save_registers(xhci);
1017 /* step 4: set CSS flag */
1018 command = readl(&xhci->op_regs->command);
1020 writel(command, &xhci->op_regs->command);
1021 xhci->broken_suspend = 0;
1022 if (xhci_handshake(&xhci->op_regs->status,
1023 STS_SAVE, 0, 20 * 1000)) {
1025 * AMD SNPS xHC 3.0 occasionally does not clear the
1026 * SSS bit of USBSTS and when driver tries to poll
1027 * to see if the xHC clears BIT(8) which never happens
1028 * and driver assumes that controller is not responding
1029 * and times out. To workaround this, its good to check
1030 * if SRE and HCE bits are not set (as per xhci
1031 * Section 5.4.2) and bypass the timeout.
1033 res = readl(&xhci->op_regs->status);
1034 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1035 (((res & STS_SRE) == 0) &&
1036 ((res & STS_HCE) == 0))) {
1037 xhci->broken_suspend = 1;
1039 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1040 spin_unlock_irq(&xhci->lock);
1044 spin_unlock_irq(&xhci->lock);
1047 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1048 * is about to be suspended.
1050 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1051 (!(xhci_all_ports_seen_u0(xhci)))) {
1052 del_timer_sync(&xhci->comp_mode_recovery_timer);
1053 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1054 "%s: compliance mode recovery timer deleted",
1058 /* step 5: remove core well power */
1059 /* synchronize irq when using MSI-X */
1060 xhci_msix_sync_irqs(xhci);
1064 EXPORT_SYMBOL_GPL(xhci_suspend);
1067 * start xHC (not bus-specific)
1069 * This is called when the machine transition from S3/S4 mode.
1072 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1074 u32 command, temp = 0;
1075 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1076 struct usb_hcd *secondary_hcd;
1078 bool comp_timer_running = false;
1083 /* Wait a bit if either of the roothubs need to settle from the
1084 * transition into bus suspend.
1086 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1087 time_before(jiffies,
1088 xhci->bus_state[1].next_statechange))
1091 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1092 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1094 spin_lock_irq(&xhci->lock);
1095 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1100 * Some controllers might lose power during suspend, so wait
1101 * for controller not ready bit to clear, just as in xHC init.
1103 retval = xhci_handshake(&xhci->op_regs->status,
1104 STS_CNR, 0, 10 * 1000 * 1000);
1106 xhci_warn(xhci, "Controller not ready at resume %d\n",
1108 spin_unlock_irq(&xhci->lock);
1111 /* step 1: restore register */
1112 xhci_restore_registers(xhci);
1113 /* step 2: initialize command ring buffer */
1114 xhci_set_cmd_ring_deq(xhci);
1115 /* step 3: restore state and start state*/
1116 /* step 3: set CRS flag */
1117 command = readl(&xhci->op_regs->command);
1119 writel(command, &xhci->op_regs->command);
1121 * Some controllers take up to 55+ ms to complete the controller
1122 * restore so setting the timeout to 100ms. Xhci specification
1123 * doesn't mention any timeout value.
1125 if (xhci_handshake(&xhci->op_regs->status,
1126 STS_RESTORE, 0, 100 * 1000)) {
1127 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1128 spin_unlock_irq(&xhci->lock);
1131 temp = readl(&xhci->op_regs->status);
1134 /* If restore operation fails, re-initialize the HC during resume */
1135 if ((temp & STS_SRE) || hibernated) {
1137 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1138 !(xhci_all_ports_seen_u0(xhci))) {
1139 del_timer_sync(&xhci->comp_mode_recovery_timer);
1140 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1141 "Compliance Mode Recovery Timer deleted!");
1144 /* Let the USB core know _both_ roothubs lost power. */
1145 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1146 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1148 xhci_dbg(xhci, "Stop HCD\n");
1150 xhci_zero_64b_regs(xhci);
1152 spin_unlock_irq(&xhci->lock);
1153 xhci_cleanup_msix(xhci);
1155 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1156 temp = readl(&xhci->op_regs->status);
1157 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1158 temp = readl(&xhci->ir_set->irq_pending);
1159 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1161 xhci_dbg(xhci, "cleaning up memory\n");
1162 xhci_mem_cleanup(xhci);
1163 xhci_debugfs_exit(xhci);
1164 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1165 readl(&xhci->op_regs->status));
1167 /* USB core calls the PCI reinit and start functions twice:
1168 * first with the primary HCD, and then with the secondary HCD.
1169 * If we don't do the same, the host will never be started.
1171 if (!usb_hcd_is_primary_hcd(hcd))
1172 secondary_hcd = hcd;
1174 secondary_hcd = xhci->shared_hcd;
1176 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1177 retval = xhci_init(hcd->primary_hcd);
1180 comp_timer_running = true;
1182 xhci_dbg(xhci, "Start the primary HCD\n");
1183 retval = xhci_run(hcd->primary_hcd);
1185 xhci_dbg(xhci, "Start the secondary HCD\n");
1186 retval = xhci_run(secondary_hcd);
1188 hcd->state = HC_STATE_SUSPENDED;
1189 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1193 /* step 4: set Run/Stop bit */
1194 command = readl(&xhci->op_regs->command);
1196 writel(command, &xhci->op_regs->command);
1197 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1200 /* step 5: walk topology and initialize portsc,
1201 * portpmsc and portli
1203 /* this is done in bus_resume */
1205 /* step 6: restart each of the previously
1206 * Running endpoints by ringing their doorbells
1209 spin_unlock_irq(&xhci->lock);
1211 xhci_dbc_resume(xhci);
1215 /* Resume root hubs only when have pending events. */
1216 if (xhci_pending_portevent(xhci)) {
1217 usb_hcd_resume_root_hub(xhci->shared_hcd);
1218 usb_hcd_resume_root_hub(hcd);
1223 * If system is subject to the Quirk, Compliance Mode Timer needs to
1224 * be re-initialized Always after a system resume. Ports are subject
1225 * to suffer the Compliance Mode issue again. It doesn't matter if
1226 * ports have entered previously to U0 before system's suspension.
1228 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1229 compliance_mode_recovery_timer_init(xhci);
1231 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1232 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1234 /* Re-enable port polling. */
1235 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1236 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1237 usb_hcd_poll_rh_status(xhci->shared_hcd);
1238 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1239 usb_hcd_poll_rh_status(hcd);
1243 EXPORT_SYMBOL_GPL(xhci_resume);
1244 #endif /* CONFIG_PM */
1246 /*-------------------------------------------------------------------------*/
1249 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1250 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1251 * value to right shift 1 for the bitmask.
1253 * Index = (epnum * 2) + direction - 1,
1254 * where direction = 0 for OUT, 1 for IN.
1255 * For control endpoints, the IN index is used (OUT index is unused), so
1256 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1258 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1261 if (usb_endpoint_xfer_control(desc))
1262 index = (unsigned int) (usb_endpoint_num(desc)*2);
1264 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1265 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1269 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1270 * address from the XHCI endpoint index.
1272 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1274 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1275 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1276 return direction | number;
1279 /* Find the flag for this endpoint (for use in the control context). Use the
1280 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1283 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1285 return 1 << (xhci_get_endpoint_index(desc) + 1);
1288 /* Find the flag for this endpoint (for use in the control context). Use the
1289 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1292 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1294 return 1 << (ep_index + 1);
1297 /* Compute the last valid endpoint context index. Basically, this is the
1298 * endpoint index plus one. For slot contexts with more than valid endpoint,
1299 * we find the most significant bit set in the added contexts flags.
1300 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1301 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1303 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1305 return fls(added_ctxs) - 1;
1308 /* Returns 1 if the arguments are OK;
1309 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1311 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1312 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1314 struct xhci_hcd *xhci;
1315 struct xhci_virt_device *virt_dev;
1317 if (!hcd || (check_ep && !ep) || !udev) {
1318 pr_debug("xHCI %s called with invalid args\n", func);
1321 if (!udev->parent) {
1322 pr_debug("xHCI %s called for root hub\n", func);
1326 xhci = hcd_to_xhci(hcd);
1327 if (check_virt_dev) {
1328 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1329 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1334 virt_dev = xhci->devs[udev->slot_id];
1335 if (virt_dev->udev != udev) {
1336 xhci_dbg(xhci, "xHCI %s called with udev and "
1337 "virt_dev does not match\n", func);
1342 if (xhci->xhc_state & XHCI_STATE_HALTED)
1348 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1349 struct usb_device *udev, struct xhci_command *command,
1350 bool ctx_change, bool must_succeed);
1353 * Full speed devices may have a max packet size greater than 8 bytes, but the
1354 * USB core doesn't know that until it reads the first 8 bytes of the
1355 * descriptor. If the usb_device's max packet size changes after that point,
1356 * we need to issue an evaluate context command and wait on it.
1358 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1359 unsigned int ep_index, struct urb *urb)
1361 struct xhci_container_ctx *out_ctx;
1362 struct xhci_input_control_ctx *ctrl_ctx;
1363 struct xhci_ep_ctx *ep_ctx;
1364 struct xhci_command *command;
1365 int max_packet_size;
1366 int hw_max_packet_size;
1369 out_ctx = xhci->devs[slot_id]->out_ctx;
1370 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1371 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1372 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1373 if (hw_max_packet_size != max_packet_size) {
1374 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1375 "Max Packet Size for ep 0 changed.");
1376 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1377 "Max packet size in usb_device = %d",
1379 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1380 "Max packet size in xHCI HW = %d",
1381 hw_max_packet_size);
1382 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1383 "Issuing evaluate context command.");
1385 /* Set up the input context flags for the command */
1386 /* FIXME: This won't work if a non-default control endpoint
1387 * changes max packet sizes.
1390 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1394 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1395 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1397 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1400 goto command_cleanup;
1402 /* Set up the modified control endpoint 0 */
1403 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1404 xhci->devs[slot_id]->out_ctx, ep_index);
1406 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1407 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1408 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1410 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1411 ctrl_ctx->drop_flags = 0;
1413 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1416 /* Clean up the input context for later use by bandwidth
1419 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1421 kfree(command->completion);
1428 * RPI: Fixup endpoint intervals when requested
1429 * - Check interval versus the (cached) endpoint context
1430 * - set the endpoint interval to the new value
1431 * - force an endpoint configure command
1432 * XXX: bandwidth is not recalculated. We should probably do that.
1434 static void xhci_fixup_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1435 struct usb_host_endpoint *ep, int interval)
1437 struct xhci_hcd *xhci;
1438 struct xhci_ep_ctx *ep_ctx_out, *ep_ctx_in;
1439 struct xhci_command *command;
1440 struct xhci_input_control_ctx *ctrl_ctx;
1441 struct xhci_virt_device *vdev;
1445 unsigned long flags;
1448 xhci = hcd_to_xhci(hcd);
1449 ep_index = xhci_get_endpoint_index(&ep->desc);
1451 /* FS/LS interval translations */
1452 if ((udev->speed == USB_SPEED_FULL ||
1453 udev->speed == USB_SPEED_LOW))
1456 mutex_lock(&xhci->mutex);
1458 spin_lock_irqsave(&xhci->lock, flags);
1460 vdev = xhci->devs[udev->slot_id];
1461 /* Get context-derived endpoint interval */
1462 ep_ctx_out = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1463 ep_ctx_in = xhci_get_ep_ctx(xhci, vdev->in_ctx, ep_index);
1464 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx_out->ep_info));
1466 if (interval == xhci_interval) {
1467 spin_unlock_irqrestore(&xhci->lock, flags);
1468 mutex_unlock(&xhci->mutex);
1472 xhci_dbg(xhci, "Fixup interval=%d xhci_interval=%d\n",
1473 interval, xhci_interval);
1474 command = xhci_alloc_command_with_ctx(xhci, true, GFP_ATOMIC);
1476 /* Failure here is benign, poll at the original rate */
1477 spin_unlock_irqrestore(&xhci->lock, flags);
1478 mutex_unlock(&xhci->mutex);
1482 /* xHCI uses exponents for intervals... */
1483 xhci_interval = fls(interval) - 1;
1484 xhci_interval = clamp_val(xhci_interval, 3, 10);
1485 ep_info_tmp = le32_to_cpu(ep_ctx_out->ep_info);
1486 ep_info_tmp &= ~EP_INTERVAL(255);
1487 ep_info_tmp |= EP_INTERVAL(xhci_interval);
1489 /* Keep the endpoint context up-to-date while issuing the command. */
1490 xhci_endpoint_copy(xhci, vdev->in_ctx,
1491 vdev->out_ctx, ep_index);
1492 ep_ctx_in->ep_info = cpu_to_le32(ep_info_tmp);
1495 * We need to drop the lock, so take an explicit copy
1496 * of the ep context.
1498 xhci_endpoint_copy(xhci, command->in_ctx, vdev->in_ctx, ep_index);
1500 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1503 "%s: Could not get input context, bad type.\n",
1505 spin_unlock_irqrestore(&xhci->lock, flags);
1506 xhci_free_command(xhci, command);
1507 mutex_unlock(&xhci->mutex);
1510 ctrl_ctx->add_flags = xhci_get_endpoint_flag_from_index(ep_index);
1511 ctrl_ctx->drop_flags = 0;
1513 spin_unlock_irqrestore(&xhci->lock, flags);
1515 ret = xhci_configure_endpoint(xhci, udev, command,
1518 xhci_warn(xhci, "%s: Configure endpoint failed: %d\n",
1520 xhci_free_command(xhci, command);
1521 mutex_unlock(&xhci->mutex);
1525 * non-error returns are a promise to giveback() the urb later
1526 * we drop ownership so next owner (or urb unlink) can get it
1528 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1531 unsigned long flags;
1533 unsigned int slot_id, ep_index;
1534 unsigned int *ep_state;
1535 struct urb_priv *urb_priv;
1538 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1539 true, true, __func__) <= 0)
1542 slot_id = urb->dev->slot_id;
1543 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1544 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1546 if (!HCD_HW_ACCESSIBLE(hcd)) {
1547 if (!in_interrupt())
1548 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1551 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1552 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1556 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1557 num_tds = urb->number_of_packets;
1558 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1559 urb->transfer_buffer_length > 0 &&
1560 urb->transfer_flags & URB_ZERO_PACKET &&
1561 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1566 urb_priv = kzalloc(sizeof(struct urb_priv) +
1567 num_tds * sizeof(struct xhci_td), mem_flags);
1571 urb_priv->num_tds = num_tds;
1572 urb_priv->num_tds_done = 0;
1573 urb->hcpriv = urb_priv;
1575 trace_xhci_urb_enqueue(urb);
1577 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1578 /* Check to see if the max packet size for the default control
1579 * endpoint changed during FS device enumeration
1581 if (urb->dev->speed == USB_SPEED_FULL) {
1582 ret = xhci_check_maxpacket(xhci, slot_id,
1585 xhci_urb_free_priv(urb_priv);
1592 spin_lock_irqsave(&xhci->lock, flags);
1594 if (xhci->xhc_state & XHCI_STATE_DYING) {
1595 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1596 urb->ep->desc.bEndpointAddress, urb);
1600 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1601 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1606 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1607 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1612 switch (usb_endpoint_type(&urb->ep->desc)) {
1614 case USB_ENDPOINT_XFER_CONTROL:
1615 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1618 case USB_ENDPOINT_XFER_BULK:
1619 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1622 case USB_ENDPOINT_XFER_INT:
1623 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1626 case USB_ENDPOINT_XFER_ISOC:
1627 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1633 xhci_urb_free_priv(urb_priv);
1636 spin_unlock_irqrestore(&xhci->lock, flags);
1641 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1642 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1643 * should pick up where it left off in the TD, unless a Set Transfer Ring
1644 * Dequeue Pointer is issued.
1646 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1647 * the ring. Since the ring is a contiguous structure, they can't be physically
1648 * removed. Instead, there are two options:
1650 * 1) If the HC is in the middle of processing the URB to be canceled, we
1651 * simply move the ring's dequeue pointer past those TRBs using the Set
1652 * Transfer Ring Dequeue Pointer command. This will be the common case,
1653 * when drivers timeout on the last submitted URB and attempt to cancel.
1655 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1656 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1657 * HC will need to invalidate the any TRBs it has cached after the stop
1658 * endpoint command, as noted in the xHCI 0.95 errata.
1660 * 3) The TD may have completed by the time the Stop Endpoint Command
1661 * completes, so software needs to handle that case too.
1663 * This function should protect against the TD enqueueing code ringing the
1664 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1665 * It also needs to account for multiple cancellations on happening at the same
1666 * time for the same endpoint.
1668 * Note that this function can be called in any context, or so says
1669 * usb_hcd_unlink_urb()
1671 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1673 unsigned long flags;
1676 struct xhci_hcd *xhci;
1677 struct urb_priv *urb_priv;
1679 unsigned int ep_index;
1680 struct xhci_ring *ep_ring;
1681 struct xhci_virt_ep *ep;
1682 struct xhci_command *command;
1683 struct xhci_virt_device *vdev;
1685 xhci = hcd_to_xhci(hcd);
1686 spin_lock_irqsave(&xhci->lock, flags);
1688 trace_xhci_urb_dequeue(urb);
1690 /* Make sure the URB hasn't completed or been unlinked already */
1691 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1695 /* give back URB now if we can't queue it for cancel */
1696 vdev = xhci->devs[urb->dev->slot_id];
1697 urb_priv = urb->hcpriv;
1698 if (!vdev || !urb_priv)
1701 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1702 ep = &vdev->eps[ep_index];
1703 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1704 if (!ep || !ep_ring)
1707 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1708 temp = readl(&xhci->op_regs->status);
1709 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1715 * check ring is not re-allocated since URB was enqueued. If it is, then
1716 * make sure none of the ring related pointers in this URB private data
1717 * are touched, such as td_list, otherwise we overwrite freed data
1719 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1720 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1721 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1722 td = &urb_priv->td[i];
1723 if (!list_empty(&td->cancelled_td_list))
1724 list_del_init(&td->cancelled_td_list);
1729 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1730 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1731 "HC halted, freeing TD manually.");
1732 for (i = urb_priv->num_tds_done;
1733 i < urb_priv->num_tds;
1735 td = &urb_priv->td[i];
1736 if (!list_empty(&td->td_list))
1737 list_del_init(&td->td_list);
1738 if (!list_empty(&td->cancelled_td_list))
1739 list_del_init(&td->cancelled_td_list);
1744 i = urb_priv->num_tds_done;
1745 if (i < urb_priv->num_tds)
1746 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1747 "Cancel URB %p, dev %s, ep 0x%x, "
1748 "starting at offset 0x%llx",
1749 urb, urb->dev->devpath,
1750 urb->ep->desc.bEndpointAddress,
1751 (unsigned long long) xhci_trb_virt_to_dma(
1752 urb_priv->td[i].start_seg,
1753 urb_priv->td[i].first_trb));
1755 for (; i < urb_priv->num_tds; i++) {
1756 td = &urb_priv->td[i];
1757 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1760 /* Queue a stop endpoint command, but only if this is
1761 * the first cancellation to be handled.
1763 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1764 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1769 ep->ep_state |= EP_STOP_CMD_PENDING;
1770 ep->stop_cmd_timer.expires = jiffies +
1771 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1772 add_timer(&ep->stop_cmd_timer);
1773 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1775 xhci_ring_cmd_db(xhci);
1778 spin_unlock_irqrestore(&xhci->lock, flags);
1783 xhci_urb_free_priv(urb_priv);
1784 usb_hcd_unlink_urb_from_ep(hcd, urb);
1785 spin_unlock_irqrestore(&xhci->lock, flags);
1786 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1790 /* Drop an endpoint from a new bandwidth configuration for this device.
1791 * Only one call to this function is allowed per endpoint before
1792 * check_bandwidth() or reset_bandwidth() must be called.
1793 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1794 * add the endpoint to the schedule with possibly new parameters denoted by a
1795 * different endpoint descriptor in usb_host_endpoint.
1796 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1799 * The USB core will not allow URBs to be queued to an endpoint that is being
1800 * disabled, so there's no need for mutual exclusion to protect
1801 * the xhci->devs[slot_id] structure.
1803 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1804 struct usb_host_endpoint *ep)
1806 struct xhci_hcd *xhci;
1807 struct xhci_container_ctx *in_ctx, *out_ctx;
1808 struct xhci_input_control_ctx *ctrl_ctx;
1809 unsigned int ep_index;
1810 struct xhci_ep_ctx *ep_ctx;
1812 u32 new_add_flags, new_drop_flags;
1815 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1818 xhci = hcd_to_xhci(hcd);
1819 if (xhci->xhc_state & XHCI_STATE_DYING)
1822 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1823 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1824 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1825 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1826 __func__, drop_flag);
1830 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1831 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1832 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1834 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1839 ep_index = xhci_get_endpoint_index(&ep->desc);
1840 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1841 /* If the HC already knows the endpoint is disabled,
1842 * or the HCD has noted it is disabled, ignore this request
1844 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1845 le32_to_cpu(ctrl_ctx->drop_flags) &
1846 xhci_get_endpoint_flag(&ep->desc)) {
1847 /* Do not warn when called after a usb_device_reset */
1848 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1849 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1854 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1855 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1857 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1858 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1860 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1862 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1864 if (xhci->quirks & XHCI_MTK_HOST)
1865 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1867 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1868 (unsigned int) ep->desc.bEndpointAddress,
1870 (unsigned int) new_drop_flags,
1871 (unsigned int) new_add_flags);
1875 /* Add an endpoint to a new possible bandwidth configuration for this device.
1876 * Only one call to this function is allowed per endpoint before
1877 * check_bandwidth() or reset_bandwidth() must be called.
1878 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1879 * add the endpoint to the schedule with possibly new parameters denoted by a
1880 * different endpoint descriptor in usb_host_endpoint.
1881 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1884 * The USB core will not allow URBs to be queued to an endpoint until the
1885 * configuration or alt setting is installed in the device, so there's no need
1886 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1888 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1889 struct usb_host_endpoint *ep)
1891 struct xhci_hcd *xhci;
1892 struct xhci_container_ctx *in_ctx;
1893 unsigned int ep_index;
1894 struct xhci_input_control_ctx *ctrl_ctx;
1896 u32 new_add_flags, new_drop_flags;
1897 struct xhci_virt_device *virt_dev;
1900 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1902 /* So we won't queue a reset ep command for a root hub */
1906 xhci = hcd_to_xhci(hcd);
1907 if (xhci->xhc_state & XHCI_STATE_DYING)
1910 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1911 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1912 /* FIXME when we have to issue an evaluate endpoint command to
1913 * deal with ep0 max packet size changing once we get the
1916 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1917 __func__, added_ctxs);
1921 virt_dev = xhci->devs[udev->slot_id];
1922 in_ctx = virt_dev->in_ctx;
1923 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1925 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1930 ep_index = xhci_get_endpoint_index(&ep->desc);
1931 /* If this endpoint is already in use, and the upper layers are trying
1932 * to add it again without dropping it, reject the addition.
1934 if (virt_dev->eps[ep_index].ring &&
1935 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1936 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1937 "without dropping it.\n",
1938 (unsigned int) ep->desc.bEndpointAddress);
1942 /* If the HCD has already noted the endpoint is enabled,
1943 * ignore this request.
1945 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1946 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1952 * Configuration and alternate setting changes must be done in
1953 * process context, not interrupt context (or so documenation
1954 * for usb_set_interface() and usb_set_configuration() claim).
1956 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1957 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1958 __func__, ep->desc.bEndpointAddress);
1962 if (xhci->quirks & XHCI_MTK_HOST) {
1963 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1965 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1966 virt_dev->eps[ep_index].new_ring = NULL;
1971 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1972 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1974 /* If xhci_endpoint_disable() was called for this endpoint, but the
1975 * xHC hasn't been notified yet through the check_bandwidth() call,
1976 * this re-adds a new state for the endpoint from the new endpoint
1977 * descriptors. We must drop and re-add this endpoint, so we leave the
1980 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1982 /* Store the usb_device pointer for later use */
1985 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1987 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1988 (unsigned int) ep->desc.bEndpointAddress,
1990 (unsigned int) new_drop_flags,
1991 (unsigned int) new_add_flags);
1995 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1997 struct xhci_input_control_ctx *ctrl_ctx;
1998 struct xhci_ep_ctx *ep_ctx;
1999 struct xhci_slot_ctx *slot_ctx;
2002 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2004 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2009 /* When a device's add flag and drop flag are zero, any subsequent
2010 * configure endpoint command will leave that endpoint's state
2011 * untouched. Make sure we don't leave any old state in the input
2012 * endpoint contexts.
2014 ctrl_ctx->drop_flags = 0;
2015 ctrl_ctx->add_flags = 0;
2016 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2017 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2018 /* Endpoint 0 is always valid */
2019 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2020 for (i = 1; i < 31; i++) {
2021 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2022 ep_ctx->ep_info = 0;
2023 ep_ctx->ep_info2 = 0;
2025 ep_ctx->tx_info = 0;
2029 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2030 struct usb_device *udev, u32 *cmd_status)
2034 switch (*cmd_status) {
2035 case COMP_COMMAND_ABORTED:
2036 case COMP_COMMAND_RING_STOPPED:
2037 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2040 case COMP_RESOURCE_ERROR:
2041 dev_warn(&udev->dev,
2042 "Not enough host controller resources for new device state.\n");
2044 /* FIXME: can we allocate more resources for the HC? */
2046 case COMP_BANDWIDTH_ERROR:
2047 case COMP_SECONDARY_BANDWIDTH_ERROR:
2048 dev_warn(&udev->dev,
2049 "Not enough bandwidth for new device state.\n");
2051 /* FIXME: can we go back to the old state? */
2053 case COMP_TRB_ERROR:
2054 /* the HCD set up something wrong */
2055 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2057 "and endpoint is not disabled.\n");
2060 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2061 dev_warn(&udev->dev,
2062 "ERROR: Incompatible device for endpoint configure command.\n");
2066 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2067 "Successful Endpoint Configure command");
2071 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2079 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2080 struct usb_device *udev, u32 *cmd_status)
2084 switch (*cmd_status) {
2085 case COMP_COMMAND_ABORTED:
2086 case COMP_COMMAND_RING_STOPPED:
2087 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2090 case COMP_PARAMETER_ERROR:
2091 dev_warn(&udev->dev,
2092 "WARN: xHCI driver setup invalid evaluate context command.\n");
2095 case COMP_SLOT_NOT_ENABLED_ERROR:
2096 dev_warn(&udev->dev,
2097 "WARN: slot not enabled for evaluate context command.\n");
2100 case COMP_CONTEXT_STATE_ERROR:
2101 dev_warn(&udev->dev,
2102 "WARN: invalid context state for evaluate context command.\n");
2105 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2106 dev_warn(&udev->dev,
2107 "ERROR: Incompatible device for evaluate context command.\n");
2110 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2111 /* Max Exit Latency too large error */
2112 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2116 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2117 "Successful evaluate context command");
2121 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2129 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2130 struct xhci_input_control_ctx *ctrl_ctx)
2132 u32 valid_add_flags;
2133 u32 valid_drop_flags;
2135 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2136 * (bit 1). The default control endpoint is added during the Address
2137 * Device command and is never removed until the slot is disabled.
2139 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2140 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2142 /* Use hweight32 to count the number of ones in the add flags, or
2143 * number of endpoints added. Don't count endpoints that are changed
2144 * (both added and dropped).
2146 return hweight32(valid_add_flags) -
2147 hweight32(valid_add_flags & valid_drop_flags);
2150 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2151 struct xhci_input_control_ctx *ctrl_ctx)
2153 u32 valid_add_flags;
2154 u32 valid_drop_flags;
2156 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2157 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2159 return hweight32(valid_drop_flags) -
2160 hweight32(valid_add_flags & valid_drop_flags);
2164 * We need to reserve the new number of endpoints before the configure endpoint
2165 * command completes. We can't subtract the dropped endpoints from the number
2166 * of active endpoints until the command completes because we can oversubscribe
2167 * the host in this case:
2169 * - the first configure endpoint command drops more endpoints than it adds
2170 * - a second configure endpoint command that adds more endpoints is queued
2171 * - the first configure endpoint command fails, so the config is unchanged
2172 * - the second command may succeed, even though there isn't enough resources
2174 * Must be called with xhci->lock held.
2176 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2177 struct xhci_input_control_ctx *ctrl_ctx)
2181 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2182 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2183 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2184 "Not enough ep ctxs: "
2185 "%u active, need to add %u, limit is %u.",
2186 xhci->num_active_eps, added_eps,
2187 xhci->limit_active_eps);
2190 xhci->num_active_eps += added_eps;
2191 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2192 "Adding %u ep ctxs, %u now active.", added_eps,
2193 xhci->num_active_eps);
2198 * The configure endpoint was failed by the xHC for some other reason, so we
2199 * need to revert the resources that failed configuration would have used.
2201 * Must be called with xhci->lock held.
2203 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2204 struct xhci_input_control_ctx *ctrl_ctx)
2208 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2209 xhci->num_active_eps -= num_failed_eps;
2210 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2211 "Removing %u failed ep ctxs, %u now active.",
2213 xhci->num_active_eps);
2217 * Now that the command has completed, clean up the active endpoint count by
2218 * subtracting out the endpoints that were dropped (but not changed).
2220 * Must be called with xhci->lock held.
2222 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2223 struct xhci_input_control_ctx *ctrl_ctx)
2225 u32 num_dropped_eps;
2227 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2228 xhci->num_active_eps -= num_dropped_eps;
2229 if (num_dropped_eps)
2230 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2231 "Removing %u dropped ep ctxs, %u now active.",
2233 xhci->num_active_eps);
2236 static unsigned int xhci_get_block_size(struct usb_device *udev)
2238 switch (udev->speed) {
2240 case USB_SPEED_FULL:
2242 case USB_SPEED_HIGH:
2244 case USB_SPEED_SUPER:
2245 case USB_SPEED_SUPER_PLUS:
2247 case USB_SPEED_UNKNOWN:
2248 case USB_SPEED_WIRELESS:
2250 /* Should never happen */
2256 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2258 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2260 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2265 /* If we are changing a LS/FS device under a HS hub,
2266 * make sure (if we are activating a new TT) that the HS bus has enough
2267 * bandwidth for this new TT.
2269 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2270 struct xhci_virt_device *virt_dev,
2273 struct xhci_interval_bw_table *bw_table;
2274 struct xhci_tt_bw_info *tt_info;
2276 /* Find the bandwidth table for the root port this TT is attached to. */
2277 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2278 tt_info = virt_dev->tt_info;
2279 /* If this TT already had active endpoints, the bandwidth for this TT
2280 * has already been added. Removing all periodic endpoints (and thus
2281 * making the TT enactive) will only decrease the bandwidth used.
2285 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2286 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2290 /* Not sure why we would have no new active endpoints...
2292 * Maybe because of an Evaluate Context change for a hub update or a
2293 * control endpoint 0 max packet size change?
2294 * FIXME: skip the bandwidth calculation in that case.
2299 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2300 struct xhci_virt_device *virt_dev)
2302 unsigned int bw_reserved;
2304 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2305 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2308 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2309 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2316 * This algorithm is a very conservative estimate of the worst-case scheduling
2317 * scenario for any one interval. The hardware dynamically schedules the
2318 * packets, so we can't tell which microframe could be the limiting factor in
2319 * the bandwidth scheduling. This only takes into account periodic endpoints.
2321 * Obviously, we can't solve an NP complete problem to find the minimum worst
2322 * case scenario. Instead, we come up with an estimate that is no less than
2323 * the worst case bandwidth used for any one microframe, but may be an
2326 * We walk the requirements for each endpoint by interval, starting with the
2327 * smallest interval, and place packets in the schedule where there is only one
2328 * possible way to schedule packets for that interval. In order to simplify
2329 * this algorithm, we record the largest max packet size for each interval, and
2330 * assume all packets will be that size.
2332 * For interval 0, we obviously must schedule all packets for each interval.
2333 * The bandwidth for interval 0 is just the amount of data to be transmitted
2334 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2335 * the number of packets).
2337 * For interval 1, we have two possible microframes to schedule those packets
2338 * in. For this algorithm, if we can schedule the same number of packets for
2339 * each possible scheduling opportunity (each microframe), we will do so. The
2340 * remaining number of packets will be saved to be transmitted in the gaps in
2341 * the next interval's scheduling sequence.
2343 * As we move those remaining packets to be scheduled with interval 2 packets,
2344 * we have to double the number of remaining packets to transmit. This is
2345 * because the intervals are actually powers of 2, and we would be transmitting
2346 * the previous interval's packets twice in this interval. We also have to be
2347 * sure that when we look at the largest max packet size for this interval, we
2348 * also look at the largest max packet size for the remaining packets and take
2349 * the greater of the two.
2351 * The algorithm continues to evenly distribute packets in each scheduling
2352 * opportunity, and push the remaining packets out, until we get to the last
2353 * interval. Then those packets and their associated overhead are just added
2354 * to the bandwidth used.
2356 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2357 struct xhci_virt_device *virt_dev,
2360 unsigned int bw_reserved;
2361 unsigned int max_bandwidth;
2362 unsigned int bw_used;
2363 unsigned int block_size;
2364 struct xhci_interval_bw_table *bw_table;
2365 unsigned int packet_size = 0;
2366 unsigned int overhead = 0;
2367 unsigned int packets_transmitted = 0;
2368 unsigned int packets_remaining = 0;
2371 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2372 return xhci_check_ss_bw(xhci, virt_dev);
2374 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2375 max_bandwidth = HS_BW_LIMIT;
2376 /* Convert percent of bus BW reserved to blocks reserved */
2377 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2379 max_bandwidth = FS_BW_LIMIT;
2380 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2383 bw_table = virt_dev->bw_table;
2384 /* We need to translate the max packet size and max ESIT payloads into
2385 * the units the hardware uses.
2387 block_size = xhci_get_block_size(virt_dev->udev);
2389 /* If we are manipulating a LS/FS device under a HS hub, double check
2390 * that the HS bus has enough bandwidth if we are activing a new TT.
2392 if (virt_dev->tt_info) {
2393 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2394 "Recalculating BW for rootport %u",
2395 virt_dev->real_port);
2396 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2397 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2398 "newly activated TT.\n");
2401 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2402 "Recalculating BW for TT slot %u port %u",
2403 virt_dev->tt_info->slot_id,
2404 virt_dev->tt_info->ttport);
2406 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2407 "Recalculating BW for rootport %u",
2408 virt_dev->real_port);
2411 /* Add in how much bandwidth will be used for interval zero, or the
2412 * rounded max ESIT payload + number of packets * largest overhead.
2414 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2415 bw_table->interval_bw[0].num_packets *
2416 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2418 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2419 unsigned int bw_added;
2420 unsigned int largest_mps;
2421 unsigned int interval_overhead;
2424 * How many packets could we transmit in this interval?
2425 * If packets didn't fit in the previous interval, we will need
2426 * to transmit that many packets twice within this interval.
2428 packets_remaining = 2 * packets_remaining +
2429 bw_table->interval_bw[i].num_packets;
2431 /* Find the largest max packet size of this or the previous
2434 if (list_empty(&bw_table->interval_bw[i].endpoints))
2437 struct xhci_virt_ep *virt_ep;
2438 struct list_head *ep_entry;
2440 ep_entry = bw_table->interval_bw[i].endpoints.next;
2441 virt_ep = list_entry(ep_entry,
2442 struct xhci_virt_ep, bw_endpoint_list);
2443 /* Convert to blocks, rounding up */
2444 largest_mps = DIV_ROUND_UP(
2445 virt_ep->bw_info.max_packet_size,
2448 if (largest_mps > packet_size)
2449 packet_size = largest_mps;
2451 /* Use the larger overhead of this or the previous interval. */
2452 interval_overhead = xhci_get_largest_overhead(
2453 &bw_table->interval_bw[i]);
2454 if (interval_overhead > overhead)
2455 overhead = interval_overhead;
2457 /* How many packets can we evenly distribute across
2458 * (1 << (i + 1)) possible scheduling opportunities?
2460 packets_transmitted = packets_remaining >> (i + 1);
2462 /* Add in the bandwidth used for those scheduled packets */
2463 bw_added = packets_transmitted * (overhead + packet_size);
2465 /* How many packets do we have remaining to transmit? */
2466 packets_remaining = packets_remaining % (1 << (i + 1));
2468 /* What largest max packet size should those packets have? */
2469 /* If we've transmitted all packets, don't carry over the
2470 * largest packet size.
2472 if (packets_remaining == 0) {
2475 } else if (packets_transmitted > 0) {
2476 /* Otherwise if we do have remaining packets, and we've
2477 * scheduled some packets in this interval, take the
2478 * largest max packet size from endpoints with this
2481 packet_size = largest_mps;
2482 overhead = interval_overhead;
2484 /* Otherwise carry over packet_size and overhead from the last
2485 * time we had a remainder.
2487 bw_used += bw_added;
2488 if (bw_used > max_bandwidth) {
2489 xhci_warn(xhci, "Not enough bandwidth. "
2490 "Proposed: %u, Max: %u\n",
2491 bw_used, max_bandwidth);
2496 * Ok, we know we have some packets left over after even-handedly
2497 * scheduling interval 15. We don't know which microframes they will
2498 * fit into, so we over-schedule and say they will be scheduled every
2501 if (packets_remaining > 0)
2502 bw_used += overhead + packet_size;
2504 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2505 unsigned int port_index = virt_dev->real_port - 1;
2507 /* OK, we're manipulating a HS device attached to a
2508 * root port bandwidth domain. Include the number of active TTs
2509 * in the bandwidth used.
2511 bw_used += TT_HS_OVERHEAD *
2512 xhci->rh_bw[port_index].num_active_tts;
2515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2516 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2517 "Available: %u " "percent",
2518 bw_used, max_bandwidth, bw_reserved,
2519 (max_bandwidth - bw_used - bw_reserved) * 100 /
2522 bw_used += bw_reserved;
2523 if (bw_used > max_bandwidth) {
2524 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2525 bw_used, max_bandwidth);
2529 bw_table->bw_used = bw_used;
2533 static bool xhci_is_async_ep(unsigned int ep_type)
2535 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2536 ep_type != ISOC_IN_EP &&
2537 ep_type != INT_IN_EP);
2540 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2542 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2545 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2547 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2549 if (ep_bw->ep_interval == 0)
2550 return SS_OVERHEAD_BURST +
2551 (ep_bw->mult * ep_bw->num_packets *
2552 (SS_OVERHEAD + mps));
2553 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2554 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2555 1 << ep_bw->ep_interval);
2559 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2560 struct xhci_bw_info *ep_bw,
2561 struct xhci_interval_bw_table *bw_table,
2562 struct usb_device *udev,
2563 struct xhci_virt_ep *virt_ep,
2564 struct xhci_tt_bw_info *tt_info)
2566 struct xhci_interval_bw *interval_bw;
2567 int normalized_interval;
2569 if (xhci_is_async_ep(ep_bw->type))
2572 if (udev->speed >= USB_SPEED_SUPER) {
2573 if (xhci_is_sync_in_ep(ep_bw->type))
2574 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2575 xhci_get_ss_bw_consumed(ep_bw);
2577 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2578 xhci_get_ss_bw_consumed(ep_bw);
2582 /* SuperSpeed endpoints never get added to intervals in the table, so
2583 * this check is only valid for HS/FS/LS devices.
2585 if (list_empty(&virt_ep->bw_endpoint_list))
2587 /* For LS/FS devices, we need to translate the interval expressed in
2588 * microframes to frames.
2590 if (udev->speed == USB_SPEED_HIGH)
2591 normalized_interval = ep_bw->ep_interval;
2593 normalized_interval = ep_bw->ep_interval - 3;
2595 if (normalized_interval == 0)
2596 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2597 interval_bw = &bw_table->interval_bw[normalized_interval];
2598 interval_bw->num_packets -= ep_bw->num_packets;
2599 switch (udev->speed) {
2601 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2603 case USB_SPEED_FULL:
2604 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2606 case USB_SPEED_HIGH:
2607 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2609 case USB_SPEED_SUPER:
2610 case USB_SPEED_SUPER_PLUS:
2611 case USB_SPEED_UNKNOWN:
2612 case USB_SPEED_WIRELESS:
2613 /* Should never happen because only LS/FS/HS endpoints will get
2614 * added to the endpoint list.
2619 tt_info->active_eps -= 1;
2620 list_del_init(&virt_ep->bw_endpoint_list);
2623 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2624 struct xhci_bw_info *ep_bw,
2625 struct xhci_interval_bw_table *bw_table,
2626 struct usb_device *udev,
2627 struct xhci_virt_ep *virt_ep,
2628 struct xhci_tt_bw_info *tt_info)
2630 struct xhci_interval_bw *interval_bw;
2631 struct xhci_virt_ep *smaller_ep;
2632 int normalized_interval;
2634 if (xhci_is_async_ep(ep_bw->type))
2637 if (udev->speed == USB_SPEED_SUPER) {
2638 if (xhci_is_sync_in_ep(ep_bw->type))
2639 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2640 xhci_get_ss_bw_consumed(ep_bw);
2642 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2643 xhci_get_ss_bw_consumed(ep_bw);
2647 /* For LS/FS devices, we need to translate the interval expressed in
2648 * microframes to frames.
2650 if (udev->speed == USB_SPEED_HIGH)
2651 normalized_interval = ep_bw->ep_interval;
2653 normalized_interval = ep_bw->ep_interval - 3;
2655 if (normalized_interval == 0)
2656 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2657 interval_bw = &bw_table->interval_bw[normalized_interval];
2658 interval_bw->num_packets += ep_bw->num_packets;
2659 switch (udev->speed) {
2661 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2663 case USB_SPEED_FULL:
2664 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2666 case USB_SPEED_HIGH:
2667 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2669 case USB_SPEED_SUPER:
2670 case USB_SPEED_SUPER_PLUS:
2671 case USB_SPEED_UNKNOWN:
2672 case USB_SPEED_WIRELESS:
2673 /* Should never happen because only LS/FS/HS endpoints will get
2674 * added to the endpoint list.
2680 tt_info->active_eps += 1;
2681 /* Insert the endpoint into the list, largest max packet size first. */
2682 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2684 if (ep_bw->max_packet_size >=
2685 smaller_ep->bw_info.max_packet_size) {
2686 /* Add the new ep before the smaller endpoint */
2687 list_add_tail(&virt_ep->bw_endpoint_list,
2688 &smaller_ep->bw_endpoint_list);
2692 /* Add the new endpoint at the end of the list. */
2693 list_add_tail(&virt_ep->bw_endpoint_list,
2694 &interval_bw->endpoints);
2697 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2698 struct xhci_virt_device *virt_dev,
2701 struct xhci_root_port_bw_info *rh_bw_info;
2702 if (!virt_dev->tt_info)
2705 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2706 if (old_active_eps == 0 &&
2707 virt_dev->tt_info->active_eps != 0) {
2708 rh_bw_info->num_active_tts += 1;
2709 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2710 } else if (old_active_eps != 0 &&
2711 virt_dev->tt_info->active_eps == 0) {
2712 rh_bw_info->num_active_tts -= 1;
2713 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2717 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2718 struct xhci_virt_device *virt_dev,
2719 struct xhci_container_ctx *in_ctx)
2721 struct xhci_bw_info ep_bw_info[31];
2723 struct xhci_input_control_ctx *ctrl_ctx;
2724 int old_active_eps = 0;
2726 if (virt_dev->tt_info)
2727 old_active_eps = virt_dev->tt_info->active_eps;
2729 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2731 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2736 for (i = 0; i < 31; i++) {
2737 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2740 /* Make a copy of the BW info in case we need to revert this */
2741 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2742 sizeof(ep_bw_info[i]));
2743 /* Drop the endpoint from the interval table if the endpoint is
2744 * being dropped or changed.
2746 if (EP_IS_DROPPED(ctrl_ctx, i))
2747 xhci_drop_ep_from_interval_table(xhci,
2748 &virt_dev->eps[i].bw_info,
2754 /* Overwrite the information stored in the endpoints' bw_info */
2755 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2756 for (i = 0; i < 31; i++) {
2757 /* Add any changed or added endpoints to the interval table */
2758 if (EP_IS_ADDED(ctrl_ctx, i))
2759 xhci_add_ep_to_interval_table(xhci,
2760 &virt_dev->eps[i].bw_info,
2767 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2768 /* Ok, this fits in the bandwidth we have.
2769 * Update the number of active TTs.
2771 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2775 /* We don't have enough bandwidth for this, revert the stored info. */
2776 for (i = 0; i < 31; i++) {
2777 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2780 /* Drop the new copies of any added or changed endpoints from
2781 * the interval table.
2783 if (EP_IS_ADDED(ctrl_ctx, i)) {
2784 xhci_drop_ep_from_interval_table(xhci,
2785 &virt_dev->eps[i].bw_info,
2791 /* Revert the endpoint back to its old information */
2792 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2793 sizeof(ep_bw_info[i]));
2794 /* Add any changed or dropped endpoints back into the table */
2795 if (EP_IS_DROPPED(ctrl_ctx, i))
2796 xhci_add_ep_to_interval_table(xhci,
2797 &virt_dev->eps[i].bw_info,
2807 /* Issue a configure endpoint command or evaluate context command
2808 * and wait for it to finish.
2810 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2811 struct usb_device *udev,
2812 struct xhci_command *command,
2813 bool ctx_change, bool must_succeed)
2816 unsigned long flags;
2817 struct xhci_input_control_ctx *ctrl_ctx;
2818 struct xhci_virt_device *virt_dev;
2819 struct xhci_slot_ctx *slot_ctx;
2824 spin_lock_irqsave(&xhci->lock, flags);
2826 if (xhci->xhc_state & XHCI_STATE_DYING) {
2827 spin_unlock_irqrestore(&xhci->lock, flags);
2831 virt_dev = xhci->devs[udev->slot_id];
2833 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2835 spin_unlock_irqrestore(&xhci->lock, flags);
2836 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2841 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2842 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2843 spin_unlock_irqrestore(&xhci->lock, flags);
2844 xhci_warn(xhci, "Not enough host resources, "
2845 "active endpoint contexts = %u\n",
2846 xhci->num_active_eps);
2849 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2850 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2851 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2852 xhci_free_host_resources(xhci, ctrl_ctx);
2853 spin_unlock_irqrestore(&xhci->lock, flags);
2854 xhci_warn(xhci, "Not enough bandwidth\n");
2858 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2859 trace_xhci_configure_endpoint(slot_ctx);
2862 ret = xhci_queue_configure_endpoint(xhci, command,
2863 command->in_ctx->dma,
2864 udev->slot_id, must_succeed);
2866 ret = xhci_queue_evaluate_context(xhci, command,
2867 command->in_ctx->dma,
2868 udev->slot_id, must_succeed);
2870 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2871 xhci_free_host_resources(xhci, ctrl_ctx);
2872 spin_unlock_irqrestore(&xhci->lock, flags);
2873 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2874 "FIXME allocate a new ring segment");
2877 xhci_ring_cmd_db(xhci);
2878 spin_unlock_irqrestore(&xhci->lock, flags);
2880 /* Wait for the configure endpoint command to complete */
2881 wait_for_completion(command->completion);
2884 ret = xhci_configure_endpoint_result(xhci, udev,
2887 ret = xhci_evaluate_context_result(xhci, udev,
2890 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2891 spin_lock_irqsave(&xhci->lock, flags);
2892 /* If the command failed, remove the reserved resources.
2893 * Otherwise, clean up the estimate to include dropped eps.
2896 xhci_free_host_resources(xhci, ctrl_ctx);
2898 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2899 spin_unlock_irqrestore(&xhci->lock, flags);
2904 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2905 struct xhci_virt_device *vdev, int i)
2907 struct xhci_virt_ep *ep = &vdev->eps[i];
2909 if (ep->ep_state & EP_HAS_STREAMS) {
2910 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2911 xhci_get_endpoint_address(i));
2912 xhci_free_stream_info(xhci, ep->stream_info);
2913 ep->stream_info = NULL;
2914 ep->ep_state &= ~EP_HAS_STREAMS;
2918 /* Called after one or more calls to xhci_add_endpoint() or
2919 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2920 * to call xhci_reset_bandwidth().
2922 * Since we are in the middle of changing either configuration or
2923 * installing a new alt setting, the USB core won't allow URBs to be
2924 * enqueued for any endpoint on the old config or interface. Nothing
2925 * else should be touching the xhci->devs[slot_id] structure, so we
2926 * don't need to take the xhci->lock for manipulating that.
2928 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2932 struct xhci_hcd *xhci;
2933 struct xhci_virt_device *virt_dev;
2934 struct xhci_input_control_ctx *ctrl_ctx;
2935 struct xhci_slot_ctx *slot_ctx;
2936 struct xhci_command *command;
2938 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2941 xhci = hcd_to_xhci(hcd);
2942 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2943 (xhci->xhc_state & XHCI_STATE_REMOVING))
2946 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2947 virt_dev = xhci->devs[udev->slot_id];
2949 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2953 command->in_ctx = virt_dev->in_ctx;
2955 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2956 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2958 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2961 goto command_cleanup;
2963 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2964 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2965 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2967 /* Don't issue the command if there's no endpoints to update. */
2968 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2969 ctrl_ctx->drop_flags == 0) {
2971 goto command_cleanup;
2973 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2974 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2975 for (i = 31; i >= 1; i--) {
2976 __le32 le32 = cpu_to_le32(BIT(i));
2978 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2979 || (ctrl_ctx->add_flags & le32) || i == 1) {
2980 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2981 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2986 ret = xhci_configure_endpoint(xhci, udev, command,
2989 /* Callee should call reset_bandwidth() */
2990 goto command_cleanup;
2992 /* Free any rings that were dropped, but not changed. */
2993 for (i = 1; i < 31; i++) {
2994 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2995 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2996 xhci_free_endpoint_ring(xhci, virt_dev, i);
2997 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3000 xhci_zero_in_ctx(xhci, virt_dev);
3002 * Install any rings for completely new endpoints or changed endpoints,
3003 * and free any old rings from changed endpoints.
3005 for (i = 1; i < 31; i++) {
3006 if (!virt_dev->eps[i].new_ring)
3008 /* Only free the old ring if it exists.
3009 * It may not if this is the first add of an endpoint.
3011 if (virt_dev->eps[i].ring) {
3012 xhci_free_endpoint_ring(xhci, virt_dev, i);
3014 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3015 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3016 virt_dev->eps[i].new_ring = NULL;
3019 kfree(command->completion);
3025 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3027 struct xhci_hcd *xhci;
3028 struct xhci_virt_device *virt_dev;
3031 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3034 xhci = hcd_to_xhci(hcd);
3036 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3037 virt_dev = xhci->devs[udev->slot_id];
3038 /* Free any rings allocated for added endpoints */
3039 for (i = 0; i < 31; i++) {
3040 if (virt_dev->eps[i].new_ring) {
3041 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3042 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3043 virt_dev->eps[i].new_ring = NULL;
3046 xhci_zero_in_ctx(xhci, virt_dev);
3049 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3050 struct xhci_container_ctx *in_ctx,
3051 struct xhci_container_ctx *out_ctx,
3052 struct xhci_input_control_ctx *ctrl_ctx,
3053 u32 add_flags, u32 drop_flags)
3055 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3056 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3057 xhci_slot_copy(xhci, in_ctx, out_ctx);
3058 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3061 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
3062 unsigned int slot_id, unsigned int ep_index,
3063 struct xhci_dequeue_state *deq_state)
3065 struct xhci_input_control_ctx *ctrl_ctx;
3066 struct xhci_container_ctx *in_ctx;
3067 struct xhci_ep_ctx *ep_ctx;
3071 in_ctx = xhci->devs[slot_id]->in_ctx;
3072 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3074 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3079 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3080 xhci->devs[slot_id]->out_ctx, ep_index);
3081 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3082 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3083 deq_state->new_deq_ptr);
3085 xhci_warn(xhci, "WARN Cannot submit config ep after "
3086 "reset ep command\n");
3087 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3088 deq_state->new_deq_seg,
3089 deq_state->new_deq_ptr);
3092 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3094 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3095 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3096 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3097 added_ctxs, added_ctxs);
3100 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
3101 unsigned int stream_id, struct xhci_td *td)
3103 struct xhci_dequeue_state deq_state;
3104 struct usb_device *udev = td->urb->dev;
3106 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3107 "Cleaning up stalled endpoint ring");
3108 /* We need to move the HW's dequeue pointer past this TD,
3109 * or it will attempt to resend it on the next doorbell ring.
3111 xhci_find_new_dequeue_state(xhci, udev->slot_id,
3112 ep_index, stream_id, td, &deq_state);
3114 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3117 /* HW with the reset endpoint quirk will use the saved dequeue state to
3118 * issue a configure endpoint command later.
3120 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3121 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3122 "Queueing new dequeue state");
3123 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
3124 ep_index, &deq_state);
3126 /* Better hope no one uses the input context between now and the
3127 * reset endpoint completion!
3128 * XXX: No idea how this hardware will react when stream rings
3131 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3132 "Setting up input context for "
3133 "configure endpoint command");
3134 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3135 ep_index, &deq_state);
3140 * Called after usb core issues a clear halt control message.
3141 * The host side of the halt should already be cleared by a reset endpoint
3142 * command issued when the STALL event was received.
3144 * The reset endpoint command may only be issued to endpoints in the halted
3145 * state. For software that wishes to reset the data toggle or sequence number
3146 * of an endpoint that isn't in the halted state this function will issue a
3147 * configure endpoint command with the Drop and Add bits set for the target
3148 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3151 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3152 struct usb_host_endpoint *host_ep)
3154 struct xhci_hcd *xhci;
3155 struct usb_device *udev;
3156 struct xhci_virt_device *vdev;
3157 struct xhci_virt_ep *ep;
3158 struct xhci_input_control_ctx *ctrl_ctx;
3159 struct xhci_command *stop_cmd, *cfg_cmd;
3160 unsigned int ep_index;
3161 unsigned long flags;
3165 xhci = hcd_to_xhci(hcd);
3166 if (!host_ep->hcpriv)
3168 udev = (struct usb_device *) host_ep->hcpriv;
3169 vdev = xhci->devs[udev->slot_id];
3170 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3171 ep = &vdev->eps[ep_index];
3173 /* Bail out if toggle is already being cleared by a endpoint reset */
3174 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3175 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3178 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3179 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3180 usb_endpoint_xfer_isoc(&host_ep->desc))
3183 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3185 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3188 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3192 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3196 spin_lock_irqsave(&xhci->lock, flags);
3198 /* block queuing new trbs and ringing ep doorbell */
3199 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3202 * Make sure endpoint ring is empty before resetting the toggle/seq.
3203 * Driver is required to synchronously cancel all transfer request.
3204 * Stop the endpoint to force xHC to update the output context
3207 if (!list_empty(&ep->ring->td_list)) {
3208 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3209 spin_unlock_irqrestore(&xhci->lock, flags);
3210 xhci_free_command(xhci, cfg_cmd);
3214 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3217 spin_unlock_irqrestore(&xhci->lock, flags);
3218 xhci_free_command(xhci, cfg_cmd);
3219 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3224 xhci_ring_cmd_db(xhci);
3225 spin_unlock_irqrestore(&xhci->lock, flags);
3227 wait_for_completion(stop_cmd->completion);
3229 spin_lock_irqsave(&xhci->lock, flags);
3231 /* config ep command clears toggle if add and drop ep flags are set */
3232 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3233 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3234 ctrl_ctx, ep_flag, ep_flag);
3235 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3237 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3238 udev->slot_id, false);
3240 spin_unlock_irqrestore(&xhci->lock, flags);
3241 xhci_free_command(xhci, cfg_cmd);
3242 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3247 xhci_ring_cmd_db(xhci);
3248 spin_unlock_irqrestore(&xhci->lock, flags);
3250 wait_for_completion(cfg_cmd->completion);
3252 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3253 xhci_free_command(xhci, cfg_cmd);
3255 xhci_free_command(xhci, stop_cmd);
3258 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3259 struct usb_device *udev, struct usb_host_endpoint *ep,
3260 unsigned int slot_id)
3263 unsigned int ep_index;
3264 unsigned int ep_state;
3268 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3271 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3272 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3273 " descriptor for ep 0x%x does not support streams\n",
3274 ep->desc.bEndpointAddress);
3278 ep_index = xhci_get_endpoint_index(&ep->desc);
3279 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3280 if (ep_state & EP_HAS_STREAMS ||
3281 ep_state & EP_GETTING_STREAMS) {
3282 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3283 "already has streams set up.\n",
3284 ep->desc.bEndpointAddress);
3285 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3286 "dynamic stream context array reallocation.\n");
3289 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3290 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3291 "endpoint 0x%x; URBs are pending.\n",
3292 ep->desc.bEndpointAddress);
3298 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3299 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3301 unsigned int max_streams;
3303 /* The stream context array size must be a power of two */
3304 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3306 * Find out how many primary stream array entries the host controller
3307 * supports. Later we may use secondary stream arrays (similar to 2nd
3308 * level page entries), but that's an optional feature for xHCI host
3309 * controllers. xHCs must support at least 4 stream IDs.
3311 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3312 if (*num_stream_ctxs > max_streams) {
3313 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3315 *num_stream_ctxs = max_streams;
3316 *num_streams = max_streams;
3320 /* Returns an error code if one of the endpoint already has streams.
3321 * This does not change any data structures, it only checks and gathers
3324 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3325 struct usb_device *udev,
3326 struct usb_host_endpoint **eps, unsigned int num_eps,
3327 unsigned int *num_streams, u32 *changed_ep_bitmask)
3329 unsigned int max_streams;
3330 unsigned int endpoint_flag;
3334 for (i = 0; i < num_eps; i++) {
3335 ret = xhci_check_streams_endpoint(xhci, udev,
3336 eps[i], udev->slot_id);
3340 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3341 if (max_streams < (*num_streams - 1)) {
3342 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3343 eps[i]->desc.bEndpointAddress,
3345 *num_streams = max_streams+1;
3348 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3349 if (*changed_ep_bitmask & endpoint_flag)
3351 *changed_ep_bitmask |= endpoint_flag;
3356 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3357 struct usb_device *udev,
3358 struct usb_host_endpoint **eps, unsigned int num_eps)
3360 u32 changed_ep_bitmask = 0;
3361 unsigned int slot_id;
3362 unsigned int ep_index;
3363 unsigned int ep_state;
3366 slot_id = udev->slot_id;
3367 if (!xhci->devs[slot_id])
3370 for (i = 0; i < num_eps; i++) {
3371 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3372 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3373 /* Are streams already being freed for the endpoint? */
3374 if (ep_state & EP_GETTING_NO_STREAMS) {
3375 xhci_warn(xhci, "WARN Can't disable streams for "
3377 "streams are being disabled already\n",
3378 eps[i]->desc.bEndpointAddress);
3381 /* Are there actually any streams to free? */
3382 if (!(ep_state & EP_HAS_STREAMS) &&
3383 !(ep_state & EP_GETTING_STREAMS)) {
3384 xhci_warn(xhci, "WARN Can't disable streams for "
3386 "streams are already disabled!\n",
3387 eps[i]->desc.bEndpointAddress);
3388 xhci_warn(xhci, "WARN xhci_free_streams() called "
3389 "with non-streams endpoint\n");
3392 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3394 return changed_ep_bitmask;
3398 * The USB device drivers use this function (through the HCD interface in USB
3399 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3400 * coordinate mass storage command queueing across multiple endpoints (basically
3401 * a stream ID == a task ID).
3403 * Setting up streams involves allocating the same size stream context array
3404 * for each endpoint and issuing a configure endpoint command for all endpoints.
3406 * Don't allow the call to succeed if one endpoint only supports one stream
3407 * (which means it doesn't support streams at all).
3409 * Drivers may get less stream IDs than they asked for, if the host controller
3410 * hardware or endpoints claim they can't support the number of requested
3413 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3414 struct usb_host_endpoint **eps, unsigned int num_eps,
3415 unsigned int num_streams, gfp_t mem_flags)
3418 struct xhci_hcd *xhci;
3419 struct xhci_virt_device *vdev;
3420 struct xhci_command *config_cmd;
3421 struct xhci_input_control_ctx *ctrl_ctx;
3422 unsigned int ep_index;
3423 unsigned int num_stream_ctxs;
3424 unsigned int max_packet;
3425 unsigned long flags;
3426 u32 changed_ep_bitmask = 0;
3431 /* Add one to the number of streams requested to account for
3432 * stream 0 that is reserved for xHCI usage.
3435 xhci = hcd_to_xhci(hcd);
3436 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3439 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3440 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3441 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3442 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3446 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3450 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3452 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3454 xhci_free_command(xhci, config_cmd);
3458 /* Check to make sure all endpoints are not already configured for
3459 * streams. While we're at it, find the maximum number of streams that
3460 * all the endpoints will support and check for duplicate endpoints.
3462 spin_lock_irqsave(&xhci->lock, flags);
3463 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3464 num_eps, &num_streams, &changed_ep_bitmask);
3466 xhci_free_command(xhci, config_cmd);
3467 spin_unlock_irqrestore(&xhci->lock, flags);
3470 if (num_streams <= 1) {
3471 xhci_warn(xhci, "WARN: endpoints can't handle "
3472 "more than one stream.\n");
3473 xhci_free_command(xhci, config_cmd);
3474 spin_unlock_irqrestore(&xhci->lock, flags);
3477 vdev = xhci->devs[udev->slot_id];
3478 /* Mark each endpoint as being in transition, so
3479 * xhci_urb_enqueue() will reject all URBs.
3481 for (i = 0; i < num_eps; i++) {
3482 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3483 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3485 spin_unlock_irqrestore(&xhci->lock, flags);
3487 /* Setup internal data structures and allocate HW data structures for
3488 * streams (but don't install the HW structures in the input context
3489 * until we're sure all memory allocation succeeded).
3491 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3492 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3493 num_stream_ctxs, num_streams);
3495 for (i = 0; i < num_eps; i++) {
3496 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3497 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3498 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3501 max_packet, mem_flags);
3502 if (!vdev->eps[ep_index].stream_info)
3504 /* Set maxPstreams in endpoint context and update deq ptr to
3505 * point to stream context array. FIXME
3509 /* Set up the input context for a configure endpoint command. */
3510 for (i = 0; i < num_eps; i++) {
3511 struct xhci_ep_ctx *ep_ctx;
3513 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3514 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3516 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3517 vdev->out_ctx, ep_index);
3518 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3519 vdev->eps[ep_index].stream_info);
3521 /* Tell the HW to drop its old copy of the endpoint context info
3522 * and add the updated copy from the input context.
3524 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3525 vdev->out_ctx, ctrl_ctx,
3526 changed_ep_bitmask, changed_ep_bitmask);
3528 /* Issue and wait for the configure endpoint command */
3529 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3532 /* xHC rejected the configure endpoint command for some reason, so we
3533 * leave the old ring intact and free our internal streams data
3539 spin_lock_irqsave(&xhci->lock, flags);
3540 for (i = 0; i < num_eps; i++) {
3541 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3542 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3543 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3544 udev->slot_id, ep_index);
3545 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3547 xhci_free_command(xhci, config_cmd);
3548 spin_unlock_irqrestore(&xhci->lock, flags);
3550 /* Subtract 1 for stream 0, which drivers can't use */
3551 return num_streams - 1;
3554 /* If it didn't work, free the streams! */
3555 for (i = 0; i < num_eps; i++) {
3556 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3557 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3558 vdev->eps[ep_index].stream_info = NULL;
3559 /* FIXME Unset maxPstreams in endpoint context and
3560 * update deq ptr to point to normal string ring.
3562 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3563 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3564 xhci_endpoint_zero(xhci, vdev, eps[i]);
3566 xhci_free_command(xhci, config_cmd);
3570 /* Transition the endpoint from using streams to being a "normal" endpoint
3573 * Modify the endpoint context state, submit a configure endpoint command,
3574 * and free all endpoint rings for streams if that completes successfully.
3576 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3577 struct usb_host_endpoint **eps, unsigned int num_eps,
3581 struct xhci_hcd *xhci;
3582 struct xhci_virt_device *vdev;
3583 struct xhci_command *command;
3584 struct xhci_input_control_ctx *ctrl_ctx;
3585 unsigned int ep_index;
3586 unsigned long flags;
3587 u32 changed_ep_bitmask;
3589 xhci = hcd_to_xhci(hcd);
3590 vdev = xhci->devs[udev->slot_id];
3592 /* Set up a configure endpoint command to remove the streams rings */
3593 spin_lock_irqsave(&xhci->lock, flags);
3594 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3595 udev, eps, num_eps);
3596 if (changed_ep_bitmask == 0) {
3597 spin_unlock_irqrestore(&xhci->lock, flags);
3601 /* Use the xhci_command structure from the first endpoint. We may have
3602 * allocated too many, but the driver may call xhci_free_streams() for
3603 * each endpoint it grouped into one call to xhci_alloc_streams().
3605 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3606 command = vdev->eps[ep_index].stream_info->free_streams_command;
3607 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3609 spin_unlock_irqrestore(&xhci->lock, flags);
3610 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3615 for (i = 0; i < num_eps; i++) {
3616 struct xhci_ep_ctx *ep_ctx;
3618 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3619 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3620 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3621 EP_GETTING_NO_STREAMS;
3623 xhci_endpoint_copy(xhci, command->in_ctx,
3624 vdev->out_ctx, ep_index);
3625 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3626 &vdev->eps[ep_index]);
3628 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3629 vdev->out_ctx, ctrl_ctx,
3630 changed_ep_bitmask, changed_ep_bitmask);
3631 spin_unlock_irqrestore(&xhci->lock, flags);
3633 /* Issue and wait for the configure endpoint command,
3634 * which must succeed.
3636 ret = xhci_configure_endpoint(xhci, udev, command,
3639 /* xHC rejected the configure endpoint command for some reason, so we
3640 * leave the streams rings intact.
3645 spin_lock_irqsave(&xhci->lock, flags);
3646 for (i = 0; i < num_eps; i++) {
3647 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3648 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3649 vdev->eps[ep_index].stream_info = NULL;
3650 /* FIXME Unset maxPstreams in endpoint context and
3651 * update deq ptr to point to normal string ring.
3653 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3654 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3656 spin_unlock_irqrestore(&xhci->lock, flags);
3662 * Deletes endpoint resources for endpoints that were active before a Reset
3663 * Device command, or a Disable Slot command. The Reset Device command leaves
3664 * the control endpoint intact, whereas the Disable Slot command deletes it.
3666 * Must be called with xhci->lock held.
3668 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3669 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3672 unsigned int num_dropped_eps = 0;
3673 unsigned int drop_flags = 0;
3675 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3676 if (virt_dev->eps[i].ring) {
3677 drop_flags |= 1 << i;
3681 xhci->num_active_eps -= num_dropped_eps;
3682 if (num_dropped_eps)
3683 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3684 "Dropped %u ep ctxs, flags = 0x%x, "
3686 num_dropped_eps, drop_flags,
3687 xhci->num_active_eps);
3691 * This submits a Reset Device Command, which will set the device state to 0,
3692 * set the device address to 0, and disable all the endpoints except the default
3693 * control endpoint. The USB core should come back and call
3694 * xhci_address_device(), and then re-set up the configuration. If this is
3695 * called because of a usb_reset_and_verify_device(), then the old alternate
3696 * settings will be re-installed through the normal bandwidth allocation
3699 * Wait for the Reset Device command to finish. Remove all structures
3700 * associated with the endpoints that were disabled. Clear the input device
3701 * structure? Reset the control endpoint 0 max packet size?
3703 * If the virt_dev to be reset does not exist or does not match the udev,
3704 * it means the device is lost, possibly due to the xHC restore error and
3705 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3706 * re-allocate the device.
3708 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3709 struct usb_device *udev)
3712 unsigned long flags;
3713 struct xhci_hcd *xhci;
3714 unsigned int slot_id;
3715 struct xhci_virt_device *virt_dev;
3716 struct xhci_command *reset_device_cmd;
3717 struct xhci_slot_ctx *slot_ctx;
3718 int old_active_eps = 0;
3720 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3723 xhci = hcd_to_xhci(hcd);
3724 slot_id = udev->slot_id;
3725 virt_dev = xhci->devs[slot_id];
3727 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3728 "not exist. Re-allocate the device\n", slot_id);
3729 ret = xhci_alloc_dev(hcd, udev);
3736 if (virt_dev->tt_info)
3737 old_active_eps = virt_dev->tt_info->active_eps;
3739 if (virt_dev->udev != udev) {
3740 /* If the virt_dev and the udev does not match, this virt_dev
3741 * may belong to another udev.
3742 * Re-allocate the device.
3744 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3745 "not match the udev. Re-allocate the device\n",
3747 ret = xhci_alloc_dev(hcd, udev);
3754 /* If device is not setup, there is no point in resetting it */
3755 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3756 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3757 SLOT_STATE_DISABLED)
3760 trace_xhci_discover_or_reset_device(slot_ctx);
3762 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3763 /* Allocate the command structure that holds the struct completion.
3764 * Assume we're in process context, since the normal device reset
3765 * process has to wait for the device anyway. Storage devices are
3766 * reset as part of error handling, so use GFP_NOIO instead of
3769 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3770 if (!reset_device_cmd) {
3771 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3775 /* Attempt to submit the Reset Device command to the command ring */
3776 spin_lock_irqsave(&xhci->lock, flags);
3778 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3780 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3781 spin_unlock_irqrestore(&xhci->lock, flags);
3782 goto command_cleanup;
3784 xhci_ring_cmd_db(xhci);
3785 spin_unlock_irqrestore(&xhci->lock, flags);
3787 /* Wait for the Reset Device command to finish */
3788 wait_for_completion(reset_device_cmd->completion);
3790 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3791 * unless we tried to reset a slot ID that wasn't enabled,
3792 * or the device wasn't in the addressed or configured state.
3794 ret = reset_device_cmd->status;
3796 case COMP_COMMAND_ABORTED:
3797 case COMP_COMMAND_RING_STOPPED:
3798 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3800 goto command_cleanup;
3801 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3802 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3803 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3805 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3806 xhci_dbg(xhci, "Not freeing device rings.\n");
3807 /* Don't treat this as an error. May change my mind later. */
3809 goto command_cleanup;
3811 xhci_dbg(xhci, "Successful reset device command.\n");
3814 if (xhci_is_vendor_info_code(xhci, ret))
3816 xhci_warn(xhci, "Unknown completion code %u for "
3817 "reset device command.\n", ret);
3819 goto command_cleanup;
3822 /* Free up host controller endpoint resources */
3823 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3824 spin_lock_irqsave(&xhci->lock, flags);
3825 /* Don't delete the default control endpoint resources */
3826 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3827 spin_unlock_irqrestore(&xhci->lock, flags);
3830 /* Everything but endpoint 0 is disabled, so free the rings. */
3831 for (i = 1; i < 31; i++) {
3832 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3834 if (ep->ep_state & EP_HAS_STREAMS) {
3835 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3836 xhci_get_endpoint_address(i));
3837 xhci_free_stream_info(xhci, ep->stream_info);
3838 ep->stream_info = NULL;
3839 ep->ep_state &= ~EP_HAS_STREAMS;
3843 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3844 xhci_free_endpoint_ring(xhci, virt_dev, i);
3846 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3847 xhci_drop_ep_from_interval_table(xhci,
3848 &virt_dev->eps[i].bw_info,
3853 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3855 /* If necessary, update the number of active TTs on this root port */
3856 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3857 virt_dev->flags = 0;
3861 xhci_free_command(xhci, reset_device_cmd);
3866 * At this point, the struct usb_device is about to go away, the device has
3867 * disconnected, and all traffic has been stopped and the endpoints have been
3868 * disabled. Free any HC data structures associated with that device.
3870 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3872 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3873 struct xhci_virt_device *virt_dev;
3874 struct xhci_slot_ctx *slot_ctx;
3877 #ifndef CONFIG_USB_DEFAULT_PERSIST
3879 * We called pm_runtime_get_noresume when the device was attached.
3880 * Decrement the counter here to allow controller to runtime suspend
3881 * if no devices remain.
3883 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3884 pm_runtime_put_noidle(hcd->self.controller);
3887 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3888 /* If the host is halted due to driver unload, we still need to free the
3891 if (ret <= 0 && ret != -ENODEV)
3894 virt_dev = xhci->devs[udev->slot_id];
3895 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3896 trace_xhci_free_dev(slot_ctx);
3898 /* Stop any wayward timer functions (which may grab the lock) */
3899 for (i = 0; i < 31; i++) {
3900 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3901 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3903 xhci_debugfs_remove_slot(xhci, udev->slot_id);
3904 virt_dev->udev = NULL;
3905 ret = xhci_disable_slot(xhci, udev->slot_id);
3907 xhci_free_virt_device(xhci, udev->slot_id);
3910 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3912 struct xhci_command *command;
3913 unsigned long flags;
3917 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3921 spin_lock_irqsave(&xhci->lock, flags);
3922 /* Don't disable the slot if the host controller is dead. */
3923 state = readl(&xhci->op_regs->status);
3924 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3925 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3926 spin_unlock_irqrestore(&xhci->lock, flags);
3931 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3934 spin_unlock_irqrestore(&xhci->lock, flags);
3938 xhci_ring_cmd_db(xhci);
3939 spin_unlock_irqrestore(&xhci->lock, flags);
3944 * Checks if we have enough host controller resources for the default control
3947 * Must be called with xhci->lock held.
3949 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3951 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3952 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3953 "Not enough ep ctxs: "
3954 "%u active, need to add 1, limit is %u.",
3955 xhci->num_active_eps, xhci->limit_active_eps);
3958 xhci->num_active_eps += 1;
3959 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3960 "Adding 1 ep ctx, %u now active.",
3961 xhci->num_active_eps);
3967 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3968 * timed out, or allocating memory failed. Returns 1 on success.
3970 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3972 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3973 struct xhci_virt_device *vdev;
3974 struct xhci_slot_ctx *slot_ctx;
3975 unsigned long flags;
3977 struct xhci_command *command;
3979 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3983 spin_lock_irqsave(&xhci->lock, flags);
3984 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3986 spin_unlock_irqrestore(&xhci->lock, flags);
3987 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3988 xhci_free_command(xhci, command);
3991 xhci_ring_cmd_db(xhci);
3992 spin_unlock_irqrestore(&xhci->lock, flags);
3994 wait_for_completion(command->completion);
3995 slot_id = command->slot_id;
3997 if (!slot_id || command->status != COMP_SUCCESS) {
3998 xhci_err(xhci, "Error while assigning device slot ID\n");
3999 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4001 readl(&xhci->cap_regs->hcs_params1)));
4002 xhci_free_command(xhci, command);
4006 xhci_free_command(xhci, command);
4008 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4009 spin_lock_irqsave(&xhci->lock, flags);
4010 ret = xhci_reserve_host_control_ep_resources(xhci);
4012 spin_unlock_irqrestore(&xhci->lock, flags);
4013 xhci_warn(xhci, "Not enough host resources, "
4014 "active endpoint contexts = %u\n",
4015 xhci->num_active_eps);
4018 spin_unlock_irqrestore(&xhci->lock, flags);
4020 /* Use GFP_NOIO, since this function can be called from
4021 * xhci_discover_or_reset_device(), which may be called as part of
4022 * mass storage driver error handling.
4024 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4025 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4028 vdev = xhci->devs[slot_id];
4029 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4030 trace_xhci_alloc_dev(slot_ctx);
4032 udev->slot_id = slot_id;
4034 xhci_debugfs_create_slot(xhci, slot_id);
4036 #ifndef CONFIG_USB_DEFAULT_PERSIST
4038 * If resetting upon resume, we can't put the controller into runtime
4039 * suspend if there is a device attached.
4041 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4042 pm_runtime_get_noresume(hcd->self.controller);
4045 /* Is this a LS or FS device under a HS hub? */
4046 /* Hub or peripherial? */
4050 ret = xhci_disable_slot(xhci, udev->slot_id);
4052 xhci_free_virt_device(xhci, udev->slot_id);
4058 * Issue an Address Device command and optionally send a corresponding
4059 * SetAddress request to the device.
4061 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4062 enum xhci_setup_dev setup)
4064 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4065 unsigned long flags;
4066 struct xhci_virt_device *virt_dev;
4068 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4069 struct xhci_slot_ctx *slot_ctx;
4070 struct xhci_input_control_ctx *ctrl_ctx;
4072 struct xhci_command *command = NULL;
4074 mutex_lock(&xhci->mutex);
4076 if (xhci->xhc_state) { /* dying, removing or halted */
4081 if (!udev->slot_id) {
4082 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4083 "Bad Slot ID %d", udev->slot_id);
4088 virt_dev = xhci->devs[udev->slot_id];
4090 if (WARN_ON(!virt_dev)) {
4092 * In plug/unplug torture test with an NEC controller,
4093 * a zero-dereference was observed once due to virt_dev = 0.
4094 * Print useful debug rather than crash if it is observed again!
4096 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4101 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4102 trace_xhci_setup_device_slot(slot_ctx);
4104 if (setup == SETUP_CONTEXT_ONLY) {
4105 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4106 SLOT_STATE_DEFAULT) {
4107 xhci_dbg(xhci, "Slot already in default state\n");
4112 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4118 command->in_ctx = virt_dev->in_ctx;
4120 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4121 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4123 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4129 * If this is the first Set Address since device plug-in or
4130 * virt_device realloaction after a resume with an xHCI power loss,
4131 * then set up the slot context.
4133 if (!slot_ctx->dev_info)
4134 xhci_setup_addressable_virt_dev(xhci, udev);
4135 /* Otherwise, update the control endpoint ring enqueue pointer. */
4137 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4138 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4139 ctrl_ctx->drop_flags = 0;
4141 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4142 le32_to_cpu(slot_ctx->dev_info) >> 27);
4144 spin_lock_irqsave(&xhci->lock, flags);
4145 trace_xhci_setup_device(virt_dev);
4146 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4147 udev->slot_id, setup);
4149 spin_unlock_irqrestore(&xhci->lock, flags);
4150 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4151 "FIXME: allocate a command ring segment");
4154 xhci_ring_cmd_db(xhci);
4155 spin_unlock_irqrestore(&xhci->lock, flags);
4157 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4158 wait_for_completion(command->completion);
4160 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4161 * the SetAddress() "recovery interval" required by USB and aborting the
4162 * command on a timeout.
4164 switch (command->status) {
4165 case COMP_COMMAND_ABORTED:
4166 case COMP_COMMAND_RING_STOPPED:
4167 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4170 case COMP_CONTEXT_STATE_ERROR:
4171 case COMP_SLOT_NOT_ENABLED_ERROR:
4172 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4173 act, udev->slot_id);
4176 case COMP_USB_TRANSACTION_ERROR:
4177 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4179 mutex_unlock(&xhci->mutex);
4180 ret = xhci_disable_slot(xhci, udev->slot_id);
4182 xhci_alloc_dev(hcd, udev);
4183 kfree(command->completion);
4186 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4187 dev_warn(&udev->dev,
4188 "ERROR: Incompatible device for setup %s command\n", act);
4192 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4193 "Successful setup %s command", act);
4197 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4198 act, command->status);
4199 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4205 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4206 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4207 "Op regs DCBAA ptr = %#016llx", temp_64);
4208 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4209 "Slot ID %d dcbaa entry @%p = %#016llx",
4211 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4212 (unsigned long long)
4213 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4214 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4215 "Output Context DMA address = %#08llx",
4216 (unsigned long long)virt_dev->out_ctx->dma);
4217 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4218 le32_to_cpu(slot_ctx->dev_info) >> 27);
4220 * USB core uses address 1 for the roothubs, so we add one to the
4221 * address given back to us by the HC.
4223 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4224 le32_to_cpu(slot_ctx->dev_info) >> 27);
4225 /* Zero the input context control for later use */
4226 ctrl_ctx->add_flags = 0;
4227 ctrl_ctx->drop_flags = 0;
4229 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4230 "Internal device address = %d",
4231 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4233 mutex_unlock(&xhci->mutex);
4235 kfree(command->completion);
4241 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4243 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4246 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4248 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4252 * Transfer the port index into real index in the HW port status
4253 * registers. Caculate offset between the port's PORTSC register
4254 * and port status base. Divide the number of per port register
4255 * to get the real index. The raw port number bases 1.
4257 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4259 struct xhci_hub *rhub;
4261 rhub = xhci_get_rhub(hcd);
4262 return rhub->ports[port1 - 1]->hw_portnum + 1;
4266 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4267 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4269 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4270 struct usb_device *udev, u16 max_exit_latency)
4272 struct xhci_virt_device *virt_dev;
4273 struct xhci_command *command;
4274 struct xhci_input_control_ctx *ctrl_ctx;
4275 struct xhci_slot_ctx *slot_ctx;
4276 unsigned long flags;
4279 spin_lock_irqsave(&xhci->lock, flags);
4281 virt_dev = xhci->devs[udev->slot_id];
4284 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4285 * xHC was re-initialized. Exit latency will be set later after
4286 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4289 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4290 spin_unlock_irqrestore(&xhci->lock, flags);
4294 /* Attempt to issue an Evaluate Context command to change the MEL. */
4295 command = xhci->lpm_command;
4296 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4298 spin_unlock_irqrestore(&xhci->lock, flags);
4299 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4304 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4305 spin_unlock_irqrestore(&xhci->lock, flags);
4307 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4308 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4309 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4310 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4311 slot_ctx->dev_state = 0;
4313 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4314 "Set up evaluate context for LPM MEL change.");
4316 /* Issue and wait for the evaluate context command. */
4317 ret = xhci_configure_endpoint(xhci, udev, command,
4321 spin_lock_irqsave(&xhci->lock, flags);
4322 virt_dev->current_mel = max_exit_latency;
4323 spin_unlock_irqrestore(&xhci->lock, flags);
4330 /* BESL to HIRD Encoding array for USB2 LPM */
4331 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4332 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4334 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4335 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4336 struct usb_device *udev)
4338 int u2del, besl, besl_host;
4339 int besl_device = 0;
4342 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4343 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4345 if (field & USB_BESL_SUPPORT) {
4346 for (besl_host = 0; besl_host < 16; besl_host++) {
4347 if (xhci_besl_encoding[besl_host] >= u2del)
4350 /* Use baseline BESL value as default */
4351 if (field & USB_BESL_BASELINE_VALID)
4352 besl_device = USB_GET_BESL_BASELINE(field);
4353 else if (field & USB_BESL_DEEP_VALID)
4354 besl_device = USB_GET_BESL_DEEP(field);
4359 besl_host = (u2del - 51) / 75 + 1;
4362 besl = besl_host + besl_device;
4369 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4370 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4377 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4379 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4380 l1 = udev->l1_params.timeout / 256;
4382 /* device has preferred BESLD */
4383 if (field & USB_BESL_DEEP_VALID) {
4384 besld = USB_GET_BESL_DEEP(field);
4388 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4391 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4392 struct usb_device *udev, int enable)
4394 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4395 struct xhci_port **ports;
4396 __le32 __iomem *pm_addr, *hlpm_addr;
4397 u32 pm_val, hlpm_val, field;
4398 unsigned int port_num;
4399 unsigned long flags;
4400 int hird, exit_latency;
4403 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4407 if (!udev->parent || udev->parent->parent ||
4408 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4411 if (udev->usb2_hw_lpm_capable != 1)
4414 spin_lock_irqsave(&xhci->lock, flags);
4416 ports = xhci->usb2_rhub.ports;
4417 port_num = udev->portnum - 1;
4418 pm_addr = ports[port_num]->addr + PORTPMSC;
4419 pm_val = readl(pm_addr);
4420 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4422 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4423 enable ? "enable" : "disable", port_num + 1);
4425 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4426 /* Host supports BESL timeout instead of HIRD */
4427 if (udev->usb2_hw_lpm_besl_capable) {
4428 /* if device doesn't have a preferred BESL value use a
4429 * default one which works with mixed HIRD and BESL
4430 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4432 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4433 if ((field & USB_BESL_SUPPORT) &&
4434 (field & USB_BESL_BASELINE_VALID))
4435 hird = USB_GET_BESL_BASELINE(field);
4437 hird = udev->l1_params.besl;
4439 exit_latency = xhci_besl_encoding[hird];
4440 spin_unlock_irqrestore(&xhci->lock, flags);
4442 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4443 * input context for link powermanagement evaluate
4444 * context commands. It is protected by hcd->bandwidth
4445 * mutex and is shared by all devices. We need to set
4446 * the max ext latency in USB 2 BESL LPM as well, so
4447 * use the same mutex and xhci_change_max_exit_latency()
4449 mutex_lock(hcd->bandwidth_mutex);
4450 ret = xhci_change_max_exit_latency(xhci, udev,
4452 mutex_unlock(hcd->bandwidth_mutex);
4456 spin_lock_irqsave(&xhci->lock, flags);
4458 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4459 writel(hlpm_val, hlpm_addr);
4463 hird = xhci_calculate_hird_besl(xhci, udev);
4466 pm_val &= ~PORT_HIRD_MASK;
4467 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4468 writel(pm_val, pm_addr);
4469 pm_val = readl(pm_addr);
4471 writel(pm_val, pm_addr);
4475 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4476 writel(pm_val, pm_addr);
4479 if (udev->usb2_hw_lpm_besl_capable) {
4480 spin_unlock_irqrestore(&xhci->lock, flags);
4481 mutex_lock(hcd->bandwidth_mutex);
4482 xhci_change_max_exit_latency(xhci, udev, 0);
4483 mutex_unlock(hcd->bandwidth_mutex);
4488 spin_unlock_irqrestore(&xhci->lock, flags);
4492 /* check if a usb2 port supports a given extened capability protocol
4493 * only USB2 ports extended protocol capability values are cached.
4494 * Return 1 if capability is supported
4496 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4497 unsigned capability)
4499 u32 port_offset, port_count;
4502 for (i = 0; i < xhci->num_ext_caps; i++) {
4503 if (xhci->ext_caps[i] & capability) {
4504 /* port offsets starts at 1 */
4505 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4506 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4507 if (port >= port_offset &&
4508 port < port_offset + port_count)
4515 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4517 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4518 int portnum = udev->portnum - 1;
4520 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4524 /* we only support lpm for non-hub device connected to root hub yet */
4525 if (!udev->parent || udev->parent->parent ||
4526 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4529 if (xhci->hw_lpm_support == 1 &&
4530 xhci_check_usb2_port_capability(
4531 xhci, portnum, XHCI_HLC)) {
4532 udev->usb2_hw_lpm_capable = 1;
4533 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4534 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4535 if (xhci_check_usb2_port_capability(xhci, portnum,
4537 udev->usb2_hw_lpm_besl_capable = 1;
4543 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4545 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4546 static unsigned long long xhci_service_interval_to_ns(
4547 struct usb_endpoint_descriptor *desc)
4549 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4552 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4553 enum usb3_link_state state)
4555 unsigned long long sel;
4556 unsigned long long pel;
4557 unsigned int max_sel_pel;
4562 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4563 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4564 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4565 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4569 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4570 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4571 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4575 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4577 return USB3_LPM_DISABLED;
4580 if (sel <= max_sel_pel && pel <= max_sel_pel)
4581 return USB3_LPM_DEVICE_INITIATED;
4583 if (sel > max_sel_pel)
4584 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4585 "due to long SEL %llu ms\n",
4588 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4589 "due to long PEL %llu ms\n",
4591 return USB3_LPM_DISABLED;
4594 /* The U1 timeout should be the maximum of the following values:
4595 * - For control endpoints, U1 system exit latency (SEL) * 3
4596 * - For bulk endpoints, U1 SEL * 5
4597 * - For interrupt endpoints:
4598 * - Notification EPs, U1 SEL * 3
4599 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4600 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4602 static unsigned long long xhci_calculate_intel_u1_timeout(
4603 struct usb_device *udev,
4604 struct usb_endpoint_descriptor *desc)
4606 unsigned long long timeout_ns;
4610 ep_type = usb_endpoint_type(desc);
4612 case USB_ENDPOINT_XFER_CONTROL:
4613 timeout_ns = udev->u1_params.sel * 3;
4615 case USB_ENDPOINT_XFER_BULK:
4616 timeout_ns = udev->u1_params.sel * 5;
4618 case USB_ENDPOINT_XFER_INT:
4619 intr_type = usb_endpoint_interrupt_type(desc);
4620 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4621 timeout_ns = udev->u1_params.sel * 3;
4624 /* Otherwise the calculation is the same as isoc eps */
4626 case USB_ENDPOINT_XFER_ISOC:
4627 timeout_ns = xhci_service_interval_to_ns(desc);
4628 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4629 if (timeout_ns < udev->u1_params.sel * 2)
4630 timeout_ns = udev->u1_params.sel * 2;
4639 /* Returns the hub-encoded U1 timeout value. */
4640 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4641 struct usb_device *udev,
4642 struct usb_endpoint_descriptor *desc)
4644 unsigned long long timeout_ns;
4646 /* Prevent U1 if service interval is shorter than U1 exit latency */
4647 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4648 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4649 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4650 return USB3_LPM_DISABLED;
4654 if (xhci->quirks & XHCI_INTEL_HOST)
4655 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4657 timeout_ns = udev->u1_params.sel;
4659 /* The U1 timeout is encoded in 1us intervals.
4660 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4662 if (timeout_ns == USB3_LPM_DISABLED)
4665 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4667 /* If the necessary timeout value is bigger than what we can set in the
4668 * USB 3.0 hub, we have to disable hub-initiated U1.
4670 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4672 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4673 "due to long timeout %llu ms\n", timeout_ns);
4674 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4677 /* The U2 timeout should be the maximum of:
4678 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4679 * - largest bInterval of any active periodic endpoint (to avoid going
4680 * into lower power link states between intervals).
4681 * - the U2 Exit Latency of the device
4683 static unsigned long long xhci_calculate_intel_u2_timeout(
4684 struct usb_device *udev,
4685 struct usb_endpoint_descriptor *desc)
4687 unsigned long long timeout_ns;
4688 unsigned long long u2_del_ns;
4690 timeout_ns = 10 * 1000 * 1000;
4692 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4693 (xhci_service_interval_to_ns(desc) > timeout_ns))
4694 timeout_ns = xhci_service_interval_to_ns(desc);
4696 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4697 if (u2_del_ns > timeout_ns)
4698 timeout_ns = u2_del_ns;
4703 /* Returns the hub-encoded U2 timeout value. */
4704 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4705 struct usb_device *udev,
4706 struct usb_endpoint_descriptor *desc)
4708 unsigned long long timeout_ns;
4710 /* Prevent U2 if service interval is shorter than U2 exit latency */
4711 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4712 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4713 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4714 return USB3_LPM_DISABLED;
4718 if (xhci->quirks & XHCI_INTEL_HOST)
4719 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4721 timeout_ns = udev->u2_params.sel;
4723 /* The U2 timeout is encoded in 256us intervals */
4724 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4725 /* If the necessary timeout value is bigger than what we can set in the
4726 * USB 3.0 hub, we have to disable hub-initiated U2.
4728 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4730 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4731 "due to long timeout %llu ms\n", timeout_ns);
4732 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4735 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4736 struct usb_device *udev,
4737 struct usb_endpoint_descriptor *desc,
4738 enum usb3_link_state state,
4741 if (state == USB3_LPM_U1)
4742 return xhci_calculate_u1_timeout(xhci, udev, desc);
4743 else if (state == USB3_LPM_U2)
4744 return xhci_calculate_u2_timeout(xhci, udev, desc);
4746 return USB3_LPM_DISABLED;
4749 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4750 struct usb_device *udev,
4751 struct usb_endpoint_descriptor *desc,
4752 enum usb3_link_state state,
4757 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4758 desc, state, timeout);
4760 /* If we found we can't enable hub-initiated LPM, and
4761 * the U1 or U2 exit latency was too high to allow
4762 * device-initiated LPM as well, then we will disable LPM
4763 * for this device, so stop searching any further.
4765 if (alt_timeout == USB3_LPM_DISABLED) {
4766 *timeout = alt_timeout;
4769 if (alt_timeout > *timeout)
4770 *timeout = alt_timeout;
4774 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4775 struct usb_device *udev,
4776 struct usb_host_interface *alt,
4777 enum usb3_link_state state,
4782 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4783 if (xhci_update_timeout_for_endpoint(xhci, udev,
4784 &alt->endpoint[j].desc, state, timeout))
4791 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4792 enum usb3_link_state state)
4794 struct usb_device *parent;
4795 unsigned int num_hubs;
4797 if (state == USB3_LPM_U2)
4800 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4801 for (parent = udev->parent, num_hubs = 0; parent->parent;
4802 parent = parent->parent)
4808 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4809 " below second-tier hub.\n");
4810 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4811 "to decrease power consumption.\n");
4815 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4816 struct usb_device *udev,
4817 enum usb3_link_state state)
4819 if (xhci->quirks & XHCI_INTEL_HOST)
4820 return xhci_check_intel_tier_policy(udev, state);
4825 /* Returns the U1 or U2 timeout that should be enabled.
4826 * If the tier check or timeout setting functions return with a non-zero exit
4827 * code, that means the timeout value has been finalized and we shouldn't look
4828 * at any more endpoints.
4830 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4831 struct usb_device *udev, enum usb3_link_state state)
4833 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4834 struct usb_host_config *config;
4837 u16 timeout = USB3_LPM_DISABLED;
4839 if (state == USB3_LPM_U1)
4841 else if (state == USB3_LPM_U2)
4844 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4849 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4852 /* Gather some information about the currently installed configuration
4853 * and alternate interface settings.
4855 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4859 config = udev->actconfig;
4863 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4864 struct usb_driver *driver;
4865 struct usb_interface *intf = config->interface[i];
4870 /* Check if any currently bound drivers want hub-initiated LPM
4873 if (intf->dev.driver) {
4874 driver = to_usb_driver(intf->dev.driver);
4875 if (driver && driver->disable_hub_initiated_lpm) {
4876 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4877 state_name, driver->name);
4878 timeout = xhci_get_timeout_no_hub_lpm(udev,
4880 if (timeout == USB3_LPM_DISABLED)
4885 /* Not sure how this could happen... */
4886 if (!intf->cur_altsetting)
4889 if (xhci_update_timeout_for_interface(xhci, udev,
4890 intf->cur_altsetting,
4897 static int calculate_max_exit_latency(struct usb_device *udev,
4898 enum usb3_link_state state_changed,
4899 u16 hub_encoded_timeout)
4901 unsigned long long u1_mel_us = 0;
4902 unsigned long long u2_mel_us = 0;
4903 unsigned long long mel_us = 0;
4909 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4910 hub_encoded_timeout == USB3_LPM_DISABLED);
4911 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4912 hub_encoded_timeout == USB3_LPM_DISABLED);
4914 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4915 hub_encoded_timeout != USB3_LPM_DISABLED);
4916 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4917 hub_encoded_timeout != USB3_LPM_DISABLED);
4919 /* If U1 was already enabled and we're not disabling it,
4920 * or we're going to enable U1, account for the U1 max exit latency.
4922 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4924 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4925 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4927 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4929 if (u1_mel_us > u2_mel_us)
4933 /* xHCI host controller max exit latency field is only 16 bits wide. */
4934 if (mel_us > MAX_EXIT) {
4935 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4936 "is too big.\n", mel_us);
4942 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4943 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4944 struct usb_device *udev, enum usb3_link_state state)
4946 struct xhci_hcd *xhci;
4947 u16 hub_encoded_timeout;
4951 xhci = hcd_to_xhci(hcd);
4952 /* The LPM timeout values are pretty host-controller specific, so don't
4953 * enable hub-initiated timeouts unless the vendor has provided
4954 * information about their timeout algorithm.
4956 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4957 !xhci->devs[udev->slot_id])
4958 return USB3_LPM_DISABLED;
4960 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4961 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4963 /* Max Exit Latency is too big, disable LPM. */
4964 hub_encoded_timeout = USB3_LPM_DISABLED;
4968 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4971 return hub_encoded_timeout;
4974 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4975 struct usb_device *udev, enum usb3_link_state state)
4977 struct xhci_hcd *xhci;
4980 xhci = hcd_to_xhci(hcd);
4981 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4982 !xhci->devs[udev->slot_id])
4985 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4986 return xhci_change_max_exit_latency(xhci, udev, mel);
4988 #else /* CONFIG_PM */
4990 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4991 struct usb_device *udev, int enable)
4996 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5001 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5002 struct usb_device *udev, enum usb3_link_state state)
5004 return USB3_LPM_DISABLED;
5007 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5008 struct usb_device *udev, enum usb3_link_state state)
5012 #endif /* CONFIG_PM */
5014 /*-------------------------------------------------------------------------*/
5016 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5017 * internal data structures for the device.
5019 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5020 struct usb_tt *tt, gfp_t mem_flags)
5022 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5023 struct xhci_virt_device *vdev;
5024 struct xhci_command *config_cmd;
5025 struct xhci_input_control_ctx *ctrl_ctx;
5026 struct xhci_slot_ctx *slot_ctx;
5027 unsigned long flags;
5028 unsigned think_time;
5031 /* Ignore root hubs */
5035 vdev = xhci->devs[hdev->slot_id];
5037 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5041 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5045 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5047 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5049 xhci_free_command(xhci, config_cmd);
5053 spin_lock_irqsave(&xhci->lock, flags);
5054 if (hdev->speed == USB_SPEED_HIGH &&
5055 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5056 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5057 xhci_free_command(xhci, config_cmd);
5058 spin_unlock_irqrestore(&xhci->lock, flags);
5062 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5063 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5064 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5065 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5067 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5068 * but it may be already set to 1 when setup an xHCI virtual
5069 * device, so clear it anyway.
5072 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5073 else if (hdev->speed == USB_SPEED_FULL)
5074 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5076 if (xhci->hci_version > 0x95) {
5077 xhci_dbg(xhci, "xHCI version %x needs hub "
5078 "TT think time and number of ports\n",
5079 (unsigned int) xhci->hci_version);
5080 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5081 /* Set TT think time - convert from ns to FS bit times.
5082 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5083 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5085 * xHCI 1.0: this field shall be 0 if the device is not a
5088 think_time = tt->think_time;
5089 if (think_time != 0)
5090 think_time = (think_time / 666) - 1;
5091 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5092 slot_ctx->tt_info |=
5093 cpu_to_le32(TT_THINK_TIME(think_time));
5095 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5096 "TT think time or number of ports\n",
5097 (unsigned int) xhci->hci_version);
5099 slot_ctx->dev_state = 0;
5100 spin_unlock_irqrestore(&xhci->lock, flags);
5102 xhci_dbg(xhci, "Set up %s for hub device.\n",
5103 (xhci->hci_version > 0x95) ?
5104 "configure endpoint" : "evaluate context");
5106 /* Issue and wait for the configure endpoint or
5107 * evaluate context command.
5109 if (xhci->hci_version > 0x95)
5110 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5113 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5116 xhci_free_command(xhci, config_cmd);
5120 static int xhci_get_frame(struct usb_hcd *hcd)
5122 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5123 /* EHCI mods by the periodic size. Why? */
5124 return readl(&xhci->run_regs->microframe_index) >> 3;
5127 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5129 struct xhci_hcd *xhci;
5131 * TODO: Check with DWC3 clients for sysdev according to
5134 struct device *dev = hcd->self.sysdev;
5135 unsigned int minor_rev;
5138 /* Accept arbitrarily long scatter-gather lists */
5139 hcd->self.sg_tablesize = ~0;
5141 /* support to build packet from discontinuous buffers */
5142 hcd->self.no_sg_constraint = 1;
5144 /* XHCI controllers don't stop the ep queue on short packets :| */
5145 hcd->self.no_stop_on_short = 1;
5147 xhci = hcd_to_xhci(hcd);
5149 if (usb_hcd_is_primary_hcd(hcd)) {
5150 xhci->main_hcd = hcd;
5151 xhci->usb2_rhub.hcd = hcd;
5152 /* Mark the first roothub as being USB 2.0.
5153 * The xHCI driver will register the USB 3.0 roothub.
5155 hcd->speed = HCD_USB2;
5156 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5158 * USB 2.0 roothub under xHCI has an integrated TT,
5159 * (rate matching hub) as opposed to having an OHCI/UHCI
5160 * companion controller.
5165 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5166 * should return 0x31 for sbrn, or that the minor revision
5167 * is a two digit BCD containig minor and sub-minor numbers.
5168 * This was later clarified in xHCI 1.2.
5170 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5171 * minor revision set to 0x1 instead of 0x10.
5173 if (xhci->usb3_rhub.min_rev == 0x1)
5176 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5178 switch (minor_rev) {
5180 hcd->speed = HCD_USB32;
5181 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5182 hcd->self.root_hub->rx_lanes = 2;
5183 hcd->self.root_hub->tx_lanes = 2;
5186 hcd->speed = HCD_USB31;
5187 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5190 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5192 minor_rev ? "Enhanced " : "");
5194 xhci->usb3_rhub.hcd = hcd;
5195 /* xHCI private pointer was set in xhci_pci_probe for the second
5196 * registered roothub.
5201 mutex_init(&xhci->mutex);
5202 xhci->cap_regs = hcd->regs;
5203 xhci->op_regs = hcd->regs +
5204 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5205 xhci->run_regs = hcd->regs +
5206 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5207 /* Cache read-only capability registers */
5208 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5209 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5210 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5211 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5212 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5213 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5214 if (xhci->hci_version > 0x100)
5215 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5217 xhci->quirks |= quirks;
5219 get_quirks(dev, xhci);
5221 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5222 * success event after a short transfer. This quirk will ignore such
5225 if (xhci->hci_version > 0x96)
5226 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5228 /* Make sure the HC is halted. */
5229 retval = xhci_halt(xhci);
5233 xhci_zero_64b_regs(xhci);
5235 xhci_dbg(xhci, "Resetting HCD\n");
5236 /* Reset the internal HC memory state and registers. */
5237 retval = xhci_reset(xhci);
5240 xhci_dbg(xhci, "Reset complete\n");
5243 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5244 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5245 * address memory pointers actually. So, this driver clears the AC64
5246 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5247 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5249 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5250 xhci->hcc_params &= ~BIT(0);
5252 /* Set dma_mask and coherent_dma_mask to 64-bits,
5253 * if xHC supports 64-bit addressing */
5254 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5255 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5256 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5257 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5260 * This is to avoid error in cases where a 32-bit USB
5261 * controller is used on a 64-bit capable system.
5263 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5266 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5267 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5270 xhci_dbg(xhci, "Calling HCD init\n");
5271 /* Initialize HCD and host controller data structures. */
5272 retval = xhci_init(hcd);
5275 xhci_dbg(xhci, "Called HCD init\n");
5277 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5278 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5282 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5284 static const struct hc_driver xhci_hc_driver = {
5285 .description = "xhci-hcd",
5286 .product_desc = "xHCI Host Controller",
5287 .hcd_priv_size = sizeof(struct xhci_hcd),
5290 * generic hardware linkage
5293 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5296 * basic lifecycle operations
5298 .reset = NULL, /* set in xhci_init_driver() */
5301 .shutdown = xhci_shutdown,
5304 * managing i/o requests and associated device resources
5306 .urb_enqueue = xhci_urb_enqueue,
5307 .urb_dequeue = xhci_urb_dequeue,
5308 .alloc_dev = xhci_alloc_dev,
5309 .free_dev = xhci_free_dev,
5310 .alloc_streams = xhci_alloc_streams,
5311 .free_streams = xhci_free_streams,
5312 .add_endpoint = xhci_add_endpoint,
5313 .drop_endpoint = xhci_drop_endpoint,
5314 .endpoint_reset = xhci_endpoint_reset,
5315 .check_bandwidth = xhci_check_bandwidth,
5316 .reset_bandwidth = xhci_reset_bandwidth,
5317 .fixup_endpoint = xhci_fixup_endpoint,
5318 .address_device = xhci_address_device,
5319 .enable_device = xhci_enable_device,
5320 .update_hub_device = xhci_update_hub_device,
5321 .reset_device = xhci_discover_or_reset_device,
5324 * scheduling support
5326 .get_frame_number = xhci_get_frame,
5331 .hub_control = xhci_hub_control,
5332 .hub_status_data = xhci_hub_status_data,
5333 .bus_suspend = xhci_bus_suspend,
5334 .bus_resume = xhci_bus_resume,
5335 .get_resuming_ports = xhci_get_resuming_ports,
5338 * call back when device connected and addressed
5340 .update_device = xhci_update_device,
5341 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5342 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5343 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5344 .find_raw_port_number = xhci_find_raw_port_number,
5347 void xhci_init_driver(struct hc_driver *drv,
5348 const struct xhci_driver_overrides *over)
5352 /* Copy the generic table to drv then apply the overrides */
5353 *drv = xhci_hc_driver;
5356 drv->hcd_priv_size += over->extra_priv_size;
5358 drv->reset = over->reset;
5360 drv->start = over->start;
5363 EXPORT_SYMBOL_GPL(xhci_init_driver);
5365 MODULE_DESCRIPTION(DRIVER_DESC);
5366 MODULE_AUTHOR(DRIVER_AUTHOR);
5367 MODULE_LICENSE("GPL");
5369 static int __init xhci_hcd_init(void)
5372 * Check the compiler generated sizes of structures that must be laid
5373 * out in specific ways for hardware access.
5375 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5376 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5377 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5378 /* xhci_device_control has eight fields, and also
5379 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5381 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5382 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5383 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5384 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5385 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5386 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5387 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5392 xhci_debugfs_create_root();
5398 * If an init function is provided, an exit function must also be provided
5399 * to allow module unload.
5401 static void __exit xhci_hcd_fini(void)
5403 xhci_debugfs_remove_root();
5406 module_init(xhci_hcd_init);
5407 module_exit(xhci_hcd_fini);