1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
113 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
116 ret = xhci_handshake(&xhci->op_regs->status,
117 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 xhci_warn(xhci, "Host halt failed, %d\n", ret);
122 xhci->xhc_state |= XHCI_STATE_HALTED;
123 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
128 * Set the run bit and wait for the host to be running.
130 int xhci_start(struct xhci_hcd *xhci)
135 temp = readl(&xhci->op_regs->command);
137 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 writel(temp, &xhci->op_regs->command);
142 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 ret = xhci_handshake(&xhci->op_regs->status,
146 STS_HALT, 0, XHCI_MAX_HALT_USEC);
147 if (ret == -ETIMEDOUT)
148 xhci_err(xhci, "Host took too long to start, "
149 "waited %u microseconds.\n",
152 /* clear state flags. Including dying, halted or removing */
154 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
163 * This resets pipelines, timers, counters, state machines, etc.
164 * Transactions will be terminated immediately, and operational registers
165 * will be set to their defaults.
167 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
173 state = readl(&xhci->op_regs->status);
175 if (state == ~(u32)0) {
176 xhci_warn(xhci, "Host not accessible, reset failed.\n");
180 if ((state & STS_HALT) == 0) {
181 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
185 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
186 command = readl(&xhci->op_regs->command);
187 command |= CMD_RESET;
188 writel(command, &xhci->op_regs->command);
190 /* Existing Intel xHCI controllers require a delay of 1 mS,
191 * after setting the CMD_RESET bit, and before accessing any
192 * HC registers. This allows the HC to complete the
193 * reset operation and be ready for HC register access.
194 * Without this delay, the subsequent HC register access,
195 * may result in a system hang very rarely.
197 if (xhci->quirks & XHCI_INTEL_HOST)
200 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
213 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
215 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
216 xhci->usb2_rhub.bus_state.suspended_ports = 0;
217 xhci->usb2_rhub.bus_state.resuming_ports = 0;
218 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb3_rhub.bus_state.suspended_ports = 0;
220 xhci->usb3_rhub.bus_state.resuming_ports = 0;
225 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
227 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
270 ARRAY_SIZE(xhci->run_regs->ir_set));
272 for (i = 0; i < intrs; i++) {
273 struct xhci_intr_reg __iomem *ir;
275 ir = &xhci->run_regs->ir_set[i];
276 val = xhci_read_64(xhci, &ir->erst_base);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_base);
279 val= xhci_read_64(xhci, &ir->erst_dequeue);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_dequeue);
284 /* Wait for the fault to appear. It will be cleared on reset */
285 err = xhci_handshake(&xhci->op_regs->status,
286 STS_FATAL, STS_FATAL,
289 xhci_info(xhci, "Fault detected\n");
292 #ifdef CONFIG_USB_PCI
296 static int xhci_setup_msi(struct xhci_hcd *xhci)
300 * TODO:Check with MSI Soc for sysdev
302 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
304 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
306 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
307 "failed to allocate MSI entry");
311 ret = request_irq(pdev->irq, xhci_msi_irq,
312 0, "xhci_hcd", xhci_to_hcd(xhci));
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "disable MSI interrupt");
316 pci_free_irq_vectors(pdev);
325 static int xhci_setup_msix(struct xhci_hcd *xhci)
328 struct usb_hcd *hcd = xhci_to_hcd(xhci);
329 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
332 * calculate number of msi-x vectors supported.
333 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
334 * with max number of interrupters based on the xhci HCSPARAMS1.
335 * - num_online_cpus: maximum msi-x vectors per CPUs core.
336 * Add additional 1 vector to ensure always available interrupt.
338 xhci->msix_count = min(num_online_cpus() + 1,
339 HCS_MAX_INTRS(xhci->hcs_params1));
341 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
344 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
345 "Failed to enable MSI-X");
349 for (i = 0; i < xhci->msix_count; i++) {
350 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
351 "xhci_hcd", xhci_to_hcd(xhci));
356 hcd->msix_enabled = 1;
360 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
362 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
363 pci_free_irq_vectors(pdev);
367 /* Free any IRQs and disable MSI-X */
368 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
370 struct usb_hcd *hcd = xhci_to_hcd(xhci);
371 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
373 if (xhci->quirks & XHCI_PLAT)
376 /* return if using legacy interrupt */
380 if (hcd->msix_enabled) {
383 for (i = 0; i < xhci->msix_count; i++)
384 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
386 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
389 pci_free_irq_vectors(pdev);
390 hcd->msix_enabled = 0;
393 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
395 struct usb_hcd *hcd = xhci_to_hcd(xhci);
397 if (hcd->msix_enabled) {
398 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
401 for (i = 0; i < xhci->msix_count; i++)
402 synchronize_irq(pci_irq_vector(pdev, i));
406 static int xhci_try_enable_msi(struct usb_hcd *hcd)
408 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
409 struct pci_dev *pdev;
412 /* The xhci platform device has set up IRQs through usb_add_hcd. */
413 if (xhci->quirks & XHCI_PLAT)
416 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
418 * Some Fresco Logic host controllers advertise MSI, but fail to
419 * generate interrupts. Don't even try to enable MSI.
421 if (xhci->quirks & XHCI_BROKEN_MSI)
424 /* unregister the legacy interrupt */
426 free_irq(hcd->irq, hcd);
429 ret = xhci_setup_msix(xhci);
431 /* fall back to msi*/
432 ret = xhci_setup_msi(xhci);
435 hcd->msi_enabled = 1;
440 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
445 if (!strlen(hcd->irq_descr))
446 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
447 hcd->driver->description, hcd->self.busnum);
449 /* fall back to legacy interrupt*/
450 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
451 hcd->irq_descr, hcd);
453 xhci_err(xhci, "request interrupt %d failed\n",
457 hcd->irq = pdev->irq;
463 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
468 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
472 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
478 static void compliance_mode_recovery(struct timer_list *t)
480 struct xhci_hcd *xhci;
482 struct xhci_hub *rhub;
486 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
487 rhub = &xhci->usb3_rhub;
489 for (i = 0; i < rhub->num_ports; i++) {
490 temp = readl(rhub->ports[i]->addr);
491 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
493 * Compliance Mode Detected. Letting USB Core
494 * handle the Warm Reset
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode detected->port %d",
499 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
500 "Attempting compliance mode recovery");
501 hcd = xhci->shared_hcd;
503 if (hcd->state == HC_STATE_SUSPENDED)
504 usb_hcd_resume_root_hub(hcd);
506 usb_hcd_poll_rh_status(hcd);
510 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
511 mod_timer(&xhci->comp_mode_recovery_timer,
512 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
516 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
517 * that causes ports behind that hardware to enter compliance mode sometimes.
518 * The quirk creates a timer that polls every 2 seconds the link state of
519 * each host controller's port and recovers it by issuing a Warm reset
520 * if Compliance mode is detected, otherwise the port will become "dead" (no
521 * device connections or disconnections will be detected anymore). Becasue no
522 * status event is generated when entering compliance mode (per xhci spec),
523 * this quirk is needed on systems that have the failing hardware installed.
525 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
527 xhci->port_status_u0 = 0;
528 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
530 xhci->comp_mode_recovery_timer.expires = jiffies +
531 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
533 add_timer(&xhci->comp_mode_recovery_timer);
534 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
535 "Compliance mode recovery timer initialized");
539 * This function identifies the systems that have installed the SN65LVPE502CP
540 * USB3.0 re-driver and that need the Compliance Mode Quirk.
542 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
544 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
546 const char *dmi_product_name, *dmi_sys_vendor;
548 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
549 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
550 if (!dmi_product_name || !dmi_sys_vendor)
553 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
556 if (strstr(dmi_product_name, "Z420") ||
557 strstr(dmi_product_name, "Z620") ||
558 strstr(dmi_product_name, "Z820") ||
559 strstr(dmi_product_name, "Z1 Workstation"))
565 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
567 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
572 * Initialize memory for HCD and xHC (one-time init).
574 * Program the PAGESIZE register, initialize the device context array, create
575 * device contexts (?), set up a command ring segment (or two?), create event
576 * ring (one for now).
578 static int xhci_init(struct usb_hcd *hcd)
580 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
583 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
584 spin_lock_init(&xhci->lock);
585 if (xhci->hci_version == 0x95 && link_quirk) {
586 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
587 "QUIRK: Not clearing Link TRB chain bits.");
588 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
590 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
591 "xHCI doesn't need link TRB QUIRK");
593 retval = xhci_mem_init(xhci, GFP_KERNEL);
594 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
596 /* Initializing Compliance Mode Recovery Data If Needed */
597 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
598 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
599 compliance_mode_recovery_timer_init(xhci);
605 /*-------------------------------------------------------------------------*/
608 static int xhci_run_finished(struct xhci_hcd *xhci)
610 if (xhci_start(xhci)) {
614 xhci->shared_hcd->state = HC_STATE_RUNNING;
615 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
617 if (xhci->quirks & XHCI_NEC_HOST)
618 xhci_ring_cmd_db(xhci);
620 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
621 "Finished xhci_run for USB3 roothub");
626 * Start the HC after it was halted.
628 * This function is called by the USB core when the HC driver is added.
629 * Its opposite is xhci_stop().
631 * xhci_init() must be called once before this function can be called.
632 * Reset the HC, enable device slot contexts, program DCBAAP, and
633 * set command ring pointer and event ring pointer.
635 * Setup MSI-X vectors and enable interrupts.
637 int xhci_run(struct usb_hcd *hcd)
642 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
644 /* Start the xHCI host controller running only after the USB 2.0 roothub
648 hcd->uses_new_polling = 1;
649 if (!usb_hcd_is_primary_hcd(hcd))
650 return xhci_run_finished(xhci);
652 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
654 ret = xhci_try_enable_msi(hcd);
658 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
659 temp_64 &= ~ERST_PTR_MASK;
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
663 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
664 "// Set the interrupt modulation register");
665 temp = readl(&xhci->ir_set->irq_control);
666 temp &= ~ER_IRQ_INTERVAL_MASK;
667 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
668 writel(temp, &xhci->ir_set->irq_control);
670 /* Set the HCD state before we enable the irqs */
671 temp = readl(&xhci->op_regs->command);
673 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
674 "// Enable interrupts, cmd = 0x%x.", temp);
675 writel(temp, &xhci->op_regs->command);
677 temp = readl(&xhci->ir_set->irq_pending);
678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
679 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
680 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
681 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
683 if (xhci->quirks & XHCI_NEC_HOST) {
684 struct xhci_command *command;
686 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
690 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
691 TRB_TYPE(TRB_NEC_GET_FW));
693 xhci_free_command(xhci, command);
695 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
696 "Finished xhci_run for USB2 roothub");
698 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
700 xhci_create_dbc_dev(xhci);
702 xhci_debugfs_init(xhci);
706 EXPORT_SYMBOL_GPL(xhci_run);
711 * This function is called by the USB core when the HC driver is removed.
712 * Its opposite is xhci_run().
714 * Disable device contexts, disable IRQs, and quiesce the HC.
715 * Reset the HC, finish any completed transactions, and cleanup memory.
717 static void xhci_stop(struct usb_hcd *hcd)
720 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
722 mutex_lock(&xhci->mutex);
724 /* Only halt host and free memory after both hcds are removed */
725 if (!usb_hcd_is_primary_hcd(hcd)) {
726 mutex_unlock(&xhci->mutex);
730 xhci_remove_dbc_dev(xhci);
732 spin_lock_irq(&xhci->lock);
733 xhci->xhc_state |= XHCI_STATE_HALTED;
734 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
736 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
737 spin_unlock_irq(&xhci->lock);
739 xhci_cleanup_msix(xhci);
741 /* Deleting Compliance Mode Recovery Timer */
742 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
743 (!(xhci_all_ports_seen_u0(xhci)))) {
744 del_timer_sync(&xhci->comp_mode_recovery_timer);
745 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
746 "%s: compliance mode recovery timer deleted",
750 if (xhci->quirks & XHCI_AMD_PLL_FIX)
753 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
754 "// Disabling event ring interrupts");
755 temp = readl(&xhci->op_regs->status);
756 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
757 temp = readl(&xhci->ir_set->irq_pending);
758 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
761 xhci_mem_cleanup(xhci);
762 xhci_debugfs_exit(xhci);
763 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
764 "xhci_stop completed - status = %x",
765 readl(&xhci->op_regs->status));
766 mutex_unlock(&xhci->mutex);
770 * Shutdown HC (not bus-specific)
772 * This is called when the machine is rebooting or halting. We assume that the
773 * machine will be powered off, and the HC's internal state will be reset.
774 * Don't bother to free memory.
776 * This will only ever be called with the main usb_hcd (the USB3 roothub).
778 void xhci_shutdown(struct usb_hcd *hcd)
780 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
782 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
783 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
785 /* Don't poll the roothubs after shutdown. */
786 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
787 __func__, hcd->self.busnum);
788 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
789 del_timer_sync(&hcd->rh_timer);
791 if (xhci->shared_hcd) {
792 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
793 del_timer_sync(&xhci->shared_hcd->rh_timer);
796 spin_lock_irq(&xhci->lock);
800 * Workaround for spurious wakeps at shutdown with HSW, and for boot
801 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
803 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
804 xhci->quirks & XHCI_RESET_TO_DEFAULT)
805 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
807 spin_unlock_irq(&xhci->lock);
809 xhci_cleanup_msix(xhci);
811 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
812 "xhci_shutdown completed - status = %x",
813 readl(&xhci->op_regs->status));
815 EXPORT_SYMBOL_GPL(xhci_shutdown);
818 static void xhci_save_registers(struct xhci_hcd *xhci)
820 xhci->s3.command = readl(&xhci->op_regs->command);
821 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
822 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
823 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
824 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
825 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
826 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
827 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
828 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
831 static void xhci_restore_registers(struct xhci_hcd *xhci)
833 writel(xhci->s3.command, &xhci->op_regs->command);
834 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
835 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
836 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
837 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
838 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
839 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
840 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
841 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
844 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
848 /* step 2: initialize command ring buffer */
849 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
850 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
851 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
852 xhci->cmd_ring->dequeue) &
853 (u64) ~CMD_RING_RSVD_BITS) |
854 xhci->cmd_ring->cycle_state;
855 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
856 "// Setting command ring address to 0x%llx",
857 (long unsigned long) val_64);
858 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
862 * The whole command ring must be cleared to zero when we suspend the host.
864 * The host doesn't save the command ring pointer in the suspend well, so we
865 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
866 * aligned, because of the reserved bits in the command ring dequeue pointer
867 * register. Therefore, we can't just set the dequeue pointer back in the
868 * middle of the ring (TRBs are 16-byte aligned).
870 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
872 struct xhci_ring *ring;
873 struct xhci_segment *seg;
875 ring = xhci->cmd_ring;
879 sizeof(union xhci_trb) * (ring->trbs_per_seg - 1));
880 seg->trbs[ring->trbs_per_seg - 1].link.control &=
881 cpu_to_le32(~TRB_CYCLE);
883 } while (seg != ring->deq_seg);
885 /* Reset the software enqueue and dequeue pointers */
886 ring->deq_seg = ring->first_seg;
887 ring->dequeue = ring->first_seg->trbs;
888 ring->enq_seg = ring->deq_seg;
889 ring->enqueue = ring->dequeue;
891 ring->num_trbs_free = ring->num_segs * (ring->trbs_per_seg - 1) - 1;
893 * Ring is now zeroed, so the HW should look for change of ownership
894 * when the cycle bit is set to 1.
896 ring->cycle_state = 1;
899 * Reset the hardware dequeue pointer.
900 * Yes, this will need to be re-written after resume, but we're paranoid
901 * and want to make sure the hardware doesn't access bogus memory
902 * because, say, the BIOS or an SMI started the host without changing
903 * the command ring pointers.
905 xhci_set_cmd_ring_deq(xhci);
909 * Disable port wake bits if do_wakeup is not set.
911 * Also clear a possible internal port wake state left hanging for ports that
912 * detected termination but never successfully enumerated (trained to 0U).
913 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
914 * at enumeration clears this wake, force one here as well for unconnected ports
917 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
918 struct xhci_hub *rhub,
925 spin_lock_irqsave(&xhci->lock, flags);
927 for (i = 0; i < rhub->num_ports; i++) {
928 portsc = readl(rhub->ports[i]->addr);
929 t1 = xhci_port_state_to_neutral(portsc);
932 /* clear wake bits if do_wake is not set */
934 t2 &= ~PORT_WAKE_BITS;
936 /* Don't touch csc bit if connected or connect change is set */
937 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
941 writel(t2, rhub->ports[i]->addr);
942 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
943 rhub->hcd->self.busnum, i + 1, portsc, t2);
946 spin_unlock_irqrestore(&xhci->lock, flags);
949 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
951 struct xhci_port **ports;
956 status = readl(&xhci->op_regs->status);
957 if (status & STS_EINT)
960 * Checking STS_EINT is not enough as there is a lag between a change
961 * bit being set and the Port Status Change Event that it generated
962 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
965 port_index = xhci->usb2_rhub.num_ports;
966 ports = xhci->usb2_rhub.ports;
967 while (port_index--) {
968 portsc = readl(ports[port_index]->addr);
969 if (portsc & PORT_CHANGE_MASK ||
970 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
973 port_index = xhci->usb3_rhub.num_ports;
974 ports = xhci->usb3_rhub.ports;
975 while (port_index--) {
976 portsc = readl(ports[port_index]->addr);
977 if (portsc & PORT_CHANGE_MASK ||
978 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
985 * Stop HC (not bus-specific)
987 * This is called when the machine transition into S3/S4 mode.
990 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
993 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
994 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1001 if (hcd->state != HC_STATE_SUSPENDED ||
1002 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
1005 /* Clear root port wake on bits if wakeup not allowed. */
1006 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1007 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1009 if (!HCD_HW_ACCESSIBLE(hcd))
1012 xhci_dbc_suspend(xhci);
1014 /* Don't poll the roothubs on bus suspend. */
1015 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1016 __func__, hcd->self.busnum);
1017 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1018 del_timer_sync(&hcd->rh_timer);
1019 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1020 del_timer_sync(&xhci->shared_hcd->rh_timer);
1022 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1023 usleep_range(1000, 1500);
1025 spin_lock_irq(&xhci->lock);
1026 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1027 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1028 /* step 1: stop endpoint */
1029 /* skipped assuming that port suspend has done */
1031 /* step 2: clear Run/Stop bit */
1032 command = readl(&xhci->op_regs->command);
1033 command &= ~CMD_RUN;
1034 writel(command, &xhci->op_regs->command);
1036 /* Some chips from Fresco Logic need an extraordinary delay */
1037 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1039 if (xhci_handshake(&xhci->op_regs->status,
1040 STS_HALT, STS_HALT, delay)) {
1041 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1042 spin_unlock_irq(&xhci->lock);
1045 xhci_clear_command_ring(xhci);
1047 /* step 3: save registers */
1048 xhci_save_registers(xhci);
1050 /* step 4: set CSS flag */
1051 command = readl(&xhci->op_regs->command);
1053 writel(command, &xhci->op_regs->command);
1054 xhci->broken_suspend = 0;
1055 if (xhci_handshake(&xhci->op_regs->status,
1056 STS_SAVE, 0, 20 * 1000)) {
1058 * AMD SNPS xHC 3.0 occasionally does not clear the
1059 * SSS bit of USBSTS and when driver tries to poll
1060 * to see if the xHC clears BIT(8) which never happens
1061 * and driver assumes that controller is not responding
1062 * and times out. To workaround this, its good to check
1063 * if SRE and HCE bits are not set (as per xhci
1064 * Section 5.4.2) and bypass the timeout.
1066 res = readl(&xhci->op_regs->status);
1067 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1068 (((res & STS_SRE) == 0) &&
1069 ((res & STS_HCE) == 0))) {
1070 xhci->broken_suspend = 1;
1072 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1073 spin_unlock_irq(&xhci->lock);
1077 spin_unlock_irq(&xhci->lock);
1080 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1081 * is about to be suspended.
1083 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1084 (!(xhci_all_ports_seen_u0(xhci)))) {
1085 del_timer_sync(&xhci->comp_mode_recovery_timer);
1086 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1087 "%s: compliance mode recovery timer deleted",
1091 /* step 5: remove core well power */
1092 /* synchronize irq when using MSI-X */
1093 xhci_msix_sync_irqs(xhci);
1097 EXPORT_SYMBOL_GPL(xhci_suspend);
1100 * start xHC (not bus-specific)
1102 * This is called when the machine transition from S3/S4 mode.
1105 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1107 u32 command, temp = 0;
1108 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1109 struct usb_hcd *secondary_hcd;
1111 bool comp_timer_running = false;
1112 bool pending_portevent = false;
1113 bool reinit_xhc = false;
1118 /* Wait a bit if either of the roothubs need to settle from the
1119 * transition into bus suspend.
1122 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1123 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1126 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1127 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1129 spin_lock_irq(&xhci->lock);
1131 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1136 * Some controllers might lose power during suspend, so wait
1137 * for controller not ready bit to clear, just as in xHC init.
1139 retval = xhci_handshake(&xhci->op_regs->status,
1140 STS_CNR, 0, 10 * 1000 * 1000);
1142 xhci_warn(xhci, "Controller not ready at resume %d\n",
1144 spin_unlock_irq(&xhci->lock);
1147 /* step 1: restore register */
1148 xhci_restore_registers(xhci);
1149 /* step 2: initialize command ring buffer */
1150 xhci_set_cmd_ring_deq(xhci);
1151 /* step 3: restore state and start state*/
1152 /* step 3: set CRS flag */
1153 command = readl(&xhci->op_regs->command);
1155 writel(command, &xhci->op_regs->command);
1157 * Some controllers take up to 55+ ms to complete the controller
1158 * restore so setting the timeout to 100ms. Xhci specification
1159 * doesn't mention any timeout value.
1161 if (xhci_handshake(&xhci->op_regs->status,
1162 STS_RESTORE, 0, 100 * 1000)) {
1163 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1164 spin_unlock_irq(&xhci->lock);
1169 temp = readl(&xhci->op_regs->status);
1171 /* re-initialize the HC on Restore Error, or Host Controller Error */
1172 if (temp & (STS_SRE | STS_HCE)) {
1174 if (!xhci->broken_suspend)
1175 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1179 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1180 !(xhci_all_ports_seen_u0(xhci))) {
1181 del_timer_sync(&xhci->comp_mode_recovery_timer);
1182 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1183 "Compliance Mode Recovery Timer deleted!");
1186 /* Let the USB core know _both_ roothubs lost power. */
1187 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1188 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1190 xhci_dbg(xhci, "Stop HCD\n");
1192 xhci_zero_64b_regs(xhci);
1193 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1194 spin_unlock_irq(&xhci->lock);
1197 xhci_cleanup_msix(xhci);
1199 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1200 temp = readl(&xhci->op_regs->status);
1201 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1202 temp = readl(&xhci->ir_set->irq_pending);
1203 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1205 xhci_dbg(xhci, "cleaning up memory\n");
1206 xhci_mem_cleanup(xhci);
1207 xhci_debugfs_exit(xhci);
1208 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1209 readl(&xhci->op_regs->status));
1211 /* USB core calls the PCI reinit and start functions twice:
1212 * first with the primary HCD, and then with the secondary HCD.
1213 * If we don't do the same, the host will never be started.
1215 if (!usb_hcd_is_primary_hcd(hcd))
1216 secondary_hcd = hcd;
1218 secondary_hcd = xhci->shared_hcd;
1220 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1221 retval = xhci_init(hcd->primary_hcd);
1224 comp_timer_running = true;
1226 xhci_dbg(xhci, "Start the primary HCD\n");
1227 retval = xhci_run(hcd->primary_hcd);
1229 xhci_dbg(xhci, "Start the secondary HCD\n");
1230 retval = xhci_run(secondary_hcd);
1232 hcd->state = HC_STATE_SUSPENDED;
1233 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1237 /* step 4: set Run/Stop bit */
1238 command = readl(&xhci->op_regs->command);
1240 writel(command, &xhci->op_regs->command);
1241 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1244 /* step 5: walk topology and initialize portsc,
1245 * portpmsc and portli
1247 /* this is done in bus_resume */
1249 /* step 6: restart each of the previously
1250 * Running endpoints by ringing their doorbells
1253 spin_unlock_irq(&xhci->lock);
1255 xhci_dbc_resume(xhci);
1260 * Resume roothubs only if there are pending events.
1261 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1262 * the first wake signalling failed, give it that chance.
1264 pending_portevent = xhci_pending_portevent(xhci);
1265 if (!pending_portevent) {
1267 pending_portevent = xhci_pending_portevent(xhci);
1270 if (pending_portevent) {
1271 usb_hcd_resume_root_hub(xhci->shared_hcd);
1272 usb_hcd_resume_root_hub(hcd);
1276 * If system is subject to the Quirk, Compliance Mode Timer needs to
1277 * be re-initialized Always after a system resume. Ports are subject
1278 * to suffer the Compliance Mode issue again. It doesn't matter if
1279 * ports have entered previously to U0 before system's suspension.
1281 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1282 compliance_mode_recovery_timer_init(xhci);
1284 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1285 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1287 /* Re-enable port polling. */
1288 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1289 __func__, hcd->self.busnum);
1290 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1291 usb_hcd_poll_rh_status(xhci->shared_hcd);
1292 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1293 usb_hcd_poll_rh_status(hcd);
1297 EXPORT_SYMBOL_GPL(xhci_resume);
1298 #endif /* CONFIG_PM */
1300 /*-------------------------------------------------------------------------*/
1302 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1306 unsigned int buf_len;
1307 enum dma_data_direction dir;
1309 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1310 buf_len = urb->transfer_buffer_length;
1312 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1313 dev_to_node(hcd->self.sysdev));
1315 if (usb_urb_dir_out(urb))
1316 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1319 urb->transfer_buffer = temp;
1320 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1321 urb->transfer_buffer,
1322 urb->transfer_buffer_length,
1325 if (dma_mapping_error(hcd->self.sysdev,
1326 urb->transfer_dma)) {
1330 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1336 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1341 unsigned int len = 0;
1342 unsigned int trb_size;
1343 unsigned int max_pkt;
1344 struct scatterlist *sg;
1345 struct scatterlist *tail_sg;
1348 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1353 if (urb->dev->speed >= USB_SPEED_SUPER)
1354 trb_size = TRB_CACHE_SIZE_SS;
1356 trb_size = TRB_CACHE_SIZE_HS;
1358 if (urb->transfer_buffer_length != 0 &&
1359 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1360 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1361 len = len + sg->length;
1362 if (i > trb_size - 2) {
1363 len = len - tail_sg->length;
1364 if (len < max_pkt) {
1369 tail_sg = sg_next(tail_sg);
1376 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1379 unsigned int buf_len;
1380 enum dma_data_direction dir;
1382 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1384 buf_len = urb->transfer_buffer_length;
1386 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1387 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1388 dma_unmap_single(hcd->self.sysdev,
1390 urb->transfer_buffer_length,
1393 if (usb_urb_dir_in(urb)) {
1394 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1395 urb->transfer_buffer,
1398 if (len != buf_len) {
1399 xhci_dbg(hcd_to_xhci(hcd),
1400 "Copy from tmp buf to urb sg list failed\n");
1401 urb->actual_length = len;
1404 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1405 kfree(urb->transfer_buffer);
1406 urb->transfer_buffer = NULL;
1410 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1411 * we'll copy the actual data into the TRB address register. This is limited to
1412 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1413 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1415 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1418 struct xhci_hcd *xhci;
1420 xhci = hcd_to_xhci(hcd);
1422 if (xhci_urb_suitable_for_idt(urb))
1425 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1426 if (xhci_urb_temp_buffer_required(hcd, urb))
1427 return xhci_map_temp_buffer(hcd, urb);
1429 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1432 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1434 struct xhci_hcd *xhci;
1435 bool unmap_temp_buf = false;
1437 xhci = hcd_to_xhci(hcd);
1439 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1440 unmap_temp_buf = true;
1442 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1443 xhci_unmap_temp_buf(hcd, urb);
1445 usb_hcd_unmap_urb_for_dma(hcd, urb);
1449 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1450 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1451 * value to right shift 1 for the bitmask.
1453 * Index = (epnum * 2) + direction - 1,
1454 * where direction = 0 for OUT, 1 for IN.
1455 * For control endpoints, the IN index is used (OUT index is unused), so
1456 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1458 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1461 if (usb_endpoint_xfer_control(desc))
1462 index = (unsigned int) (usb_endpoint_num(desc)*2);
1464 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1465 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1468 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1470 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1471 * address from the XHCI endpoint index.
1473 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1475 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1476 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1477 return direction | number;
1480 /* Find the flag for this endpoint (for use in the control context). Use the
1481 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1484 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1486 return 1 << (xhci_get_endpoint_index(desc) + 1);
1489 /* Compute the last valid endpoint context index. Basically, this is the
1490 * endpoint index plus one. For slot contexts with more than valid endpoint,
1491 * we find the most significant bit set in the added contexts flags.
1492 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1493 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1495 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1497 return fls(added_ctxs) - 1;
1500 /* Returns 1 if the arguments are OK;
1501 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1503 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1504 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1506 struct xhci_hcd *xhci;
1507 struct xhci_virt_device *virt_dev;
1509 if (!hcd || (check_ep && !ep) || !udev) {
1510 pr_debug("xHCI %s called with invalid args\n", func);
1513 if (!udev->parent) {
1514 pr_debug("xHCI %s called for root hub\n", func);
1518 xhci = hcd_to_xhci(hcd);
1519 if (check_virt_dev) {
1520 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1521 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1526 virt_dev = xhci->devs[udev->slot_id];
1527 if (virt_dev->udev != udev) {
1528 xhci_dbg(xhci, "xHCI %s called with udev and "
1529 "virt_dev does not match\n", func);
1534 if (xhci->xhc_state & XHCI_STATE_HALTED)
1540 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1541 struct usb_device *udev, struct xhci_command *command,
1542 bool ctx_change, bool must_succeed);
1545 * Full speed devices may have a max packet size greater than 8 bytes, but the
1546 * USB core doesn't know that until it reads the first 8 bytes of the
1547 * descriptor. If the usb_device's max packet size changes after that point,
1548 * we need to issue an evaluate context command and wait on it.
1550 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1551 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1553 struct xhci_container_ctx *out_ctx;
1554 struct xhci_input_control_ctx *ctrl_ctx;
1555 struct xhci_ep_ctx *ep_ctx;
1556 struct xhci_command *command;
1557 int max_packet_size;
1558 int hw_max_packet_size;
1561 out_ctx = xhci->devs[slot_id]->out_ctx;
1562 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1563 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1564 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1565 if (hw_max_packet_size != max_packet_size) {
1566 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1567 "Max Packet Size for ep 0 changed.");
1568 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1569 "Max packet size in usb_device = %d",
1571 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1572 "Max packet size in xHCI HW = %d",
1573 hw_max_packet_size);
1574 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1575 "Issuing evaluate context command.");
1577 /* Set up the input context flags for the command */
1578 /* FIXME: This won't work if a non-default control endpoint
1579 * changes max packet sizes.
1582 command = xhci_alloc_command(xhci, true, mem_flags);
1586 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1587 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1589 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1592 goto command_cleanup;
1594 /* Set up the modified control endpoint 0 */
1595 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1596 xhci->devs[slot_id]->out_ctx, ep_index);
1598 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1599 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1600 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1601 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1603 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1604 ctrl_ctx->drop_flags = 0;
1606 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1609 /* Clean up the input context for later use by bandwidth
1612 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1614 kfree(command->completion);
1621 * RPI: Fixup endpoint intervals when requested
1622 * - Check interval versus the (cached) endpoint context
1623 * - set the endpoint interval to the new value
1624 * - force an endpoint configure command
1625 * XXX: bandwidth is not recalculated. We should probably do that.
1628 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1630 return 1 << (ep_index + 1);
1633 static void xhci_fixup_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1634 struct usb_host_endpoint *ep, int interval)
1636 struct xhci_hcd *xhci;
1637 struct xhci_ep_ctx *ep_ctx_out, *ep_ctx_in;
1638 struct xhci_command *command;
1639 struct xhci_input_control_ctx *ctrl_ctx;
1640 struct xhci_virt_device *vdev;
1644 unsigned long flags;
1647 xhci = hcd_to_xhci(hcd);
1648 ep_index = xhci_get_endpoint_index(&ep->desc);
1650 /* FS/LS interval translations */
1651 if ((udev->speed == USB_SPEED_FULL ||
1652 udev->speed == USB_SPEED_LOW))
1655 mutex_lock(&xhci->mutex);
1657 spin_lock_irqsave(&xhci->lock, flags);
1659 vdev = xhci->devs[udev->slot_id];
1660 /* Get context-derived endpoint interval */
1661 ep_ctx_out = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1662 ep_ctx_in = xhci_get_ep_ctx(xhci, vdev->in_ctx, ep_index);
1663 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx_out->ep_info));
1665 if (interval == xhci_interval) {
1666 spin_unlock_irqrestore(&xhci->lock, flags);
1667 mutex_unlock(&xhci->mutex);
1671 xhci_dbg(xhci, "Fixup interval=%d xhci_interval=%d\n",
1672 interval, xhci_interval);
1673 command = xhci_alloc_command_with_ctx(xhci, true, GFP_ATOMIC);
1675 /* Failure here is benign, poll at the original rate */
1676 spin_unlock_irqrestore(&xhci->lock, flags);
1677 mutex_unlock(&xhci->mutex);
1681 /* xHCI uses exponents for intervals... */
1682 xhci_interval = fls(interval) - 1;
1683 xhci_interval = clamp_val(xhci_interval, 3, 10);
1684 ep_info_tmp = le32_to_cpu(ep_ctx_out->ep_info);
1685 ep_info_tmp &= ~EP_INTERVAL(255);
1686 ep_info_tmp |= EP_INTERVAL(xhci_interval);
1688 /* Keep the endpoint context up-to-date while issuing the command. */
1689 xhci_endpoint_copy(xhci, vdev->in_ctx,
1690 vdev->out_ctx, ep_index);
1691 ep_ctx_in->ep_info = cpu_to_le32(ep_info_tmp);
1694 * We need to drop the lock, so take an explicit copy
1695 * of the ep context.
1697 xhci_endpoint_copy(xhci, command->in_ctx, vdev->in_ctx, ep_index);
1699 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1702 "%s: Could not get input context, bad type.\n",
1704 spin_unlock_irqrestore(&xhci->lock, flags);
1705 xhci_free_command(xhci, command);
1706 mutex_unlock(&xhci->mutex);
1709 ctrl_ctx->add_flags = xhci_get_endpoint_flag_from_index(ep_index);
1710 ctrl_ctx->drop_flags = 0;
1712 spin_unlock_irqrestore(&xhci->lock, flags);
1714 ret = xhci_configure_endpoint(xhci, udev, command,
1717 xhci_warn(xhci, "%s: Configure endpoint failed: %d\n",
1719 xhci_free_command(xhci, command);
1720 mutex_unlock(&xhci->mutex);
1724 * non-error returns are a promise to giveback() the urb later
1725 * we drop ownership so next owner (or urb unlink) can get it
1727 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1729 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1730 unsigned long flags;
1732 unsigned int slot_id, ep_index;
1733 unsigned int *ep_state;
1734 struct urb_priv *urb_priv;
1739 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1740 true, true, __func__);
1742 return ret ? ret : -EINVAL;
1744 slot_id = urb->dev->slot_id;
1745 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1746 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1748 if (!HCD_HW_ACCESSIBLE(hcd))
1751 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1752 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1756 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1757 num_tds = urb->number_of_packets;
1758 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1759 urb->transfer_buffer_length > 0 &&
1760 urb->transfer_flags & URB_ZERO_PACKET &&
1761 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1766 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1770 urb_priv->num_tds = num_tds;
1771 urb_priv->num_tds_done = 0;
1772 urb->hcpriv = urb_priv;
1774 trace_xhci_urb_enqueue(urb);
1776 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1777 /* Check to see if the max packet size for the default control
1778 * endpoint changed during FS device enumeration
1780 if (urb->dev->speed == USB_SPEED_FULL) {
1781 ret = xhci_check_maxpacket(xhci, slot_id,
1782 ep_index, urb, mem_flags);
1784 xhci_urb_free_priv(urb_priv);
1791 spin_lock_irqsave(&xhci->lock, flags);
1793 if (xhci->xhc_state & XHCI_STATE_DYING) {
1794 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1795 urb->ep->desc.bEndpointAddress, urb);
1799 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1800 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1805 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1806 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1811 switch (usb_endpoint_type(&urb->ep->desc)) {
1813 case USB_ENDPOINT_XFER_CONTROL:
1814 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1817 case USB_ENDPOINT_XFER_BULK:
1818 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1821 case USB_ENDPOINT_XFER_INT:
1822 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1825 case USB_ENDPOINT_XFER_ISOC:
1826 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1832 xhci_urb_free_priv(urb_priv);
1835 spin_unlock_irqrestore(&xhci->lock, flags);
1840 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1841 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1842 * should pick up where it left off in the TD, unless a Set Transfer Ring
1843 * Dequeue Pointer is issued.
1845 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1846 * the ring. Since the ring is a contiguous structure, they can't be physically
1847 * removed. Instead, there are two options:
1849 * 1) If the HC is in the middle of processing the URB to be canceled, we
1850 * simply move the ring's dequeue pointer past those TRBs using the Set
1851 * Transfer Ring Dequeue Pointer command. This will be the common case,
1852 * when drivers timeout on the last submitted URB and attempt to cancel.
1854 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1855 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1856 * HC will need to invalidate the any TRBs it has cached after the stop
1857 * endpoint command, as noted in the xHCI 0.95 errata.
1859 * 3) The TD may have completed by the time the Stop Endpoint Command
1860 * completes, so software needs to handle that case too.
1862 * This function should protect against the TD enqueueing code ringing the
1863 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1864 * It also needs to account for multiple cancellations on happening at the same
1865 * time for the same endpoint.
1867 * Note that this function can be called in any context, or so says
1868 * usb_hcd_unlink_urb()
1870 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1872 unsigned long flags;
1875 struct xhci_hcd *xhci;
1876 struct urb_priv *urb_priv;
1878 unsigned int ep_index;
1879 struct xhci_ring *ep_ring;
1880 struct xhci_virt_ep *ep;
1881 struct xhci_command *command;
1882 struct xhci_virt_device *vdev;
1884 xhci = hcd_to_xhci(hcd);
1885 spin_lock_irqsave(&xhci->lock, flags);
1887 trace_xhci_urb_dequeue(urb);
1889 /* Make sure the URB hasn't completed or been unlinked already */
1890 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1894 /* give back URB now if we can't queue it for cancel */
1895 vdev = xhci->devs[urb->dev->slot_id];
1896 urb_priv = urb->hcpriv;
1897 if (!vdev || !urb_priv)
1900 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1901 ep = &vdev->eps[ep_index];
1902 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1903 if (!ep || !ep_ring)
1906 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1907 temp = readl(&xhci->op_regs->status);
1908 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1914 * check ring is not re-allocated since URB was enqueued. If it is, then
1915 * make sure none of the ring related pointers in this URB private data
1916 * are touched, such as td_list, otherwise we overwrite freed data
1918 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1919 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1920 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1921 td = &urb_priv->td[i];
1922 if (!list_empty(&td->cancelled_td_list))
1923 list_del_init(&td->cancelled_td_list);
1928 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1929 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1930 "HC halted, freeing TD manually.");
1931 for (i = urb_priv->num_tds_done;
1932 i < urb_priv->num_tds;
1934 td = &urb_priv->td[i];
1935 if (!list_empty(&td->td_list))
1936 list_del_init(&td->td_list);
1937 if (!list_empty(&td->cancelled_td_list))
1938 list_del_init(&td->cancelled_td_list);
1943 i = urb_priv->num_tds_done;
1944 if (i < urb_priv->num_tds)
1945 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1946 "Cancel URB %p, dev %s, ep 0x%x, "
1947 "starting at offset 0x%llx",
1948 urb, urb->dev->devpath,
1949 urb->ep->desc.bEndpointAddress,
1950 (unsigned long long) xhci_trb_virt_to_dma(
1951 urb_priv->td[i].start_seg,
1952 urb_priv->td[i].first_trb));
1954 for (; i < urb_priv->num_tds; i++) {
1955 td = &urb_priv->td[i];
1956 /* TD can already be on cancelled list if ep halted on it */
1957 if (list_empty(&td->cancelled_td_list)) {
1958 td->cancel_status = TD_DIRTY;
1959 list_add_tail(&td->cancelled_td_list,
1960 &ep->cancelled_td_list);
1964 /* Queue a stop endpoint command, but only if this is
1965 * the first cancellation to be handled.
1967 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1968 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1973 ep->ep_state |= EP_STOP_CMD_PENDING;
1974 ep->stop_cmd_timer.expires = jiffies +
1975 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1976 add_timer(&ep->stop_cmd_timer);
1977 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1979 xhci_ring_cmd_db(xhci);
1982 spin_unlock_irqrestore(&xhci->lock, flags);
1987 xhci_urb_free_priv(urb_priv);
1988 usb_hcd_unlink_urb_from_ep(hcd, urb);
1989 spin_unlock_irqrestore(&xhci->lock, flags);
1990 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1994 /* Drop an endpoint from a new bandwidth configuration for this device.
1995 * Only one call to this function is allowed per endpoint before
1996 * check_bandwidth() or reset_bandwidth() must be called.
1997 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1998 * add the endpoint to the schedule with possibly new parameters denoted by a
1999 * different endpoint descriptor in usb_host_endpoint.
2000 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
2003 * The USB core will not allow URBs to be queued to an endpoint that is being
2004 * disabled, so there's no need for mutual exclusion to protect
2005 * the xhci->devs[slot_id] structure.
2007 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2008 struct usb_host_endpoint *ep)
2010 struct xhci_hcd *xhci;
2011 struct xhci_container_ctx *in_ctx, *out_ctx;
2012 struct xhci_input_control_ctx *ctrl_ctx;
2013 unsigned int ep_index;
2014 struct xhci_ep_ctx *ep_ctx;
2016 u32 new_add_flags, new_drop_flags;
2019 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2022 xhci = hcd_to_xhci(hcd);
2023 if (xhci->xhc_state & XHCI_STATE_DYING)
2026 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2027 drop_flag = xhci_get_endpoint_flag(&ep->desc);
2028 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
2029 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
2030 __func__, drop_flag);
2034 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
2035 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
2036 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2038 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2043 ep_index = xhci_get_endpoint_index(&ep->desc);
2044 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
2045 /* If the HC already knows the endpoint is disabled,
2046 * or the HCD has noted it is disabled, ignore this request
2048 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
2049 le32_to_cpu(ctrl_ctx->drop_flags) &
2050 xhci_get_endpoint_flag(&ep->desc)) {
2051 /* Do not warn when called after a usb_device_reset */
2052 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
2053 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
2058 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
2059 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2061 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
2062 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2064 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
2066 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
2068 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2069 (unsigned int) ep->desc.bEndpointAddress,
2071 (unsigned int) new_drop_flags,
2072 (unsigned int) new_add_flags);
2075 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
2077 /* Add an endpoint to a new possible bandwidth configuration for this device.
2078 * Only one call to this function is allowed per endpoint before
2079 * check_bandwidth() or reset_bandwidth() must be called.
2080 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
2081 * add the endpoint to the schedule with possibly new parameters denoted by a
2082 * different endpoint descriptor in usb_host_endpoint.
2083 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
2086 * The USB core will not allow URBs to be queued to an endpoint until the
2087 * configuration or alt setting is installed in the device, so there's no need
2088 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2090 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2091 struct usb_host_endpoint *ep)
2093 struct xhci_hcd *xhci;
2094 struct xhci_container_ctx *in_ctx;
2095 unsigned int ep_index;
2096 struct xhci_input_control_ctx *ctrl_ctx;
2097 struct xhci_ep_ctx *ep_ctx;
2099 u32 new_add_flags, new_drop_flags;
2100 struct xhci_virt_device *virt_dev;
2103 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2105 /* So we won't queue a reset ep command for a root hub */
2109 xhci = hcd_to_xhci(hcd);
2110 if (xhci->xhc_state & XHCI_STATE_DYING)
2113 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2114 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2115 /* FIXME when we have to issue an evaluate endpoint command to
2116 * deal with ep0 max packet size changing once we get the
2119 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2120 __func__, added_ctxs);
2124 virt_dev = xhci->devs[udev->slot_id];
2125 in_ctx = virt_dev->in_ctx;
2126 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2128 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2133 ep_index = xhci_get_endpoint_index(&ep->desc);
2134 /* If this endpoint is already in use, and the upper layers are trying
2135 * to add it again without dropping it, reject the addition.
2137 if (virt_dev->eps[ep_index].ring &&
2138 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2139 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2140 "without dropping it.\n",
2141 (unsigned int) ep->desc.bEndpointAddress);
2145 /* If the HCD has already noted the endpoint is enabled,
2146 * ignore this request.
2148 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2149 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2155 * Configuration and alternate setting changes must be done in
2156 * process context, not interrupt context (or so documenation
2157 * for usb_set_interface() and usb_set_configuration() claim).
2159 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2160 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2161 __func__, ep->desc.bEndpointAddress);
2165 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2166 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2168 /* If xhci_endpoint_disable() was called for this endpoint, but the
2169 * xHC hasn't been notified yet through the check_bandwidth() call,
2170 * this re-adds a new state for the endpoint from the new endpoint
2171 * descriptors. We must drop and re-add this endpoint, so we leave the
2174 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2176 /* Store the usb_device pointer for later use */
2179 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2180 trace_xhci_add_endpoint(ep_ctx);
2182 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2183 (unsigned int) ep->desc.bEndpointAddress,
2185 (unsigned int) new_drop_flags,
2186 (unsigned int) new_add_flags);
2189 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2191 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2193 struct xhci_input_control_ctx *ctrl_ctx;
2194 struct xhci_ep_ctx *ep_ctx;
2195 struct xhci_slot_ctx *slot_ctx;
2198 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2200 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2205 /* When a device's add flag and drop flag are zero, any subsequent
2206 * configure endpoint command will leave that endpoint's state
2207 * untouched. Make sure we don't leave any old state in the input
2208 * endpoint contexts.
2210 ctrl_ctx->drop_flags = 0;
2211 ctrl_ctx->add_flags = 0;
2212 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2213 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2214 /* Endpoint 0 is always valid */
2215 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2216 for (i = 1; i < 31; i++) {
2217 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2218 ep_ctx->ep_info = 0;
2219 ep_ctx->ep_info2 = 0;
2221 ep_ctx->tx_info = 0;
2225 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2226 struct usb_device *udev, u32 *cmd_status)
2230 switch (*cmd_status) {
2231 case COMP_COMMAND_ABORTED:
2232 case COMP_COMMAND_RING_STOPPED:
2233 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2236 case COMP_RESOURCE_ERROR:
2237 dev_warn(&udev->dev,
2238 "Not enough host controller resources for new device state.\n");
2240 /* FIXME: can we allocate more resources for the HC? */
2242 case COMP_BANDWIDTH_ERROR:
2243 case COMP_SECONDARY_BANDWIDTH_ERROR:
2244 dev_warn(&udev->dev,
2245 "Not enough bandwidth for new device state.\n");
2247 /* FIXME: can we go back to the old state? */
2249 case COMP_TRB_ERROR:
2250 /* the HCD set up something wrong */
2251 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2253 "and endpoint is not disabled.\n");
2256 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2257 dev_warn(&udev->dev,
2258 "ERROR: Incompatible device for endpoint configure command.\n");
2262 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2263 "Successful Endpoint Configure command");
2267 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2275 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2276 struct usb_device *udev, u32 *cmd_status)
2280 switch (*cmd_status) {
2281 case COMP_COMMAND_ABORTED:
2282 case COMP_COMMAND_RING_STOPPED:
2283 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2286 case COMP_PARAMETER_ERROR:
2287 dev_warn(&udev->dev,
2288 "WARN: xHCI driver setup invalid evaluate context command.\n");
2291 case COMP_SLOT_NOT_ENABLED_ERROR:
2292 dev_warn(&udev->dev,
2293 "WARN: slot not enabled for evaluate context command.\n");
2296 case COMP_CONTEXT_STATE_ERROR:
2297 dev_warn(&udev->dev,
2298 "WARN: invalid context state for evaluate context command.\n");
2301 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2302 dev_warn(&udev->dev,
2303 "ERROR: Incompatible device for evaluate context command.\n");
2306 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2307 /* Max Exit Latency too large error */
2308 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2312 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2313 "Successful evaluate context command");
2317 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2325 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2326 struct xhci_input_control_ctx *ctrl_ctx)
2328 u32 valid_add_flags;
2329 u32 valid_drop_flags;
2331 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2332 * (bit 1). The default control endpoint is added during the Address
2333 * Device command and is never removed until the slot is disabled.
2335 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2336 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2338 /* Use hweight32 to count the number of ones in the add flags, or
2339 * number of endpoints added. Don't count endpoints that are changed
2340 * (both added and dropped).
2342 return hweight32(valid_add_flags) -
2343 hweight32(valid_add_flags & valid_drop_flags);
2346 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2347 struct xhci_input_control_ctx *ctrl_ctx)
2349 u32 valid_add_flags;
2350 u32 valid_drop_flags;
2352 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2353 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2355 return hweight32(valid_drop_flags) -
2356 hweight32(valid_add_flags & valid_drop_flags);
2360 * We need to reserve the new number of endpoints before the configure endpoint
2361 * command completes. We can't subtract the dropped endpoints from the number
2362 * of active endpoints until the command completes because we can oversubscribe
2363 * the host in this case:
2365 * - the first configure endpoint command drops more endpoints than it adds
2366 * - a second configure endpoint command that adds more endpoints is queued
2367 * - the first configure endpoint command fails, so the config is unchanged
2368 * - the second command may succeed, even though there isn't enough resources
2370 * Must be called with xhci->lock held.
2372 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2373 struct xhci_input_control_ctx *ctrl_ctx)
2377 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2378 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2379 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2380 "Not enough ep ctxs: "
2381 "%u active, need to add %u, limit is %u.",
2382 xhci->num_active_eps, added_eps,
2383 xhci->limit_active_eps);
2386 xhci->num_active_eps += added_eps;
2387 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2388 "Adding %u ep ctxs, %u now active.", added_eps,
2389 xhci->num_active_eps);
2394 * The configure endpoint was failed by the xHC for some other reason, so we
2395 * need to revert the resources that failed configuration would have used.
2397 * Must be called with xhci->lock held.
2399 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2400 struct xhci_input_control_ctx *ctrl_ctx)
2404 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2405 xhci->num_active_eps -= num_failed_eps;
2406 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2407 "Removing %u failed ep ctxs, %u now active.",
2409 xhci->num_active_eps);
2413 * Now that the command has completed, clean up the active endpoint count by
2414 * subtracting out the endpoints that were dropped (but not changed).
2416 * Must be called with xhci->lock held.
2418 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2419 struct xhci_input_control_ctx *ctrl_ctx)
2421 u32 num_dropped_eps;
2423 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2424 xhci->num_active_eps -= num_dropped_eps;
2425 if (num_dropped_eps)
2426 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2427 "Removing %u dropped ep ctxs, %u now active.",
2429 xhci->num_active_eps);
2432 static unsigned int xhci_get_block_size(struct usb_device *udev)
2434 switch (udev->speed) {
2436 case USB_SPEED_FULL:
2438 case USB_SPEED_HIGH:
2440 case USB_SPEED_SUPER:
2441 case USB_SPEED_SUPER_PLUS:
2443 case USB_SPEED_UNKNOWN:
2444 case USB_SPEED_WIRELESS:
2446 /* Should never happen */
2452 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2454 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2456 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2461 /* If we are changing a LS/FS device under a HS hub,
2462 * make sure (if we are activating a new TT) that the HS bus has enough
2463 * bandwidth for this new TT.
2465 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2466 struct xhci_virt_device *virt_dev,
2469 struct xhci_interval_bw_table *bw_table;
2470 struct xhci_tt_bw_info *tt_info;
2472 /* Find the bandwidth table for the root port this TT is attached to. */
2473 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2474 tt_info = virt_dev->tt_info;
2475 /* If this TT already had active endpoints, the bandwidth for this TT
2476 * has already been added. Removing all periodic endpoints (and thus
2477 * making the TT enactive) will only decrease the bandwidth used.
2481 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2482 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2486 /* Not sure why we would have no new active endpoints...
2488 * Maybe because of an Evaluate Context change for a hub update or a
2489 * control endpoint 0 max packet size change?
2490 * FIXME: skip the bandwidth calculation in that case.
2495 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2496 struct xhci_virt_device *virt_dev)
2498 unsigned int bw_reserved;
2500 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2501 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2504 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2505 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2512 * This algorithm is a very conservative estimate of the worst-case scheduling
2513 * scenario for any one interval. The hardware dynamically schedules the
2514 * packets, so we can't tell which microframe could be the limiting factor in
2515 * the bandwidth scheduling. This only takes into account periodic endpoints.
2517 * Obviously, we can't solve an NP complete problem to find the minimum worst
2518 * case scenario. Instead, we come up with an estimate that is no less than
2519 * the worst case bandwidth used for any one microframe, but may be an
2522 * We walk the requirements for each endpoint by interval, starting with the
2523 * smallest interval, and place packets in the schedule where there is only one
2524 * possible way to schedule packets for that interval. In order to simplify
2525 * this algorithm, we record the largest max packet size for each interval, and
2526 * assume all packets will be that size.
2528 * For interval 0, we obviously must schedule all packets for each interval.
2529 * The bandwidth for interval 0 is just the amount of data to be transmitted
2530 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2531 * the number of packets).
2533 * For interval 1, we have two possible microframes to schedule those packets
2534 * in. For this algorithm, if we can schedule the same number of packets for
2535 * each possible scheduling opportunity (each microframe), we will do so. The
2536 * remaining number of packets will be saved to be transmitted in the gaps in
2537 * the next interval's scheduling sequence.
2539 * As we move those remaining packets to be scheduled with interval 2 packets,
2540 * we have to double the number of remaining packets to transmit. This is
2541 * because the intervals are actually powers of 2, and we would be transmitting
2542 * the previous interval's packets twice in this interval. We also have to be
2543 * sure that when we look at the largest max packet size for this interval, we
2544 * also look at the largest max packet size for the remaining packets and take
2545 * the greater of the two.
2547 * The algorithm continues to evenly distribute packets in each scheduling
2548 * opportunity, and push the remaining packets out, until we get to the last
2549 * interval. Then those packets and their associated overhead are just added
2550 * to the bandwidth used.
2552 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2553 struct xhci_virt_device *virt_dev,
2556 unsigned int bw_reserved;
2557 unsigned int max_bandwidth;
2558 unsigned int bw_used;
2559 unsigned int block_size;
2560 struct xhci_interval_bw_table *bw_table;
2561 unsigned int packet_size = 0;
2562 unsigned int overhead = 0;
2563 unsigned int packets_transmitted = 0;
2564 unsigned int packets_remaining = 0;
2567 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2568 return xhci_check_ss_bw(xhci, virt_dev);
2570 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2571 max_bandwidth = HS_BW_LIMIT;
2572 /* Convert percent of bus BW reserved to blocks reserved */
2573 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2575 max_bandwidth = FS_BW_LIMIT;
2576 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2579 bw_table = virt_dev->bw_table;
2580 /* We need to translate the max packet size and max ESIT payloads into
2581 * the units the hardware uses.
2583 block_size = xhci_get_block_size(virt_dev->udev);
2585 /* If we are manipulating a LS/FS device under a HS hub, double check
2586 * that the HS bus has enough bandwidth if we are activing a new TT.
2588 if (virt_dev->tt_info) {
2589 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2590 "Recalculating BW for rootport %u",
2591 virt_dev->real_port);
2592 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2593 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2594 "newly activated TT.\n");
2597 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2598 "Recalculating BW for TT slot %u port %u",
2599 virt_dev->tt_info->slot_id,
2600 virt_dev->tt_info->ttport);
2602 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2603 "Recalculating BW for rootport %u",
2604 virt_dev->real_port);
2607 /* Add in how much bandwidth will be used for interval zero, or the
2608 * rounded max ESIT payload + number of packets * largest overhead.
2610 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2611 bw_table->interval_bw[0].num_packets *
2612 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2614 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2615 unsigned int bw_added;
2616 unsigned int largest_mps;
2617 unsigned int interval_overhead;
2620 * How many packets could we transmit in this interval?
2621 * If packets didn't fit in the previous interval, we will need
2622 * to transmit that many packets twice within this interval.
2624 packets_remaining = 2 * packets_remaining +
2625 bw_table->interval_bw[i].num_packets;
2627 /* Find the largest max packet size of this or the previous
2630 if (list_empty(&bw_table->interval_bw[i].endpoints))
2633 struct xhci_virt_ep *virt_ep;
2634 struct list_head *ep_entry;
2636 ep_entry = bw_table->interval_bw[i].endpoints.next;
2637 virt_ep = list_entry(ep_entry,
2638 struct xhci_virt_ep, bw_endpoint_list);
2639 /* Convert to blocks, rounding up */
2640 largest_mps = DIV_ROUND_UP(
2641 virt_ep->bw_info.max_packet_size,
2644 if (largest_mps > packet_size)
2645 packet_size = largest_mps;
2647 /* Use the larger overhead of this or the previous interval. */
2648 interval_overhead = xhci_get_largest_overhead(
2649 &bw_table->interval_bw[i]);
2650 if (interval_overhead > overhead)
2651 overhead = interval_overhead;
2653 /* How many packets can we evenly distribute across
2654 * (1 << (i + 1)) possible scheduling opportunities?
2656 packets_transmitted = packets_remaining >> (i + 1);
2658 /* Add in the bandwidth used for those scheduled packets */
2659 bw_added = packets_transmitted * (overhead + packet_size);
2661 /* How many packets do we have remaining to transmit? */
2662 packets_remaining = packets_remaining % (1 << (i + 1));
2664 /* What largest max packet size should those packets have? */
2665 /* If we've transmitted all packets, don't carry over the
2666 * largest packet size.
2668 if (packets_remaining == 0) {
2671 } else if (packets_transmitted > 0) {
2672 /* Otherwise if we do have remaining packets, and we've
2673 * scheduled some packets in this interval, take the
2674 * largest max packet size from endpoints with this
2677 packet_size = largest_mps;
2678 overhead = interval_overhead;
2680 /* Otherwise carry over packet_size and overhead from the last
2681 * time we had a remainder.
2683 bw_used += bw_added;
2684 if (bw_used > max_bandwidth) {
2685 xhci_warn(xhci, "Not enough bandwidth. "
2686 "Proposed: %u, Max: %u\n",
2687 bw_used, max_bandwidth);
2692 * Ok, we know we have some packets left over after even-handedly
2693 * scheduling interval 15. We don't know which microframes they will
2694 * fit into, so we over-schedule and say they will be scheduled every
2697 if (packets_remaining > 0)
2698 bw_used += overhead + packet_size;
2700 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2701 unsigned int port_index = virt_dev->real_port - 1;
2703 /* OK, we're manipulating a HS device attached to a
2704 * root port bandwidth domain. Include the number of active TTs
2705 * in the bandwidth used.
2707 bw_used += TT_HS_OVERHEAD *
2708 xhci->rh_bw[port_index].num_active_tts;
2711 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2712 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2713 "Available: %u " "percent",
2714 bw_used, max_bandwidth, bw_reserved,
2715 (max_bandwidth - bw_used - bw_reserved) * 100 /
2718 bw_used += bw_reserved;
2719 if (bw_used > max_bandwidth) {
2720 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2721 bw_used, max_bandwidth);
2725 bw_table->bw_used = bw_used;
2729 static bool xhci_is_async_ep(unsigned int ep_type)
2731 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2732 ep_type != ISOC_IN_EP &&
2733 ep_type != INT_IN_EP);
2736 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2738 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2741 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2743 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2745 if (ep_bw->ep_interval == 0)
2746 return SS_OVERHEAD_BURST +
2747 (ep_bw->mult * ep_bw->num_packets *
2748 (SS_OVERHEAD + mps));
2749 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2750 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2751 1 << ep_bw->ep_interval);
2755 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2756 struct xhci_bw_info *ep_bw,
2757 struct xhci_interval_bw_table *bw_table,
2758 struct usb_device *udev,
2759 struct xhci_virt_ep *virt_ep,
2760 struct xhci_tt_bw_info *tt_info)
2762 struct xhci_interval_bw *interval_bw;
2763 int normalized_interval;
2765 if (xhci_is_async_ep(ep_bw->type))
2768 if (udev->speed >= USB_SPEED_SUPER) {
2769 if (xhci_is_sync_in_ep(ep_bw->type))
2770 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2771 xhci_get_ss_bw_consumed(ep_bw);
2773 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2774 xhci_get_ss_bw_consumed(ep_bw);
2778 /* SuperSpeed endpoints never get added to intervals in the table, so
2779 * this check is only valid for HS/FS/LS devices.
2781 if (list_empty(&virt_ep->bw_endpoint_list))
2783 /* For LS/FS devices, we need to translate the interval expressed in
2784 * microframes to frames.
2786 if (udev->speed == USB_SPEED_HIGH)
2787 normalized_interval = ep_bw->ep_interval;
2789 normalized_interval = ep_bw->ep_interval - 3;
2791 if (normalized_interval == 0)
2792 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2793 interval_bw = &bw_table->interval_bw[normalized_interval];
2794 interval_bw->num_packets -= ep_bw->num_packets;
2795 switch (udev->speed) {
2797 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2799 case USB_SPEED_FULL:
2800 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2802 case USB_SPEED_HIGH:
2803 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2805 case USB_SPEED_SUPER:
2806 case USB_SPEED_SUPER_PLUS:
2807 case USB_SPEED_UNKNOWN:
2808 case USB_SPEED_WIRELESS:
2809 /* Should never happen because only LS/FS/HS endpoints will get
2810 * added to the endpoint list.
2815 tt_info->active_eps -= 1;
2816 list_del_init(&virt_ep->bw_endpoint_list);
2819 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2820 struct xhci_bw_info *ep_bw,
2821 struct xhci_interval_bw_table *bw_table,
2822 struct usb_device *udev,
2823 struct xhci_virt_ep *virt_ep,
2824 struct xhci_tt_bw_info *tt_info)
2826 struct xhci_interval_bw *interval_bw;
2827 struct xhci_virt_ep *smaller_ep;
2828 int normalized_interval;
2830 if (xhci_is_async_ep(ep_bw->type))
2833 if (udev->speed == USB_SPEED_SUPER) {
2834 if (xhci_is_sync_in_ep(ep_bw->type))
2835 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2836 xhci_get_ss_bw_consumed(ep_bw);
2838 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2839 xhci_get_ss_bw_consumed(ep_bw);
2843 /* For LS/FS devices, we need to translate the interval expressed in
2844 * microframes to frames.
2846 if (udev->speed == USB_SPEED_HIGH)
2847 normalized_interval = ep_bw->ep_interval;
2849 normalized_interval = ep_bw->ep_interval - 3;
2851 if (normalized_interval == 0)
2852 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2853 interval_bw = &bw_table->interval_bw[normalized_interval];
2854 interval_bw->num_packets += ep_bw->num_packets;
2855 switch (udev->speed) {
2857 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2859 case USB_SPEED_FULL:
2860 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2862 case USB_SPEED_HIGH:
2863 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2865 case USB_SPEED_SUPER:
2866 case USB_SPEED_SUPER_PLUS:
2867 case USB_SPEED_UNKNOWN:
2868 case USB_SPEED_WIRELESS:
2869 /* Should never happen because only LS/FS/HS endpoints will get
2870 * added to the endpoint list.
2876 tt_info->active_eps += 1;
2877 /* Insert the endpoint into the list, largest max packet size first. */
2878 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2880 if (ep_bw->max_packet_size >=
2881 smaller_ep->bw_info.max_packet_size) {
2882 /* Add the new ep before the smaller endpoint */
2883 list_add_tail(&virt_ep->bw_endpoint_list,
2884 &smaller_ep->bw_endpoint_list);
2888 /* Add the new endpoint at the end of the list. */
2889 list_add_tail(&virt_ep->bw_endpoint_list,
2890 &interval_bw->endpoints);
2893 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2894 struct xhci_virt_device *virt_dev,
2897 struct xhci_root_port_bw_info *rh_bw_info;
2898 if (!virt_dev->tt_info)
2901 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2902 if (old_active_eps == 0 &&
2903 virt_dev->tt_info->active_eps != 0) {
2904 rh_bw_info->num_active_tts += 1;
2905 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2906 } else if (old_active_eps != 0 &&
2907 virt_dev->tt_info->active_eps == 0) {
2908 rh_bw_info->num_active_tts -= 1;
2909 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2913 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2914 struct xhci_virt_device *virt_dev,
2915 struct xhci_container_ctx *in_ctx)
2917 struct xhci_bw_info ep_bw_info[31];
2919 struct xhci_input_control_ctx *ctrl_ctx;
2920 int old_active_eps = 0;
2922 if (virt_dev->tt_info)
2923 old_active_eps = virt_dev->tt_info->active_eps;
2925 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2927 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2932 for (i = 0; i < 31; i++) {
2933 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2936 /* Make a copy of the BW info in case we need to revert this */
2937 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2938 sizeof(ep_bw_info[i]));
2939 /* Drop the endpoint from the interval table if the endpoint is
2940 * being dropped or changed.
2942 if (EP_IS_DROPPED(ctrl_ctx, i))
2943 xhci_drop_ep_from_interval_table(xhci,
2944 &virt_dev->eps[i].bw_info,
2950 /* Overwrite the information stored in the endpoints' bw_info */
2951 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2952 for (i = 0; i < 31; i++) {
2953 /* Add any changed or added endpoints to the interval table */
2954 if (EP_IS_ADDED(ctrl_ctx, i))
2955 xhci_add_ep_to_interval_table(xhci,
2956 &virt_dev->eps[i].bw_info,
2963 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2964 /* Ok, this fits in the bandwidth we have.
2965 * Update the number of active TTs.
2967 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2971 /* We don't have enough bandwidth for this, revert the stored info. */
2972 for (i = 0; i < 31; i++) {
2973 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2976 /* Drop the new copies of any added or changed endpoints from
2977 * the interval table.
2979 if (EP_IS_ADDED(ctrl_ctx, i)) {
2980 xhci_drop_ep_from_interval_table(xhci,
2981 &virt_dev->eps[i].bw_info,
2987 /* Revert the endpoint back to its old information */
2988 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2989 sizeof(ep_bw_info[i]));
2990 /* Add any changed or dropped endpoints back into the table */
2991 if (EP_IS_DROPPED(ctrl_ctx, i))
2992 xhci_add_ep_to_interval_table(xhci,
2993 &virt_dev->eps[i].bw_info,
3003 /* Issue a configure endpoint command or evaluate context command
3004 * and wait for it to finish.
3006 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
3007 struct usb_device *udev,
3008 struct xhci_command *command,
3009 bool ctx_change, bool must_succeed)
3012 unsigned long flags;
3013 struct xhci_input_control_ctx *ctrl_ctx;
3014 struct xhci_virt_device *virt_dev;
3015 struct xhci_slot_ctx *slot_ctx;
3020 spin_lock_irqsave(&xhci->lock, flags);
3022 if (xhci->xhc_state & XHCI_STATE_DYING) {
3023 spin_unlock_irqrestore(&xhci->lock, flags);
3027 virt_dev = xhci->devs[udev->slot_id];
3029 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3031 spin_unlock_irqrestore(&xhci->lock, flags);
3032 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3037 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
3038 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
3039 spin_unlock_irqrestore(&xhci->lock, flags);
3040 xhci_warn(xhci, "Not enough host resources, "
3041 "active endpoint contexts = %u\n",
3042 xhci->num_active_eps);
3045 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
3046 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
3047 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
3048 xhci_free_host_resources(xhci, ctrl_ctx);
3049 spin_unlock_irqrestore(&xhci->lock, flags);
3050 xhci_warn(xhci, "Not enough bandwidth\n");
3054 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3056 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
3057 trace_xhci_configure_endpoint(slot_ctx);
3060 ret = xhci_queue_configure_endpoint(xhci, command,
3061 command->in_ctx->dma,
3062 udev->slot_id, must_succeed);
3064 ret = xhci_queue_evaluate_context(xhci, command,
3065 command->in_ctx->dma,
3066 udev->slot_id, must_succeed);
3068 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
3069 xhci_free_host_resources(xhci, ctrl_ctx);
3070 spin_unlock_irqrestore(&xhci->lock, flags);
3071 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
3072 "FIXME allocate a new ring segment");
3075 xhci_ring_cmd_db(xhci);
3076 spin_unlock_irqrestore(&xhci->lock, flags);
3078 /* Wait for the configure endpoint command to complete */
3079 wait_for_completion(command->completion);
3082 ret = xhci_configure_endpoint_result(xhci, udev,
3085 ret = xhci_evaluate_context_result(xhci, udev,
3088 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3089 spin_lock_irqsave(&xhci->lock, flags);
3090 /* If the command failed, remove the reserved resources.
3091 * Otherwise, clean up the estimate to include dropped eps.
3094 xhci_free_host_resources(xhci, ctrl_ctx);
3096 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3097 spin_unlock_irqrestore(&xhci->lock, flags);
3102 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3103 struct xhci_virt_device *vdev, int i)
3105 struct xhci_virt_ep *ep = &vdev->eps[i];
3107 if (ep->ep_state & EP_HAS_STREAMS) {
3108 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3109 xhci_get_endpoint_address(i));
3110 xhci_free_stream_info(xhci, ep->stream_info);
3111 ep->stream_info = NULL;
3112 ep->ep_state &= ~EP_HAS_STREAMS;
3116 /* Called after one or more calls to xhci_add_endpoint() or
3117 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3118 * to call xhci_reset_bandwidth().
3120 * Since we are in the middle of changing either configuration or
3121 * installing a new alt setting, the USB core won't allow URBs to be
3122 * enqueued for any endpoint on the old config or interface. Nothing
3123 * else should be touching the xhci->devs[slot_id] structure, so we
3124 * don't need to take the xhci->lock for manipulating that.
3126 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3130 struct xhci_hcd *xhci;
3131 struct xhci_virt_device *virt_dev;
3132 struct xhci_input_control_ctx *ctrl_ctx;
3133 struct xhci_slot_ctx *slot_ctx;
3134 struct xhci_command *command;
3136 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3139 xhci = hcd_to_xhci(hcd);
3140 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3141 (xhci->xhc_state & XHCI_STATE_REMOVING))
3144 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3145 virt_dev = xhci->devs[udev->slot_id];
3147 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3151 command->in_ctx = virt_dev->in_ctx;
3153 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3154 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3156 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3159 goto command_cleanup;
3161 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3162 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3163 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3165 /* Don't issue the command if there's no endpoints to update. */
3166 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3167 ctrl_ctx->drop_flags == 0) {
3169 goto command_cleanup;
3171 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3172 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3173 for (i = 31; i >= 1; i--) {
3174 __le32 le32 = cpu_to_le32(BIT(i));
3176 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3177 || (ctrl_ctx->add_flags & le32) || i == 1) {
3178 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3179 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3184 ret = xhci_configure_endpoint(xhci, udev, command,
3187 /* Callee should call reset_bandwidth() */
3188 goto command_cleanup;
3190 /* Free any rings that were dropped, but not changed. */
3191 for (i = 1; i < 31; i++) {
3192 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3193 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3194 xhci_free_endpoint_ring(xhci, virt_dev, i);
3195 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3198 xhci_zero_in_ctx(xhci, virt_dev);
3200 * Install any rings for completely new endpoints or changed endpoints,
3201 * and free any old rings from changed endpoints.
3203 for (i = 1; i < 31; i++) {
3204 if (!virt_dev->eps[i].new_ring)
3206 /* Only free the old ring if it exists.
3207 * It may not if this is the first add of an endpoint.
3209 if (virt_dev->eps[i].ring) {
3210 xhci_free_endpoint_ring(xhci, virt_dev, i);
3212 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3213 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3214 virt_dev->eps[i].new_ring = NULL;
3215 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3218 kfree(command->completion);
3223 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3225 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3227 struct xhci_hcd *xhci;
3228 struct xhci_virt_device *virt_dev;
3231 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3234 xhci = hcd_to_xhci(hcd);
3236 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3237 virt_dev = xhci->devs[udev->slot_id];
3238 /* Free any rings allocated for added endpoints */
3239 for (i = 0; i < 31; i++) {
3240 if (virt_dev->eps[i].new_ring) {
3241 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3242 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3243 virt_dev->eps[i].new_ring = NULL;
3246 xhci_zero_in_ctx(xhci, virt_dev);
3248 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3250 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3251 struct xhci_container_ctx *in_ctx,
3252 struct xhci_container_ctx *out_ctx,
3253 struct xhci_input_control_ctx *ctrl_ctx,
3254 u32 add_flags, u32 drop_flags)
3256 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3257 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3258 xhci_slot_copy(xhci, in_ctx, out_ctx);
3259 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3262 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3263 struct usb_host_endpoint *host_ep)
3265 struct xhci_hcd *xhci;
3266 struct xhci_virt_device *vdev;
3267 struct xhci_virt_ep *ep;
3268 struct usb_device *udev;
3269 unsigned long flags;
3270 unsigned int ep_index;
3272 xhci = hcd_to_xhci(hcd);
3274 spin_lock_irqsave(&xhci->lock, flags);
3276 udev = (struct usb_device *)host_ep->hcpriv;
3277 if (!udev || !udev->slot_id)
3280 vdev = xhci->devs[udev->slot_id];
3284 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3285 ep = &vdev->eps[ep_index];
3289 /* wait for hub_tt_work to finish clearing hub TT */
3290 if (ep->ep_state & EP_CLEARING_TT) {
3291 spin_unlock_irqrestore(&xhci->lock, flags);
3292 schedule_timeout_uninterruptible(1);
3297 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3300 host_ep->hcpriv = NULL;
3301 spin_unlock_irqrestore(&xhci->lock, flags);
3305 * Called after usb core issues a clear halt control message.
3306 * The host side of the halt should already be cleared by a reset endpoint
3307 * command issued when the STALL event was received.
3309 * The reset endpoint command may only be issued to endpoints in the halted
3310 * state. For software that wishes to reset the data toggle or sequence number
3311 * of an endpoint that isn't in the halted state this function will issue a
3312 * configure endpoint command with the Drop and Add bits set for the target
3313 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3316 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3317 struct usb_host_endpoint *host_ep)
3319 struct xhci_hcd *xhci;
3320 struct usb_device *udev;
3321 struct xhci_virt_device *vdev;
3322 struct xhci_virt_ep *ep;
3323 struct xhci_input_control_ctx *ctrl_ctx;
3324 struct xhci_command *stop_cmd, *cfg_cmd;
3325 unsigned int ep_index;
3326 unsigned long flags;
3330 xhci = hcd_to_xhci(hcd);
3331 if (!host_ep->hcpriv)
3333 udev = (struct usb_device *) host_ep->hcpriv;
3334 vdev = xhci->devs[udev->slot_id];
3337 * vdev may be lost due to xHC restore error and re-initialization
3338 * during S3/S4 resume. A new vdev will be allocated later by
3339 * xhci_discover_or_reset_device()
3341 if (!udev->slot_id || !vdev)
3343 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3344 ep = &vdev->eps[ep_index];
3348 /* Bail out if toggle is already being cleared by a endpoint reset */
3349 spin_lock_irqsave(&xhci->lock, flags);
3350 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3351 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3352 spin_unlock_irqrestore(&xhci->lock, flags);
3355 spin_unlock_irqrestore(&xhci->lock, flags);
3356 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3357 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3358 usb_endpoint_xfer_isoc(&host_ep->desc))
3361 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3363 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3366 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3370 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3374 spin_lock_irqsave(&xhci->lock, flags);
3376 /* block queuing new trbs and ringing ep doorbell */
3377 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3380 * Make sure endpoint ring is empty before resetting the toggle/seq.
3381 * Driver is required to synchronously cancel all transfer request.
3382 * Stop the endpoint to force xHC to update the output context
3385 if (!list_empty(&ep->ring->td_list)) {
3386 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3387 spin_unlock_irqrestore(&xhci->lock, flags);
3388 xhci_free_command(xhci, cfg_cmd);
3392 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3395 spin_unlock_irqrestore(&xhci->lock, flags);
3396 xhci_free_command(xhci, cfg_cmd);
3397 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3402 xhci_ring_cmd_db(xhci);
3403 spin_unlock_irqrestore(&xhci->lock, flags);
3405 wait_for_completion(stop_cmd->completion);
3407 spin_lock_irqsave(&xhci->lock, flags);
3409 /* config ep command clears toggle if add and drop ep flags are set */
3410 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3412 spin_unlock_irqrestore(&xhci->lock, flags);
3413 xhci_free_command(xhci, cfg_cmd);
3414 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3419 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3420 ctrl_ctx, ep_flag, ep_flag);
3421 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3423 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3424 udev->slot_id, false);
3426 spin_unlock_irqrestore(&xhci->lock, flags);
3427 xhci_free_command(xhci, cfg_cmd);
3428 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3433 xhci_ring_cmd_db(xhci);
3434 spin_unlock_irqrestore(&xhci->lock, flags);
3436 wait_for_completion(cfg_cmd->completion);
3438 xhci_free_command(xhci, cfg_cmd);
3440 xhci_free_command(xhci, stop_cmd);
3441 spin_lock_irqsave(&xhci->lock, flags);
3442 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3443 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3444 spin_unlock_irqrestore(&xhci->lock, flags);
3447 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3448 struct usb_device *udev, struct usb_host_endpoint *ep,
3449 unsigned int slot_id)
3452 unsigned int ep_index;
3453 unsigned int ep_state;
3457 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3459 return ret ? ret : -EINVAL;
3460 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3461 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3462 " descriptor for ep 0x%x does not support streams\n",
3463 ep->desc.bEndpointAddress);
3467 ep_index = xhci_get_endpoint_index(&ep->desc);
3468 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3469 if (ep_state & EP_HAS_STREAMS ||
3470 ep_state & EP_GETTING_STREAMS) {
3471 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3472 "already has streams set up.\n",
3473 ep->desc.bEndpointAddress);
3474 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3475 "dynamic stream context array reallocation.\n");
3478 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3479 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3480 "endpoint 0x%x; URBs are pending.\n",
3481 ep->desc.bEndpointAddress);
3487 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3488 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3490 unsigned int max_streams;
3492 /* The stream context array size must be a power of two */
3493 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3495 * Find out how many primary stream array entries the host controller
3496 * supports. Later we may use secondary stream arrays (similar to 2nd
3497 * level page entries), but that's an optional feature for xHCI host
3498 * controllers. xHCs must support at least 4 stream IDs.
3500 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3501 if (*num_stream_ctxs > max_streams) {
3502 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3504 *num_stream_ctxs = max_streams;
3505 *num_streams = max_streams;
3509 /* Returns an error code if one of the endpoint already has streams.
3510 * This does not change any data structures, it only checks and gathers
3513 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3514 struct usb_device *udev,
3515 struct usb_host_endpoint **eps, unsigned int num_eps,
3516 unsigned int *num_streams, u32 *changed_ep_bitmask)
3518 unsigned int max_streams;
3519 unsigned int endpoint_flag;
3523 for (i = 0; i < num_eps; i++) {
3524 ret = xhci_check_streams_endpoint(xhci, udev,
3525 eps[i], udev->slot_id);
3529 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3530 if (max_streams < (*num_streams - 1)) {
3531 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3532 eps[i]->desc.bEndpointAddress,
3534 *num_streams = max_streams+1;
3537 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3538 if (*changed_ep_bitmask & endpoint_flag)
3540 *changed_ep_bitmask |= endpoint_flag;
3545 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3546 struct usb_device *udev,
3547 struct usb_host_endpoint **eps, unsigned int num_eps)
3549 u32 changed_ep_bitmask = 0;
3550 unsigned int slot_id;
3551 unsigned int ep_index;
3552 unsigned int ep_state;
3555 slot_id = udev->slot_id;
3556 if (!xhci->devs[slot_id])
3559 for (i = 0; i < num_eps; i++) {
3560 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3561 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3562 /* Are streams already being freed for the endpoint? */
3563 if (ep_state & EP_GETTING_NO_STREAMS) {
3564 xhci_warn(xhci, "WARN Can't disable streams for "
3566 "streams are being disabled already\n",
3567 eps[i]->desc.bEndpointAddress);
3570 /* Are there actually any streams to free? */
3571 if (!(ep_state & EP_HAS_STREAMS) &&
3572 !(ep_state & EP_GETTING_STREAMS)) {
3573 xhci_warn(xhci, "WARN Can't disable streams for "
3575 "streams are already disabled!\n",
3576 eps[i]->desc.bEndpointAddress);
3577 xhci_warn(xhci, "WARN xhci_free_streams() called "
3578 "with non-streams endpoint\n");
3581 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3583 return changed_ep_bitmask;
3587 * The USB device drivers use this function (through the HCD interface in USB
3588 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3589 * coordinate mass storage command queueing across multiple endpoints (basically
3590 * a stream ID == a task ID).
3592 * Setting up streams involves allocating the same size stream context array
3593 * for each endpoint and issuing a configure endpoint command for all endpoints.
3595 * Don't allow the call to succeed if one endpoint only supports one stream
3596 * (which means it doesn't support streams at all).
3598 * Drivers may get less stream IDs than they asked for, if the host controller
3599 * hardware or endpoints claim they can't support the number of requested
3602 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3603 struct usb_host_endpoint **eps, unsigned int num_eps,
3604 unsigned int num_streams, gfp_t mem_flags)
3607 struct xhci_hcd *xhci;
3608 struct xhci_virt_device *vdev;
3609 struct xhci_command *config_cmd;
3610 struct xhci_input_control_ctx *ctrl_ctx;
3611 unsigned int ep_index;
3612 unsigned int num_stream_ctxs;
3613 unsigned int max_packet;
3614 unsigned long flags;
3615 u32 changed_ep_bitmask = 0;
3620 /* Add one to the number of streams requested to account for
3621 * stream 0 that is reserved for xHCI usage.
3624 xhci = hcd_to_xhci(hcd);
3625 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3628 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3629 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3630 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3631 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3635 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3639 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3641 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3643 xhci_free_command(xhci, config_cmd);
3647 /* Check to make sure all endpoints are not already configured for
3648 * streams. While we're at it, find the maximum number of streams that
3649 * all the endpoints will support and check for duplicate endpoints.
3651 spin_lock_irqsave(&xhci->lock, flags);
3652 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3653 num_eps, &num_streams, &changed_ep_bitmask);
3655 xhci_free_command(xhci, config_cmd);
3656 spin_unlock_irqrestore(&xhci->lock, flags);
3659 if (num_streams <= 1) {
3660 xhci_warn(xhci, "WARN: endpoints can't handle "
3661 "more than one stream.\n");
3662 xhci_free_command(xhci, config_cmd);
3663 spin_unlock_irqrestore(&xhci->lock, flags);
3666 vdev = xhci->devs[udev->slot_id];
3667 /* Mark each endpoint as being in transition, so
3668 * xhci_urb_enqueue() will reject all URBs.
3670 for (i = 0; i < num_eps; i++) {
3671 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3672 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3674 spin_unlock_irqrestore(&xhci->lock, flags);
3676 /* Setup internal data structures and allocate HW data structures for
3677 * streams (but don't install the HW structures in the input context
3678 * until we're sure all memory allocation succeeded).
3680 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3681 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3682 num_stream_ctxs, num_streams);
3684 for (i = 0; i < num_eps; i++) {
3685 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3686 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3687 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3690 max_packet, mem_flags);
3691 if (!vdev->eps[ep_index].stream_info)
3693 /* Set maxPstreams in endpoint context and update deq ptr to
3694 * point to stream context array. FIXME
3698 /* Set up the input context for a configure endpoint command. */
3699 for (i = 0; i < num_eps; i++) {
3700 struct xhci_ep_ctx *ep_ctx;
3702 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3703 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3705 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3706 vdev->out_ctx, ep_index);
3707 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3708 vdev->eps[ep_index].stream_info);
3710 /* Tell the HW to drop its old copy of the endpoint context info
3711 * and add the updated copy from the input context.
3713 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3714 vdev->out_ctx, ctrl_ctx,
3715 changed_ep_bitmask, changed_ep_bitmask);
3717 /* Issue and wait for the configure endpoint command */
3718 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3721 /* xHC rejected the configure endpoint command for some reason, so we
3722 * leave the old ring intact and free our internal streams data
3728 spin_lock_irqsave(&xhci->lock, flags);
3729 for (i = 0; i < num_eps; i++) {
3730 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3731 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3732 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3733 udev->slot_id, ep_index);
3734 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3736 xhci_free_command(xhci, config_cmd);
3737 spin_unlock_irqrestore(&xhci->lock, flags);
3739 for (i = 0; i < num_eps; i++) {
3740 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3741 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3743 /* Subtract 1 for stream 0, which drivers can't use */
3744 return num_streams - 1;
3747 /* If it didn't work, free the streams! */
3748 for (i = 0; i < num_eps; i++) {
3749 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3750 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3751 vdev->eps[ep_index].stream_info = NULL;
3752 /* FIXME Unset maxPstreams in endpoint context and
3753 * update deq ptr to point to normal string ring.
3755 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3756 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3757 xhci_endpoint_zero(xhci, vdev, eps[i]);
3759 xhci_free_command(xhci, config_cmd);
3763 /* Transition the endpoint from using streams to being a "normal" endpoint
3766 * Modify the endpoint context state, submit a configure endpoint command,
3767 * and free all endpoint rings for streams if that completes successfully.
3769 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3770 struct usb_host_endpoint **eps, unsigned int num_eps,
3774 struct xhci_hcd *xhci;
3775 struct xhci_virt_device *vdev;
3776 struct xhci_command *command;
3777 struct xhci_input_control_ctx *ctrl_ctx;
3778 unsigned int ep_index;
3779 unsigned long flags;
3780 u32 changed_ep_bitmask;
3782 xhci = hcd_to_xhci(hcd);
3783 vdev = xhci->devs[udev->slot_id];
3785 /* Set up a configure endpoint command to remove the streams rings */
3786 spin_lock_irqsave(&xhci->lock, flags);
3787 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3788 udev, eps, num_eps);
3789 if (changed_ep_bitmask == 0) {
3790 spin_unlock_irqrestore(&xhci->lock, flags);
3794 /* Use the xhci_command structure from the first endpoint. We may have
3795 * allocated too many, but the driver may call xhci_free_streams() for
3796 * each endpoint it grouped into one call to xhci_alloc_streams().
3798 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3799 command = vdev->eps[ep_index].stream_info->free_streams_command;
3800 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3802 spin_unlock_irqrestore(&xhci->lock, flags);
3803 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3808 for (i = 0; i < num_eps; i++) {
3809 struct xhci_ep_ctx *ep_ctx;
3811 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3812 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3813 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3814 EP_GETTING_NO_STREAMS;
3816 xhci_endpoint_copy(xhci, command->in_ctx,
3817 vdev->out_ctx, ep_index);
3818 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3819 &vdev->eps[ep_index]);
3821 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3822 vdev->out_ctx, ctrl_ctx,
3823 changed_ep_bitmask, changed_ep_bitmask);
3824 spin_unlock_irqrestore(&xhci->lock, flags);
3826 /* Issue and wait for the configure endpoint command,
3827 * which must succeed.
3829 ret = xhci_configure_endpoint(xhci, udev, command,
3832 /* xHC rejected the configure endpoint command for some reason, so we
3833 * leave the streams rings intact.
3838 spin_lock_irqsave(&xhci->lock, flags);
3839 for (i = 0; i < num_eps; i++) {
3840 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3841 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3842 vdev->eps[ep_index].stream_info = NULL;
3843 /* FIXME Unset maxPstreams in endpoint context and
3844 * update deq ptr to point to normal string ring.
3846 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3847 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3849 spin_unlock_irqrestore(&xhci->lock, flags);
3855 * Deletes endpoint resources for endpoints that were active before a Reset
3856 * Device command, or a Disable Slot command. The Reset Device command leaves
3857 * the control endpoint intact, whereas the Disable Slot command deletes it.
3859 * Must be called with xhci->lock held.
3861 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3862 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3865 unsigned int num_dropped_eps = 0;
3866 unsigned int drop_flags = 0;
3868 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3869 if (virt_dev->eps[i].ring) {
3870 drop_flags |= 1 << i;
3874 xhci->num_active_eps -= num_dropped_eps;
3875 if (num_dropped_eps)
3876 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3877 "Dropped %u ep ctxs, flags = 0x%x, "
3879 num_dropped_eps, drop_flags,
3880 xhci->num_active_eps);
3884 * This submits a Reset Device Command, which will set the device state to 0,
3885 * set the device address to 0, and disable all the endpoints except the default
3886 * control endpoint. The USB core should come back and call
3887 * xhci_address_device(), and then re-set up the configuration. If this is
3888 * called because of a usb_reset_and_verify_device(), then the old alternate
3889 * settings will be re-installed through the normal bandwidth allocation
3892 * Wait for the Reset Device command to finish. Remove all structures
3893 * associated with the endpoints that were disabled. Clear the input device
3894 * structure? Reset the control endpoint 0 max packet size?
3896 * If the virt_dev to be reset does not exist or does not match the udev,
3897 * it means the device is lost, possibly due to the xHC restore error and
3898 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3899 * re-allocate the device.
3901 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3902 struct usb_device *udev)
3905 unsigned long flags;
3906 struct xhci_hcd *xhci;
3907 unsigned int slot_id;
3908 struct xhci_virt_device *virt_dev;
3909 struct xhci_command *reset_device_cmd;
3910 struct xhci_slot_ctx *slot_ctx;
3911 int old_active_eps = 0;
3913 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3916 xhci = hcd_to_xhci(hcd);
3917 slot_id = udev->slot_id;
3918 virt_dev = xhci->devs[slot_id];
3920 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3921 "not exist. Re-allocate the device\n", slot_id);
3922 ret = xhci_alloc_dev(hcd, udev);
3929 if (virt_dev->tt_info)
3930 old_active_eps = virt_dev->tt_info->active_eps;
3932 if (virt_dev->udev != udev) {
3933 /* If the virt_dev and the udev does not match, this virt_dev
3934 * may belong to another udev.
3935 * Re-allocate the device.
3937 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3938 "not match the udev. Re-allocate the device\n",
3940 ret = xhci_alloc_dev(hcd, udev);
3947 /* If device is not setup, there is no point in resetting it */
3948 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3949 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3950 SLOT_STATE_DISABLED)
3953 trace_xhci_discover_or_reset_device(slot_ctx);
3955 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3956 /* Allocate the command structure that holds the struct completion.
3957 * Assume we're in process context, since the normal device reset
3958 * process has to wait for the device anyway. Storage devices are
3959 * reset as part of error handling, so use GFP_NOIO instead of
3962 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3963 if (!reset_device_cmd) {
3964 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3968 /* Attempt to submit the Reset Device command to the command ring */
3969 spin_lock_irqsave(&xhci->lock, flags);
3971 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3973 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3974 spin_unlock_irqrestore(&xhci->lock, flags);
3975 goto command_cleanup;
3977 xhci_ring_cmd_db(xhci);
3978 spin_unlock_irqrestore(&xhci->lock, flags);
3980 /* Wait for the Reset Device command to finish */
3981 wait_for_completion(reset_device_cmd->completion);
3983 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3984 * unless we tried to reset a slot ID that wasn't enabled,
3985 * or the device wasn't in the addressed or configured state.
3987 ret = reset_device_cmd->status;
3989 case COMP_COMMAND_ABORTED:
3990 case COMP_COMMAND_RING_STOPPED:
3991 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3993 goto command_cleanup;
3994 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3995 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3996 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3998 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3999 xhci_dbg(xhci, "Not freeing device rings.\n");
4000 /* Don't treat this as an error. May change my mind later. */
4002 goto command_cleanup;
4004 xhci_dbg(xhci, "Successful reset device command.\n");
4007 if (xhci_is_vendor_info_code(xhci, ret))
4009 xhci_warn(xhci, "Unknown completion code %u for "
4010 "reset device command.\n", ret);
4012 goto command_cleanup;
4015 /* Free up host controller endpoint resources */
4016 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4017 spin_lock_irqsave(&xhci->lock, flags);
4018 /* Don't delete the default control endpoint resources */
4019 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
4020 spin_unlock_irqrestore(&xhci->lock, flags);
4023 /* Everything but endpoint 0 is disabled, so free the rings. */
4024 for (i = 1; i < 31; i++) {
4025 struct xhci_virt_ep *ep = &virt_dev->eps[i];
4027 if (ep->ep_state & EP_HAS_STREAMS) {
4028 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
4029 xhci_get_endpoint_address(i));
4030 xhci_free_stream_info(xhci, ep->stream_info);
4031 ep->stream_info = NULL;
4032 ep->ep_state &= ~EP_HAS_STREAMS;
4036 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
4037 xhci_free_endpoint_ring(xhci, virt_dev, i);
4039 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
4040 xhci_drop_ep_from_interval_table(xhci,
4041 &virt_dev->eps[i].bw_info,
4046 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
4048 /* If necessary, update the number of active TTs on this root port */
4049 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
4050 virt_dev->flags = 0;
4054 xhci_free_command(xhci, reset_device_cmd);
4059 * At this point, the struct usb_device is about to go away, the device has
4060 * disconnected, and all traffic has been stopped and the endpoints have been
4061 * disabled. Free any HC data structures associated with that device.
4063 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4065 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4066 struct xhci_virt_device *virt_dev;
4067 struct xhci_slot_ctx *slot_ctx;
4071 * We called pm_runtime_get_noresume when the device was attached.
4072 * Decrement the counter here to allow controller to runtime suspend
4073 * if no devices remain.
4075 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4076 pm_runtime_put_noidle(hcd->self.controller);
4078 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
4079 /* If the host is halted due to driver unload, we still need to free the
4082 if (ret <= 0 && ret != -ENODEV)
4085 virt_dev = xhci->devs[udev->slot_id];
4086 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4087 trace_xhci_free_dev(slot_ctx);
4089 /* Stop any wayward timer functions (which may grab the lock) */
4090 for (i = 0; i < 31; i++) {
4091 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4092 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
4094 virt_dev->udev = NULL;
4095 xhci_disable_slot(xhci, udev->slot_id);
4096 xhci_free_virt_device(xhci, udev->slot_id);
4099 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4101 struct xhci_command *command;
4102 unsigned long flags;
4106 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4110 xhci_debugfs_remove_slot(xhci, slot_id);
4112 spin_lock_irqsave(&xhci->lock, flags);
4113 /* Don't disable the slot if the host controller is dead. */
4114 state = readl(&xhci->op_regs->status);
4115 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4116 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4117 spin_unlock_irqrestore(&xhci->lock, flags);
4122 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4125 spin_unlock_irqrestore(&xhci->lock, flags);
4129 xhci_ring_cmd_db(xhci);
4130 spin_unlock_irqrestore(&xhci->lock, flags);
4132 wait_for_completion(command->completion);
4134 if (command->status != COMP_SUCCESS)
4135 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4136 slot_id, command->status);
4138 xhci_free_command(xhci, command);
4144 * Checks if we have enough host controller resources for the default control
4147 * Must be called with xhci->lock held.
4149 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4151 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4153 "Not enough ep ctxs: "
4154 "%u active, need to add 1, limit is %u.",
4155 xhci->num_active_eps, xhci->limit_active_eps);
4158 xhci->num_active_eps += 1;
4159 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4160 "Adding 1 ep ctx, %u now active.",
4161 xhci->num_active_eps);
4167 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4168 * timed out, or allocating memory failed. Returns 1 on success.
4170 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4172 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4173 struct xhci_virt_device *vdev;
4174 struct xhci_slot_ctx *slot_ctx;
4175 unsigned long flags;
4177 struct xhci_command *command;
4179 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4183 spin_lock_irqsave(&xhci->lock, flags);
4184 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4186 spin_unlock_irqrestore(&xhci->lock, flags);
4187 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4188 xhci_free_command(xhci, command);
4191 xhci_ring_cmd_db(xhci);
4192 spin_unlock_irqrestore(&xhci->lock, flags);
4194 wait_for_completion(command->completion);
4195 slot_id = command->slot_id;
4197 if (!slot_id || command->status != COMP_SUCCESS) {
4198 xhci_err(xhci, "Error while assigning device slot ID\n");
4199 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4201 readl(&xhci->cap_regs->hcs_params1)));
4202 xhci_free_command(xhci, command);
4206 xhci_free_command(xhci, command);
4208 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4209 spin_lock_irqsave(&xhci->lock, flags);
4210 ret = xhci_reserve_host_control_ep_resources(xhci);
4212 spin_unlock_irqrestore(&xhci->lock, flags);
4213 xhci_warn(xhci, "Not enough host resources, "
4214 "active endpoint contexts = %u\n",
4215 xhci->num_active_eps);
4218 spin_unlock_irqrestore(&xhci->lock, flags);
4220 /* Use GFP_NOIO, since this function can be called from
4221 * xhci_discover_or_reset_device(), which may be called as part of
4222 * mass storage driver error handling.
4224 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4225 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4228 vdev = xhci->devs[slot_id];
4229 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4230 trace_xhci_alloc_dev(slot_ctx);
4232 udev->slot_id = slot_id;
4234 xhci_debugfs_create_slot(xhci, slot_id);
4237 * If resetting upon resume, we can't put the controller into runtime
4238 * suspend if there is a device attached.
4240 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4241 pm_runtime_get_noresume(hcd->self.controller);
4243 /* Is this a LS or FS device under a HS hub? */
4244 /* Hub or peripherial? */
4248 xhci_disable_slot(xhci, udev->slot_id);
4249 xhci_free_virt_device(xhci, udev->slot_id);
4255 * Issue an Address Device command and optionally send a corresponding
4256 * SetAddress request to the device.
4258 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4259 enum xhci_setup_dev setup)
4261 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4262 unsigned long flags;
4263 struct xhci_virt_device *virt_dev;
4265 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4266 struct xhci_slot_ctx *slot_ctx;
4267 struct xhci_input_control_ctx *ctrl_ctx;
4269 struct xhci_command *command = NULL;
4271 mutex_lock(&xhci->mutex);
4273 if (xhci->xhc_state) { /* dying, removing or halted */
4278 if (!udev->slot_id) {
4279 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4280 "Bad Slot ID %d", udev->slot_id);
4285 virt_dev = xhci->devs[udev->slot_id];
4287 if (WARN_ON(!virt_dev)) {
4289 * In plug/unplug torture test with an NEC controller,
4290 * a zero-dereference was observed once due to virt_dev = 0.
4291 * Print useful debug rather than crash if it is observed again!
4293 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4298 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4299 trace_xhci_setup_device_slot(slot_ctx);
4301 if (setup == SETUP_CONTEXT_ONLY) {
4302 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4303 SLOT_STATE_DEFAULT) {
4304 xhci_dbg(xhci, "Slot already in default state\n");
4309 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4315 command->in_ctx = virt_dev->in_ctx;
4317 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4318 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4320 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4326 * If this is the first Set Address since device plug-in or
4327 * virt_device realloaction after a resume with an xHCI power loss,
4328 * then set up the slot context.
4330 if (!slot_ctx->dev_info)
4331 xhci_setup_addressable_virt_dev(xhci, udev);
4332 /* Otherwise, update the control endpoint ring enqueue pointer. */
4334 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4335 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4336 ctrl_ctx->drop_flags = 0;
4338 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4339 le32_to_cpu(slot_ctx->dev_info) >> 27);
4341 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4342 spin_lock_irqsave(&xhci->lock, flags);
4343 trace_xhci_setup_device(virt_dev);
4344 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4345 udev->slot_id, setup);
4347 spin_unlock_irqrestore(&xhci->lock, flags);
4348 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4349 "FIXME: allocate a command ring segment");
4352 xhci_ring_cmd_db(xhci);
4353 spin_unlock_irqrestore(&xhci->lock, flags);
4355 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4356 wait_for_completion(command->completion);
4358 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4359 * the SetAddress() "recovery interval" required by USB and aborting the
4360 * command on a timeout.
4362 switch (command->status) {
4363 case COMP_COMMAND_ABORTED:
4364 case COMP_COMMAND_RING_STOPPED:
4365 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4368 case COMP_CONTEXT_STATE_ERROR:
4369 case COMP_SLOT_NOT_ENABLED_ERROR:
4370 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4371 act, udev->slot_id);
4374 case COMP_USB_TRANSACTION_ERROR:
4375 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4377 mutex_unlock(&xhci->mutex);
4378 ret = xhci_disable_slot(xhci, udev->slot_id);
4379 xhci_free_virt_device(xhci, udev->slot_id);
4381 xhci_alloc_dev(hcd, udev);
4382 kfree(command->completion);
4385 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4386 dev_warn(&udev->dev,
4387 "ERROR: Incompatible device for setup %s command\n", act);
4391 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4392 "Successful setup %s command", act);
4396 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4397 act, command->status);
4398 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4404 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4405 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4406 "Op regs DCBAA ptr = %#016llx", temp_64);
4407 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4408 "Slot ID %d dcbaa entry @%p = %#016llx",
4410 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4411 (unsigned long long)
4412 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4413 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4414 "Output Context DMA address = %#08llx",
4415 (unsigned long long)virt_dev->out_ctx->dma);
4416 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4417 le32_to_cpu(slot_ctx->dev_info) >> 27);
4419 * USB core uses address 1 for the roothubs, so we add one to the
4420 * address given back to us by the HC.
4422 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4423 le32_to_cpu(slot_ctx->dev_info) >> 27);
4424 /* Zero the input context control for later use */
4425 ctrl_ctx->add_flags = 0;
4426 ctrl_ctx->drop_flags = 0;
4427 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4428 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4430 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4431 "Internal device address = %d",
4432 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4434 mutex_unlock(&xhci->mutex);
4436 kfree(command->completion);
4442 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4444 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4447 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4449 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4453 * Transfer the port index into real index in the HW port status
4454 * registers. Caculate offset between the port's PORTSC register
4455 * and port status base. Divide the number of per port register
4456 * to get the real index. The raw port number bases 1.
4458 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4460 struct xhci_hub *rhub;
4462 rhub = xhci_get_rhub(hcd);
4463 return rhub->ports[port1 - 1]->hw_portnum + 1;
4467 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4468 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4470 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4471 struct usb_device *udev, u16 max_exit_latency)
4473 struct xhci_virt_device *virt_dev;
4474 struct xhci_command *command;
4475 struct xhci_input_control_ctx *ctrl_ctx;
4476 struct xhci_slot_ctx *slot_ctx;
4477 unsigned long flags;
4480 spin_lock_irqsave(&xhci->lock, flags);
4482 virt_dev = xhci->devs[udev->slot_id];
4485 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4486 * xHC was re-initialized. Exit latency will be set later after
4487 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4490 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4491 spin_unlock_irqrestore(&xhci->lock, flags);
4495 /* Attempt to issue an Evaluate Context command to change the MEL. */
4496 command = xhci->lpm_command;
4497 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4499 spin_unlock_irqrestore(&xhci->lock, flags);
4500 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4505 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4506 spin_unlock_irqrestore(&xhci->lock, flags);
4508 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4509 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4510 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4511 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4512 slot_ctx->dev_state = 0;
4514 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4515 "Set up evaluate context for LPM MEL change.");
4517 /* Issue and wait for the evaluate context command. */
4518 ret = xhci_configure_endpoint(xhci, udev, command,
4522 spin_lock_irqsave(&xhci->lock, flags);
4523 virt_dev->current_mel = max_exit_latency;
4524 spin_unlock_irqrestore(&xhci->lock, flags);
4531 /* BESL to HIRD Encoding array for USB2 LPM */
4532 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4533 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4535 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4536 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4537 struct usb_device *udev)
4539 int u2del, besl, besl_host;
4540 int besl_device = 0;
4543 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4544 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4546 if (field & USB_BESL_SUPPORT) {
4547 for (besl_host = 0; besl_host < 16; besl_host++) {
4548 if (xhci_besl_encoding[besl_host] >= u2del)
4551 /* Use baseline BESL value as default */
4552 if (field & USB_BESL_BASELINE_VALID)
4553 besl_device = USB_GET_BESL_BASELINE(field);
4554 else if (field & USB_BESL_DEEP_VALID)
4555 besl_device = USB_GET_BESL_DEEP(field);
4560 besl_host = (u2del - 51) / 75 + 1;
4563 besl = besl_host + besl_device;
4570 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4571 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4578 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4580 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4581 l1 = udev->l1_params.timeout / 256;
4583 /* device has preferred BESLD */
4584 if (field & USB_BESL_DEEP_VALID) {
4585 besld = USB_GET_BESL_DEEP(field);
4589 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4592 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4593 struct usb_device *udev, int enable)
4595 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4596 struct xhci_port **ports;
4597 __le32 __iomem *pm_addr, *hlpm_addr;
4598 u32 pm_val, hlpm_val, field;
4599 unsigned int port_num;
4600 unsigned long flags;
4601 int hird, exit_latency;
4604 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4607 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4611 if (!udev->parent || udev->parent->parent ||
4612 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4615 if (udev->usb2_hw_lpm_capable != 1)
4618 spin_lock_irqsave(&xhci->lock, flags);
4620 ports = xhci->usb2_rhub.ports;
4621 port_num = udev->portnum - 1;
4622 pm_addr = ports[port_num]->addr + PORTPMSC;
4623 pm_val = readl(pm_addr);
4624 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4626 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4627 enable ? "enable" : "disable", port_num + 1);
4630 /* Host supports BESL timeout instead of HIRD */
4631 if (udev->usb2_hw_lpm_besl_capable) {
4632 /* if device doesn't have a preferred BESL value use a
4633 * default one which works with mixed HIRD and BESL
4634 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4636 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4637 if ((field & USB_BESL_SUPPORT) &&
4638 (field & USB_BESL_BASELINE_VALID))
4639 hird = USB_GET_BESL_BASELINE(field);
4641 hird = udev->l1_params.besl;
4643 exit_latency = xhci_besl_encoding[hird];
4644 spin_unlock_irqrestore(&xhci->lock, flags);
4646 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4647 * input context for link powermanagement evaluate
4648 * context commands. It is protected by hcd->bandwidth
4649 * mutex and is shared by all devices. We need to set
4650 * the max ext latency in USB 2 BESL LPM as well, so
4651 * use the same mutex and xhci_change_max_exit_latency()
4653 mutex_lock(hcd->bandwidth_mutex);
4654 ret = xhci_change_max_exit_latency(xhci, udev,
4656 mutex_unlock(hcd->bandwidth_mutex);
4660 spin_lock_irqsave(&xhci->lock, flags);
4662 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4663 writel(hlpm_val, hlpm_addr);
4667 hird = xhci_calculate_hird_besl(xhci, udev);
4670 pm_val &= ~PORT_HIRD_MASK;
4671 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4672 writel(pm_val, pm_addr);
4673 pm_val = readl(pm_addr);
4675 writel(pm_val, pm_addr);
4679 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4680 writel(pm_val, pm_addr);
4683 if (udev->usb2_hw_lpm_besl_capable) {
4684 spin_unlock_irqrestore(&xhci->lock, flags);
4685 mutex_lock(hcd->bandwidth_mutex);
4686 xhci_change_max_exit_latency(xhci, udev, 0);
4687 mutex_unlock(hcd->bandwidth_mutex);
4688 readl_poll_timeout(ports[port_num]->addr, pm_val,
4689 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4695 spin_unlock_irqrestore(&xhci->lock, flags);
4699 /* check if a usb2 port supports a given extened capability protocol
4700 * only USB2 ports extended protocol capability values are cached.
4701 * Return 1 if capability is supported
4703 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4704 unsigned capability)
4706 u32 port_offset, port_count;
4709 for (i = 0; i < xhci->num_ext_caps; i++) {
4710 if (xhci->ext_caps[i] & capability) {
4711 /* port offsets starts at 1 */
4712 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4713 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4714 if (port >= port_offset &&
4715 port < port_offset + port_count)
4722 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4724 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4725 int portnum = udev->portnum - 1;
4727 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4730 /* we only support lpm for non-hub device connected to root hub yet */
4731 if (!udev->parent || udev->parent->parent ||
4732 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4735 if (xhci->hw_lpm_support == 1 &&
4736 xhci_check_usb2_port_capability(
4737 xhci, portnum, XHCI_HLC)) {
4738 udev->usb2_hw_lpm_capable = 1;
4739 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4740 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4741 if (xhci_check_usb2_port_capability(xhci, portnum,
4743 udev->usb2_hw_lpm_besl_capable = 1;
4749 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4751 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4752 static unsigned long long xhci_service_interval_to_ns(
4753 struct usb_endpoint_descriptor *desc)
4755 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4758 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4759 enum usb3_link_state state)
4761 unsigned long long sel;
4762 unsigned long long pel;
4763 unsigned int max_sel_pel;
4768 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4769 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4770 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4771 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4775 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4776 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4777 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4781 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4783 return USB3_LPM_DISABLED;
4786 if (sel <= max_sel_pel && pel <= max_sel_pel)
4787 return USB3_LPM_DEVICE_INITIATED;
4789 if (sel > max_sel_pel)
4790 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4791 "due to long SEL %llu ms\n",
4794 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4795 "due to long PEL %llu ms\n",
4797 return USB3_LPM_DISABLED;
4800 /* The U1 timeout should be the maximum of the following values:
4801 * - For control endpoints, U1 system exit latency (SEL) * 3
4802 * - For bulk endpoints, U1 SEL * 5
4803 * - For interrupt endpoints:
4804 * - Notification EPs, U1 SEL * 3
4805 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4806 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4808 static unsigned long long xhci_calculate_intel_u1_timeout(
4809 struct usb_device *udev,
4810 struct usb_endpoint_descriptor *desc)
4812 unsigned long long timeout_ns;
4816 ep_type = usb_endpoint_type(desc);
4818 case USB_ENDPOINT_XFER_CONTROL:
4819 timeout_ns = udev->u1_params.sel * 3;
4821 case USB_ENDPOINT_XFER_BULK:
4822 timeout_ns = udev->u1_params.sel * 5;
4824 case USB_ENDPOINT_XFER_INT:
4825 intr_type = usb_endpoint_interrupt_type(desc);
4826 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4827 timeout_ns = udev->u1_params.sel * 3;
4830 /* Otherwise the calculation is the same as isoc eps */
4832 case USB_ENDPOINT_XFER_ISOC:
4833 timeout_ns = xhci_service_interval_to_ns(desc);
4834 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4835 if (timeout_ns < udev->u1_params.sel * 2)
4836 timeout_ns = udev->u1_params.sel * 2;
4845 /* Returns the hub-encoded U1 timeout value. */
4846 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4847 struct usb_device *udev,
4848 struct usb_endpoint_descriptor *desc)
4850 unsigned long long timeout_ns;
4852 /* Prevent U1 if service interval is shorter than U1 exit latency */
4853 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4854 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4855 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4856 return USB3_LPM_DISABLED;
4860 if (xhci->quirks & XHCI_INTEL_HOST)
4861 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4863 timeout_ns = udev->u1_params.sel;
4865 /* The U1 timeout is encoded in 1us intervals.
4866 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4868 if (timeout_ns == USB3_LPM_DISABLED)
4871 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4873 /* If the necessary timeout value is bigger than what we can set in the
4874 * USB 3.0 hub, we have to disable hub-initiated U1.
4876 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4878 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4879 "due to long timeout %llu ms\n", timeout_ns);
4880 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4883 /* The U2 timeout should be the maximum of:
4884 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4885 * - largest bInterval of any active periodic endpoint (to avoid going
4886 * into lower power link states between intervals).
4887 * - the U2 Exit Latency of the device
4889 static unsigned long long xhci_calculate_intel_u2_timeout(
4890 struct usb_device *udev,
4891 struct usb_endpoint_descriptor *desc)
4893 unsigned long long timeout_ns;
4894 unsigned long long u2_del_ns;
4896 timeout_ns = 10 * 1000 * 1000;
4898 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4899 (xhci_service_interval_to_ns(desc) > timeout_ns))
4900 timeout_ns = xhci_service_interval_to_ns(desc);
4902 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4903 if (u2_del_ns > timeout_ns)
4904 timeout_ns = u2_del_ns;
4909 /* Returns the hub-encoded U2 timeout value. */
4910 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4911 struct usb_device *udev,
4912 struct usb_endpoint_descriptor *desc)
4914 unsigned long long timeout_ns;
4916 /* Prevent U2 if service interval is shorter than U2 exit latency */
4917 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4918 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4919 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4920 return USB3_LPM_DISABLED;
4924 if (xhci->quirks & XHCI_INTEL_HOST)
4925 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4927 timeout_ns = udev->u2_params.sel;
4929 /* The U2 timeout is encoded in 256us intervals */
4930 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4931 /* If the necessary timeout value is bigger than what we can set in the
4932 * USB 3.0 hub, we have to disable hub-initiated U2.
4934 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4936 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4937 "due to long timeout %llu ms\n", timeout_ns);
4938 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4941 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4942 struct usb_device *udev,
4943 struct usb_endpoint_descriptor *desc,
4944 enum usb3_link_state state,
4947 if (state == USB3_LPM_U1)
4948 return xhci_calculate_u1_timeout(xhci, udev, desc);
4949 else if (state == USB3_LPM_U2)
4950 return xhci_calculate_u2_timeout(xhci, udev, desc);
4952 return USB3_LPM_DISABLED;
4955 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4956 struct usb_device *udev,
4957 struct usb_endpoint_descriptor *desc,
4958 enum usb3_link_state state,
4963 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4964 desc, state, timeout);
4966 /* If we found we can't enable hub-initiated LPM, and
4967 * the U1 or U2 exit latency was too high to allow
4968 * device-initiated LPM as well, then we will disable LPM
4969 * for this device, so stop searching any further.
4971 if (alt_timeout == USB3_LPM_DISABLED) {
4972 *timeout = alt_timeout;
4975 if (alt_timeout > *timeout)
4976 *timeout = alt_timeout;
4980 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4981 struct usb_device *udev,
4982 struct usb_host_interface *alt,
4983 enum usb3_link_state state,
4988 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4989 if (xhci_update_timeout_for_endpoint(xhci, udev,
4990 &alt->endpoint[j].desc, state, timeout))
4996 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4997 enum usb3_link_state state)
4999 struct usb_device *parent;
5000 unsigned int num_hubs;
5002 if (state == USB3_LPM_U2)
5005 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
5006 for (parent = udev->parent, num_hubs = 0; parent->parent;
5007 parent = parent->parent)
5013 dev_dbg(&udev->dev, "Disabling U1 link state for device"
5014 " below second-tier hub.\n");
5015 dev_dbg(&udev->dev, "Plug device into first-tier hub "
5016 "to decrease power consumption.\n");
5020 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
5021 struct usb_device *udev,
5022 enum usb3_link_state state)
5024 if (xhci->quirks & XHCI_INTEL_HOST)
5025 return xhci_check_intel_tier_policy(udev, state);
5030 /* Returns the U1 or U2 timeout that should be enabled.
5031 * If the tier check or timeout setting functions return with a non-zero exit
5032 * code, that means the timeout value has been finalized and we shouldn't look
5033 * at any more endpoints.
5035 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
5036 struct usb_device *udev, enum usb3_link_state state)
5038 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5039 struct usb_host_config *config;
5042 u16 timeout = USB3_LPM_DISABLED;
5044 if (state == USB3_LPM_U1)
5046 else if (state == USB3_LPM_U2)
5049 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
5054 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5057 /* Gather some information about the currently installed configuration
5058 * and alternate interface settings.
5060 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
5064 config = udev->actconfig;
5068 for (i = 0; i < config->desc.bNumInterfaces; i++) {
5069 struct usb_driver *driver;
5070 struct usb_interface *intf = config->interface[i];
5075 /* Check if any currently bound drivers want hub-initiated LPM
5078 if (intf->dev.driver) {
5079 driver = to_usb_driver(intf->dev.driver);
5080 if (driver && driver->disable_hub_initiated_lpm) {
5081 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
5082 state_name, driver->name);
5083 timeout = xhci_get_timeout_no_hub_lpm(udev,
5085 if (timeout == USB3_LPM_DISABLED)
5090 /* Not sure how this could happen... */
5091 if (!intf->cur_altsetting)
5094 if (xhci_update_timeout_for_interface(xhci, udev,
5095 intf->cur_altsetting,
5102 static int calculate_max_exit_latency(struct usb_device *udev,
5103 enum usb3_link_state state_changed,
5104 u16 hub_encoded_timeout)
5106 unsigned long long u1_mel_us = 0;
5107 unsigned long long u2_mel_us = 0;
5108 unsigned long long mel_us = 0;
5114 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5115 hub_encoded_timeout == USB3_LPM_DISABLED);
5116 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5117 hub_encoded_timeout == USB3_LPM_DISABLED);
5119 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5120 hub_encoded_timeout != USB3_LPM_DISABLED);
5121 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5122 hub_encoded_timeout != USB3_LPM_DISABLED);
5124 /* If U1 was already enabled and we're not disabling it,
5125 * or we're going to enable U1, account for the U1 max exit latency.
5127 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5129 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5130 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5132 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5134 if (u1_mel_us > u2_mel_us)
5138 /* xHCI host controller max exit latency field is only 16 bits wide. */
5139 if (mel_us > MAX_EXIT) {
5140 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5141 "is too big.\n", mel_us);
5147 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5148 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5149 struct usb_device *udev, enum usb3_link_state state)
5151 struct xhci_hcd *xhci;
5152 u16 hub_encoded_timeout;
5156 xhci = hcd_to_xhci(hcd);
5157 /* The LPM timeout values are pretty host-controller specific, so don't
5158 * enable hub-initiated timeouts unless the vendor has provided
5159 * information about their timeout algorithm.
5161 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5162 !xhci->devs[udev->slot_id])
5163 return USB3_LPM_DISABLED;
5165 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5166 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5168 /* Max Exit Latency is too big, disable LPM. */
5169 hub_encoded_timeout = USB3_LPM_DISABLED;
5173 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5176 return hub_encoded_timeout;
5179 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5180 struct usb_device *udev, enum usb3_link_state state)
5182 struct xhci_hcd *xhci;
5185 xhci = hcd_to_xhci(hcd);
5186 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5187 !xhci->devs[udev->slot_id])
5190 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5191 return xhci_change_max_exit_latency(xhci, udev, mel);
5193 #else /* CONFIG_PM */
5195 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5196 struct usb_device *udev, int enable)
5201 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5206 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5207 struct usb_device *udev, enum usb3_link_state state)
5209 return USB3_LPM_DISABLED;
5212 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5213 struct usb_device *udev, enum usb3_link_state state)
5217 #endif /* CONFIG_PM */
5219 /*-------------------------------------------------------------------------*/
5221 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5222 * internal data structures for the device.
5224 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5225 struct usb_tt *tt, gfp_t mem_flags)
5227 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5228 struct xhci_virt_device *vdev;
5229 struct xhci_command *config_cmd;
5230 struct xhci_input_control_ctx *ctrl_ctx;
5231 struct xhci_slot_ctx *slot_ctx;
5232 unsigned long flags;
5233 unsigned think_time;
5236 /* Ignore root hubs */
5240 vdev = xhci->devs[hdev->slot_id];
5242 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5246 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5250 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5252 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5254 xhci_free_command(xhci, config_cmd);
5258 spin_lock_irqsave(&xhci->lock, flags);
5259 if (hdev->speed == USB_SPEED_HIGH &&
5260 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5261 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5262 xhci_free_command(xhci, config_cmd);
5263 spin_unlock_irqrestore(&xhci->lock, flags);
5267 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5268 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5269 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5270 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5272 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5273 * but it may be already set to 1 when setup an xHCI virtual
5274 * device, so clear it anyway.
5277 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5278 else if (hdev->speed == USB_SPEED_FULL)
5279 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5281 if (xhci->hci_version > 0x95) {
5282 xhci_dbg(xhci, "xHCI version %x needs hub "
5283 "TT think time and number of ports\n",
5284 (unsigned int) xhci->hci_version);
5285 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5286 /* Set TT think time - convert from ns to FS bit times.
5287 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5288 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5290 * xHCI 1.0: this field shall be 0 if the device is not a
5293 think_time = tt->think_time;
5294 if (think_time != 0)
5295 think_time = (think_time / 666) - 1;
5296 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5297 slot_ctx->tt_info |=
5298 cpu_to_le32(TT_THINK_TIME(think_time));
5300 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5301 "TT think time or number of ports\n",
5302 (unsigned int) xhci->hci_version);
5304 slot_ctx->dev_state = 0;
5305 spin_unlock_irqrestore(&xhci->lock, flags);
5307 xhci_dbg(xhci, "Set up %s for hub device.\n",
5308 (xhci->hci_version > 0x95) ?
5309 "configure endpoint" : "evaluate context");
5311 /* Issue and wait for the configure endpoint or
5312 * evaluate context command.
5314 if (xhci->hci_version > 0x95)
5315 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5318 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5321 xhci_free_command(xhci, config_cmd);
5325 static int xhci_get_frame(struct usb_hcd *hcd)
5327 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5328 /* EHCI mods by the periodic size. Why? */
5329 return readl(&xhci->run_regs->microframe_index) >> 3;
5332 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5334 struct xhci_hcd *xhci;
5336 * TODO: Check with DWC3 clients for sysdev according to
5339 struct device *dev = hcd->self.sysdev;
5340 unsigned int minor_rev;
5343 /* Accept arbitrarily long scatter-gather lists */
5344 hcd->self.sg_tablesize = ~0;
5346 /* support to build packet from discontinuous buffers */
5347 hcd->self.no_sg_constraint = 1;
5349 /* XHCI controllers don't stop the ep queue on short packets :| */
5350 hcd->self.no_stop_on_short = 1;
5352 xhci = hcd_to_xhci(hcd);
5354 if (usb_hcd_is_primary_hcd(hcd)) {
5355 xhci->main_hcd = hcd;
5356 xhci->usb2_rhub.hcd = hcd;
5357 /* Mark the first roothub as being USB 2.0.
5358 * The xHCI driver will register the USB 3.0 roothub.
5360 hcd->speed = HCD_USB2;
5361 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5363 * USB 2.0 roothub under xHCI has an integrated TT,
5364 * (rate matching hub) as opposed to having an OHCI/UHCI
5365 * companion controller.
5370 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5371 * should return 0x31 for sbrn, or that the minor revision
5372 * is a two digit BCD containig minor and sub-minor numbers.
5373 * This was later clarified in xHCI 1.2.
5375 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5376 * minor revision set to 0x1 instead of 0x10.
5378 if (xhci->usb3_rhub.min_rev == 0x1)
5381 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5383 switch (minor_rev) {
5385 hcd->speed = HCD_USB32;
5386 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5387 hcd->self.root_hub->rx_lanes = 2;
5388 hcd->self.root_hub->tx_lanes = 2;
5389 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5392 hcd->speed = HCD_USB31;
5393 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5394 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5397 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5399 minor_rev ? "Enhanced " : "");
5401 xhci->usb3_rhub.hcd = hcd;
5402 /* xHCI private pointer was set in xhci_pci_probe for the second
5403 * registered roothub.
5408 mutex_init(&xhci->mutex);
5409 xhci->cap_regs = hcd->regs;
5410 xhci->op_regs = hcd->regs +
5411 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5412 xhci->run_regs = hcd->regs +
5413 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5414 /* Cache read-only capability registers */
5415 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5416 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5417 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5418 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5419 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5420 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5421 if (xhci->hci_version > 0x100)
5422 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5424 xhci->quirks |= quirks;
5426 get_quirks(dev, xhci);
5428 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5429 * success event after a short transfer. This quirk will ignore such
5432 if (xhci->hci_version > 0x96)
5433 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5435 /* Make sure the HC is halted. */
5436 retval = xhci_halt(xhci);
5440 xhci_zero_64b_regs(xhci);
5442 xhci_dbg(xhci, "Resetting HCD\n");
5443 /* Reset the internal HC memory state and registers. */
5444 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5447 xhci_dbg(xhci, "Reset complete\n");
5450 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5451 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5452 * address memory pointers actually. So, this driver clears the AC64
5453 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5454 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5456 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5457 xhci->hcc_params &= ~BIT(0);
5459 /* Set dma_mask and coherent_dma_mask to 64-bits,
5460 * if xHC supports 64-bit addressing */
5461 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5462 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5463 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5464 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5467 * This is to avoid error in cases where a 32-bit USB
5468 * controller is used on a 64-bit capable system.
5470 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5473 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5474 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5477 xhci_dbg(xhci, "Calling HCD init\n");
5478 /* Initialize HCD and host controller data structures. */
5479 retval = xhci_init(hcd);
5482 xhci_dbg(xhci, "Called HCD init\n");
5484 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5485 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5489 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5491 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5492 struct usb_host_endpoint *ep)
5494 struct xhci_hcd *xhci;
5495 struct usb_device *udev;
5496 unsigned int slot_id;
5497 unsigned int ep_index;
5498 unsigned long flags;
5500 xhci = hcd_to_xhci(hcd);
5502 spin_lock_irqsave(&xhci->lock, flags);
5503 udev = (struct usb_device *)ep->hcpriv;
5504 slot_id = udev->slot_id;
5505 ep_index = xhci_get_endpoint_index(&ep->desc);
5507 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5508 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5509 spin_unlock_irqrestore(&xhci->lock, flags);
5512 static const struct hc_driver xhci_hc_driver = {
5513 .description = "xhci-hcd",
5514 .product_desc = "xHCI Host Controller",
5515 .hcd_priv_size = sizeof(struct xhci_hcd),
5518 * generic hardware linkage
5521 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5525 * basic lifecycle operations
5527 .reset = NULL, /* set in xhci_init_driver() */
5530 .shutdown = xhci_shutdown,
5533 * managing i/o requests and associated device resources
5535 .map_urb_for_dma = xhci_map_urb_for_dma,
5536 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5537 .urb_enqueue = xhci_urb_enqueue,
5538 .urb_dequeue = xhci_urb_dequeue,
5539 .alloc_dev = xhci_alloc_dev,
5540 .free_dev = xhci_free_dev,
5541 .alloc_streams = xhci_alloc_streams,
5542 .free_streams = xhci_free_streams,
5543 .add_endpoint = xhci_add_endpoint,
5544 .drop_endpoint = xhci_drop_endpoint,
5545 .endpoint_disable = xhci_endpoint_disable,
5546 .endpoint_reset = xhci_endpoint_reset,
5547 .check_bandwidth = xhci_check_bandwidth,
5548 .reset_bandwidth = xhci_reset_bandwidth,
5549 .fixup_endpoint = xhci_fixup_endpoint,
5550 .address_device = xhci_address_device,
5551 .enable_device = xhci_enable_device,
5552 .update_hub_device = xhci_update_hub_device,
5553 .reset_device = xhci_discover_or_reset_device,
5556 * scheduling support
5558 .get_frame_number = xhci_get_frame,
5563 .hub_control = xhci_hub_control,
5564 .hub_status_data = xhci_hub_status_data,
5565 .bus_suspend = xhci_bus_suspend,
5566 .bus_resume = xhci_bus_resume,
5567 .get_resuming_ports = xhci_get_resuming_ports,
5570 * call back when device connected and addressed
5572 .update_device = xhci_update_device,
5573 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5574 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5575 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5576 .find_raw_port_number = xhci_find_raw_port_number,
5577 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5580 void xhci_init_driver(struct hc_driver *drv,
5581 const struct xhci_driver_overrides *over)
5585 /* Copy the generic table to drv then apply the overrides */
5586 *drv = xhci_hc_driver;
5589 drv->hcd_priv_size += over->extra_priv_size;
5591 drv->reset = over->reset;
5593 drv->start = over->start;
5594 if (over->add_endpoint)
5595 drv->add_endpoint = over->add_endpoint;
5596 if (over->drop_endpoint)
5597 drv->drop_endpoint = over->drop_endpoint;
5598 if (over->check_bandwidth)
5599 drv->check_bandwidth = over->check_bandwidth;
5600 if (over->reset_bandwidth)
5601 drv->reset_bandwidth = over->reset_bandwidth;
5604 EXPORT_SYMBOL_GPL(xhci_init_driver);
5606 MODULE_DESCRIPTION(DRIVER_DESC);
5607 MODULE_AUTHOR(DRIVER_AUTHOR);
5608 MODULE_LICENSE("GPL");
5610 static int __init xhci_hcd_init(void)
5613 * Check the compiler generated sizes of structures that must be laid
5614 * out in specific ways for hardware access.
5616 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5617 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5618 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5619 /* xhci_device_control has eight fields, and also
5620 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5622 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5623 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5624 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5625 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5626 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5627 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5628 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5633 xhci_debugfs_create_root();
5639 * If an init function is provided, an exit function must also be provided
5640 * to allow module unload.
5642 static void __exit xhci_hcd_fini(void)
5644 xhci_debugfs_remove_root();
5647 module_init(xhci_hcd_init);
5648 module_exit(xhci_hcd_fini);