1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
55 /* TODO: copied from ehci-hcd.c - can this be refactored? */
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
75 if (result == ~(u32)0) /* card removed */
87 * Disable interrupts and begin the xHCI halting process.
89 void xhci_quiesce(struct xhci_hcd *xhci)
96 halted = readl(&xhci->op_regs->status) & STS_HALT;
100 cmd = readl(&xhci->op_regs->command);
102 writel(cmd, &xhci->op_regs->command);
106 * Force HC into halt state.
108 * Disable any IRQs and clear the run/stop bit.
109 * HC will complete any current and actively pipelined transactions, and
110 * should halt within 16 ms of the run/stop bit being cleared.
111 * Read HC Halted bit in the status register to see when the HC is finished.
113 int xhci_halt(struct xhci_hcd *xhci)
116 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
119 ret = xhci_handshake(&xhci->op_regs->status,
120 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
122 xhci_warn(xhci, "Host halt failed, %d\n", ret);
125 xhci->xhc_state |= XHCI_STATE_HALTED;
126 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
164 * This resets pipelines, timers, counters, state machines, etc.
165 * Transactions will be terminated immediately, and operational registers
166 * will be set to their defaults.
168 int xhci_reset(struct xhci_hcd *xhci)
174 state = readl(&xhci->op_regs->status);
176 if (state == ~(u32)0) {
177 xhci_warn(xhci, "Host not accessible, reset failed.\n");
181 if ((state & STS_HALT) == 0) {
182 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
187 command = readl(&xhci->op_regs->command);
188 command |= CMD_RESET;
189 writel(command, &xhci->op_regs->command);
191 /* Existing Intel xHCI controllers require a delay of 1 mS,
192 * after setting the CMD_RESET bit, and before accessing any
193 * HC registers. This allows the HC to complete the
194 * reset operation and be ready for HC register access.
195 * Without this delay, the subsequent HC register access,
196 * may result in a system hang very rarely.
198 if (xhci->quirks & XHCI_INTEL_HOST)
201 ret = xhci_handshake(&xhci->op_regs->command,
202 CMD_RESET, 0, 10 * 1000 * 1000);
206 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
207 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
210 "Wait for controller to be ready for doorbell rings");
212 * xHCI cannot write to any doorbells or operational registers other
213 * than status until the "Controller Not Ready" flag is cleared.
215 ret = xhci_handshake(&xhci->op_regs->status,
216 STS_CNR, 0, 10 * 1000 * 1000);
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
228 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
235 * Some Renesas controllers get into a weird state if they are
236 * reset while programmed with 64bit addresses (they will preserve
237 * the top half of the address in internal, non visible
238 * registers). You end up with half the address coming from the
239 * kernel, and the other half coming from the firmware. Also,
240 * changing the programming leads to extra accesses even if the
241 * controller is supposed to be halted. The controller ends up with
242 * a fatal fault, and is then ripe for being properly reset.
244 * Special care is taken to only apply this if the device is behind
245 * an iommu. Doing anything when there is no iommu is definitely
248 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
251 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
253 /* Clear HSEIE so that faults do not get signaled */
254 val = readl(&xhci->op_regs->command);
256 writel(val, &xhci->op_regs->command);
258 /* Clear HSE (aka FATAL) */
259 val = readl(&xhci->op_regs->status);
261 writel(val, &xhci->op_regs->status);
263 /* Now zero the registers, and brace for impact */
264 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
265 if (upper_32_bits(val))
266 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
267 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
268 if (upper_32_bits(val))
269 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
271 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
272 struct xhci_intr_reg __iomem *ir;
274 ir = &xhci->run_regs->ir_set[i];
275 val = xhci_read_64(xhci, &ir->erst_base);
276 if (upper_32_bits(val))
277 xhci_write_64(xhci, 0, &ir->erst_base);
278 val= xhci_read_64(xhci, &ir->erst_dequeue);
279 if (upper_32_bits(val))
280 xhci_write_64(xhci, 0, &ir->erst_dequeue);
283 /* Wait for the fault to appear. It will be cleared on reset */
284 err = xhci_handshake(&xhci->op_regs->status,
285 STS_FATAL, STS_FATAL,
288 xhci_info(xhci, "Fault detected\n");
291 #ifdef CONFIG_USB_PCI
295 static int xhci_setup_msi(struct xhci_hcd *xhci)
299 * TODO:Check with MSI Soc for sysdev
301 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
303 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
305 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
306 "failed to allocate MSI entry");
310 ret = request_irq(pdev->irq, xhci_msi_irq,
311 0, "xhci_hcd", xhci_to_hcd(xhci));
313 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
314 "disable MSI interrupt");
315 pci_free_irq_vectors(pdev);
324 static int xhci_setup_msix(struct xhci_hcd *xhci)
327 struct usb_hcd *hcd = xhci_to_hcd(xhci);
328 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
331 * calculate number of msi-x vectors supported.
332 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
333 * with max number of interrupters based on the xhci HCSPARAMS1.
334 * - num_online_cpus: maximum msi-x vectors per CPUs core.
335 * Add additional 1 vector to ensure always available interrupt.
337 xhci->msix_count = min(num_online_cpus() + 1,
338 HCS_MAX_INTRS(xhci->hcs_params1));
340 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
343 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
344 "Failed to enable MSI-X");
348 for (i = 0; i < xhci->msix_count; i++) {
349 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
350 "xhci_hcd", xhci_to_hcd(xhci));
355 hcd->msix_enabled = 1;
359 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
361 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
362 pci_free_irq_vectors(pdev);
366 /* Free any IRQs and disable MSI-X */
367 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
369 struct usb_hcd *hcd = xhci_to_hcd(xhci);
370 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
372 if (xhci->quirks & XHCI_PLAT)
375 /* return if using legacy interrupt */
379 if (hcd->msix_enabled) {
382 for (i = 0; i < xhci->msix_count; i++)
383 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
385 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
388 pci_free_irq_vectors(pdev);
389 hcd->msix_enabled = 0;
392 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
394 struct usb_hcd *hcd = xhci_to_hcd(xhci);
396 if (hcd->msix_enabled) {
397 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
400 for (i = 0; i < xhci->msix_count; i++)
401 synchronize_irq(pci_irq_vector(pdev, i));
405 static int xhci_try_enable_msi(struct usb_hcd *hcd)
407 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
408 struct pci_dev *pdev;
411 /* The xhci platform device has set up IRQs through usb_add_hcd. */
412 if (xhci->quirks & XHCI_PLAT)
415 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
417 * Some Fresco Logic host controllers advertise MSI, but fail to
418 * generate interrupts. Don't even try to enable MSI.
420 if (xhci->quirks & XHCI_BROKEN_MSI)
423 /* unregister the legacy interrupt */
425 free_irq(hcd->irq, hcd);
428 ret = xhci_setup_msix(xhci);
430 /* fall back to msi*/
431 ret = xhci_setup_msi(xhci);
434 hcd->msi_enabled = 1;
439 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
444 if (!strlen(hcd->irq_descr))
445 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
446 hcd->driver->description, hcd->self.busnum);
448 /* fall back to legacy interrupt*/
449 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
450 hcd->irq_descr, hcd);
452 xhci_err(xhci, "request interrupt %d failed\n",
456 hcd->irq = pdev->irq;
462 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
467 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
471 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
477 static void compliance_mode_recovery(struct timer_list *t)
479 struct xhci_hcd *xhci;
481 struct xhci_hub *rhub;
485 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
486 rhub = &xhci->usb3_rhub;
488 for (i = 0; i < rhub->num_ports; i++) {
489 temp = readl(rhub->ports[i]->addr);
490 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
492 * Compliance Mode Detected. Letting USB Core
493 * handle the Warm Reset
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode detected->port %d",
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Attempting compliance mode recovery");
500 hcd = xhci->shared_hcd;
502 if (hcd->state == HC_STATE_SUSPENDED)
503 usb_hcd_resume_root_hub(hcd);
505 usb_hcd_poll_rh_status(hcd);
509 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
510 mod_timer(&xhci->comp_mode_recovery_timer,
511 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
515 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
516 * that causes ports behind that hardware to enter compliance mode sometimes.
517 * The quirk creates a timer that polls every 2 seconds the link state of
518 * each host controller's port and recovers it by issuing a Warm reset
519 * if Compliance mode is detected, otherwise the port will become "dead" (no
520 * device connections or disconnections will be detected anymore). Becasue no
521 * status event is generated when entering compliance mode (per xhci spec),
522 * this quirk is needed on systems that have the failing hardware installed.
524 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
526 xhci->port_status_u0 = 0;
527 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
529 xhci->comp_mode_recovery_timer.expires = jiffies +
530 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
532 add_timer(&xhci->comp_mode_recovery_timer);
533 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
534 "Compliance mode recovery timer initialized");
538 * This function identifies the systems that have installed the SN65LVPE502CP
539 * USB3.0 re-driver and that need the Compliance Mode Quirk.
541 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
543 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
545 const char *dmi_product_name, *dmi_sys_vendor;
547 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
548 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
549 if (!dmi_product_name || !dmi_sys_vendor)
552 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
555 if (strstr(dmi_product_name, "Z420") ||
556 strstr(dmi_product_name, "Z620") ||
557 strstr(dmi_product_name, "Z820") ||
558 strstr(dmi_product_name, "Z1 Workstation"))
564 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
566 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
571 * Initialize memory for HCD and xHC (one-time init).
573 * Program the PAGESIZE register, initialize the device context array, create
574 * device contexts (?), set up a command ring segment (or two?), create event
575 * ring (one for now).
577 static int xhci_init(struct usb_hcd *hcd)
579 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
582 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
583 spin_lock_init(&xhci->lock);
584 if (xhci->hci_version == 0x95 && link_quirk) {
585 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
586 "QUIRK: Not clearing Link TRB chain bits.");
587 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
590 "xHCI doesn't need link TRB QUIRK");
592 retval = xhci_mem_init(xhci, GFP_KERNEL);
593 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
595 /* Initializing Compliance Mode Recovery Data If Needed */
596 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
597 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
598 compliance_mode_recovery_timer_init(xhci);
604 /*-------------------------------------------------------------------------*/
607 static int xhci_run_finished(struct xhci_hcd *xhci)
609 if (xhci_start(xhci)) {
613 xhci->shared_hcd->state = HC_STATE_RUNNING;
614 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
616 if (xhci->quirks & XHCI_NEC_HOST)
617 xhci_ring_cmd_db(xhci);
619 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
620 "Finished xhci_run for USB3 roothub");
625 * Start the HC after it was halted.
627 * This function is called by the USB core when the HC driver is added.
628 * Its opposite is xhci_stop().
630 * xhci_init() must be called once before this function can be called.
631 * Reset the HC, enable device slot contexts, program DCBAAP, and
632 * set command ring pointer and event ring pointer.
634 * Setup MSI-X vectors and enable interrupts.
636 int xhci_run(struct usb_hcd *hcd)
641 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
643 /* Start the xHCI host controller running only after the USB 2.0 roothub
647 hcd->uses_new_polling = 1;
648 if (!usb_hcd_is_primary_hcd(hcd))
649 return xhci_run_finished(xhci);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
653 ret = xhci_try_enable_msi(hcd);
657 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
658 temp_64 &= ~ERST_PTR_MASK;
659 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
660 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
662 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
663 "// Set the interrupt modulation register");
664 temp = readl(&xhci->ir_set->irq_control);
665 temp &= ~ER_IRQ_INTERVAL_MASK;
666 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
667 writel(temp, &xhci->ir_set->irq_control);
669 /* Set the HCD state before we enable the irqs */
670 temp = readl(&xhci->op_regs->command);
672 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
673 "// Enable interrupts, cmd = 0x%x.", temp);
674 writel(temp, &xhci->op_regs->command);
676 temp = readl(&xhci->ir_set->irq_pending);
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
678 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
679 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
680 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
682 if (xhci->quirks & XHCI_NEC_HOST) {
683 struct xhci_command *command;
685 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
689 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
690 TRB_TYPE(TRB_NEC_GET_FW));
692 xhci_free_command(xhci, command);
694 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
695 "Finished xhci_run for USB2 roothub");
699 xhci_debugfs_init(xhci);
703 EXPORT_SYMBOL_GPL(xhci_run);
708 * This function is called by the USB core when the HC driver is removed.
709 * Its opposite is xhci_run().
711 * Disable device contexts, disable IRQs, and quiesce the HC.
712 * Reset the HC, finish any completed transactions, and cleanup memory.
714 static void xhci_stop(struct usb_hcd *hcd)
717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
719 mutex_lock(&xhci->mutex);
721 /* Only halt host and free memory after both hcds are removed */
722 if (!usb_hcd_is_primary_hcd(hcd)) {
723 mutex_unlock(&xhci->mutex);
729 spin_lock_irq(&xhci->lock);
730 xhci->xhc_state |= XHCI_STATE_HALTED;
731 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
734 spin_unlock_irq(&xhci->lock);
736 xhci_cleanup_msix(xhci);
738 /* Deleting Compliance Mode Recovery Timer */
739 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
740 (!(xhci_all_ports_seen_u0(xhci)))) {
741 del_timer_sync(&xhci->comp_mode_recovery_timer);
742 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
743 "%s: compliance mode recovery timer deleted",
747 if (xhci->quirks & XHCI_AMD_PLL_FIX)
750 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
751 "// Disabling event ring interrupts");
752 temp = readl(&xhci->op_regs->status);
753 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
754 temp = readl(&xhci->ir_set->irq_pending);
755 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
757 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
758 xhci_mem_cleanup(xhci);
759 xhci_debugfs_exit(xhci);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
761 "xhci_stop completed - status = %x",
762 readl(&xhci->op_regs->status));
763 mutex_unlock(&xhci->mutex);
767 * Shutdown HC (not bus-specific)
769 * This is called when the machine is rebooting or halting. We assume that the
770 * machine will be powered off, and the HC's internal state will be reset.
771 * Don't bother to free memory.
773 * This will only ever be called with the main usb_hcd (the USB3 roothub).
775 static void xhci_shutdown(struct usb_hcd *hcd)
777 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
779 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
780 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
782 spin_lock_irq(&xhci->lock);
784 /* Workaround for spurious wakeups at shutdown with HSW */
785 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
787 spin_unlock_irq(&xhci->lock);
789 xhci_cleanup_msix(xhci);
791 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
792 "xhci_shutdown completed - status = %x",
793 readl(&xhci->op_regs->status));
795 /* Yet another workaround for spurious wakeups at shutdown with HSW */
796 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
797 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
801 static void xhci_save_registers(struct xhci_hcd *xhci)
803 xhci->s3.command = readl(&xhci->op_regs->command);
804 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
805 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
806 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
807 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
808 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
809 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
810 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
811 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
814 static void xhci_restore_registers(struct xhci_hcd *xhci)
816 writel(xhci->s3.command, &xhci->op_regs->command);
817 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
818 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
819 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
820 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
821 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
822 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
823 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
824 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
827 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
831 /* step 2: initialize command ring buffer */
832 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
833 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
834 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
835 xhci->cmd_ring->dequeue) &
836 (u64) ~CMD_RING_RSVD_BITS) |
837 xhci->cmd_ring->cycle_state;
838 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
839 "// Setting command ring address to 0x%llx",
840 (long unsigned long) val_64);
841 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
845 * The whole command ring must be cleared to zero when we suspend the host.
847 * The host doesn't save the command ring pointer in the suspend well, so we
848 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
849 * aligned, because of the reserved bits in the command ring dequeue pointer
850 * register. Therefore, we can't just set the dequeue pointer back in the
851 * middle of the ring (TRBs are 16-byte aligned).
853 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
855 struct xhci_ring *ring;
856 struct xhci_segment *seg;
858 ring = xhci->cmd_ring;
862 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
863 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
864 cpu_to_le32(~TRB_CYCLE);
866 } while (seg != ring->deq_seg);
868 /* Reset the software enqueue and dequeue pointers */
869 ring->deq_seg = ring->first_seg;
870 ring->dequeue = ring->first_seg->trbs;
871 ring->enq_seg = ring->deq_seg;
872 ring->enqueue = ring->dequeue;
874 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
876 * Ring is now zeroed, so the HW should look for change of ownership
877 * when the cycle bit is set to 1.
879 ring->cycle_state = 1;
882 * Reset the hardware dequeue pointer.
883 * Yes, this will need to be re-written after resume, but we're paranoid
884 * and want to make sure the hardware doesn't access bogus memory
885 * because, say, the BIOS or an SMI started the host without changing
886 * the command ring pointers.
888 xhci_set_cmd_ring_deq(xhci);
891 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
893 struct xhci_port **ports;
898 spin_lock_irqsave(&xhci->lock, flags);
900 /* disable usb3 ports Wake bits */
901 port_index = xhci->usb3_rhub.num_ports;
902 ports = xhci->usb3_rhub.ports;
903 while (port_index--) {
904 t1 = readl(ports[port_index]->addr);
906 t1 = xhci_port_state_to_neutral(t1);
907 t2 = t1 & ~PORT_WAKE_BITS;
909 writel(t2, ports[port_index]->addr);
910 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
911 xhci->usb3_rhub.hcd->self.busnum,
912 port_index + 1, portsc, t2);
916 /* disable usb2 ports Wake bits */
917 port_index = xhci->usb2_rhub.num_ports;
918 ports = xhci->usb2_rhub.ports;
919 while (port_index--) {
920 t1 = readl(ports[port_index]->addr);
922 t1 = xhci_port_state_to_neutral(t1);
923 t2 = t1 & ~PORT_WAKE_BITS;
925 writel(t2, ports[port_index]->addr);
926 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
927 xhci->usb2_rhub.hcd->self.busnum,
928 port_index + 1, portsc, t2);
931 spin_unlock_irqrestore(&xhci->lock, flags);
934 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
936 struct xhci_port **ports;
941 status = readl(&xhci->op_regs->status);
942 if (status & STS_EINT)
945 * Checking STS_EINT is not enough as there is a lag between a change
946 * bit being set and the Port Status Change Event that it generated
947 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
950 port_index = xhci->usb2_rhub.num_ports;
951 ports = xhci->usb2_rhub.ports;
952 while (port_index--) {
953 portsc = readl(ports[port_index]->addr);
954 if (portsc & PORT_CHANGE_MASK ||
955 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
958 port_index = xhci->usb3_rhub.num_ports;
959 ports = xhci->usb3_rhub.ports;
960 while (port_index--) {
961 portsc = readl(ports[port_index]->addr);
962 if (portsc & PORT_CHANGE_MASK ||
963 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
970 * Stop HC (not bus-specific)
972 * This is called when the machine transition into S3/S4 mode.
975 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
978 unsigned int delay = XHCI_MAX_HALT_USEC;
979 struct usb_hcd *hcd = xhci_to_hcd(xhci);
986 if (hcd->state != HC_STATE_SUSPENDED ||
987 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
990 xhci_dbc_suspend(xhci);
992 /* Clear root port wake on bits if wakeup not allowed. */
994 xhci_disable_port_wake_on_bits(xhci);
996 /* Don't poll the roothubs on bus suspend. */
997 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
998 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
999 del_timer_sync(&hcd->rh_timer);
1000 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1001 del_timer_sync(&xhci->shared_hcd->rh_timer);
1003 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1004 usleep_range(1000, 1500);
1006 spin_lock_irq(&xhci->lock);
1007 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1008 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1009 /* step 1: stop endpoint */
1010 /* skipped assuming that port suspend has done */
1012 /* step 2: clear Run/Stop bit */
1013 command = readl(&xhci->op_regs->command);
1014 command &= ~CMD_RUN;
1015 writel(command, &xhci->op_regs->command);
1017 /* Some chips from Fresco Logic need an extraordinary delay */
1018 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1020 if (xhci_handshake(&xhci->op_regs->status,
1021 STS_HALT, STS_HALT, delay)) {
1022 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1023 spin_unlock_irq(&xhci->lock);
1026 xhci_clear_command_ring(xhci);
1028 /* step 3: save registers */
1029 xhci_save_registers(xhci);
1031 /* step 4: set CSS flag */
1032 command = readl(&xhci->op_regs->command);
1034 writel(command, &xhci->op_regs->command);
1035 xhci->broken_suspend = 0;
1036 if (xhci_handshake(&xhci->op_regs->status,
1037 STS_SAVE, 0, 10 * 1000)) {
1039 * AMD SNPS xHC 3.0 occasionally does not clear the
1040 * SSS bit of USBSTS and when driver tries to poll
1041 * to see if the xHC clears BIT(8) which never happens
1042 * and driver assumes that controller is not responding
1043 * and times out. To workaround this, its good to check
1044 * if SRE and HCE bits are not set (as per xhci
1045 * Section 5.4.2) and bypass the timeout.
1047 res = readl(&xhci->op_regs->status);
1048 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1049 (((res & STS_SRE) == 0) &&
1050 ((res & STS_HCE) == 0))) {
1051 xhci->broken_suspend = 1;
1053 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1054 spin_unlock_irq(&xhci->lock);
1058 spin_unlock_irq(&xhci->lock);
1061 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1062 * is about to be suspended.
1064 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1065 (!(xhci_all_ports_seen_u0(xhci)))) {
1066 del_timer_sync(&xhci->comp_mode_recovery_timer);
1067 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1068 "%s: compliance mode recovery timer deleted",
1072 /* step 5: remove core well power */
1073 /* synchronize irq when using MSI-X */
1074 xhci_msix_sync_irqs(xhci);
1078 EXPORT_SYMBOL_GPL(xhci_suspend);
1081 * start xHC (not bus-specific)
1083 * This is called when the machine transition from S3/S4 mode.
1086 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1088 u32 command, temp = 0;
1089 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1090 struct usb_hcd *secondary_hcd;
1092 bool comp_timer_running = false;
1097 /* Wait a bit if either of the roothubs need to settle from the
1098 * transition into bus suspend.
1101 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1102 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1105 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1106 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1108 spin_lock_irq(&xhci->lock);
1109 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1113 /* step 1: restore register */
1114 xhci_restore_registers(xhci);
1115 /* step 2: initialize command ring buffer */
1116 xhci_set_cmd_ring_deq(xhci);
1117 /* step 3: restore state and start state*/
1118 /* step 3: set CRS flag */
1119 command = readl(&xhci->op_regs->command);
1121 writel(command, &xhci->op_regs->command);
1123 * Some controllers take up to 55+ ms to complete the controller
1124 * restore so setting the timeout to 100ms. Xhci specification
1125 * doesn't mention any timeout value.
1127 if (xhci_handshake(&xhci->op_regs->status,
1128 STS_RESTORE, 0, 100 * 1000)) {
1129 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1130 spin_unlock_irq(&xhci->lock);
1133 temp = readl(&xhci->op_regs->status);
1136 /* If restore operation fails, re-initialize the HC during resume */
1137 if ((temp & STS_SRE) || hibernated) {
1139 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1140 !(xhci_all_ports_seen_u0(xhci))) {
1141 del_timer_sync(&xhci->comp_mode_recovery_timer);
1142 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1143 "Compliance Mode Recovery Timer deleted!");
1146 /* Let the USB core know _both_ roothubs lost power. */
1147 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1148 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1150 xhci_dbg(xhci, "Stop HCD\n");
1152 xhci_zero_64b_regs(xhci);
1154 spin_unlock_irq(&xhci->lock);
1155 xhci_cleanup_msix(xhci);
1157 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1158 temp = readl(&xhci->op_regs->status);
1159 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1160 temp = readl(&xhci->ir_set->irq_pending);
1161 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1163 xhci_dbg(xhci, "cleaning up memory\n");
1164 xhci_mem_cleanup(xhci);
1165 xhci_debugfs_exit(xhci);
1166 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1167 readl(&xhci->op_regs->status));
1169 /* USB core calls the PCI reinit and start functions twice:
1170 * first with the primary HCD, and then with the secondary HCD.
1171 * If we don't do the same, the host will never be started.
1173 if (!usb_hcd_is_primary_hcd(hcd))
1174 secondary_hcd = hcd;
1176 secondary_hcd = xhci->shared_hcd;
1178 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1179 retval = xhci_init(hcd->primary_hcd);
1182 comp_timer_running = true;
1184 xhci_dbg(xhci, "Start the primary HCD\n");
1185 retval = xhci_run(hcd->primary_hcd);
1187 xhci_dbg(xhci, "Start the secondary HCD\n");
1188 retval = xhci_run(secondary_hcd);
1190 hcd->state = HC_STATE_SUSPENDED;
1191 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1195 /* step 4: set Run/Stop bit */
1196 command = readl(&xhci->op_regs->command);
1198 writel(command, &xhci->op_regs->command);
1199 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1202 /* step 5: walk topology and initialize portsc,
1203 * portpmsc and portli
1205 /* this is done in bus_resume */
1207 /* step 6: restart each of the previously
1208 * Running endpoints by ringing their doorbells
1211 spin_unlock_irq(&xhci->lock);
1213 xhci_dbc_resume(xhci);
1217 /* Resume root hubs only when have pending events. */
1218 if (xhci_pending_portevent(xhci)) {
1219 usb_hcd_resume_root_hub(xhci->shared_hcd);
1220 usb_hcd_resume_root_hub(hcd);
1225 * If system is subject to the Quirk, Compliance Mode Timer needs to
1226 * be re-initialized Always after a system resume. Ports are subject
1227 * to suffer the Compliance Mode issue again. It doesn't matter if
1228 * ports have entered previously to U0 before system's suspension.
1230 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1231 compliance_mode_recovery_timer_init(xhci);
1233 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1234 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1236 /* Re-enable port polling. */
1237 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1238 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1239 usb_hcd_poll_rh_status(xhci->shared_hcd);
1240 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1241 usb_hcd_poll_rh_status(hcd);
1245 EXPORT_SYMBOL_GPL(xhci_resume);
1246 #endif /* CONFIG_PM */
1248 /*-------------------------------------------------------------------------*/
1251 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1252 * we'll copy the actual data into the TRB address register. This is limited to
1253 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1254 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1256 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1259 if (xhci_urb_suitable_for_idt(urb))
1262 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1266 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1267 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1268 * value to right shift 1 for the bitmask.
1270 * Index = (epnum * 2) + direction - 1,
1271 * where direction = 0 for OUT, 1 for IN.
1272 * For control endpoints, the IN index is used (OUT index is unused), so
1273 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1275 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1278 if (usb_endpoint_xfer_control(desc))
1279 index = (unsigned int) (usb_endpoint_num(desc)*2);
1281 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1282 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1286 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1287 * address from the XHCI endpoint index.
1289 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1291 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1292 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1293 return direction | number;
1296 /* Find the flag for this endpoint (for use in the control context). Use the
1297 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1300 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1302 return 1 << (xhci_get_endpoint_index(desc) + 1);
1305 /* Find the flag for this endpoint (for use in the control context). Use the
1306 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1309 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1311 return 1 << (ep_index + 1);
1314 /* Compute the last valid endpoint context index. Basically, this is the
1315 * endpoint index plus one. For slot contexts with more than valid endpoint,
1316 * we find the most significant bit set in the added contexts flags.
1317 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1318 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1320 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1322 return fls(added_ctxs) - 1;
1325 /* Returns 1 if the arguments are OK;
1326 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1328 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1329 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1331 struct xhci_hcd *xhci;
1332 struct xhci_virt_device *virt_dev;
1334 if (!hcd || (check_ep && !ep) || !udev) {
1335 pr_debug("xHCI %s called with invalid args\n", func);
1338 if (!udev->parent) {
1339 pr_debug("xHCI %s called for root hub\n", func);
1343 xhci = hcd_to_xhci(hcd);
1344 if (check_virt_dev) {
1345 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1346 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1351 virt_dev = xhci->devs[udev->slot_id];
1352 if (virt_dev->udev != udev) {
1353 xhci_dbg(xhci, "xHCI %s called with udev and "
1354 "virt_dev does not match\n", func);
1359 if (xhci->xhc_state & XHCI_STATE_HALTED)
1365 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1366 struct usb_device *udev, struct xhci_command *command,
1367 bool ctx_change, bool must_succeed);
1370 * Full speed devices may have a max packet size greater than 8 bytes, but the
1371 * USB core doesn't know that until it reads the first 8 bytes of the
1372 * descriptor. If the usb_device's max packet size changes after that point,
1373 * we need to issue an evaluate context command and wait on it.
1375 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1376 unsigned int ep_index, struct urb *urb)
1378 struct xhci_container_ctx *out_ctx;
1379 struct xhci_input_control_ctx *ctrl_ctx;
1380 struct xhci_ep_ctx *ep_ctx;
1381 struct xhci_command *command;
1382 int max_packet_size;
1383 int hw_max_packet_size;
1386 out_ctx = xhci->devs[slot_id]->out_ctx;
1387 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1388 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1389 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1390 if (hw_max_packet_size != max_packet_size) {
1391 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1392 "Max Packet Size for ep 0 changed.");
1393 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1394 "Max packet size in usb_device = %d",
1396 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1397 "Max packet size in xHCI HW = %d",
1398 hw_max_packet_size);
1399 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1400 "Issuing evaluate context command.");
1402 /* Set up the input context flags for the command */
1403 /* FIXME: This won't work if a non-default control endpoint
1404 * changes max packet sizes.
1407 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1411 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1412 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1414 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1417 goto command_cleanup;
1419 /* Set up the modified control endpoint 0 */
1420 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1421 xhci->devs[slot_id]->out_ctx, ep_index);
1423 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1424 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1425 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1427 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1428 ctrl_ctx->drop_flags = 0;
1430 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1433 /* Clean up the input context for later use by bandwidth
1436 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1438 kfree(command->completion);
1445 * non-error returns are a promise to giveback() the urb later
1446 * we drop ownership so next owner (or urb unlink) can get it
1448 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1450 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1451 unsigned long flags;
1453 unsigned int slot_id, ep_index;
1454 unsigned int *ep_state;
1455 struct urb_priv *urb_priv;
1458 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1459 true, true, __func__) <= 0)
1462 slot_id = urb->dev->slot_id;
1463 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1464 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1466 if (!HCD_HW_ACCESSIBLE(hcd)) {
1467 if (!in_interrupt())
1468 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1472 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1473 num_tds = urb->number_of_packets;
1474 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1475 urb->transfer_buffer_length > 0 &&
1476 urb->transfer_flags & URB_ZERO_PACKET &&
1477 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1482 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1486 urb_priv->num_tds = num_tds;
1487 urb_priv->num_tds_done = 0;
1488 urb->hcpriv = urb_priv;
1490 trace_xhci_urb_enqueue(urb);
1492 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1493 /* Check to see if the max packet size for the default control
1494 * endpoint changed during FS device enumeration
1496 if (urb->dev->speed == USB_SPEED_FULL) {
1497 ret = xhci_check_maxpacket(xhci, slot_id,
1500 xhci_urb_free_priv(urb_priv);
1507 spin_lock_irqsave(&xhci->lock, flags);
1509 if (xhci->xhc_state & XHCI_STATE_DYING) {
1510 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1511 urb->ep->desc.bEndpointAddress, urb);
1515 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1516 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1521 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1522 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1527 switch (usb_endpoint_type(&urb->ep->desc)) {
1529 case USB_ENDPOINT_XFER_CONTROL:
1530 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1533 case USB_ENDPOINT_XFER_BULK:
1534 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1537 case USB_ENDPOINT_XFER_INT:
1538 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1541 case USB_ENDPOINT_XFER_ISOC:
1542 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1548 xhci_urb_free_priv(urb_priv);
1551 spin_unlock_irqrestore(&xhci->lock, flags);
1556 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1557 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1558 * should pick up where it left off in the TD, unless a Set Transfer Ring
1559 * Dequeue Pointer is issued.
1561 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1562 * the ring. Since the ring is a contiguous structure, they can't be physically
1563 * removed. Instead, there are two options:
1565 * 1) If the HC is in the middle of processing the URB to be canceled, we
1566 * simply move the ring's dequeue pointer past those TRBs using the Set
1567 * Transfer Ring Dequeue Pointer command. This will be the common case,
1568 * when drivers timeout on the last submitted URB and attempt to cancel.
1570 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1571 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1572 * HC will need to invalidate the any TRBs it has cached after the stop
1573 * endpoint command, as noted in the xHCI 0.95 errata.
1575 * 3) The TD may have completed by the time the Stop Endpoint Command
1576 * completes, so software needs to handle that case too.
1578 * This function should protect against the TD enqueueing code ringing the
1579 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1580 * It also needs to account for multiple cancellations on happening at the same
1581 * time for the same endpoint.
1583 * Note that this function can be called in any context, or so says
1584 * usb_hcd_unlink_urb()
1586 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1588 unsigned long flags;
1591 struct xhci_hcd *xhci;
1592 struct urb_priv *urb_priv;
1594 unsigned int ep_index;
1595 struct xhci_ring *ep_ring;
1596 struct xhci_virt_ep *ep;
1597 struct xhci_command *command;
1598 struct xhci_virt_device *vdev;
1600 xhci = hcd_to_xhci(hcd);
1601 spin_lock_irqsave(&xhci->lock, flags);
1603 trace_xhci_urb_dequeue(urb);
1605 /* Make sure the URB hasn't completed or been unlinked already */
1606 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1610 /* give back URB now if we can't queue it for cancel */
1611 vdev = xhci->devs[urb->dev->slot_id];
1612 urb_priv = urb->hcpriv;
1613 if (!vdev || !urb_priv)
1616 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1617 ep = &vdev->eps[ep_index];
1618 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1619 if (!ep || !ep_ring)
1622 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1623 temp = readl(&xhci->op_regs->status);
1624 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1630 * check ring is not re-allocated since URB was enqueued. If it is, then
1631 * make sure none of the ring related pointers in this URB private data
1632 * are touched, such as td_list, otherwise we overwrite freed data
1634 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1635 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1636 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1637 td = &urb_priv->td[i];
1638 if (!list_empty(&td->cancelled_td_list))
1639 list_del_init(&td->cancelled_td_list);
1644 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1645 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1646 "HC halted, freeing TD manually.");
1647 for (i = urb_priv->num_tds_done;
1648 i < urb_priv->num_tds;
1650 td = &urb_priv->td[i];
1651 if (!list_empty(&td->td_list))
1652 list_del_init(&td->td_list);
1653 if (!list_empty(&td->cancelled_td_list))
1654 list_del_init(&td->cancelled_td_list);
1659 i = urb_priv->num_tds_done;
1660 if (i < urb_priv->num_tds)
1661 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1662 "Cancel URB %p, dev %s, ep 0x%x, "
1663 "starting at offset 0x%llx",
1664 urb, urb->dev->devpath,
1665 urb->ep->desc.bEndpointAddress,
1666 (unsigned long long) xhci_trb_virt_to_dma(
1667 urb_priv->td[i].start_seg,
1668 urb_priv->td[i].first_trb));
1670 for (; i < urb_priv->num_tds; i++) {
1671 td = &urb_priv->td[i];
1672 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1675 /* Queue a stop endpoint command, but only if this is
1676 * the first cancellation to be handled.
1678 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1679 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1684 ep->ep_state |= EP_STOP_CMD_PENDING;
1685 ep->stop_cmd_timer.expires = jiffies +
1686 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1687 add_timer(&ep->stop_cmd_timer);
1688 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1690 xhci_ring_cmd_db(xhci);
1693 spin_unlock_irqrestore(&xhci->lock, flags);
1698 xhci_urb_free_priv(urb_priv);
1699 usb_hcd_unlink_urb_from_ep(hcd, urb);
1700 spin_unlock_irqrestore(&xhci->lock, flags);
1701 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1705 /* Drop an endpoint from a new bandwidth configuration for this device.
1706 * Only one call to this function is allowed per endpoint before
1707 * check_bandwidth() or reset_bandwidth() must be called.
1708 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1709 * add the endpoint to the schedule with possibly new parameters denoted by a
1710 * different endpoint descriptor in usb_host_endpoint.
1711 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1714 * The USB core will not allow URBs to be queued to an endpoint that is being
1715 * disabled, so there's no need for mutual exclusion to protect
1716 * the xhci->devs[slot_id] structure.
1718 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1719 struct usb_host_endpoint *ep)
1721 struct xhci_hcd *xhci;
1722 struct xhci_container_ctx *in_ctx, *out_ctx;
1723 struct xhci_input_control_ctx *ctrl_ctx;
1724 unsigned int ep_index;
1725 struct xhci_ep_ctx *ep_ctx;
1727 u32 new_add_flags, new_drop_flags;
1730 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1733 xhci = hcd_to_xhci(hcd);
1734 if (xhci->xhc_state & XHCI_STATE_DYING)
1737 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1738 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1739 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1740 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1741 __func__, drop_flag);
1745 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1746 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1747 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1749 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1754 ep_index = xhci_get_endpoint_index(&ep->desc);
1755 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1756 /* If the HC already knows the endpoint is disabled,
1757 * or the HCD has noted it is disabled, ignore this request
1759 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1760 le32_to_cpu(ctrl_ctx->drop_flags) &
1761 xhci_get_endpoint_flag(&ep->desc)) {
1762 /* Do not warn when called after a usb_device_reset */
1763 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1764 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1769 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1770 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1772 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1773 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1775 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1777 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1779 if (xhci->quirks & XHCI_MTK_HOST)
1780 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1782 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1783 (unsigned int) ep->desc.bEndpointAddress,
1785 (unsigned int) new_drop_flags,
1786 (unsigned int) new_add_flags);
1790 /* Add an endpoint to a new possible bandwidth configuration for this device.
1791 * Only one call to this function is allowed per endpoint before
1792 * check_bandwidth() or reset_bandwidth() must be called.
1793 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1794 * add the endpoint to the schedule with possibly new parameters denoted by a
1795 * different endpoint descriptor in usb_host_endpoint.
1796 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1799 * The USB core will not allow URBs to be queued to an endpoint until the
1800 * configuration or alt setting is installed in the device, so there's no need
1801 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1803 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1804 struct usb_host_endpoint *ep)
1806 struct xhci_hcd *xhci;
1807 struct xhci_container_ctx *in_ctx;
1808 unsigned int ep_index;
1809 struct xhci_input_control_ctx *ctrl_ctx;
1811 u32 new_add_flags, new_drop_flags;
1812 struct xhci_virt_device *virt_dev;
1815 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1817 /* So we won't queue a reset ep command for a root hub */
1821 xhci = hcd_to_xhci(hcd);
1822 if (xhci->xhc_state & XHCI_STATE_DYING)
1825 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1826 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1827 /* FIXME when we have to issue an evaluate endpoint command to
1828 * deal with ep0 max packet size changing once we get the
1831 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1832 __func__, added_ctxs);
1836 virt_dev = xhci->devs[udev->slot_id];
1837 in_ctx = virt_dev->in_ctx;
1838 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1840 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1845 ep_index = xhci_get_endpoint_index(&ep->desc);
1846 /* If this endpoint is already in use, and the upper layers are trying
1847 * to add it again without dropping it, reject the addition.
1849 if (virt_dev->eps[ep_index].ring &&
1850 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1851 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1852 "without dropping it.\n",
1853 (unsigned int) ep->desc.bEndpointAddress);
1857 /* If the HCD has already noted the endpoint is enabled,
1858 * ignore this request.
1860 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1861 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1867 * Configuration and alternate setting changes must be done in
1868 * process context, not interrupt context (or so documenation
1869 * for usb_set_interface() and usb_set_configuration() claim).
1871 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1872 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1873 __func__, ep->desc.bEndpointAddress);
1877 if (xhci->quirks & XHCI_MTK_HOST) {
1878 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1880 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1881 virt_dev->eps[ep_index].new_ring = NULL;
1886 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1887 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1889 /* If xhci_endpoint_disable() was called for this endpoint, but the
1890 * xHC hasn't been notified yet through the check_bandwidth() call,
1891 * this re-adds a new state for the endpoint from the new endpoint
1892 * descriptors. We must drop and re-add this endpoint, so we leave the
1895 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1897 /* Store the usb_device pointer for later use */
1900 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1902 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1903 (unsigned int) ep->desc.bEndpointAddress,
1905 (unsigned int) new_drop_flags,
1906 (unsigned int) new_add_flags);
1910 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1912 struct xhci_input_control_ctx *ctrl_ctx;
1913 struct xhci_ep_ctx *ep_ctx;
1914 struct xhci_slot_ctx *slot_ctx;
1917 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1919 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1924 /* When a device's add flag and drop flag are zero, any subsequent
1925 * configure endpoint command will leave that endpoint's state
1926 * untouched. Make sure we don't leave any old state in the input
1927 * endpoint contexts.
1929 ctrl_ctx->drop_flags = 0;
1930 ctrl_ctx->add_flags = 0;
1931 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1932 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1933 /* Endpoint 0 is always valid */
1934 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1935 for (i = 1; i < 31; i++) {
1936 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1937 ep_ctx->ep_info = 0;
1938 ep_ctx->ep_info2 = 0;
1940 ep_ctx->tx_info = 0;
1944 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1945 struct usb_device *udev, u32 *cmd_status)
1949 switch (*cmd_status) {
1950 case COMP_COMMAND_ABORTED:
1951 case COMP_COMMAND_RING_STOPPED:
1952 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1955 case COMP_RESOURCE_ERROR:
1956 dev_warn(&udev->dev,
1957 "Not enough host controller resources for new device state.\n");
1959 /* FIXME: can we allocate more resources for the HC? */
1961 case COMP_BANDWIDTH_ERROR:
1962 case COMP_SECONDARY_BANDWIDTH_ERROR:
1963 dev_warn(&udev->dev,
1964 "Not enough bandwidth for new device state.\n");
1966 /* FIXME: can we go back to the old state? */
1968 case COMP_TRB_ERROR:
1969 /* the HCD set up something wrong */
1970 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1972 "and endpoint is not disabled.\n");
1975 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1976 dev_warn(&udev->dev,
1977 "ERROR: Incompatible device for endpoint configure command.\n");
1981 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1982 "Successful Endpoint Configure command");
1986 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1994 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1995 struct usb_device *udev, u32 *cmd_status)
1999 switch (*cmd_status) {
2000 case COMP_COMMAND_ABORTED:
2001 case COMP_COMMAND_RING_STOPPED:
2002 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2005 case COMP_PARAMETER_ERROR:
2006 dev_warn(&udev->dev,
2007 "WARN: xHCI driver setup invalid evaluate context command.\n");
2010 case COMP_SLOT_NOT_ENABLED_ERROR:
2011 dev_warn(&udev->dev,
2012 "WARN: slot not enabled for evaluate context command.\n");
2015 case COMP_CONTEXT_STATE_ERROR:
2016 dev_warn(&udev->dev,
2017 "WARN: invalid context state for evaluate context command.\n");
2020 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2021 dev_warn(&udev->dev,
2022 "ERROR: Incompatible device for evaluate context command.\n");
2025 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2026 /* Max Exit Latency too large error */
2027 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2031 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2032 "Successful evaluate context command");
2036 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2044 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2045 struct xhci_input_control_ctx *ctrl_ctx)
2047 u32 valid_add_flags;
2048 u32 valid_drop_flags;
2050 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2051 * (bit 1). The default control endpoint is added during the Address
2052 * Device command and is never removed until the slot is disabled.
2054 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2055 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2057 /* Use hweight32 to count the number of ones in the add flags, or
2058 * number of endpoints added. Don't count endpoints that are changed
2059 * (both added and dropped).
2061 return hweight32(valid_add_flags) -
2062 hweight32(valid_add_flags & valid_drop_flags);
2065 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2066 struct xhci_input_control_ctx *ctrl_ctx)
2068 u32 valid_add_flags;
2069 u32 valid_drop_flags;
2071 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2072 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2074 return hweight32(valid_drop_flags) -
2075 hweight32(valid_add_flags & valid_drop_flags);
2079 * We need to reserve the new number of endpoints before the configure endpoint
2080 * command completes. We can't subtract the dropped endpoints from the number
2081 * of active endpoints until the command completes because we can oversubscribe
2082 * the host in this case:
2084 * - the first configure endpoint command drops more endpoints than it adds
2085 * - a second configure endpoint command that adds more endpoints is queued
2086 * - the first configure endpoint command fails, so the config is unchanged
2087 * - the second command may succeed, even though there isn't enough resources
2089 * Must be called with xhci->lock held.
2091 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2092 struct xhci_input_control_ctx *ctrl_ctx)
2096 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2097 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2098 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2099 "Not enough ep ctxs: "
2100 "%u active, need to add %u, limit is %u.",
2101 xhci->num_active_eps, added_eps,
2102 xhci->limit_active_eps);
2105 xhci->num_active_eps += added_eps;
2106 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2107 "Adding %u ep ctxs, %u now active.", added_eps,
2108 xhci->num_active_eps);
2113 * The configure endpoint was failed by the xHC for some other reason, so we
2114 * need to revert the resources that failed configuration would have used.
2116 * Must be called with xhci->lock held.
2118 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2119 struct xhci_input_control_ctx *ctrl_ctx)
2123 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2124 xhci->num_active_eps -= num_failed_eps;
2125 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2126 "Removing %u failed ep ctxs, %u now active.",
2128 xhci->num_active_eps);
2132 * Now that the command has completed, clean up the active endpoint count by
2133 * subtracting out the endpoints that were dropped (but not changed).
2135 * Must be called with xhci->lock held.
2137 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2138 struct xhci_input_control_ctx *ctrl_ctx)
2140 u32 num_dropped_eps;
2142 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2143 xhci->num_active_eps -= num_dropped_eps;
2144 if (num_dropped_eps)
2145 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2146 "Removing %u dropped ep ctxs, %u now active.",
2148 xhci->num_active_eps);
2151 static unsigned int xhci_get_block_size(struct usb_device *udev)
2153 switch (udev->speed) {
2155 case USB_SPEED_FULL:
2157 case USB_SPEED_HIGH:
2159 case USB_SPEED_SUPER:
2160 case USB_SPEED_SUPER_PLUS:
2162 case USB_SPEED_UNKNOWN:
2163 case USB_SPEED_WIRELESS:
2165 /* Should never happen */
2171 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2173 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2175 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2180 /* If we are changing a LS/FS device under a HS hub,
2181 * make sure (if we are activating a new TT) that the HS bus has enough
2182 * bandwidth for this new TT.
2184 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2185 struct xhci_virt_device *virt_dev,
2188 struct xhci_interval_bw_table *bw_table;
2189 struct xhci_tt_bw_info *tt_info;
2191 /* Find the bandwidth table for the root port this TT is attached to. */
2192 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2193 tt_info = virt_dev->tt_info;
2194 /* If this TT already had active endpoints, the bandwidth for this TT
2195 * has already been added. Removing all periodic endpoints (and thus
2196 * making the TT enactive) will only decrease the bandwidth used.
2200 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2201 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2205 /* Not sure why we would have no new active endpoints...
2207 * Maybe because of an Evaluate Context change for a hub update or a
2208 * control endpoint 0 max packet size change?
2209 * FIXME: skip the bandwidth calculation in that case.
2214 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2215 struct xhci_virt_device *virt_dev)
2217 unsigned int bw_reserved;
2219 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2220 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2223 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2224 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2231 * This algorithm is a very conservative estimate of the worst-case scheduling
2232 * scenario for any one interval. The hardware dynamically schedules the
2233 * packets, so we can't tell which microframe could be the limiting factor in
2234 * the bandwidth scheduling. This only takes into account periodic endpoints.
2236 * Obviously, we can't solve an NP complete problem to find the minimum worst
2237 * case scenario. Instead, we come up with an estimate that is no less than
2238 * the worst case bandwidth used for any one microframe, but may be an
2241 * We walk the requirements for each endpoint by interval, starting with the
2242 * smallest interval, and place packets in the schedule where there is only one
2243 * possible way to schedule packets for that interval. In order to simplify
2244 * this algorithm, we record the largest max packet size for each interval, and
2245 * assume all packets will be that size.
2247 * For interval 0, we obviously must schedule all packets for each interval.
2248 * The bandwidth for interval 0 is just the amount of data to be transmitted
2249 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2250 * the number of packets).
2252 * For interval 1, we have two possible microframes to schedule those packets
2253 * in. For this algorithm, if we can schedule the same number of packets for
2254 * each possible scheduling opportunity (each microframe), we will do so. The
2255 * remaining number of packets will be saved to be transmitted in the gaps in
2256 * the next interval's scheduling sequence.
2258 * As we move those remaining packets to be scheduled with interval 2 packets,
2259 * we have to double the number of remaining packets to transmit. This is
2260 * because the intervals are actually powers of 2, and we would be transmitting
2261 * the previous interval's packets twice in this interval. We also have to be
2262 * sure that when we look at the largest max packet size for this interval, we
2263 * also look at the largest max packet size for the remaining packets and take
2264 * the greater of the two.
2266 * The algorithm continues to evenly distribute packets in each scheduling
2267 * opportunity, and push the remaining packets out, until we get to the last
2268 * interval. Then those packets and their associated overhead are just added
2269 * to the bandwidth used.
2271 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2272 struct xhci_virt_device *virt_dev,
2275 unsigned int bw_reserved;
2276 unsigned int max_bandwidth;
2277 unsigned int bw_used;
2278 unsigned int block_size;
2279 struct xhci_interval_bw_table *bw_table;
2280 unsigned int packet_size = 0;
2281 unsigned int overhead = 0;
2282 unsigned int packets_transmitted = 0;
2283 unsigned int packets_remaining = 0;
2286 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2287 return xhci_check_ss_bw(xhci, virt_dev);
2289 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2290 max_bandwidth = HS_BW_LIMIT;
2291 /* Convert percent of bus BW reserved to blocks reserved */
2292 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2294 max_bandwidth = FS_BW_LIMIT;
2295 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2298 bw_table = virt_dev->bw_table;
2299 /* We need to translate the max packet size and max ESIT payloads into
2300 * the units the hardware uses.
2302 block_size = xhci_get_block_size(virt_dev->udev);
2304 /* If we are manipulating a LS/FS device under a HS hub, double check
2305 * that the HS bus has enough bandwidth if we are activing a new TT.
2307 if (virt_dev->tt_info) {
2308 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2309 "Recalculating BW for rootport %u",
2310 virt_dev->real_port);
2311 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2312 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2313 "newly activated TT.\n");
2316 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2317 "Recalculating BW for TT slot %u port %u",
2318 virt_dev->tt_info->slot_id,
2319 virt_dev->tt_info->ttport);
2321 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2322 "Recalculating BW for rootport %u",
2323 virt_dev->real_port);
2326 /* Add in how much bandwidth will be used for interval zero, or the
2327 * rounded max ESIT payload + number of packets * largest overhead.
2329 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2330 bw_table->interval_bw[0].num_packets *
2331 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2333 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2334 unsigned int bw_added;
2335 unsigned int largest_mps;
2336 unsigned int interval_overhead;
2339 * How many packets could we transmit in this interval?
2340 * If packets didn't fit in the previous interval, we will need
2341 * to transmit that many packets twice within this interval.
2343 packets_remaining = 2 * packets_remaining +
2344 bw_table->interval_bw[i].num_packets;
2346 /* Find the largest max packet size of this or the previous
2349 if (list_empty(&bw_table->interval_bw[i].endpoints))
2352 struct xhci_virt_ep *virt_ep;
2353 struct list_head *ep_entry;
2355 ep_entry = bw_table->interval_bw[i].endpoints.next;
2356 virt_ep = list_entry(ep_entry,
2357 struct xhci_virt_ep, bw_endpoint_list);
2358 /* Convert to blocks, rounding up */
2359 largest_mps = DIV_ROUND_UP(
2360 virt_ep->bw_info.max_packet_size,
2363 if (largest_mps > packet_size)
2364 packet_size = largest_mps;
2366 /* Use the larger overhead of this or the previous interval. */
2367 interval_overhead = xhci_get_largest_overhead(
2368 &bw_table->interval_bw[i]);
2369 if (interval_overhead > overhead)
2370 overhead = interval_overhead;
2372 /* How many packets can we evenly distribute across
2373 * (1 << (i + 1)) possible scheduling opportunities?
2375 packets_transmitted = packets_remaining >> (i + 1);
2377 /* Add in the bandwidth used for those scheduled packets */
2378 bw_added = packets_transmitted * (overhead + packet_size);
2380 /* How many packets do we have remaining to transmit? */
2381 packets_remaining = packets_remaining % (1 << (i + 1));
2383 /* What largest max packet size should those packets have? */
2384 /* If we've transmitted all packets, don't carry over the
2385 * largest packet size.
2387 if (packets_remaining == 0) {
2390 } else if (packets_transmitted > 0) {
2391 /* Otherwise if we do have remaining packets, and we've
2392 * scheduled some packets in this interval, take the
2393 * largest max packet size from endpoints with this
2396 packet_size = largest_mps;
2397 overhead = interval_overhead;
2399 /* Otherwise carry over packet_size and overhead from the last
2400 * time we had a remainder.
2402 bw_used += bw_added;
2403 if (bw_used > max_bandwidth) {
2404 xhci_warn(xhci, "Not enough bandwidth. "
2405 "Proposed: %u, Max: %u\n",
2406 bw_used, max_bandwidth);
2411 * Ok, we know we have some packets left over after even-handedly
2412 * scheduling interval 15. We don't know which microframes they will
2413 * fit into, so we over-schedule and say they will be scheduled every
2416 if (packets_remaining > 0)
2417 bw_used += overhead + packet_size;
2419 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2420 unsigned int port_index = virt_dev->real_port - 1;
2422 /* OK, we're manipulating a HS device attached to a
2423 * root port bandwidth domain. Include the number of active TTs
2424 * in the bandwidth used.
2426 bw_used += TT_HS_OVERHEAD *
2427 xhci->rh_bw[port_index].num_active_tts;
2430 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2431 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2432 "Available: %u " "percent",
2433 bw_used, max_bandwidth, bw_reserved,
2434 (max_bandwidth - bw_used - bw_reserved) * 100 /
2437 bw_used += bw_reserved;
2438 if (bw_used > max_bandwidth) {
2439 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2440 bw_used, max_bandwidth);
2444 bw_table->bw_used = bw_used;
2448 static bool xhci_is_async_ep(unsigned int ep_type)
2450 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2451 ep_type != ISOC_IN_EP &&
2452 ep_type != INT_IN_EP);
2455 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2457 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2460 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2462 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2464 if (ep_bw->ep_interval == 0)
2465 return SS_OVERHEAD_BURST +
2466 (ep_bw->mult * ep_bw->num_packets *
2467 (SS_OVERHEAD + mps));
2468 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2469 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2470 1 << ep_bw->ep_interval);
2474 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2475 struct xhci_bw_info *ep_bw,
2476 struct xhci_interval_bw_table *bw_table,
2477 struct usb_device *udev,
2478 struct xhci_virt_ep *virt_ep,
2479 struct xhci_tt_bw_info *tt_info)
2481 struct xhci_interval_bw *interval_bw;
2482 int normalized_interval;
2484 if (xhci_is_async_ep(ep_bw->type))
2487 if (udev->speed >= USB_SPEED_SUPER) {
2488 if (xhci_is_sync_in_ep(ep_bw->type))
2489 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2490 xhci_get_ss_bw_consumed(ep_bw);
2492 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2493 xhci_get_ss_bw_consumed(ep_bw);
2497 /* SuperSpeed endpoints never get added to intervals in the table, so
2498 * this check is only valid for HS/FS/LS devices.
2500 if (list_empty(&virt_ep->bw_endpoint_list))
2502 /* For LS/FS devices, we need to translate the interval expressed in
2503 * microframes to frames.
2505 if (udev->speed == USB_SPEED_HIGH)
2506 normalized_interval = ep_bw->ep_interval;
2508 normalized_interval = ep_bw->ep_interval - 3;
2510 if (normalized_interval == 0)
2511 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2512 interval_bw = &bw_table->interval_bw[normalized_interval];
2513 interval_bw->num_packets -= ep_bw->num_packets;
2514 switch (udev->speed) {
2516 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2518 case USB_SPEED_FULL:
2519 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2521 case USB_SPEED_HIGH:
2522 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2524 case USB_SPEED_SUPER:
2525 case USB_SPEED_SUPER_PLUS:
2526 case USB_SPEED_UNKNOWN:
2527 case USB_SPEED_WIRELESS:
2528 /* Should never happen because only LS/FS/HS endpoints will get
2529 * added to the endpoint list.
2534 tt_info->active_eps -= 1;
2535 list_del_init(&virt_ep->bw_endpoint_list);
2538 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2539 struct xhci_bw_info *ep_bw,
2540 struct xhci_interval_bw_table *bw_table,
2541 struct usb_device *udev,
2542 struct xhci_virt_ep *virt_ep,
2543 struct xhci_tt_bw_info *tt_info)
2545 struct xhci_interval_bw *interval_bw;
2546 struct xhci_virt_ep *smaller_ep;
2547 int normalized_interval;
2549 if (xhci_is_async_ep(ep_bw->type))
2552 if (udev->speed == USB_SPEED_SUPER) {
2553 if (xhci_is_sync_in_ep(ep_bw->type))
2554 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2555 xhci_get_ss_bw_consumed(ep_bw);
2557 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2558 xhci_get_ss_bw_consumed(ep_bw);
2562 /* For LS/FS devices, we need to translate the interval expressed in
2563 * microframes to frames.
2565 if (udev->speed == USB_SPEED_HIGH)
2566 normalized_interval = ep_bw->ep_interval;
2568 normalized_interval = ep_bw->ep_interval - 3;
2570 if (normalized_interval == 0)
2571 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2572 interval_bw = &bw_table->interval_bw[normalized_interval];
2573 interval_bw->num_packets += ep_bw->num_packets;
2574 switch (udev->speed) {
2576 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2578 case USB_SPEED_FULL:
2579 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2581 case USB_SPEED_HIGH:
2582 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2584 case USB_SPEED_SUPER:
2585 case USB_SPEED_SUPER_PLUS:
2586 case USB_SPEED_UNKNOWN:
2587 case USB_SPEED_WIRELESS:
2588 /* Should never happen because only LS/FS/HS endpoints will get
2589 * added to the endpoint list.
2595 tt_info->active_eps += 1;
2596 /* Insert the endpoint into the list, largest max packet size first. */
2597 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2599 if (ep_bw->max_packet_size >=
2600 smaller_ep->bw_info.max_packet_size) {
2601 /* Add the new ep before the smaller endpoint */
2602 list_add_tail(&virt_ep->bw_endpoint_list,
2603 &smaller_ep->bw_endpoint_list);
2607 /* Add the new endpoint at the end of the list. */
2608 list_add_tail(&virt_ep->bw_endpoint_list,
2609 &interval_bw->endpoints);
2612 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2613 struct xhci_virt_device *virt_dev,
2616 struct xhci_root_port_bw_info *rh_bw_info;
2617 if (!virt_dev->tt_info)
2620 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2621 if (old_active_eps == 0 &&
2622 virt_dev->tt_info->active_eps != 0) {
2623 rh_bw_info->num_active_tts += 1;
2624 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2625 } else if (old_active_eps != 0 &&
2626 virt_dev->tt_info->active_eps == 0) {
2627 rh_bw_info->num_active_tts -= 1;
2628 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2632 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2633 struct xhci_virt_device *virt_dev,
2634 struct xhci_container_ctx *in_ctx)
2636 struct xhci_bw_info ep_bw_info[31];
2638 struct xhci_input_control_ctx *ctrl_ctx;
2639 int old_active_eps = 0;
2641 if (virt_dev->tt_info)
2642 old_active_eps = virt_dev->tt_info->active_eps;
2644 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2646 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2651 for (i = 0; i < 31; i++) {
2652 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2655 /* Make a copy of the BW info in case we need to revert this */
2656 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2657 sizeof(ep_bw_info[i]));
2658 /* Drop the endpoint from the interval table if the endpoint is
2659 * being dropped or changed.
2661 if (EP_IS_DROPPED(ctrl_ctx, i))
2662 xhci_drop_ep_from_interval_table(xhci,
2663 &virt_dev->eps[i].bw_info,
2669 /* Overwrite the information stored in the endpoints' bw_info */
2670 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2671 for (i = 0; i < 31; i++) {
2672 /* Add any changed or added endpoints to the interval table */
2673 if (EP_IS_ADDED(ctrl_ctx, i))
2674 xhci_add_ep_to_interval_table(xhci,
2675 &virt_dev->eps[i].bw_info,
2682 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2683 /* Ok, this fits in the bandwidth we have.
2684 * Update the number of active TTs.
2686 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2690 /* We don't have enough bandwidth for this, revert the stored info. */
2691 for (i = 0; i < 31; i++) {
2692 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2695 /* Drop the new copies of any added or changed endpoints from
2696 * the interval table.
2698 if (EP_IS_ADDED(ctrl_ctx, i)) {
2699 xhci_drop_ep_from_interval_table(xhci,
2700 &virt_dev->eps[i].bw_info,
2706 /* Revert the endpoint back to its old information */
2707 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2708 sizeof(ep_bw_info[i]));
2709 /* Add any changed or dropped endpoints back into the table */
2710 if (EP_IS_DROPPED(ctrl_ctx, i))
2711 xhci_add_ep_to_interval_table(xhci,
2712 &virt_dev->eps[i].bw_info,
2722 /* Issue a configure endpoint command or evaluate context command
2723 * and wait for it to finish.
2725 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2726 struct usb_device *udev,
2727 struct xhci_command *command,
2728 bool ctx_change, bool must_succeed)
2731 unsigned long flags;
2732 struct xhci_input_control_ctx *ctrl_ctx;
2733 struct xhci_virt_device *virt_dev;
2734 struct xhci_slot_ctx *slot_ctx;
2739 spin_lock_irqsave(&xhci->lock, flags);
2741 if (xhci->xhc_state & XHCI_STATE_DYING) {
2742 spin_unlock_irqrestore(&xhci->lock, flags);
2746 virt_dev = xhci->devs[udev->slot_id];
2748 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2750 spin_unlock_irqrestore(&xhci->lock, flags);
2751 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2756 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2757 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2758 spin_unlock_irqrestore(&xhci->lock, flags);
2759 xhci_warn(xhci, "Not enough host resources, "
2760 "active endpoint contexts = %u\n",
2761 xhci->num_active_eps);
2764 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2765 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2766 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2767 xhci_free_host_resources(xhci, ctrl_ctx);
2768 spin_unlock_irqrestore(&xhci->lock, flags);
2769 xhci_warn(xhci, "Not enough bandwidth\n");
2773 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2775 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2776 trace_xhci_configure_endpoint(slot_ctx);
2779 ret = xhci_queue_configure_endpoint(xhci, command,
2780 command->in_ctx->dma,
2781 udev->slot_id, must_succeed);
2783 ret = xhci_queue_evaluate_context(xhci, command,
2784 command->in_ctx->dma,
2785 udev->slot_id, must_succeed);
2787 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2788 xhci_free_host_resources(xhci, ctrl_ctx);
2789 spin_unlock_irqrestore(&xhci->lock, flags);
2790 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2791 "FIXME allocate a new ring segment");
2794 xhci_ring_cmd_db(xhci);
2795 spin_unlock_irqrestore(&xhci->lock, flags);
2797 /* Wait for the configure endpoint command to complete */
2798 wait_for_completion(command->completion);
2801 ret = xhci_configure_endpoint_result(xhci, udev,
2804 ret = xhci_evaluate_context_result(xhci, udev,
2807 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2808 spin_lock_irqsave(&xhci->lock, flags);
2809 /* If the command failed, remove the reserved resources.
2810 * Otherwise, clean up the estimate to include dropped eps.
2813 xhci_free_host_resources(xhci, ctrl_ctx);
2815 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2816 spin_unlock_irqrestore(&xhci->lock, flags);
2821 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2822 struct xhci_virt_device *vdev, int i)
2824 struct xhci_virt_ep *ep = &vdev->eps[i];
2826 if (ep->ep_state & EP_HAS_STREAMS) {
2827 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2828 xhci_get_endpoint_address(i));
2829 xhci_free_stream_info(xhci, ep->stream_info);
2830 ep->stream_info = NULL;
2831 ep->ep_state &= ~EP_HAS_STREAMS;
2835 /* Called after one or more calls to xhci_add_endpoint() or
2836 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2837 * to call xhci_reset_bandwidth().
2839 * Since we are in the middle of changing either configuration or
2840 * installing a new alt setting, the USB core won't allow URBs to be
2841 * enqueued for any endpoint on the old config or interface. Nothing
2842 * else should be touching the xhci->devs[slot_id] structure, so we
2843 * don't need to take the xhci->lock for manipulating that.
2845 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2849 struct xhci_hcd *xhci;
2850 struct xhci_virt_device *virt_dev;
2851 struct xhci_input_control_ctx *ctrl_ctx;
2852 struct xhci_slot_ctx *slot_ctx;
2853 struct xhci_command *command;
2855 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2858 xhci = hcd_to_xhci(hcd);
2859 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2860 (xhci->xhc_state & XHCI_STATE_REMOVING))
2863 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2864 virt_dev = xhci->devs[udev->slot_id];
2866 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2870 command->in_ctx = virt_dev->in_ctx;
2872 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2873 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2875 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2878 goto command_cleanup;
2880 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2881 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2882 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2884 /* Don't issue the command if there's no endpoints to update. */
2885 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2886 ctrl_ctx->drop_flags == 0) {
2888 goto command_cleanup;
2890 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2891 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2892 for (i = 31; i >= 1; i--) {
2893 __le32 le32 = cpu_to_le32(BIT(i));
2895 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2896 || (ctrl_ctx->add_flags & le32) || i == 1) {
2897 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2898 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2903 ret = xhci_configure_endpoint(xhci, udev, command,
2906 /* Callee should call reset_bandwidth() */
2907 goto command_cleanup;
2909 /* Free any rings that were dropped, but not changed. */
2910 for (i = 1; i < 31; i++) {
2911 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2912 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2913 xhci_free_endpoint_ring(xhci, virt_dev, i);
2914 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2917 xhci_zero_in_ctx(xhci, virt_dev);
2919 * Install any rings for completely new endpoints or changed endpoints,
2920 * and free any old rings from changed endpoints.
2922 for (i = 1; i < 31; i++) {
2923 if (!virt_dev->eps[i].new_ring)
2925 /* Only free the old ring if it exists.
2926 * It may not if this is the first add of an endpoint.
2928 if (virt_dev->eps[i].ring) {
2929 xhci_free_endpoint_ring(xhci, virt_dev, i);
2931 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2932 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2933 virt_dev->eps[i].new_ring = NULL;
2936 kfree(command->completion);
2942 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2944 struct xhci_hcd *xhci;
2945 struct xhci_virt_device *virt_dev;
2948 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2951 xhci = hcd_to_xhci(hcd);
2953 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2954 virt_dev = xhci->devs[udev->slot_id];
2955 /* Free any rings allocated for added endpoints */
2956 for (i = 0; i < 31; i++) {
2957 if (virt_dev->eps[i].new_ring) {
2958 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2959 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2960 virt_dev->eps[i].new_ring = NULL;
2963 xhci_zero_in_ctx(xhci, virt_dev);
2966 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2967 struct xhci_container_ctx *in_ctx,
2968 struct xhci_container_ctx *out_ctx,
2969 struct xhci_input_control_ctx *ctrl_ctx,
2970 u32 add_flags, u32 drop_flags)
2972 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2973 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2974 xhci_slot_copy(xhci, in_ctx, out_ctx);
2975 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2978 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2979 unsigned int slot_id, unsigned int ep_index,
2980 struct xhci_dequeue_state *deq_state)
2982 struct xhci_input_control_ctx *ctrl_ctx;
2983 struct xhci_container_ctx *in_ctx;
2984 struct xhci_ep_ctx *ep_ctx;
2988 in_ctx = xhci->devs[slot_id]->in_ctx;
2989 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2991 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2996 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2997 xhci->devs[slot_id]->out_ctx, ep_index);
2998 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2999 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3000 deq_state->new_deq_ptr);
3002 xhci_warn(xhci, "WARN Cannot submit config ep after "
3003 "reset ep command\n");
3004 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3005 deq_state->new_deq_seg,
3006 deq_state->new_deq_ptr);
3009 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3011 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3012 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3013 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3014 added_ctxs, added_ctxs);
3017 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
3018 unsigned int stream_id, struct xhci_td *td)
3020 struct xhci_dequeue_state deq_state;
3021 struct usb_device *udev = td->urb->dev;
3023 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3024 "Cleaning up stalled endpoint ring");
3025 /* We need to move the HW's dequeue pointer past this TD,
3026 * or it will attempt to resend it on the next doorbell ring.
3028 xhci_find_new_dequeue_state(xhci, udev->slot_id,
3029 ep_index, stream_id, td, &deq_state);
3031 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3034 /* HW with the reset endpoint quirk will use the saved dequeue state to
3035 * issue a configure endpoint command later.
3037 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3038 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3039 "Queueing new dequeue state");
3040 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
3041 ep_index, &deq_state);
3043 /* Better hope no one uses the input context between now and the
3044 * reset endpoint completion!
3045 * XXX: No idea how this hardware will react when stream rings
3048 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3049 "Setting up input context for "
3050 "configure endpoint command");
3051 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3052 ep_index, &deq_state);
3057 * Called after usb core issues a clear halt control message.
3058 * The host side of the halt should already be cleared by a reset endpoint
3059 * command issued when the STALL event was received.
3061 * The reset endpoint command may only be issued to endpoints in the halted
3062 * state. For software that wishes to reset the data toggle or sequence number
3063 * of an endpoint that isn't in the halted state this function will issue a
3064 * configure endpoint command with the Drop and Add bits set for the target
3065 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3068 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3069 struct usb_host_endpoint *host_ep)
3071 struct xhci_hcd *xhci;
3072 struct usb_device *udev;
3073 struct xhci_virt_device *vdev;
3074 struct xhci_virt_ep *ep;
3075 struct xhci_input_control_ctx *ctrl_ctx;
3076 struct xhci_command *stop_cmd, *cfg_cmd;
3077 unsigned int ep_index;
3078 unsigned long flags;
3081 xhci = hcd_to_xhci(hcd);
3082 if (!host_ep->hcpriv)
3084 udev = (struct usb_device *) host_ep->hcpriv;
3085 vdev = xhci->devs[udev->slot_id];
3086 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3087 ep = &vdev->eps[ep_index];
3089 /* Bail out if toggle is already being cleared by a endpoint reset */
3090 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3091 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3094 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3095 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3096 usb_endpoint_xfer_isoc(&host_ep->desc))
3099 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3101 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3104 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3108 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3112 spin_lock_irqsave(&xhci->lock, flags);
3114 /* block queuing new trbs and ringing ep doorbell */
3115 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3118 * Make sure endpoint ring is empty before resetting the toggle/seq.
3119 * Driver is required to synchronously cancel all transfer request.
3120 * Stop the endpoint to force xHC to update the output context
3123 if (!list_empty(&ep->ring->td_list)) {
3124 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3125 spin_unlock_irqrestore(&xhci->lock, flags);
3126 xhci_free_command(xhci, cfg_cmd);
3129 xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
3130 xhci_ring_cmd_db(xhci);
3131 spin_unlock_irqrestore(&xhci->lock, flags);
3133 wait_for_completion(stop_cmd->completion);
3135 spin_lock_irqsave(&xhci->lock, flags);
3137 /* config ep command clears toggle if add and drop ep flags are set */
3138 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3139 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3140 ctrl_ctx, ep_flag, ep_flag);
3141 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3143 xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3144 udev->slot_id, false);
3145 xhci_ring_cmd_db(xhci);
3146 spin_unlock_irqrestore(&xhci->lock, flags);
3148 wait_for_completion(cfg_cmd->completion);
3150 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3151 xhci_free_command(xhci, cfg_cmd);
3153 xhci_free_command(xhci, stop_cmd);
3156 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3157 struct usb_device *udev, struct usb_host_endpoint *ep,
3158 unsigned int slot_id)
3161 unsigned int ep_index;
3162 unsigned int ep_state;
3166 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3169 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3170 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3171 " descriptor for ep 0x%x does not support streams\n",
3172 ep->desc.bEndpointAddress);
3176 ep_index = xhci_get_endpoint_index(&ep->desc);
3177 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3178 if (ep_state & EP_HAS_STREAMS ||
3179 ep_state & EP_GETTING_STREAMS) {
3180 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3181 "already has streams set up.\n",
3182 ep->desc.bEndpointAddress);
3183 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3184 "dynamic stream context array reallocation.\n");
3187 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3188 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3189 "endpoint 0x%x; URBs are pending.\n",
3190 ep->desc.bEndpointAddress);
3196 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3197 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3199 unsigned int max_streams;
3201 /* The stream context array size must be a power of two */
3202 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3204 * Find out how many primary stream array entries the host controller
3205 * supports. Later we may use secondary stream arrays (similar to 2nd
3206 * level page entries), but that's an optional feature for xHCI host
3207 * controllers. xHCs must support at least 4 stream IDs.
3209 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3210 if (*num_stream_ctxs > max_streams) {
3211 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3213 *num_stream_ctxs = max_streams;
3214 *num_streams = max_streams;
3218 /* Returns an error code if one of the endpoint already has streams.
3219 * This does not change any data structures, it only checks and gathers
3222 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3223 struct usb_device *udev,
3224 struct usb_host_endpoint **eps, unsigned int num_eps,
3225 unsigned int *num_streams, u32 *changed_ep_bitmask)
3227 unsigned int max_streams;
3228 unsigned int endpoint_flag;
3232 for (i = 0; i < num_eps; i++) {
3233 ret = xhci_check_streams_endpoint(xhci, udev,
3234 eps[i], udev->slot_id);
3238 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3239 if (max_streams < (*num_streams - 1)) {
3240 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3241 eps[i]->desc.bEndpointAddress,
3243 *num_streams = max_streams+1;
3246 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3247 if (*changed_ep_bitmask & endpoint_flag)
3249 *changed_ep_bitmask |= endpoint_flag;
3254 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3255 struct usb_device *udev,
3256 struct usb_host_endpoint **eps, unsigned int num_eps)
3258 u32 changed_ep_bitmask = 0;
3259 unsigned int slot_id;
3260 unsigned int ep_index;
3261 unsigned int ep_state;
3264 slot_id = udev->slot_id;
3265 if (!xhci->devs[slot_id])
3268 for (i = 0; i < num_eps; i++) {
3269 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3270 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3271 /* Are streams already being freed for the endpoint? */
3272 if (ep_state & EP_GETTING_NO_STREAMS) {
3273 xhci_warn(xhci, "WARN Can't disable streams for "
3275 "streams are being disabled already\n",
3276 eps[i]->desc.bEndpointAddress);
3279 /* Are there actually any streams to free? */
3280 if (!(ep_state & EP_HAS_STREAMS) &&
3281 !(ep_state & EP_GETTING_STREAMS)) {
3282 xhci_warn(xhci, "WARN Can't disable streams for "
3284 "streams are already disabled!\n",
3285 eps[i]->desc.bEndpointAddress);
3286 xhci_warn(xhci, "WARN xhci_free_streams() called "
3287 "with non-streams endpoint\n");
3290 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3292 return changed_ep_bitmask;
3296 * The USB device drivers use this function (through the HCD interface in USB
3297 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3298 * coordinate mass storage command queueing across multiple endpoints (basically
3299 * a stream ID == a task ID).
3301 * Setting up streams involves allocating the same size stream context array
3302 * for each endpoint and issuing a configure endpoint command for all endpoints.
3304 * Don't allow the call to succeed if one endpoint only supports one stream
3305 * (which means it doesn't support streams at all).
3307 * Drivers may get less stream IDs than they asked for, if the host controller
3308 * hardware or endpoints claim they can't support the number of requested
3311 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3312 struct usb_host_endpoint **eps, unsigned int num_eps,
3313 unsigned int num_streams, gfp_t mem_flags)
3316 struct xhci_hcd *xhci;
3317 struct xhci_virt_device *vdev;
3318 struct xhci_command *config_cmd;
3319 struct xhci_input_control_ctx *ctrl_ctx;
3320 unsigned int ep_index;
3321 unsigned int num_stream_ctxs;
3322 unsigned int max_packet;
3323 unsigned long flags;
3324 u32 changed_ep_bitmask = 0;
3329 /* Add one to the number of streams requested to account for
3330 * stream 0 that is reserved for xHCI usage.
3333 xhci = hcd_to_xhci(hcd);
3334 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3337 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3338 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3339 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3340 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3344 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3348 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3350 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3352 xhci_free_command(xhci, config_cmd);
3356 /* Check to make sure all endpoints are not already configured for
3357 * streams. While we're at it, find the maximum number of streams that
3358 * all the endpoints will support and check for duplicate endpoints.
3360 spin_lock_irqsave(&xhci->lock, flags);
3361 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3362 num_eps, &num_streams, &changed_ep_bitmask);
3364 xhci_free_command(xhci, config_cmd);
3365 spin_unlock_irqrestore(&xhci->lock, flags);
3368 if (num_streams <= 1) {
3369 xhci_warn(xhci, "WARN: endpoints can't handle "
3370 "more than one stream.\n");
3371 xhci_free_command(xhci, config_cmd);
3372 spin_unlock_irqrestore(&xhci->lock, flags);
3375 vdev = xhci->devs[udev->slot_id];
3376 /* Mark each endpoint as being in transition, so
3377 * xhci_urb_enqueue() will reject all URBs.
3379 for (i = 0; i < num_eps; i++) {
3380 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3381 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3383 spin_unlock_irqrestore(&xhci->lock, flags);
3385 /* Setup internal data structures and allocate HW data structures for
3386 * streams (but don't install the HW structures in the input context
3387 * until we're sure all memory allocation succeeded).
3389 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3390 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3391 num_stream_ctxs, num_streams);
3393 for (i = 0; i < num_eps; i++) {
3394 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3395 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3396 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3399 max_packet, mem_flags);
3400 if (!vdev->eps[ep_index].stream_info)
3402 /* Set maxPstreams in endpoint context and update deq ptr to
3403 * point to stream context array. FIXME
3407 /* Set up the input context for a configure endpoint command. */
3408 for (i = 0; i < num_eps; i++) {
3409 struct xhci_ep_ctx *ep_ctx;
3411 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3412 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3414 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3415 vdev->out_ctx, ep_index);
3416 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3417 vdev->eps[ep_index].stream_info);
3419 /* Tell the HW to drop its old copy of the endpoint context info
3420 * and add the updated copy from the input context.
3422 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3423 vdev->out_ctx, ctrl_ctx,
3424 changed_ep_bitmask, changed_ep_bitmask);
3426 /* Issue and wait for the configure endpoint command */
3427 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3430 /* xHC rejected the configure endpoint command for some reason, so we
3431 * leave the old ring intact and free our internal streams data
3437 spin_lock_irqsave(&xhci->lock, flags);
3438 for (i = 0; i < num_eps; i++) {
3439 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3440 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3441 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3442 udev->slot_id, ep_index);
3443 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3445 xhci_free_command(xhci, config_cmd);
3446 spin_unlock_irqrestore(&xhci->lock, flags);
3448 /* Subtract 1 for stream 0, which drivers can't use */
3449 return num_streams - 1;
3452 /* If it didn't work, free the streams! */
3453 for (i = 0; i < num_eps; i++) {
3454 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3455 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3456 vdev->eps[ep_index].stream_info = NULL;
3457 /* FIXME Unset maxPstreams in endpoint context and
3458 * update deq ptr to point to normal string ring.
3460 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3461 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3462 xhci_endpoint_zero(xhci, vdev, eps[i]);
3464 xhci_free_command(xhci, config_cmd);
3468 /* Transition the endpoint from using streams to being a "normal" endpoint
3471 * Modify the endpoint context state, submit a configure endpoint command,
3472 * and free all endpoint rings for streams if that completes successfully.
3474 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3475 struct usb_host_endpoint **eps, unsigned int num_eps,
3479 struct xhci_hcd *xhci;
3480 struct xhci_virt_device *vdev;
3481 struct xhci_command *command;
3482 struct xhci_input_control_ctx *ctrl_ctx;
3483 unsigned int ep_index;
3484 unsigned long flags;
3485 u32 changed_ep_bitmask;
3487 xhci = hcd_to_xhci(hcd);
3488 vdev = xhci->devs[udev->slot_id];
3490 /* Set up a configure endpoint command to remove the streams rings */
3491 spin_lock_irqsave(&xhci->lock, flags);
3492 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3493 udev, eps, num_eps);
3494 if (changed_ep_bitmask == 0) {
3495 spin_unlock_irqrestore(&xhci->lock, flags);
3499 /* Use the xhci_command structure from the first endpoint. We may have
3500 * allocated too many, but the driver may call xhci_free_streams() for
3501 * each endpoint it grouped into one call to xhci_alloc_streams().
3503 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3504 command = vdev->eps[ep_index].stream_info->free_streams_command;
3505 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3507 spin_unlock_irqrestore(&xhci->lock, flags);
3508 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3513 for (i = 0; i < num_eps; i++) {
3514 struct xhci_ep_ctx *ep_ctx;
3516 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3517 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3518 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3519 EP_GETTING_NO_STREAMS;
3521 xhci_endpoint_copy(xhci, command->in_ctx,
3522 vdev->out_ctx, ep_index);
3523 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3524 &vdev->eps[ep_index]);
3526 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3527 vdev->out_ctx, ctrl_ctx,
3528 changed_ep_bitmask, changed_ep_bitmask);
3529 spin_unlock_irqrestore(&xhci->lock, flags);
3531 /* Issue and wait for the configure endpoint command,
3532 * which must succeed.
3534 ret = xhci_configure_endpoint(xhci, udev, command,
3537 /* xHC rejected the configure endpoint command for some reason, so we
3538 * leave the streams rings intact.
3543 spin_lock_irqsave(&xhci->lock, flags);
3544 for (i = 0; i < num_eps; i++) {
3545 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3546 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3547 vdev->eps[ep_index].stream_info = NULL;
3548 /* FIXME Unset maxPstreams in endpoint context and
3549 * update deq ptr to point to normal string ring.
3551 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3552 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3554 spin_unlock_irqrestore(&xhci->lock, flags);
3560 * Deletes endpoint resources for endpoints that were active before a Reset
3561 * Device command, or a Disable Slot command. The Reset Device command leaves
3562 * the control endpoint intact, whereas the Disable Slot command deletes it.
3564 * Must be called with xhci->lock held.
3566 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3567 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3570 unsigned int num_dropped_eps = 0;
3571 unsigned int drop_flags = 0;
3573 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3574 if (virt_dev->eps[i].ring) {
3575 drop_flags |= 1 << i;
3579 xhci->num_active_eps -= num_dropped_eps;
3580 if (num_dropped_eps)
3581 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3582 "Dropped %u ep ctxs, flags = 0x%x, "
3584 num_dropped_eps, drop_flags,
3585 xhci->num_active_eps);
3589 * This submits a Reset Device Command, which will set the device state to 0,
3590 * set the device address to 0, and disable all the endpoints except the default
3591 * control endpoint. The USB core should come back and call
3592 * xhci_address_device(), and then re-set up the configuration. If this is
3593 * called because of a usb_reset_and_verify_device(), then the old alternate
3594 * settings will be re-installed through the normal bandwidth allocation
3597 * Wait for the Reset Device command to finish. Remove all structures
3598 * associated with the endpoints that were disabled. Clear the input device
3599 * structure? Reset the control endpoint 0 max packet size?
3601 * If the virt_dev to be reset does not exist or does not match the udev,
3602 * it means the device is lost, possibly due to the xHC restore error and
3603 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3604 * re-allocate the device.
3606 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3607 struct usb_device *udev)
3610 unsigned long flags;
3611 struct xhci_hcd *xhci;
3612 unsigned int slot_id;
3613 struct xhci_virt_device *virt_dev;
3614 struct xhci_command *reset_device_cmd;
3615 struct xhci_slot_ctx *slot_ctx;
3616 int old_active_eps = 0;
3618 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3621 xhci = hcd_to_xhci(hcd);
3622 slot_id = udev->slot_id;
3623 virt_dev = xhci->devs[slot_id];
3625 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3626 "not exist. Re-allocate the device\n", slot_id);
3627 ret = xhci_alloc_dev(hcd, udev);
3634 if (virt_dev->tt_info)
3635 old_active_eps = virt_dev->tt_info->active_eps;
3637 if (virt_dev->udev != udev) {
3638 /* If the virt_dev and the udev does not match, this virt_dev
3639 * may belong to another udev.
3640 * Re-allocate the device.
3642 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3643 "not match the udev. Re-allocate the device\n",
3645 ret = xhci_alloc_dev(hcd, udev);
3652 /* If device is not setup, there is no point in resetting it */
3653 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3654 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3655 SLOT_STATE_DISABLED)
3658 trace_xhci_discover_or_reset_device(slot_ctx);
3660 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3661 /* Allocate the command structure that holds the struct completion.
3662 * Assume we're in process context, since the normal device reset
3663 * process has to wait for the device anyway. Storage devices are
3664 * reset as part of error handling, so use GFP_NOIO instead of
3667 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3668 if (!reset_device_cmd) {
3669 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3673 /* Attempt to submit the Reset Device command to the command ring */
3674 spin_lock_irqsave(&xhci->lock, flags);
3676 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3678 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3679 spin_unlock_irqrestore(&xhci->lock, flags);
3680 goto command_cleanup;
3682 xhci_ring_cmd_db(xhci);
3683 spin_unlock_irqrestore(&xhci->lock, flags);
3685 /* Wait for the Reset Device command to finish */
3686 wait_for_completion(reset_device_cmd->completion);
3688 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3689 * unless we tried to reset a slot ID that wasn't enabled,
3690 * or the device wasn't in the addressed or configured state.
3692 ret = reset_device_cmd->status;
3694 case COMP_COMMAND_ABORTED:
3695 case COMP_COMMAND_RING_STOPPED:
3696 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3698 goto command_cleanup;
3699 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3700 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3701 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3703 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3704 xhci_dbg(xhci, "Not freeing device rings.\n");
3705 /* Don't treat this as an error. May change my mind later. */
3707 goto command_cleanup;
3709 xhci_dbg(xhci, "Successful reset device command.\n");
3712 if (xhci_is_vendor_info_code(xhci, ret))
3714 xhci_warn(xhci, "Unknown completion code %u for "
3715 "reset device command.\n", ret);
3717 goto command_cleanup;
3720 /* Free up host controller endpoint resources */
3721 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3722 spin_lock_irqsave(&xhci->lock, flags);
3723 /* Don't delete the default control endpoint resources */
3724 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3725 spin_unlock_irqrestore(&xhci->lock, flags);
3728 /* Everything but endpoint 0 is disabled, so free the rings. */
3729 for (i = 1; i < 31; i++) {
3730 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3732 if (ep->ep_state & EP_HAS_STREAMS) {
3733 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3734 xhci_get_endpoint_address(i));
3735 xhci_free_stream_info(xhci, ep->stream_info);
3736 ep->stream_info = NULL;
3737 ep->ep_state &= ~EP_HAS_STREAMS;
3741 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3742 xhci_free_endpoint_ring(xhci, virt_dev, i);
3744 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3745 xhci_drop_ep_from_interval_table(xhci,
3746 &virt_dev->eps[i].bw_info,
3751 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3753 /* If necessary, update the number of active TTs on this root port */
3754 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3758 xhci_free_command(xhci, reset_device_cmd);
3763 * At this point, the struct usb_device is about to go away, the device has
3764 * disconnected, and all traffic has been stopped and the endpoints have been
3765 * disabled. Free any HC data structures associated with that device.
3767 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3769 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3770 struct xhci_virt_device *virt_dev;
3771 struct xhci_slot_ctx *slot_ctx;
3774 #ifndef CONFIG_USB_DEFAULT_PERSIST
3776 * We called pm_runtime_get_noresume when the device was attached.
3777 * Decrement the counter here to allow controller to runtime suspend
3778 * if no devices remain.
3780 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3781 pm_runtime_put_noidle(hcd->self.controller);
3784 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3785 /* If the host is halted due to driver unload, we still need to free the
3788 if (ret <= 0 && ret != -ENODEV)
3791 virt_dev = xhci->devs[udev->slot_id];
3792 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3793 trace_xhci_free_dev(slot_ctx);
3795 /* Stop any wayward timer functions (which may grab the lock) */
3796 for (i = 0; i < 31; i++) {
3797 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3798 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3800 xhci_debugfs_remove_slot(xhci, udev->slot_id);
3801 virt_dev->udev = NULL;
3802 ret = xhci_disable_slot(xhci, udev->slot_id);
3804 xhci_free_virt_device(xhci, udev->slot_id);
3807 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3809 struct xhci_command *command;
3810 unsigned long flags;
3814 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3818 spin_lock_irqsave(&xhci->lock, flags);
3819 /* Don't disable the slot if the host controller is dead. */
3820 state = readl(&xhci->op_regs->status);
3821 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3822 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3823 spin_unlock_irqrestore(&xhci->lock, flags);
3828 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3831 spin_unlock_irqrestore(&xhci->lock, flags);
3835 xhci_ring_cmd_db(xhci);
3836 spin_unlock_irqrestore(&xhci->lock, flags);
3841 * Checks if we have enough host controller resources for the default control
3844 * Must be called with xhci->lock held.
3846 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3848 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3849 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3850 "Not enough ep ctxs: "
3851 "%u active, need to add 1, limit is %u.",
3852 xhci->num_active_eps, xhci->limit_active_eps);
3855 xhci->num_active_eps += 1;
3856 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3857 "Adding 1 ep ctx, %u now active.",
3858 xhci->num_active_eps);
3864 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3865 * timed out, or allocating memory failed. Returns 1 on success.
3867 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3869 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3870 struct xhci_virt_device *vdev;
3871 struct xhci_slot_ctx *slot_ctx;
3872 unsigned long flags;
3874 struct xhci_command *command;
3876 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3880 spin_lock_irqsave(&xhci->lock, flags);
3881 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3884 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3885 xhci_free_command(xhci, command);
3888 xhci_ring_cmd_db(xhci);
3889 spin_unlock_irqrestore(&xhci->lock, flags);
3891 wait_for_completion(command->completion);
3892 slot_id = command->slot_id;
3894 if (!slot_id || command->status != COMP_SUCCESS) {
3895 xhci_err(xhci, "Error while assigning device slot ID\n");
3896 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3898 readl(&xhci->cap_regs->hcs_params1)));
3899 xhci_free_command(xhci, command);
3903 xhci_free_command(xhci, command);
3905 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3906 spin_lock_irqsave(&xhci->lock, flags);
3907 ret = xhci_reserve_host_control_ep_resources(xhci);
3909 spin_unlock_irqrestore(&xhci->lock, flags);
3910 xhci_warn(xhci, "Not enough host resources, "
3911 "active endpoint contexts = %u\n",
3912 xhci->num_active_eps);
3915 spin_unlock_irqrestore(&xhci->lock, flags);
3917 /* Use GFP_NOIO, since this function can be called from
3918 * xhci_discover_or_reset_device(), which may be called as part of
3919 * mass storage driver error handling.
3921 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3922 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3925 vdev = xhci->devs[slot_id];
3926 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3927 trace_xhci_alloc_dev(slot_ctx);
3929 udev->slot_id = slot_id;
3931 xhci_debugfs_create_slot(xhci, slot_id);
3933 #ifndef CONFIG_USB_DEFAULT_PERSIST
3935 * If resetting upon resume, we can't put the controller into runtime
3936 * suspend if there is a device attached.
3938 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3939 pm_runtime_get_noresume(hcd->self.controller);
3942 /* Is this a LS or FS device under a HS hub? */
3943 /* Hub or peripherial? */
3947 ret = xhci_disable_slot(xhci, udev->slot_id);
3949 xhci_free_virt_device(xhci, udev->slot_id);
3955 * Issue an Address Device command and optionally send a corresponding
3956 * SetAddress request to the device.
3958 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3959 enum xhci_setup_dev setup)
3961 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3962 unsigned long flags;
3963 struct xhci_virt_device *virt_dev;
3965 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3966 struct xhci_slot_ctx *slot_ctx;
3967 struct xhci_input_control_ctx *ctrl_ctx;
3969 struct xhci_command *command = NULL;
3971 mutex_lock(&xhci->mutex);
3973 if (xhci->xhc_state) { /* dying, removing or halted */
3978 if (!udev->slot_id) {
3979 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3980 "Bad Slot ID %d", udev->slot_id);
3985 virt_dev = xhci->devs[udev->slot_id];
3987 if (WARN_ON(!virt_dev)) {
3989 * In plug/unplug torture test with an NEC controller,
3990 * a zero-dereference was observed once due to virt_dev = 0.
3991 * Print useful debug rather than crash if it is observed again!
3993 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3998 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3999 trace_xhci_setup_device_slot(slot_ctx);
4001 if (setup == SETUP_CONTEXT_ONLY) {
4002 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4003 SLOT_STATE_DEFAULT) {
4004 xhci_dbg(xhci, "Slot already in default state\n");
4009 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4015 command->in_ctx = virt_dev->in_ctx;
4017 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4018 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4020 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4026 * If this is the first Set Address since device plug-in or
4027 * virt_device realloaction after a resume with an xHCI power loss,
4028 * then set up the slot context.
4030 if (!slot_ctx->dev_info)
4031 xhci_setup_addressable_virt_dev(xhci, udev);
4032 /* Otherwise, update the control endpoint ring enqueue pointer. */
4034 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4035 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4036 ctrl_ctx->drop_flags = 0;
4038 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4039 le32_to_cpu(slot_ctx->dev_info) >> 27);
4041 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4042 spin_lock_irqsave(&xhci->lock, flags);
4043 trace_xhci_setup_device(virt_dev);
4044 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4045 udev->slot_id, setup);
4047 spin_unlock_irqrestore(&xhci->lock, flags);
4048 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4049 "FIXME: allocate a command ring segment");
4052 xhci_ring_cmd_db(xhci);
4053 spin_unlock_irqrestore(&xhci->lock, flags);
4055 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4056 wait_for_completion(command->completion);
4058 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4059 * the SetAddress() "recovery interval" required by USB and aborting the
4060 * command on a timeout.
4062 switch (command->status) {
4063 case COMP_COMMAND_ABORTED:
4064 case COMP_COMMAND_RING_STOPPED:
4065 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4068 case COMP_CONTEXT_STATE_ERROR:
4069 case COMP_SLOT_NOT_ENABLED_ERROR:
4070 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4071 act, udev->slot_id);
4074 case COMP_USB_TRANSACTION_ERROR:
4075 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4077 mutex_unlock(&xhci->mutex);
4078 ret = xhci_disable_slot(xhci, udev->slot_id);
4080 xhci_alloc_dev(hcd, udev);
4081 kfree(command->completion);
4084 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4085 dev_warn(&udev->dev,
4086 "ERROR: Incompatible device for setup %s command\n", act);
4090 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4091 "Successful setup %s command", act);
4095 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4096 act, command->status);
4097 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4103 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4104 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4105 "Op regs DCBAA ptr = %#016llx", temp_64);
4106 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4107 "Slot ID %d dcbaa entry @%p = %#016llx",
4109 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4110 (unsigned long long)
4111 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4112 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4113 "Output Context DMA address = %#08llx",
4114 (unsigned long long)virt_dev->out_ctx->dma);
4115 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4116 le32_to_cpu(slot_ctx->dev_info) >> 27);
4118 * USB core uses address 1 for the roothubs, so we add one to the
4119 * address given back to us by the HC.
4121 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4122 le32_to_cpu(slot_ctx->dev_info) >> 27);
4123 /* Zero the input context control for later use */
4124 ctrl_ctx->add_flags = 0;
4125 ctrl_ctx->drop_flags = 0;
4127 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4128 "Internal device address = %d",
4129 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4131 mutex_unlock(&xhci->mutex);
4133 kfree(command->completion);
4139 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4141 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4144 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4146 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4150 * Transfer the port index into real index in the HW port status
4151 * registers. Caculate offset between the port's PORTSC register
4152 * and port status base. Divide the number of per port register
4153 * to get the real index. The raw port number bases 1.
4155 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4157 struct xhci_hub *rhub;
4159 rhub = xhci_get_rhub(hcd);
4160 return rhub->ports[port1 - 1]->hw_portnum + 1;
4164 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4165 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4167 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4168 struct usb_device *udev, u16 max_exit_latency)
4170 struct xhci_virt_device *virt_dev;
4171 struct xhci_command *command;
4172 struct xhci_input_control_ctx *ctrl_ctx;
4173 struct xhci_slot_ctx *slot_ctx;
4174 unsigned long flags;
4177 spin_lock_irqsave(&xhci->lock, flags);
4179 virt_dev = xhci->devs[udev->slot_id];
4182 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4183 * xHC was re-initialized. Exit latency will be set later after
4184 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4187 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4188 spin_unlock_irqrestore(&xhci->lock, flags);
4192 /* Attempt to issue an Evaluate Context command to change the MEL. */
4193 command = xhci->lpm_command;
4194 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4196 spin_unlock_irqrestore(&xhci->lock, flags);
4197 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4202 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4203 spin_unlock_irqrestore(&xhci->lock, flags);
4205 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4206 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4207 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4208 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4209 slot_ctx->dev_state = 0;
4211 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4212 "Set up evaluate context for LPM MEL change.");
4214 /* Issue and wait for the evaluate context command. */
4215 ret = xhci_configure_endpoint(xhci, udev, command,
4219 spin_lock_irqsave(&xhci->lock, flags);
4220 virt_dev->current_mel = max_exit_latency;
4221 spin_unlock_irqrestore(&xhci->lock, flags);
4228 /* BESL to HIRD Encoding array for USB2 LPM */
4229 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4230 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4232 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4233 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4234 struct usb_device *udev)
4236 int u2del, besl, besl_host;
4237 int besl_device = 0;
4240 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4241 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4243 if (field & USB_BESL_SUPPORT) {
4244 for (besl_host = 0; besl_host < 16; besl_host++) {
4245 if (xhci_besl_encoding[besl_host] >= u2del)
4248 /* Use baseline BESL value as default */
4249 if (field & USB_BESL_BASELINE_VALID)
4250 besl_device = USB_GET_BESL_BASELINE(field);
4251 else if (field & USB_BESL_DEEP_VALID)
4252 besl_device = USB_GET_BESL_DEEP(field);
4257 besl_host = (u2del - 51) / 75 + 1;
4260 besl = besl_host + besl_device;
4267 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4268 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4275 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4277 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4278 l1 = udev->l1_params.timeout / 256;
4280 /* device has preferred BESLD */
4281 if (field & USB_BESL_DEEP_VALID) {
4282 besld = USB_GET_BESL_DEEP(field);
4286 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4289 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4290 struct usb_device *udev, int enable)
4292 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4293 struct xhci_port **ports;
4294 __le32 __iomem *pm_addr, *hlpm_addr;
4295 u32 pm_val, hlpm_val, field;
4296 unsigned int port_num;
4297 unsigned long flags;
4298 int hird, exit_latency;
4301 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4305 if (!udev->parent || udev->parent->parent ||
4306 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4309 if (udev->usb2_hw_lpm_capable != 1)
4312 spin_lock_irqsave(&xhci->lock, flags);
4314 ports = xhci->usb2_rhub.ports;
4315 port_num = udev->portnum - 1;
4316 pm_addr = ports[port_num]->addr + PORTPMSC;
4317 pm_val = readl(pm_addr);
4318 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4319 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4321 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4322 enable ? "enable" : "disable", port_num + 1);
4324 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4325 /* Host supports BESL timeout instead of HIRD */
4326 if (udev->usb2_hw_lpm_besl_capable) {
4327 /* if device doesn't have a preferred BESL value use a
4328 * default one which works with mixed HIRD and BESL
4329 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4331 if ((field & USB_BESL_SUPPORT) &&
4332 (field & USB_BESL_BASELINE_VALID))
4333 hird = USB_GET_BESL_BASELINE(field);
4335 hird = udev->l1_params.besl;
4337 exit_latency = xhci_besl_encoding[hird];
4338 spin_unlock_irqrestore(&xhci->lock, flags);
4340 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4341 * input context for link powermanagement evaluate
4342 * context commands. It is protected by hcd->bandwidth
4343 * mutex and is shared by all devices. We need to set
4344 * the max ext latency in USB 2 BESL LPM as well, so
4345 * use the same mutex and xhci_change_max_exit_latency()
4347 mutex_lock(hcd->bandwidth_mutex);
4348 ret = xhci_change_max_exit_latency(xhci, udev,
4350 mutex_unlock(hcd->bandwidth_mutex);
4354 spin_lock_irqsave(&xhci->lock, flags);
4356 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4357 writel(hlpm_val, hlpm_addr);
4361 hird = xhci_calculate_hird_besl(xhci, udev);
4364 pm_val &= ~PORT_HIRD_MASK;
4365 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4366 writel(pm_val, pm_addr);
4367 pm_val = readl(pm_addr);
4369 writel(pm_val, pm_addr);
4373 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4374 writel(pm_val, pm_addr);
4377 if (udev->usb2_hw_lpm_besl_capable) {
4378 spin_unlock_irqrestore(&xhci->lock, flags);
4379 mutex_lock(hcd->bandwidth_mutex);
4380 xhci_change_max_exit_latency(xhci, udev, 0);
4381 mutex_unlock(hcd->bandwidth_mutex);
4386 spin_unlock_irqrestore(&xhci->lock, flags);
4390 /* check if a usb2 port supports a given extened capability protocol
4391 * only USB2 ports extended protocol capability values are cached.
4392 * Return 1 if capability is supported
4394 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4395 unsigned capability)
4397 u32 port_offset, port_count;
4400 for (i = 0; i < xhci->num_ext_caps; i++) {
4401 if (xhci->ext_caps[i] & capability) {
4402 /* port offsets starts at 1 */
4403 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4404 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4405 if (port >= port_offset &&
4406 port < port_offset + port_count)
4413 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4415 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4416 int portnum = udev->portnum - 1;
4418 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4421 /* we only support lpm for non-hub device connected to root hub yet */
4422 if (!udev->parent || udev->parent->parent ||
4423 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4426 if (xhci->hw_lpm_support == 1 &&
4427 xhci_check_usb2_port_capability(
4428 xhci, portnum, XHCI_HLC)) {
4429 udev->usb2_hw_lpm_capable = 1;
4430 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4431 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4432 if (xhci_check_usb2_port_capability(xhci, portnum,
4434 udev->usb2_hw_lpm_besl_capable = 1;
4440 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4442 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4443 static unsigned long long xhci_service_interval_to_ns(
4444 struct usb_endpoint_descriptor *desc)
4446 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4449 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4450 enum usb3_link_state state)
4452 unsigned long long sel;
4453 unsigned long long pel;
4454 unsigned int max_sel_pel;
4459 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4460 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4461 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4462 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4466 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4467 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4468 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4472 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4474 return USB3_LPM_DISABLED;
4477 if (sel <= max_sel_pel && pel <= max_sel_pel)
4478 return USB3_LPM_DEVICE_INITIATED;
4480 if (sel > max_sel_pel)
4481 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4482 "due to long SEL %llu ms\n",
4485 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4486 "due to long PEL %llu ms\n",
4488 return USB3_LPM_DISABLED;
4491 /* The U1 timeout should be the maximum of the following values:
4492 * - For control endpoints, U1 system exit latency (SEL) * 3
4493 * - For bulk endpoints, U1 SEL * 5
4494 * - For interrupt endpoints:
4495 * - Notification EPs, U1 SEL * 3
4496 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4497 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4499 static unsigned long long xhci_calculate_intel_u1_timeout(
4500 struct usb_device *udev,
4501 struct usb_endpoint_descriptor *desc)
4503 unsigned long long timeout_ns;
4507 ep_type = usb_endpoint_type(desc);
4509 case USB_ENDPOINT_XFER_CONTROL:
4510 timeout_ns = udev->u1_params.sel * 3;
4512 case USB_ENDPOINT_XFER_BULK:
4513 timeout_ns = udev->u1_params.sel * 5;
4515 case USB_ENDPOINT_XFER_INT:
4516 intr_type = usb_endpoint_interrupt_type(desc);
4517 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4518 timeout_ns = udev->u1_params.sel * 3;
4521 /* Otherwise the calculation is the same as isoc eps */
4523 case USB_ENDPOINT_XFER_ISOC:
4524 timeout_ns = xhci_service_interval_to_ns(desc);
4525 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4526 if (timeout_ns < udev->u1_params.sel * 2)
4527 timeout_ns = udev->u1_params.sel * 2;
4536 /* Returns the hub-encoded U1 timeout value. */
4537 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4538 struct usb_device *udev,
4539 struct usb_endpoint_descriptor *desc)
4541 unsigned long long timeout_ns;
4543 /* Prevent U1 if service interval is shorter than U1 exit latency */
4544 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4545 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4546 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4547 return USB3_LPM_DISABLED;
4551 if (xhci->quirks & XHCI_INTEL_HOST)
4552 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4554 timeout_ns = udev->u1_params.sel;
4556 /* The U1 timeout is encoded in 1us intervals.
4557 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4559 if (timeout_ns == USB3_LPM_DISABLED)
4562 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4564 /* If the necessary timeout value is bigger than what we can set in the
4565 * USB 3.0 hub, we have to disable hub-initiated U1.
4567 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4569 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4570 "due to long timeout %llu ms\n", timeout_ns);
4571 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4574 /* The U2 timeout should be the maximum of:
4575 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4576 * - largest bInterval of any active periodic endpoint (to avoid going
4577 * into lower power link states between intervals).
4578 * - the U2 Exit Latency of the device
4580 static unsigned long long xhci_calculate_intel_u2_timeout(
4581 struct usb_device *udev,
4582 struct usb_endpoint_descriptor *desc)
4584 unsigned long long timeout_ns;
4585 unsigned long long u2_del_ns;
4587 timeout_ns = 10 * 1000 * 1000;
4589 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4590 (xhci_service_interval_to_ns(desc) > timeout_ns))
4591 timeout_ns = xhci_service_interval_to_ns(desc);
4593 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4594 if (u2_del_ns > timeout_ns)
4595 timeout_ns = u2_del_ns;
4600 /* Returns the hub-encoded U2 timeout value. */
4601 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4602 struct usb_device *udev,
4603 struct usb_endpoint_descriptor *desc)
4605 unsigned long long timeout_ns;
4607 /* Prevent U2 if service interval is shorter than U2 exit latency */
4608 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4609 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4610 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4611 return USB3_LPM_DISABLED;
4615 if (xhci->quirks & XHCI_INTEL_HOST)
4616 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4618 timeout_ns = udev->u2_params.sel;
4620 /* The U2 timeout is encoded in 256us intervals */
4621 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4622 /* If the necessary timeout value is bigger than what we can set in the
4623 * USB 3.0 hub, we have to disable hub-initiated U2.
4625 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4627 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4628 "due to long timeout %llu ms\n", timeout_ns);
4629 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4632 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4633 struct usb_device *udev,
4634 struct usb_endpoint_descriptor *desc,
4635 enum usb3_link_state state,
4638 if (state == USB3_LPM_U1)
4639 return xhci_calculate_u1_timeout(xhci, udev, desc);
4640 else if (state == USB3_LPM_U2)
4641 return xhci_calculate_u2_timeout(xhci, udev, desc);
4643 return USB3_LPM_DISABLED;
4646 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4647 struct usb_device *udev,
4648 struct usb_endpoint_descriptor *desc,
4649 enum usb3_link_state state,
4654 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4655 desc, state, timeout);
4657 /* If we found we can't enable hub-initiated LPM, or
4658 * the U1 or U2 exit latency was too high to allow
4659 * device-initiated LPM as well, just stop searching.
4661 if (alt_timeout == USB3_LPM_DISABLED ||
4662 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4663 *timeout = alt_timeout;
4666 if (alt_timeout > *timeout)
4667 *timeout = alt_timeout;
4671 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4672 struct usb_device *udev,
4673 struct usb_host_interface *alt,
4674 enum usb3_link_state state,
4679 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4680 if (xhci_update_timeout_for_endpoint(xhci, udev,
4681 &alt->endpoint[j].desc, state, timeout))
4688 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4689 enum usb3_link_state state)
4691 struct usb_device *parent;
4692 unsigned int num_hubs;
4694 if (state == USB3_LPM_U2)
4697 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4698 for (parent = udev->parent, num_hubs = 0; parent->parent;
4699 parent = parent->parent)
4705 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4706 " below second-tier hub.\n");
4707 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4708 "to decrease power consumption.\n");
4712 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4713 struct usb_device *udev,
4714 enum usb3_link_state state)
4716 if (xhci->quirks & XHCI_INTEL_HOST)
4717 return xhci_check_intel_tier_policy(udev, state);
4722 /* Returns the U1 or U2 timeout that should be enabled.
4723 * If the tier check or timeout setting functions return with a non-zero exit
4724 * code, that means the timeout value has been finalized and we shouldn't look
4725 * at any more endpoints.
4727 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4728 struct usb_device *udev, enum usb3_link_state state)
4730 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4731 struct usb_host_config *config;
4734 u16 timeout = USB3_LPM_DISABLED;
4736 if (state == USB3_LPM_U1)
4738 else if (state == USB3_LPM_U2)
4741 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4746 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4749 /* Gather some information about the currently installed configuration
4750 * and alternate interface settings.
4752 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4756 config = udev->actconfig;
4760 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4761 struct usb_driver *driver;
4762 struct usb_interface *intf = config->interface[i];
4767 /* Check if any currently bound drivers want hub-initiated LPM
4770 if (intf->dev.driver) {
4771 driver = to_usb_driver(intf->dev.driver);
4772 if (driver && driver->disable_hub_initiated_lpm) {
4773 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4774 "at request of driver %s\n",
4775 state_name, driver->name);
4776 return xhci_get_timeout_no_hub_lpm(udev, state);
4780 /* Not sure how this could happen... */
4781 if (!intf->cur_altsetting)
4784 if (xhci_update_timeout_for_interface(xhci, udev,
4785 intf->cur_altsetting,
4792 static int calculate_max_exit_latency(struct usb_device *udev,
4793 enum usb3_link_state state_changed,
4794 u16 hub_encoded_timeout)
4796 unsigned long long u1_mel_us = 0;
4797 unsigned long long u2_mel_us = 0;
4798 unsigned long long mel_us = 0;
4804 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4805 hub_encoded_timeout == USB3_LPM_DISABLED);
4806 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4807 hub_encoded_timeout == USB3_LPM_DISABLED);
4809 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4810 hub_encoded_timeout != USB3_LPM_DISABLED);
4811 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4812 hub_encoded_timeout != USB3_LPM_DISABLED);
4814 /* If U1 was already enabled and we're not disabling it,
4815 * or we're going to enable U1, account for the U1 max exit latency.
4817 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4819 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4820 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4822 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4824 if (u1_mel_us > u2_mel_us)
4828 /* xHCI host controller max exit latency field is only 16 bits wide. */
4829 if (mel_us > MAX_EXIT) {
4830 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4831 "is too big.\n", mel_us);
4837 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4838 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4839 struct usb_device *udev, enum usb3_link_state state)
4841 struct xhci_hcd *xhci;
4842 u16 hub_encoded_timeout;
4846 xhci = hcd_to_xhci(hcd);
4847 /* The LPM timeout values are pretty host-controller specific, so don't
4848 * enable hub-initiated timeouts unless the vendor has provided
4849 * information about their timeout algorithm.
4851 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4852 !xhci->devs[udev->slot_id])
4853 return USB3_LPM_DISABLED;
4855 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4856 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4858 /* Max Exit Latency is too big, disable LPM. */
4859 hub_encoded_timeout = USB3_LPM_DISABLED;
4863 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4866 return hub_encoded_timeout;
4869 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4870 struct usb_device *udev, enum usb3_link_state state)
4872 struct xhci_hcd *xhci;
4875 xhci = hcd_to_xhci(hcd);
4876 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4877 !xhci->devs[udev->slot_id])
4880 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4881 return xhci_change_max_exit_latency(xhci, udev, mel);
4883 #else /* CONFIG_PM */
4885 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4886 struct usb_device *udev, int enable)
4891 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4896 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4897 struct usb_device *udev, enum usb3_link_state state)
4899 return USB3_LPM_DISABLED;
4902 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4903 struct usb_device *udev, enum usb3_link_state state)
4907 #endif /* CONFIG_PM */
4909 /*-------------------------------------------------------------------------*/
4911 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4912 * internal data structures for the device.
4914 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4915 struct usb_tt *tt, gfp_t mem_flags)
4917 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4918 struct xhci_virt_device *vdev;
4919 struct xhci_command *config_cmd;
4920 struct xhci_input_control_ctx *ctrl_ctx;
4921 struct xhci_slot_ctx *slot_ctx;
4922 unsigned long flags;
4923 unsigned think_time;
4926 /* Ignore root hubs */
4930 vdev = xhci->devs[hdev->slot_id];
4932 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4936 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
4940 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4942 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4944 xhci_free_command(xhci, config_cmd);
4948 spin_lock_irqsave(&xhci->lock, flags);
4949 if (hdev->speed == USB_SPEED_HIGH &&
4950 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4951 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4952 xhci_free_command(xhci, config_cmd);
4953 spin_unlock_irqrestore(&xhci->lock, flags);
4957 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4958 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4959 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4960 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4962 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4963 * but it may be already set to 1 when setup an xHCI virtual
4964 * device, so clear it anyway.
4967 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4968 else if (hdev->speed == USB_SPEED_FULL)
4969 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4971 if (xhci->hci_version > 0x95) {
4972 xhci_dbg(xhci, "xHCI version %x needs hub "
4973 "TT think time and number of ports\n",
4974 (unsigned int) xhci->hci_version);
4975 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4976 /* Set TT think time - convert from ns to FS bit times.
4977 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4978 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4980 * xHCI 1.0: this field shall be 0 if the device is not a
4983 think_time = tt->think_time;
4984 if (think_time != 0)
4985 think_time = (think_time / 666) - 1;
4986 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4987 slot_ctx->tt_info |=
4988 cpu_to_le32(TT_THINK_TIME(think_time));
4990 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4991 "TT think time or number of ports\n",
4992 (unsigned int) xhci->hci_version);
4994 slot_ctx->dev_state = 0;
4995 spin_unlock_irqrestore(&xhci->lock, flags);
4997 xhci_dbg(xhci, "Set up %s for hub device.\n",
4998 (xhci->hci_version > 0x95) ?
4999 "configure endpoint" : "evaluate context");
5001 /* Issue and wait for the configure endpoint or
5002 * evaluate context command.
5004 if (xhci->hci_version > 0x95)
5005 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5008 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5011 xhci_free_command(xhci, config_cmd);
5015 static int xhci_get_frame(struct usb_hcd *hcd)
5017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5018 /* EHCI mods by the periodic size. Why? */
5019 return readl(&xhci->run_regs->microframe_index) >> 3;
5022 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5024 struct xhci_hcd *xhci;
5026 * TODO: Check with DWC3 clients for sysdev according to
5029 struct device *dev = hcd->self.sysdev;
5030 unsigned int minor_rev;
5033 /* Accept arbitrarily long scatter-gather lists */
5034 hcd->self.sg_tablesize = ~0;
5036 /* support to build packet from discontinuous buffers */
5037 hcd->self.no_sg_constraint = 1;
5039 /* XHCI controllers don't stop the ep queue on short packets :| */
5040 hcd->self.no_stop_on_short = 1;
5042 xhci = hcd_to_xhci(hcd);
5044 if (usb_hcd_is_primary_hcd(hcd)) {
5045 xhci->main_hcd = hcd;
5046 xhci->usb2_rhub.hcd = hcd;
5047 /* Mark the first roothub as being USB 2.0.
5048 * The xHCI driver will register the USB 3.0 roothub.
5050 hcd->speed = HCD_USB2;
5051 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5053 * USB 2.0 roothub under xHCI has an integrated TT,
5054 * (rate matching hub) as opposed to having an OHCI/UHCI
5055 * companion controller.
5060 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
5061 * minor revision instead of sbrn
5063 minor_rev = xhci->usb3_rhub.min_rev;
5065 hcd->speed = HCD_USB31;
5066 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5068 xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n",
5070 minor_rev ? "Enhanced" : "");
5072 xhci->usb3_rhub.hcd = hcd;
5073 /* xHCI private pointer was set in xhci_pci_probe for the second
5074 * registered roothub.
5079 mutex_init(&xhci->mutex);
5080 xhci->cap_regs = hcd->regs;
5081 xhci->op_regs = hcd->regs +
5082 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5083 xhci->run_regs = hcd->regs +
5084 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5085 /* Cache read-only capability registers */
5086 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5087 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5088 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5089 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5090 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5091 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5092 if (xhci->hci_version > 0x100)
5093 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5095 xhci->quirks |= quirks;
5097 get_quirks(dev, xhci);
5099 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5100 * success event after a short transfer. This quirk will ignore such
5103 if (xhci->hci_version > 0x96)
5104 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5106 /* Make sure the HC is halted. */
5107 retval = xhci_halt(xhci);
5111 xhci_zero_64b_regs(xhci);
5113 xhci_dbg(xhci, "Resetting HCD\n");
5114 /* Reset the internal HC memory state and registers. */
5115 retval = xhci_reset(xhci);
5118 xhci_dbg(xhci, "Reset complete\n");
5121 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5122 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5123 * address memory pointers actually. So, this driver clears the AC64
5124 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5125 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5127 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5128 xhci->hcc_params &= ~BIT(0);
5130 /* Set dma_mask and coherent_dma_mask to 64-bits,
5131 * if xHC supports 64-bit addressing */
5132 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5133 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5134 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5135 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5138 * This is to avoid error in cases where a 32-bit USB
5139 * controller is used on a 64-bit capable system.
5141 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5144 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5145 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5148 xhci_dbg(xhci, "Calling HCD init\n");
5149 /* Initialize HCD and host controller data structures. */
5150 retval = xhci_init(hcd);
5153 xhci_dbg(xhci, "Called HCD init\n");
5155 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5156 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5160 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5162 static const struct hc_driver xhci_hc_driver = {
5163 .description = "xhci-hcd",
5164 .product_desc = "xHCI Host Controller",
5165 .hcd_priv_size = sizeof(struct xhci_hcd),
5168 * generic hardware linkage
5171 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5174 * basic lifecycle operations
5176 .reset = NULL, /* set in xhci_init_driver() */
5179 .shutdown = xhci_shutdown,
5182 * managing i/o requests and associated device resources
5184 .map_urb_for_dma = xhci_map_urb_for_dma,
5185 .urb_enqueue = xhci_urb_enqueue,
5186 .urb_dequeue = xhci_urb_dequeue,
5187 .alloc_dev = xhci_alloc_dev,
5188 .free_dev = xhci_free_dev,
5189 .alloc_streams = xhci_alloc_streams,
5190 .free_streams = xhci_free_streams,
5191 .add_endpoint = xhci_add_endpoint,
5192 .drop_endpoint = xhci_drop_endpoint,
5193 .endpoint_reset = xhci_endpoint_reset,
5194 .check_bandwidth = xhci_check_bandwidth,
5195 .reset_bandwidth = xhci_reset_bandwidth,
5196 .address_device = xhci_address_device,
5197 .enable_device = xhci_enable_device,
5198 .update_hub_device = xhci_update_hub_device,
5199 .reset_device = xhci_discover_or_reset_device,
5202 * scheduling support
5204 .get_frame_number = xhci_get_frame,
5209 .hub_control = xhci_hub_control,
5210 .hub_status_data = xhci_hub_status_data,
5211 .bus_suspend = xhci_bus_suspend,
5212 .bus_resume = xhci_bus_resume,
5213 .get_resuming_ports = xhci_get_resuming_ports,
5216 * call back when device connected and addressed
5218 .update_device = xhci_update_device,
5219 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5220 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5221 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5222 .find_raw_port_number = xhci_find_raw_port_number,
5225 void xhci_init_driver(struct hc_driver *drv,
5226 const struct xhci_driver_overrides *over)
5230 /* Copy the generic table to drv then apply the overrides */
5231 *drv = xhci_hc_driver;
5234 drv->hcd_priv_size += over->extra_priv_size;
5236 drv->reset = over->reset;
5238 drv->start = over->start;
5241 EXPORT_SYMBOL_GPL(xhci_init_driver);
5243 MODULE_DESCRIPTION(DRIVER_DESC);
5244 MODULE_AUTHOR(DRIVER_AUTHOR);
5245 MODULE_LICENSE("GPL");
5247 static int __init xhci_hcd_init(void)
5250 * Check the compiler generated sizes of structures that must be laid
5251 * out in specific ways for hardware access.
5253 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5254 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5255 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5256 /* xhci_device_control has eight fields, and also
5257 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5259 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5260 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5261 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5262 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5263 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5264 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5265 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5270 xhci_debugfs_create_root();
5276 * If an init function is provided, an exit function must also be provided
5277 * to allow module unload.
5279 static void __exit xhci_hcd_fini(void)
5281 xhci_debugfs_remove_root();
5284 module_init(xhci_hcd_init);
5285 module_exit(xhci_hcd_fini);