1 // SPDX-License-Identifier: GPL-2.0
3 * NVIDIA Tegra xHCI host controller driver
5 * Copyright (C) 2014 NVIDIA Corporation
6 * Copyright (C) 2014 Google, Inc.
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/tegra/xusb.h>
20 #include <linux/platform_device.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/reset.h>
26 #include <linux/slab.h>
27 #include <soc/tegra/pmc.h>
31 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
32 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
34 /* FPCI CFG registers */
35 #define XUSB_CFG_1 0x004
36 #define XUSB_IO_SPACE_EN BIT(0)
37 #define XUSB_MEM_SPACE_EN BIT(1)
38 #define XUSB_BUS_MASTER_EN BIT(2)
39 #define XUSB_CFG_4 0x010
40 #define XUSB_BASE_ADDR_SHIFT 15
41 #define XUSB_BASE_ADDR_MASK 0x1ffff
42 #define XUSB_CFG_16 0x040
43 #define XUSB_CFG_24 0x060
44 #define XUSB_CFG_AXI_CFG 0x0f8
45 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
46 #define XUSB_CFG_ARU_CONTEXT 0x43c
47 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478
48 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c
49 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480
50 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484
51 #define XUSB_CFG_CSB_BASE_ADDR 0x800
53 /* FPCI mailbox registers */
54 /* XUSB_CFG_ARU_MBOX_CMD */
55 #define MBOX_DEST_FALC BIT(27)
56 #define MBOX_DEST_PME BIT(28)
57 #define MBOX_DEST_SMI BIT(29)
58 #define MBOX_DEST_XHCI BIT(30)
59 #define MBOX_INT_EN BIT(31)
60 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
61 #define CMD_DATA_SHIFT 0
62 #define CMD_DATA_MASK 0xffffff
63 #define CMD_TYPE_SHIFT 24
64 #define CMD_TYPE_MASK 0xff
65 /* XUSB_CFG_ARU_MBOX_OWNER */
66 #define MBOX_OWNER_NONE 0
67 #define MBOX_OWNER_FW 1
68 #define MBOX_OWNER_SW 2
69 #define XUSB_CFG_ARU_SMI_INTR 0x428
70 #define MBOX_SMI_INTR_FW_HANG BIT(1)
71 #define MBOX_SMI_INTR_EN BIT(3)
74 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0
75 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4
76 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8
77 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100
78 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140
79 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
80 #define IPFS_EN_FPCI BIT(0)
81 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184
82 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
83 #define IPFS_IP_INT_MASK BIT(16)
84 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198
85 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c
86 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
87 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc
89 #define CSB_PAGE_SELECT_MASK 0x7fffff
90 #define CSB_PAGE_SELECT_SHIFT 9
91 #define CSB_PAGE_OFFSET_MASK 0x1ff
92 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
94 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
96 /* Falcon CSB registers */
97 #define XUSB_FALC_CPUCTL 0x100
98 #define CPUCTL_STARTCPU BIT(1)
99 #define CPUCTL_STATE_HALTED BIT(4)
100 #define CPUCTL_STATE_STOPPED BIT(5)
101 #define XUSB_FALC_BOOTVEC 0x104
102 #define XUSB_FALC_DMACTL 0x10c
103 #define XUSB_FALC_IMFILLRNG1 0x154
104 #define IMFILLRNG1_TAG_MASK 0xffff
105 #define IMFILLRNG1_TAG_LO_SHIFT 0
106 #define IMFILLRNG1_TAG_HI_SHIFT 16
107 #define XUSB_FALC_IMFILLCTL 0x158
109 /* MP CSB registers */
110 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
111 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
112 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
113 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
114 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
115 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
116 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
117 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
118 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
119 #define L2IMEMOP_ACTION_SHIFT 24
120 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
121 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
122 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18
123 #define L2IMEMOP_RESULT_VLD BIT(31)
124 #define XUSB_CSB_MP_APMAP 0x10181c
125 #define APMAP_BOOTPATH BIT(31)
127 #define IMEM_BLOCK_SIZE 256
129 struct tegra_xusb_fw_header {
130 __le32 boot_loadaddr_in_imem;
131 __le32 boot_codedfi_offset;
133 __le32 boot_codesize;
135 __le16 reqphys_memsize;
136 __le16 alloc_phys_memsize;
137 __le32 rodata_img_offset;
138 __le32 rodata_section_start;
139 __le32 rodata_section_end;
142 __le32 fwimg_created_time;
143 __le32 imem_resident_start;
144 __le32 imem_resident_end;
145 __le32 idirect_start;
147 __le32 l2_imem_start;
152 __le32 phys_addr_log_buffer;
153 __le32 total_log_entries;
158 __le32 ss_low_power_entry_timeout;
160 u8 padding[139]; /* Pad to 256 bytes */
163 struct tegra_xusb_phy_type {
168 struct tegra_xusb_mbox_regs {
175 struct tegra_xusb_context_soc {
177 const unsigned int *offsets;
178 unsigned int num_offsets;
182 const unsigned int *offsets;
183 unsigned int num_offsets;
187 struct tegra_xusb_soc {
188 const char *firmware;
189 const char * const *supply_names;
190 unsigned int num_supplies;
191 const struct tegra_xusb_phy_type *phy_types;
192 unsigned int num_types;
193 const struct tegra_xusb_context_soc *context;
199 } usb2, ulpi, hsic, usb3;
202 struct tegra_xusb_mbox_regs mbox;
208 struct tegra_xusb_context {
223 void __iomem *ipfs_base;
224 void __iomem *fpci_base;
226 const struct tegra_xusb_soc *soc;
228 struct regulator_bulk_data *supplies;
230 struct tegra_xusb_padctl *padctl;
232 struct clk *host_clk;
233 struct clk *falcon_clk;
235 struct clk *ss_src_clk;
236 struct clk *hs_src_clk;
237 struct clk *fs_src_clk;
238 struct clk *pll_u_480m;
242 struct reset_control *host_rst;
243 struct reset_control *ss_rst;
245 struct device *genpd_dev_host;
246 struct device *genpd_dev_ss;
247 struct device_link *genpd_dl_host;
248 struct device_link *genpd_dl_ss;
251 unsigned int num_phys;
253 /* Firmware loading related */
260 struct tegra_xusb_context context;
263 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
265 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
267 return readl(tegra->fpci_base + offset);
270 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
273 writel(value, tegra->fpci_base + offset);
276 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
278 return readl(tegra->ipfs_base + offset);
281 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
284 writel(value, tegra->ipfs_base + offset);
287 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
289 u32 page = CSB_PAGE_SELECT(offset);
290 u32 ofs = CSB_PAGE_OFFSET(offset);
292 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
294 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
297 static void csb_writel(struct tegra_xusb *tegra, u32 value,
300 u32 page = CSB_PAGE_SELECT(offset);
301 u32 ofs = CSB_PAGE_OFFSET(offset);
303 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
304 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
307 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
310 unsigned long new_parent_rate, old_parent_rate;
311 struct clk *clk = tegra->ss_src_clk;
315 if (clk_get_rate(clk) == rate)
319 case TEGRA_XHCI_SS_HIGH_SPEED:
321 * Reparent to PLLU_480M. Set divider first to avoid
324 old_parent_rate = clk_get_rate(clk_get_parent(clk));
325 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
326 div = new_parent_rate / rate;
328 err = clk_set_rate(clk, old_parent_rate / div);
332 err = clk_set_parent(clk, tegra->pll_u_480m);
337 * The rate should already be correct, but set it again just
340 err = clk_set_rate(clk, rate);
346 case TEGRA_XHCI_SS_LOW_SPEED:
347 /* Reparent to CLK_M */
348 err = clk_set_parent(clk, tegra->clk_m);
352 err = clk_set_rate(clk, rate);
359 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
363 if (clk_get_rate(clk) != rate) {
364 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
371 static unsigned long extract_field(u32 value, unsigned int start,
374 return (value >> start) & ((1 << count) - 1);
377 /* Command requests from the firmware */
378 enum tegra_xusb_mbox_cmd {
379 MBOX_CMD_MSG_ENABLED = 1,
380 MBOX_CMD_INC_FALC_CLOCK,
381 MBOX_CMD_DEC_FALC_CLOCK,
382 MBOX_CMD_INC_SSPI_CLOCK,
383 MBOX_CMD_DEC_SSPI_CLOCK,
384 MBOX_CMD_SET_BW, /* no ACK/NAK required */
385 MBOX_CMD_SET_SS_PWR_GATING,
386 MBOX_CMD_SET_SS_PWR_UNGATING,
387 MBOX_CMD_SAVE_DFE_CTLE_CTX,
388 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
389 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
390 MBOX_CMD_START_HSIC_IDLE,
391 MBOX_CMD_STOP_HSIC_IDLE,
392 MBOX_CMD_DBC_WAKE_STACK, /* unused */
393 MBOX_CMD_HSIC_PRETEND_CONNECT,
395 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
396 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
400 /* Response message to above commands */
405 struct tegra_xusb_mbox_msg {
410 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
412 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
413 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
415 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
418 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
419 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
422 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
425 case MBOX_CMD_SET_BW:
435 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
436 const struct tegra_xusb_mbox_msg *msg)
438 bool wait_for_idle = false;
442 * Acquire the mailbox. The firmware still owns the mailbox for
445 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
446 value = fpci_readl(tegra, tegra->soc->mbox.owner);
447 if (value != MBOX_OWNER_NONE) {
448 dev_err(tegra->dev, "mailbox is busy\n");
452 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
454 value = fpci_readl(tegra, tegra->soc->mbox.owner);
455 if (value != MBOX_OWNER_SW) {
456 dev_err(tegra->dev, "failed to acquire mailbox\n");
460 wait_for_idle = true;
463 value = tegra_xusb_mbox_pack(msg);
464 fpci_writel(tegra, value, tegra->soc->mbox.data_in);
466 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
467 value |= MBOX_INT_EN | MBOX_DEST_FALC;
468 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
471 unsigned long timeout = jiffies + msecs_to_jiffies(250);
473 while (time_before(jiffies, timeout)) {
474 value = fpci_readl(tegra, tegra->soc->mbox.owner);
475 if (value == MBOX_OWNER_NONE)
478 usleep_range(10, 20);
481 if (time_after(jiffies, timeout))
482 value = fpci_readl(tegra, tegra->soc->mbox.owner);
484 if (value != MBOX_OWNER_NONE)
491 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
493 struct tegra_xusb *tegra = data;
496 /* clear mailbox interrupts */
497 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
498 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
500 if (value & MBOX_SMI_INTR_FW_HANG)
501 dev_err(tegra->dev, "controller firmware hang\n");
503 return IRQ_WAKE_THREAD;
506 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
507 const struct tegra_xusb_mbox_msg *msg)
509 struct tegra_xusb_padctl *padctl = tegra->padctl;
510 const struct tegra_xusb_soc *soc = tegra->soc;
511 struct device *dev = tegra->dev;
512 struct tegra_xusb_mbox_msg rsp;
518 memset(&rsp, 0, sizeof(rsp));
521 case MBOX_CMD_INC_FALC_CLOCK:
522 case MBOX_CMD_DEC_FALC_CLOCK:
523 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
524 if (rsp.data != msg->data)
525 rsp.cmd = MBOX_CMD_NAK;
527 rsp.cmd = MBOX_CMD_ACK;
531 case MBOX_CMD_INC_SSPI_CLOCK:
532 case MBOX_CMD_DEC_SSPI_CLOCK:
533 if (tegra->soc->scale_ss_clock) {
534 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
536 rsp.cmd = MBOX_CMD_NAK;
538 rsp.cmd = MBOX_CMD_ACK;
540 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
542 rsp.cmd = MBOX_CMD_ACK;
543 rsp.data = msg->data;
548 case MBOX_CMD_SET_BW:
550 * TODO: Request bandwidth once EMC scaling is supported.
551 * Ignore for now since ACK/NAK is not required for SET_BW
556 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
557 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
559 dev_err(dev, "failed to save context for USB3#%u: %d\n",
561 rsp.cmd = MBOX_CMD_NAK;
563 rsp.cmd = MBOX_CMD_ACK;
566 rsp.data = msg->data;
569 case MBOX_CMD_START_HSIC_IDLE:
570 case MBOX_CMD_STOP_HSIC_IDLE:
571 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
576 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
577 soc->ports.hsic.count);
579 for_each_set_bit(port, &mask, 32) {
580 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
587 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
588 idle ? "idle" : "busy", err);
589 rsp.cmd = MBOX_CMD_NAK;
591 rsp.cmd = MBOX_CMD_ACK;
594 rsp.data = msg->data;
597 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
598 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
599 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
604 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
605 soc->ports.usb3.count);
607 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
608 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
617 "failed to %s LFPS detection on USB3#%u: %d\n",
618 enable ? "enable" : "disable", port, err);
619 rsp.cmd = MBOX_CMD_NAK;
621 rsp.cmd = MBOX_CMD_ACK;
624 rsp.data = msg->data;
628 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
633 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
635 err = tegra_xusb_mbox_send(tegra, &rsp);
637 dev_err(dev, "failed to send %s: %d\n", cmd, err);
641 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
643 struct tegra_xusb *tegra = data;
644 struct tegra_xusb_mbox_msg msg;
647 mutex_lock(&tegra->lock);
649 value = fpci_readl(tegra, tegra->soc->mbox.data_out);
650 tegra_xusb_mbox_unpack(&msg, value);
652 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
653 value &= ~MBOX_DEST_SMI;
654 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
656 /* clear mailbox owner if no ACK/NAK is required */
657 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
658 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
660 tegra_xusb_mbox_handle(tegra, &msg);
662 mutex_unlock(&tegra->lock);
666 static void tegra_xusb_config(struct tegra_xusb *tegra)
668 u32 regs = tegra->hcd->rsrc_start;
671 if (tegra->soc->has_ipfs) {
672 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
673 value |= IPFS_EN_FPCI;
674 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
676 usleep_range(10, 20);
679 /* Program BAR0 space */
680 value = fpci_readl(tegra, XUSB_CFG_4);
681 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
682 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
683 fpci_writel(tegra, value, XUSB_CFG_4);
685 usleep_range(100, 200);
687 /* Enable bus master */
688 value = fpci_readl(tegra, XUSB_CFG_1);
689 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
690 fpci_writel(tegra, value, XUSB_CFG_1);
692 if (tegra->soc->has_ipfs) {
693 /* Enable interrupt assertion */
694 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
695 value |= IPFS_IP_INT_MASK;
696 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
699 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
703 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
707 err = clk_prepare_enable(tegra->pll_e);
711 err = clk_prepare_enable(tegra->host_clk);
715 err = clk_prepare_enable(tegra->ss_clk);
719 err = clk_prepare_enable(tegra->falcon_clk);
723 err = clk_prepare_enable(tegra->fs_src_clk);
727 err = clk_prepare_enable(tegra->hs_src_clk);
731 if (tegra->soc->scale_ss_clock) {
732 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
740 clk_disable_unprepare(tegra->hs_src_clk);
742 clk_disable_unprepare(tegra->fs_src_clk);
744 clk_disable_unprepare(tegra->falcon_clk);
746 clk_disable_unprepare(tegra->ss_clk);
748 clk_disable_unprepare(tegra->host_clk);
750 clk_disable_unprepare(tegra->pll_e);
754 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
756 clk_disable_unprepare(tegra->pll_e);
757 clk_disable_unprepare(tegra->host_clk);
758 clk_disable_unprepare(tegra->ss_clk);
759 clk_disable_unprepare(tegra->falcon_clk);
760 clk_disable_unprepare(tegra->fs_src_clk);
761 clk_disable_unprepare(tegra->hs_src_clk);
764 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
769 for (i = 0; i < tegra->num_phys; i++) {
770 err = phy_init(tegra->phys[i]);
774 err = phy_power_on(tegra->phys[i]);
776 phy_exit(tegra->phys[i]);
785 phy_power_off(tegra->phys[i]);
786 phy_exit(tegra->phys[i]);
792 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
796 for (i = 0; i < tegra->num_phys; i++) {
797 phy_power_off(tegra->phys[i]);
798 phy_exit(tegra->phys[i]);
802 static int tegra_xusb_runtime_suspend(struct device *dev)
804 struct tegra_xusb *tegra = dev_get_drvdata(dev);
806 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
807 tegra_xusb_clk_disable(tegra);
812 static int tegra_xusb_runtime_resume(struct device *dev)
814 struct tegra_xusb *tegra = dev_get_drvdata(dev);
817 err = tegra_xusb_clk_enable(tegra);
819 dev_err(dev, "failed to enable clocks: %d\n", err);
823 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
825 dev_err(dev, "failed to enable regulators: %d\n", err);
832 tegra_xusb_clk_disable(tegra);
836 #ifdef CONFIG_PM_SLEEP
837 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
839 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
841 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
842 sizeof(u32), GFP_KERNEL);
843 if (!tegra->context.ipfs)
846 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
847 sizeof(u32), GFP_KERNEL);
848 if (!tegra->context.fpci)
854 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
860 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
862 struct tegra_xusb_fw_header *header;
863 const struct firmware *fw;
866 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
868 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
872 /* Load Falcon controller with its firmware. */
873 header = (struct tegra_xusb_fw_header *)fw->data;
874 tegra->fw.size = le32_to_cpu(header->fwimg_len);
876 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
877 &tegra->fw.phys, GFP_KERNEL);
878 if (!tegra->fw.virt) {
879 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
880 release_firmware(fw);
884 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
885 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
886 release_firmware(fw);
891 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
893 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
894 struct xhci_cap_regs __iomem *cap = tegra->regs;
895 struct tegra_xusb_fw_header *header;
896 struct device *dev = tegra->dev;
897 struct xhci_op_regs __iomem *op;
898 unsigned long timeout;
905 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
906 op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
908 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
909 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
910 csb_readl(tegra, XUSB_FALC_CPUCTL));
914 /* Program the size of DFI into ILOAD_ATTR. */
915 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
918 * Boot code of the firmware reads the ILOAD_BASE registers
919 * to get to the start of the DFI in system memory.
921 address = tegra->fw.phys + sizeof(*header);
922 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
923 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
925 /* Set BOOTPATH to 1 in APMAP. */
926 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
928 /* Invalidate L2IMEM. */
929 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
932 * Initiate fetch of bootcode from system memory into L2IMEM.
933 * Program bootcode location and size in system memory.
935 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
937 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
939 code_blocks = code_tag_blocks + code_size_blocks;
941 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
942 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
943 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
944 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
945 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
947 /* Trigger L2IMEM load operation. */
948 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
949 XUSB_CSB_MP_L2IMEMOP_TRIG);
951 /* Setup Falcon auto-fill. */
952 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
954 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
955 IMFILLRNG1_TAG_LO_SHIFT) |
956 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
957 IMFILLRNG1_TAG_HI_SHIFT);
958 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
960 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
962 /* wait for RESULT_VLD to get set */
963 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
964 err = readx_poll_timeout(tegra_csb_readl,
965 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
966 value & L2IMEMOP_RESULT_VLD, 100, 10000);
968 dev_err(dev, "DMA controller not ready %#010x\n", value);
971 #undef tegra_csb_readl
973 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
976 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
977 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
979 timeout = jiffies + msecs_to_jiffies(200);
982 value = readl(&op->status);
983 if ((value & STS_CNR) == 0)
986 usleep_range(1000, 2000);
987 } while (time_is_after_jiffies(timeout));
989 value = readl(&op->status);
990 if (value & STS_CNR) {
991 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
992 dev_err(dev, "XHCI controller not read: %#010x\n", value);
996 timestamp = le32_to_cpu(header->fwimg_created_time);
997 time64_to_tm(timestamp, 0, &time);
999 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
1000 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
1001 time.tm_hour, time.tm_min, time.tm_sec);
1006 static void tegra_xusb_powerdomain_remove(struct device *dev,
1007 struct tegra_xusb *tegra)
1009 if (tegra->genpd_dl_ss)
1010 device_link_del(tegra->genpd_dl_ss);
1011 if (tegra->genpd_dl_host)
1012 device_link_del(tegra->genpd_dl_host);
1013 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1014 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1015 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1016 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1019 static int tegra_xusb_powerdomain_init(struct device *dev,
1020 struct tegra_xusb *tegra)
1024 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1025 if (IS_ERR(tegra->genpd_dev_host)) {
1026 err = PTR_ERR(tegra->genpd_dev_host);
1027 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1031 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1032 if (IS_ERR(tegra->genpd_dev_ss)) {
1033 err = PTR_ERR(tegra->genpd_dev_ss);
1034 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1038 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
1039 DL_FLAG_PM_RUNTIME |
1041 if (!tegra->genpd_dl_host) {
1042 dev_err(dev, "adding host device link failed!\n");
1046 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
1047 DL_FLAG_PM_RUNTIME |
1049 if (!tegra->genpd_dl_ss) {
1050 dev_err(dev, "adding superspeed device link failed!\n");
1057 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1059 struct tegra_xusb_mbox_msg msg;
1062 /* Enable firmware messages from controller. */
1063 msg.cmd = MBOX_CMD_MSG_ENABLED;
1066 err = tegra_xusb_mbox_send(tegra, &msg);
1068 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1073 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1077 mutex_lock(&tegra->lock);
1078 err = __tegra_xusb_enable_firmware_messages(tegra);
1079 mutex_unlock(&tegra->lock);
1084 static int tegra_xusb_probe(struct platform_device *pdev)
1086 struct tegra_xusb *tegra;
1087 struct resource *regs;
1088 struct xhci_hcd *xhci;
1089 unsigned int i, j, k;
1093 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1095 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1099 tegra->soc = of_device_get_match_data(&pdev->dev);
1100 mutex_init(&tegra->lock);
1101 tegra->dev = &pdev->dev;
1103 err = tegra_xusb_init_context(tegra);
1107 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
1109 if (IS_ERR(tegra->regs))
1110 return PTR_ERR(tegra->regs);
1112 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1113 if (IS_ERR(tegra->fpci_base))
1114 return PTR_ERR(tegra->fpci_base);
1116 if (tegra->soc->has_ipfs) {
1117 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1118 if (IS_ERR(tegra->ipfs_base))
1119 return PTR_ERR(tegra->ipfs_base);
1122 tegra->xhci_irq = platform_get_irq(pdev, 0);
1123 if (tegra->xhci_irq < 0)
1124 return tegra->xhci_irq;
1126 tegra->mbox_irq = platform_get_irq(pdev, 1);
1127 if (tegra->mbox_irq < 0)
1128 return tegra->mbox_irq;
1130 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1131 if (IS_ERR(tegra->padctl))
1132 return PTR_ERR(tegra->padctl);
1134 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1135 if (IS_ERR(tegra->host_clk)) {
1136 err = PTR_ERR(tegra->host_clk);
1137 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1141 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1142 if (IS_ERR(tegra->falcon_clk)) {
1143 err = PTR_ERR(tegra->falcon_clk);
1144 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1148 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1149 if (IS_ERR(tegra->ss_clk)) {
1150 err = PTR_ERR(tegra->ss_clk);
1151 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1155 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1156 if (IS_ERR(tegra->ss_src_clk)) {
1157 err = PTR_ERR(tegra->ss_src_clk);
1158 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1162 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1163 if (IS_ERR(tegra->hs_src_clk)) {
1164 err = PTR_ERR(tegra->hs_src_clk);
1165 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1169 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1170 if (IS_ERR(tegra->fs_src_clk)) {
1171 err = PTR_ERR(tegra->fs_src_clk);
1172 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1176 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1177 if (IS_ERR(tegra->pll_u_480m)) {
1178 err = PTR_ERR(tegra->pll_u_480m);
1179 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1183 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1184 if (IS_ERR(tegra->clk_m)) {
1185 err = PTR_ERR(tegra->clk_m);
1186 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1190 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1191 if (IS_ERR(tegra->pll_e)) {
1192 err = PTR_ERR(tegra->pll_e);
1193 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1197 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1198 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1200 if (IS_ERR(tegra->host_rst)) {
1201 err = PTR_ERR(tegra->host_rst);
1203 "failed to get xusb_host reset: %d\n", err);
1207 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1208 if (IS_ERR(tegra->ss_rst)) {
1209 err = PTR_ERR(tegra->ss_rst);
1210 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1215 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1220 "failed to enable XUSBA domain: %d\n", err);
1224 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1228 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1230 "failed to enable XUSBC domain: %d\n", err);
1234 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1236 goto put_powerdomains;
1239 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1240 sizeof(*tegra->supplies), GFP_KERNEL);
1241 if (!tegra->supplies) {
1243 goto put_powerdomains;
1246 regulator_bulk_set_supply_names(tegra->supplies,
1247 tegra->soc->supply_names,
1248 tegra->soc->num_supplies);
1250 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1253 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1254 goto put_powerdomains;
1257 for (i = 0; i < tegra->soc->num_types; i++)
1258 tegra->num_phys += tegra->soc->phy_types[i].num;
1260 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1261 sizeof(*tegra->phys), GFP_KERNEL);
1264 goto put_powerdomains;
1267 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1270 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1271 snprintf(prop, sizeof(prop), "%s-%d",
1272 tegra->soc->phy_types[i].name, j);
1274 phy = devm_phy_optional_get(&pdev->dev, prop);
1277 "failed to get PHY %s: %ld\n", prop,
1280 goto put_powerdomains;
1283 tegra->phys[k++] = phy;
1287 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1288 dev_name(&pdev->dev));
1291 goto put_powerdomains;
1294 tegra->hcd->regs = tegra->regs;
1295 tegra->hcd->rsrc_start = regs->start;
1296 tegra->hcd->rsrc_len = resource_size(regs);
1299 * This must happen after usb_create_hcd(), because usb_create_hcd()
1300 * will overwrite the drvdata of the device with the hcd it creates.
1302 platform_set_drvdata(pdev, tegra);
1304 err = tegra_xusb_phy_enable(tegra);
1306 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1311 * The XUSB Falcon microcontroller can only address 40 bits, so set
1312 * the DMA mask accordingly.
1314 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1316 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1320 err = tegra_xusb_request_firmware(tegra);
1322 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1326 pm_runtime_enable(&pdev->dev);
1328 if (!pm_runtime_enabled(&pdev->dev))
1329 err = tegra_xusb_runtime_resume(&pdev->dev);
1331 err = pm_runtime_get_sync(&pdev->dev);
1334 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1338 tegra_xusb_config(tegra);
1340 err = tegra_xusb_load_firmware(tegra);
1342 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1346 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1348 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1352 device_wakeup_enable(tegra->hcd->self.controller);
1354 xhci = hcd_to_xhci(tegra->hcd);
1356 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1358 dev_name(&pdev->dev),
1360 if (!xhci->shared_hcd) {
1361 dev_err(&pdev->dev, "failed to create shared HCD\n");
1366 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1368 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1372 err = tegra_xusb_enable_firmware_messages(tegra);
1374 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1378 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1379 tegra_xusb_mbox_irq,
1380 tegra_xusb_mbox_thread, 0,
1381 dev_name(&pdev->dev), tegra);
1383 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1390 usb_remove_hcd(xhci->shared_hcd);
1392 usb_put_hcd(xhci->shared_hcd);
1394 usb_remove_hcd(tegra->hcd);
1396 if (!pm_runtime_status_suspended(&pdev->dev))
1397 tegra_xusb_runtime_suspend(&pdev->dev);
1399 usb_put_hcd(tegra->hcd);
1401 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1404 tegra_xusb_phy_disable(tegra);
1405 pm_runtime_disable(&pdev->dev);
1407 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1408 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1409 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1411 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1414 tegra_xusb_padctl_put(tegra->padctl);
1418 static int tegra_xusb_remove(struct platform_device *pdev)
1420 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1421 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1423 usb_remove_hcd(xhci->shared_hcd);
1424 usb_put_hcd(xhci->shared_hcd);
1425 xhci->shared_hcd = NULL;
1426 usb_remove_hcd(tegra->hcd);
1427 usb_put_hcd(tegra->hcd);
1429 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1432 pm_runtime_put_sync(&pdev->dev);
1433 pm_runtime_disable(&pdev->dev);
1435 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1436 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1437 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1439 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1442 tegra_xusb_phy_disable(tegra);
1444 tegra_xusb_padctl_put(tegra->padctl);
1449 #ifdef CONFIG_PM_SLEEP
1450 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1452 struct device *dev = hub->hcd->self.controller;
1457 for (i = 0; i < hub->num_ports; i++) {
1458 value = readl(hub->ports[i]->addr);
1459 if ((value & PORT_PE) == 0)
1462 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1463 dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1464 hub->hcd->self.busnum, i + 1, value);
1472 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1474 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1475 unsigned long flags;
1478 spin_lock_irqsave(&xhci->lock, flags);
1480 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1481 !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1484 spin_unlock_irqrestore(&xhci->lock, flags);
1489 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1491 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1492 struct tegra_xusb_context *ctx = &tegra->context;
1495 if (soc->ipfs.num_offsets > 0) {
1496 for (i = 0; i < soc->ipfs.num_offsets; i++)
1497 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1500 if (soc->fpci.num_offsets > 0) {
1501 for (i = 0; i < soc->fpci.num_offsets; i++)
1502 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1506 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1508 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1509 struct tegra_xusb_context *ctx = &tegra->context;
1512 if (soc->fpci.num_offsets > 0) {
1513 for (i = 0; i < soc->fpci.num_offsets; i++)
1514 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1517 if (soc->ipfs.num_offsets > 0) {
1518 for (i = 0; i < soc->ipfs.num_offsets; i++)
1519 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1523 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup)
1525 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1528 err = tegra_xusb_check_ports(tegra);
1530 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1534 err = xhci_suspend(xhci, wakeup);
1536 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
1540 tegra_xusb_save_context(tegra);
1541 tegra_xusb_phy_disable(tegra);
1542 tegra_xusb_clk_disable(tegra);
1547 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
1549 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1552 err = tegra_xusb_clk_enable(tegra);
1554 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1558 err = tegra_xusb_phy_enable(tegra);
1560 dev_err(tegra->dev, "failed to enable PHYs: %d\n", err);
1564 tegra_xusb_config(tegra);
1565 tegra_xusb_restore_context(tegra);
1567 err = tegra_xusb_load_firmware(tegra);
1569 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
1573 err = __tegra_xusb_enable_firmware_messages(tegra);
1575 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1579 err = xhci_resume(xhci, true);
1581 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
1588 tegra_xusb_phy_disable(tegra);
1590 tegra_xusb_clk_disable(tegra);
1594 static int tegra_xusb_suspend(struct device *dev)
1596 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1597 bool wakeup = device_may_wakeup(dev);
1600 synchronize_irq(tegra->mbox_irq);
1602 mutex_lock(&tegra->lock);
1603 err = tegra_xusb_enter_elpg(tegra, wakeup);
1604 mutex_unlock(&tegra->lock);
1609 static int tegra_xusb_resume(struct device *dev)
1611 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1612 bool wakeup = device_may_wakeup(dev);
1615 mutex_lock(&tegra->lock);
1616 err = tegra_xusb_exit_elpg(tegra, wakeup);
1617 mutex_unlock(&tegra->lock);
1623 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1624 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1625 tegra_xusb_runtime_resume, NULL)
1626 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1629 static const char * const tegra124_supply_names[] = {
1637 "hvdd-usb-ss-pll-e",
1640 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1641 { .name = "usb3", .num = 2, },
1642 { .name = "usb2", .num = 3, },
1643 { .name = "hsic", .num = 2, },
1646 static const unsigned int tegra124_xusb_context_ipfs[] = {
1647 IPFS_XUSB_HOST_MSI_BAR_SZ_0,
1648 IPFS_XUSB_HOST_MSI_BAR_SZ_0,
1649 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
1650 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
1651 IPFS_XUSB_HOST_MSI_VEC0_0,
1652 IPFS_XUSB_HOST_MSI_EN_VEC0_0,
1653 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
1654 IPFS_XUSB_HOST_INTR_MASK_0,
1655 IPFS_XUSB_HOST_INTR_ENABLE_0,
1656 IPFS_XUSB_HOST_UFPCI_CONFIG_0,
1657 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
1658 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
1661 static const unsigned int tegra124_xusb_context_fpci[] = {
1662 XUSB_CFG_ARU_CONTEXT_HS_PLS,
1663 XUSB_CFG_ARU_CONTEXT_FS_PLS,
1664 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
1665 XUSB_CFG_ARU_CONTEXT_HSFS_PP,
1666 XUSB_CFG_ARU_CONTEXT,
1672 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
1674 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
1675 .offsets = tegra124_xusb_context_ipfs,
1678 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
1679 .offsets = tegra124_xusb_context_fpci,
1683 static const struct tegra_xusb_soc tegra124_soc = {
1684 .firmware = "nvidia/tegra124/xusb.bin",
1685 .supply_names = tegra124_supply_names,
1686 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1687 .phy_types = tegra124_phy_types,
1688 .num_types = ARRAY_SIZE(tegra124_phy_types),
1689 .context = &tegra124_xusb_context,
1691 .usb2 = { .offset = 4, .count = 4, },
1692 .hsic = { .offset = 6, .count = 2, },
1693 .usb3 = { .offset = 0, .count = 2, },
1695 .scale_ss_clock = true,
1704 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1706 static const char * const tegra210_supply_names[] = {
1716 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1717 { .name = "usb3", .num = 4, },
1718 { .name = "usb2", .num = 4, },
1719 { .name = "hsic", .num = 1, },
1722 static const struct tegra_xusb_soc tegra210_soc = {
1723 .firmware = "nvidia/tegra210/xusb.bin",
1724 .supply_names = tegra210_supply_names,
1725 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1726 .phy_types = tegra210_phy_types,
1727 .num_types = ARRAY_SIZE(tegra210_phy_types),
1728 .context = &tegra124_xusb_context,
1730 .usb2 = { .offset = 4, .count = 4, },
1731 .hsic = { .offset = 8, .count = 1, },
1732 .usb3 = { .offset = 0, .count = 4, },
1734 .scale_ss_clock = false,
1743 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1745 static const char * const tegra186_supply_names[] = {
1747 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
1749 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
1750 { .name = "usb3", .num = 3, },
1751 { .name = "usb2", .num = 3, },
1752 { .name = "hsic", .num = 1, },
1755 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
1757 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
1758 .offsets = tegra124_xusb_context_fpci,
1762 static const struct tegra_xusb_soc tegra186_soc = {
1763 .firmware = "nvidia/tegra186/xusb.bin",
1764 .supply_names = tegra186_supply_names,
1765 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
1766 .phy_types = tegra186_phy_types,
1767 .num_types = ARRAY_SIZE(tegra186_phy_types),
1768 .context = &tegra186_xusb_context,
1770 .usb3 = { .offset = 0, .count = 3, },
1771 .usb2 = { .offset = 3, .count = 3, },
1772 .hsic = { .offset = 6, .count = 1, },
1774 .scale_ss_clock = false,
1784 static const char * const tegra194_supply_names[] = {
1787 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
1788 { .name = "usb3", .num = 4, },
1789 { .name = "usb2", .num = 4, },
1792 static const struct tegra_xusb_soc tegra194_soc = {
1793 .firmware = "nvidia/tegra194/xusb.bin",
1794 .supply_names = tegra194_supply_names,
1795 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
1796 .phy_types = tegra194_phy_types,
1797 .num_types = ARRAY_SIZE(tegra194_phy_types),
1798 .context = &tegra186_xusb_context,
1800 .usb3 = { .offset = 0, .count = 4, },
1801 .usb2 = { .offset = 4, .count = 4, },
1803 .scale_ss_clock = false,
1812 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
1814 static const struct of_device_id tegra_xusb_of_match[] = {
1815 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1816 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1817 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
1818 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
1821 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1823 static struct platform_driver tegra_xusb_driver = {
1824 .probe = tegra_xusb_probe,
1825 .remove = tegra_xusb_remove,
1827 .name = "tegra-xusb",
1828 .pm = &tegra_xusb_pm_ops,
1829 .of_match_table = tegra_xusb_of_match,
1833 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1835 xhci->quirks |= XHCI_PLAT;
1838 static int tegra_xhci_setup(struct usb_hcd *hcd)
1840 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1843 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1844 .reset = tegra_xhci_setup,
1847 static int __init tegra_xusb_init(void)
1849 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1851 return platform_driver_register(&tegra_xusb_driver);
1853 module_init(tegra_xusb_init);
1855 static void __exit tegra_xusb_exit(void)
1857 platform_driver_unregister(&tegra_xusb_driver);
1859 module_exit(tegra_xusb_exit);
1861 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1862 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1863 MODULE_LICENSE("GPL v2");