drivers/usb/host/xhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVIDIA Tegra xHCI host controller driver
   4  *
   5  * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
   6  * Copyright (C) 2014 Google, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/phy/tegra/xusb.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/usb/ch9.h>
  23 #include <linux/pm.h>
  24 #include <linux/pm_domain.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/reset.h>
  28 #include <linux/slab.h>
  29 #include <linux/usb/otg.h>
  30 #include <linux/usb/phy.h>
  31 #include <linux/usb/role.h>
  32 #include <soc/tegra/pmc.h>
  33
  34 #include "xhci.h"
  35
  36 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  37 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  38
  39 /* FPCI CFG registers */
  40 #define XUSB_CFG_1                              0x004
  41 #define  XUSB_IO_SPACE_EN                       BIT(0)
  42 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  43 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  44 #define XUSB_CFG_4                              0x010
  45 #define  XUSB_BASE_ADDR_SHIFT                   15
  46 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  47 #define XUSB_CFG_16                             0x040
  48 #define XUSB_CFG_24                             0x060
  49 #define XUSB_CFG_AXI_CFG                        0x0f8
  50 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  51 #define XUSB_CFG_ARU_CONTEXT                    0x43c
  52 #define XUSB_CFG_ARU_CONTEXT_HS_PLS             0x478
  53 #define XUSB_CFG_ARU_CONTEXT_FS_PLS             0x47c
  54 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED         0x480
  55 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP            0x484
  56 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  57
  58 /* FPCI mailbox registers */
  59 /* XUSB_CFG_ARU_MBOX_CMD */
  60 #define  MBOX_DEST_FALC                         BIT(27)
  61 #define  MBOX_DEST_PME                          BIT(28)
  62 #define  MBOX_DEST_SMI                          BIT(29)
  63 #define  MBOX_DEST_XHCI                         BIT(30)
  64 #define  MBOX_INT_EN                            BIT(31)
  65 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
  66 #define  CMD_DATA_SHIFT                         0
  67 #define  CMD_DATA_MASK                          0xffffff
  68 #define  CMD_TYPE_SHIFT                         24
  69 #define  CMD_TYPE_MASK                          0xff
  70 /* XUSB_CFG_ARU_MBOX_OWNER */
  71 #define  MBOX_OWNER_NONE                        0
  72 #define  MBOX_OWNER_FW                          1
  73 #define  MBOX_OWNER_SW                          2
  74 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  75 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  76 #define  MBOX_SMI_INTR_EN                       BIT(3)
  77
  78 /* IPFS registers */
  79 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0             0x0c0
  80 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0         0x0c4
  81 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0        0x0c8
  82 #define IPFS_XUSB_HOST_MSI_VEC0_0               0x100
  83 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0            0x140
  84 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
  85 #define  IPFS_EN_FPCI                           BIT(0)
  86 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0       0x184
  87 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
  88 #define  IPFS_IP_INT_MASK                       BIT(16)
  89 #define IPFS_XUSB_HOST_INTR_ENABLE_0            0x198
  90 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0           0x19c
  91 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
  92 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0         0x1dc
  93
  94 #define CSB_PAGE_SELECT_MASK                    0x7fffff
  95 #define CSB_PAGE_SELECT_SHIFT                   9
  96 #define CSB_PAGE_OFFSET_MASK                    0x1ff
  97 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
  98                                  CSB_PAGE_SELECT_MASK)
  99 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
 100
 101 /* Falcon CSB registers */
 102 #define XUSB_FALC_CPUCTL                        0x100
 103 #define  CPUCTL_STARTCPU                        BIT(1)
 104 #define  CPUCTL_STATE_HALTED                    BIT(4)
 105 #define  CPUCTL_STATE_STOPPED                   BIT(5)
 106 #define XUSB_FALC_BOOTVEC                       0x104
 107 #define XUSB_FALC_DMACTL                        0x10c
 108 #define XUSB_FALC_IMFILLRNG1                    0x154
 109 #define  IMFILLRNG1_TAG_MASK                    0xffff
 110 #define  IMFILLRNG1_TAG_LO_SHIFT                0
 111 #define  IMFILLRNG1_TAG_HI_SHIFT                16
 112 #define XUSB_FALC_IMFILLCTL                     0x158
 113
 114 /* MP CSB registers */
 115 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
 116 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
 117 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
 118 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
 119 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
 120 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
 121 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 122 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 123 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 124 #define  L2IMEMOP_ACTION_SHIFT                  24
 125 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 126 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 127 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101a18
 128 #define  L2IMEMOP_RESULT_VLD                    BIT(31)
 129 #define XUSB_CSB_MP_APMAP                       0x10181c
 130 #define  APMAP_BOOTPATH                         BIT(31)
 131
 132 #define IMEM_BLOCK_SIZE                         256
 133
 134 struct tegra_xusb_fw_header {
 135         __le32 boot_loadaddr_in_imem;
 136         __le32 boot_codedfi_offset;
 137         __le32 boot_codetag;
 138         __le32 boot_codesize;
 139         __le32 phys_memaddr;
 140         __le16 reqphys_memsize;
 141         __le16 alloc_phys_memsize;
 142         __le32 rodata_img_offset;
 143         __le32 rodata_section_start;
 144         __le32 rodata_section_end;
 145         __le32 main_fnaddr;
 146         __le32 fwimg_cksum;
 147         __le32 fwimg_created_time;
 148         __le32 imem_resident_start;
 149         __le32 imem_resident_end;
 150         __le32 idirect_start;
 151         __le32 idirect_end;
 152         __le32 l2_imem_start;
 153         __le32 l2_imem_end;
 154         __le32 version_id;
 155         u8 init_ddirect;
 156         u8 reserved[3];
 157         __le32 phys_addr_log_buffer;
 158         __le32 total_log_entries;
 159         __le32 dequeue_ptr;
 160         __le32 dummy_var[2];
 161         __le32 fwimg_len;
 162         u8 magic[8];
 163         __le32 ss_low_power_entry_timeout;
 164         u8 num_hsic_port;
 165         u8 padding[139]; /* Pad to 256 bytes */
 166 };
 167
 168 struct tegra_xusb_phy_type {
 169         const char *name;
 170         unsigned int num;
 171 };
 172
 173 struct tegra_xusb_mbox_regs {
 174         u16 cmd;
 175         u16 data_in;
 176         u16 data_out;
 177         u16 owner;
 178 };
 179
 180 struct tegra_xusb_context_soc {
 181         struct {
 182                 const unsigned int *offsets;
 183                 unsigned int num_offsets;
 184         } ipfs;
 185
 186         struct {
 187                 const unsigned int *offsets;
 188                 unsigned int num_offsets;
 189         } fpci;
 190 };
 191
 192 struct tegra_xusb_soc {
 193         const char *firmware;
 194         const char * const *supply_names;
 195         unsigned int num_supplies;
 196         const struct tegra_xusb_phy_type *phy_types;
 197         unsigned int num_types;
 198         const struct tegra_xusb_context_soc *context;
 199
 200         struct {
 201                 struct {
 202                         unsigned int offset;
 203                         unsigned int count;
 204                 } usb2, ulpi, hsic, usb3;
 205         } ports;
 206
 207         struct tegra_xusb_mbox_regs mbox;
 208
 209         bool scale_ss_clock;
 210         bool has_ipfs;
 211         bool lpm_support;
 212         bool otg_reset_sspi;
 213 };
 214
 215 struct tegra_xusb_context {
 216         u32 *ipfs;
 217         u32 *fpci;
 218 };
 219
 220 struct tegra_xusb {
 221         struct device *dev;
 222         void __iomem *regs;
 223         struct usb_hcd *hcd;
 224
 225         struct mutex lock;
 226
 227         int xhci_irq;
 228         int mbox_irq;
 229         int padctl_irq;
 230
 231         void __iomem *ipfs_base;
 232         void __iomem *fpci_base;
 233
 234         const struct tegra_xusb_soc *soc;
 235
 236         struct regulator_bulk_data *supplies;
 237
 238         struct tegra_xusb_padctl *padctl;
 239
 240         struct clk *host_clk;
 241         struct clk *falcon_clk;
 242         struct clk *ss_clk;
 243         struct clk *ss_src_clk;
 244         struct clk *hs_src_clk;
 245         struct clk *fs_src_clk;
 246         struct clk *pll_u_480m;
 247         struct clk *clk_m;
 248         struct clk *pll_e;
 249
 250         struct reset_control *host_rst;
 251         struct reset_control *ss_rst;
 252
 253         struct device *genpd_dev_host;
 254         struct device *genpd_dev_ss;
 255         bool use_genpd;
 256
 257         struct phy **phys;
 258         unsigned int num_phys;
 259
 260         struct usb_phy **usbphy;
 261         unsigned int num_usb_phys;
 262         int otg_usb2_port;
 263         int otg_usb3_port;
 264         bool host_mode;
 265         struct notifier_block id_nb;
 266         struct work_struct id_work;
 267
 268         /* Firmware loading related */
 269         struct {
 270                 size_t size;
 271                 void *virt;
 272                 dma_addr_t phys;
 273         } fw;
 274
 275         bool suspended;
 276         struct tegra_xusb_context context;
 277 };
 278
 279 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 280
 281 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 282 {
 283         return readl(tegra->fpci_base + offset);
 284 }
 285
 286 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 287                                unsigned int offset)
 288 {
 289         writel(value, tegra->fpci_base + offset);
 290 }
 291
 292 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 293 {
 294         return readl(tegra->ipfs_base + offset);
 295 }
 296
 297 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 298                                unsigned int offset)
 299 {
 300         writel(value, tegra->ipfs_base + offset);
 301 }
 302
 303 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 304 {
 305         u32 page = CSB_PAGE_SELECT(offset);
 306         u32 ofs = CSB_PAGE_OFFSET(offset);
 307
 308         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 309
 310         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 311 }
 312
 313 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 314                        unsigned int offset)
 315 {
 316         u32 page = CSB_PAGE_SELECT(offset);
 317         u32 ofs = CSB_PAGE_OFFSET(offset);
 318
 319         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 320         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 321 }
 322
 323 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 324                                  unsigned long rate)
 325 {
 326         unsigned long new_parent_rate, old_parent_rate;
 327         struct clk *clk = tegra->ss_src_clk;
 328         unsigned int div;
 329         int err;
 330
 331         if (clk_get_rate(clk) == rate)
 332                 return 0;
 333
 334         switch (rate) {
 335         case TEGRA_XHCI_SS_HIGH_SPEED:
 336                 /*
 337                  * Reparent to PLLU_480M. Set divider first to avoid
 338                  * overclocking.
 339                  */
 340                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 341                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 342                 div = new_parent_rate / rate;
 343
 344                 err = clk_set_rate(clk, old_parent_rate / div);
 345                 if (err)
 346                         return err;
 347
 348                 err = clk_set_parent(clk, tegra->pll_u_480m);
 349                 if (err)
 350                         return err;
 351
 352                 /*
 353                  * The rate should already be correct, but set it again just
 354                  * to be sure.
 355                  */
 356                 err = clk_set_rate(clk, rate);
 357                 if (err)
 358                         return err;
 359
 360                 break;
 361
 362         case TEGRA_XHCI_SS_LOW_SPEED:
 363                 /* Reparent to CLK_M */
 364                 err = clk_set_parent(clk, tegra->clk_m);
 365                 if (err)
 366                         return err;
 367
 368                 err = clk_set_rate(clk, rate);
 369                 if (err)
 370                         return err;
 371
 372                 break;
 373
 374         default:
 375                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 376                 return -EINVAL;
 377         }
 378
 379         if (clk_get_rate(clk) != rate) {
 380                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 381                 return -EINVAL;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static unsigned long extract_field(u32 value, unsigned int start,
 388                                    unsigned int count)
 389 {
 390         return (value >> start) & ((1 << count) - 1);
 391 }
 392
 393 /* Command requests from the firmware */
 394 enum tegra_xusb_mbox_cmd {
 395         MBOX_CMD_MSG_ENABLED = 1,
 396         MBOX_CMD_INC_FALC_CLOCK,
 397         MBOX_CMD_DEC_FALC_CLOCK,
 398         MBOX_CMD_INC_SSPI_CLOCK,
 399         MBOX_CMD_DEC_SSPI_CLOCK,
 400         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 401         MBOX_CMD_SET_SS_PWR_GATING,
 402         MBOX_CMD_SET_SS_PWR_UNGATING,
 403         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 404         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 405         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 406         MBOX_CMD_START_HSIC_IDLE,
 407         MBOX_CMD_STOP_HSIC_IDLE,
 408         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 409         MBOX_CMD_HSIC_PRETEND_CONNECT,
 410         MBOX_CMD_RESET_SSPI,
 411         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 412         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 413
 414         MBOX_CMD_MAX,
 415
 416         /* Response message to above commands */
 417         MBOX_CMD_ACK = 128,
 418         MBOX_CMD_NAK
 419 };
 420
 421 struct tegra_xusb_mbox_msg {
 422         u32 cmd;
 423         u32 data;
 424 };
 425
 426 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 427 {
 428         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 429                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 430 }
 431 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 432                                           u32 value)
 433 {
 434         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 435         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 436 }
 437
 438 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 439 {
 440         switch (cmd) {
 441         case MBOX_CMD_SET_BW:
 442         case MBOX_CMD_ACK:
 443         case MBOX_CMD_NAK:
 444                 return false;
 445
 446         default:
 447                 return true;
 448         }
 449 }
 450
 451 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 452                                 const struct tegra_xusb_mbox_msg *msg)
 453 {
 454         bool wait_for_idle = false;
 455         u32 value;
 456
 457         /*
 458          * Acquire the mailbox. The firmware still owns the mailbox for
 459          * ACK/NAK messages.
 460          */
 461         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 462                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 463                 if (value != MBOX_OWNER_NONE) {
 464                         dev_err(tegra->dev, "mailbox is busy\n");
 465                         return -EBUSY;
 466                 }
 467
 468                 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
 469
 470                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 471                 if (value != MBOX_OWNER_SW) {
 472                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 473                         return -EBUSY;
 474                 }
 475
 476                 wait_for_idle = true;
 477         }
 478
 479         value = tegra_xusb_mbox_pack(msg);
 480         fpci_writel(tegra, value, tegra->soc->mbox.data_in);
 481
 482         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 483         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 484         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 485
 486         if (wait_for_idle) {
 487                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 488
 489                 while (time_before(jiffies, timeout)) {
 490                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 491                         if (value == MBOX_OWNER_NONE)
 492                                 break;
 493
 494                         usleep_range(10, 20);
 495                 }
 496
 497                 if (time_after(jiffies, timeout))
 498                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 499
 500                 if (value != MBOX_OWNER_NONE)
 501                         return -ETIMEDOUT;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 508 {
 509         struct tegra_xusb *tegra = data;
 510         u32 value;
 511
 512         /* clear mailbox interrupts */
 513         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
 514         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
 515
 516         if (value & MBOX_SMI_INTR_FW_HANG)
 517                 dev_err(tegra->dev, "controller firmware hang\n");
 518
 519         return IRQ_WAKE_THREAD;
 520 }
 521
 522 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 523                                    const struct tegra_xusb_mbox_msg *msg)
 524 {
 525         struct tegra_xusb_padctl *padctl = tegra->padctl;
 526         const struct tegra_xusb_soc *soc = tegra->soc;
 527         struct device *dev = tegra->dev;
 528         struct tegra_xusb_mbox_msg rsp;
 529         unsigned long mask;
 530         unsigned int port;
 531         bool idle, enable;
 532         int err = 0;
 533
 534         memset(&rsp, 0, sizeof(rsp));
 535
 536         switch (msg->cmd) {
 537         case MBOX_CMD_INC_FALC_CLOCK:
 538         case MBOX_CMD_DEC_FALC_CLOCK:
 539                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 540                 if (rsp.data != msg->data)
 541                         rsp.cmd = MBOX_CMD_NAK;
 542                 else
 543                         rsp.cmd = MBOX_CMD_ACK;
 544
 545                 break;
 546
 547         case MBOX_CMD_INC_SSPI_CLOCK:
 548         case MBOX_CMD_DEC_SSPI_CLOCK:
 549                 if (tegra->soc->scale_ss_clock) {
 550                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 551                         if (err < 0)
 552                                 rsp.cmd = MBOX_CMD_NAK;
 553                         else
 554                                 rsp.cmd = MBOX_CMD_ACK;
 555
 556                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 557                 } else {
 558                         rsp.cmd = MBOX_CMD_ACK;
 559                         rsp.data = msg->data;
 560                 }
 561
 562                 break;
 563
 564         case MBOX_CMD_SET_BW:
 565                 /*
 566                  * TODO: Request bandwidth once EMC scaling is supported.
 567                  * Ignore for now since ACK/NAK is not required for SET_BW
 568                  * messages.
 569                  */
 570                 break;
 571
 572         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 573                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 574                 if (err < 0) {
 575                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 576                                 msg->data, err);
 577                         rsp.cmd = MBOX_CMD_NAK;
 578                 } else {
 579                         rsp.cmd = MBOX_CMD_ACK;
 580                 }
 581
 582                 rsp.data = msg->data;
 583                 break;
 584
 585         case MBOX_CMD_START_HSIC_IDLE:
 586         case MBOX_CMD_STOP_HSIC_IDLE:
 587                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 588                         idle = false;
 589                 else
 590                         idle = true;
 591
 592                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 593                                      soc->ports.hsic.count);
 594
 595                 for_each_set_bit(port, &mask, 32) {
 596                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 597                                                               idle);
 598                         if (err < 0)
 599                                 break;
 600                 }
 601
 602                 if (err < 0) {
 603                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 604                                 idle ? "idle" : "busy", err);
 605                         rsp.cmd = MBOX_CMD_NAK;
 606                 } else {
 607                         rsp.cmd = MBOX_CMD_ACK;
 608                 }
 609
 610                 rsp.data = msg->data;
 611                 break;
 612
 613         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 614         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 615                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 616                         enable = false;
 617                 else
 618                         enable = true;
 619
 620                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 621                                      soc->ports.usb3.count);
 622
 623                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 624                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 625                                                                      port,
 626                                                                      enable);
 627                         if (err < 0)
 628                                 break;
 629
 630                         /*
 631                          * wait 500us for LFPS detector to be disabled before
 632                          * sending ACK
 633                          */
 634                         if (!enable)
 635                                 usleep_range(500, 1000);
 636                 }
 637
 638                 if (err < 0) {
 639                         dev_err(dev,
 640                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 641                                 enable ? "enable" : "disable", port, err);
 642                         rsp.cmd = MBOX_CMD_NAK;
 643                 } else {
 644                         rsp.cmd = MBOX_CMD_ACK;
 645                 }
 646
 647                 rsp.data = msg->data;
 648                 break;
 649
 650         default:
 651                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 652                 break;
 653         }
 654
 655         if (rsp.cmd) {
 656                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 657
 658                 err = tegra_xusb_mbox_send(tegra, &rsp);
 659                 if (err < 0)
 660                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 661         }
 662 }
 663
 664 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 665 {
 666         struct tegra_xusb *tegra = data;
 667         struct tegra_xusb_mbox_msg msg;
 668         u32 value;
 669
 670         mutex_lock(&tegra->lock);
 671
 672         if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
 673                 goto out;
 674
 675         value = fpci_readl(tegra, tegra->soc->mbox.data_out);
 676         tegra_xusb_mbox_unpack(&msg, value);
 677
 678         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 679         value &= ~MBOX_DEST_SMI;
 680         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 681
 682         /* clear mailbox owner if no ACK/NAK is required */
 683         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 684                 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
 685
 686         tegra_xusb_mbox_handle(tegra, &msg);
 687
 688 out:
 689         mutex_unlock(&tegra->lock);
 690         return IRQ_HANDLED;
 691 }
 692
 693 static void tegra_xusb_config(struct tegra_xusb *tegra)
 694 {
 695         u32 regs = tegra->hcd->rsrc_start;
 696         u32 value;
 697
 698         if (tegra->soc->has_ipfs) {
 699                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 700                 value |= IPFS_EN_FPCI;
 701                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 702
 703                 usleep_range(10, 20);
 704         }
 705
 706         /* Program BAR0 space */
 707         value = fpci_readl(tegra, XUSB_CFG_4);
 708         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 709         value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 710         fpci_writel(tegra, value, XUSB_CFG_4);
 711
 712         usleep_range(100, 200);
 713
 714         /* Enable bus master */
 715         value = fpci_readl(tegra, XUSB_CFG_1);
 716         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 717         fpci_writel(tegra, value, XUSB_CFG_1);
 718
 719         if (tegra->soc->has_ipfs) {
 720                 /* Enable interrupt assertion */
 721                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 722                 value |= IPFS_IP_INT_MASK;
 723                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 724
 725                 /* Set hysteresis */
 726                 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 727         }
 728 }
 729
 730 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 731 {
 732         int err;
 733
 734         err = clk_prepare_enable(tegra->pll_e);
 735         if (err < 0)
 736                 return err;
 737
 738         err = clk_prepare_enable(tegra->host_clk);
 739         if (err < 0)
 740                 goto disable_plle;
 741
 742         err = clk_prepare_enable(tegra->ss_clk);
 743         if (err < 0)
 744                 goto disable_host;
 745
 746         err = clk_prepare_enable(tegra->falcon_clk);
 747         if (err < 0)
 748                 goto disable_ss;
 749
 750         err = clk_prepare_enable(tegra->fs_src_clk);
 751         if (err < 0)
 752                 goto disable_falc;
 753
 754         err = clk_prepare_enable(tegra->hs_src_clk);
 755         if (err < 0)
 756                 goto disable_fs_src;
 757
 758         if (tegra->soc->scale_ss_clock) {
 759                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 760                 if (err < 0)
 761                         goto disable_hs_src;
 762         }
 763
 764         return 0;
 765
 766 disable_hs_src:
 767         clk_disable_unprepare(tegra->hs_src_clk);
 768 disable_fs_src:
 769         clk_disable_unprepare(tegra->fs_src_clk);
 770 disable_falc:
 771         clk_disable_unprepare(tegra->falcon_clk);
 772 disable_ss:
 773         clk_disable_unprepare(tegra->ss_clk);
 774 disable_host:
 775         clk_disable_unprepare(tegra->host_clk);
 776 disable_plle:
 777         clk_disable_unprepare(tegra->pll_e);
 778         return err;
 779 }
 780
 781 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 782 {
 783         clk_disable_unprepare(tegra->pll_e);
 784         clk_disable_unprepare(tegra->host_clk);
 785         clk_disable_unprepare(tegra->ss_clk);
 786         clk_disable_unprepare(tegra->falcon_clk);
 787         clk_disable_unprepare(tegra->fs_src_clk);
 788         clk_disable_unprepare(tegra->hs_src_clk);
 789 }
 790
 791 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 792 {
 793         unsigned int i;
 794         int err;
 795
 796         for (i = 0; i < tegra->num_phys; i++) {
 797                 err = phy_init(tegra->phys[i]);
 798                 if (err)
 799                         goto disable_phy;
 800
 801                 err = phy_power_on(tegra->phys[i]);
 802                 if (err) {
 803                         phy_exit(tegra->phys[i]);
 804                         goto disable_phy;
 805                 }
 806         }
 807
 808         return 0;
 809
 810 disable_phy:
 811         while (i--) {
 812                 phy_power_off(tegra->phys[i]);
 813                 phy_exit(tegra->phys[i]);
 814         }
 815
 816         return err;
 817 }
 818
 819 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 820 {
 821         unsigned int i;
 822
 823         for (i = 0; i < tegra->num_phys; i++) {
 824                 phy_power_off(tegra->phys[i]);
 825                 phy_exit(tegra->phys[i]);
 826         }
 827 }
 828
 829 #ifdef CONFIG_PM_SLEEP
 830 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
 831 {
 832         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
 833
 834         tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
 835                                            sizeof(u32), GFP_KERNEL);
 836         if (!tegra->context.ipfs)
 837                 return -ENOMEM;
 838
 839         tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
 840                                            sizeof(u32), GFP_KERNEL);
 841         if (!tegra->context.fpci)
 842                 return -ENOMEM;
 843
 844         return 0;
 845 }
 846 #else
 847 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
 848 {
 849         return 0;
 850 }
 851 #endif
 852
 853 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
 854 {
 855         struct tegra_xusb_fw_header *header;
 856         const struct firmware *fw;
 857         int err;
 858
 859         err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
 860         if (err < 0) {
 861                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 862                 return err;
 863         }
 864
 865         /* Load Falcon controller with its firmware. */
 866         header = (struct tegra_xusb_fw_header *)fw->data;
 867         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 868
 869         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 870                                             &tegra->fw.phys, GFP_KERNEL);
 871         if (!tegra->fw.virt) {
 872                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 873                 release_firmware(fw);
 874                 return -ENOMEM;
 875         }
 876
 877         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 878         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 879         release_firmware(fw);
 880
 881         return 0;
 882 }
 883
 884 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
 885 {
 886         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
 887         struct xhci_cap_regs __iomem *cap = tegra->regs;
 888         struct tegra_xusb_fw_header *header;
 889         struct device *dev = tegra->dev;
 890         struct xhci_op_regs __iomem *op;
 891         unsigned long timeout;
 892         time64_t timestamp;
 893         u64 address;
 894         u32 value;
 895         int err;
 896
 897         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 898         op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
 899
 900         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
 901                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
 902                          csb_readl(tegra, XUSB_FALC_CPUCTL));
 903                 return 0;
 904         }
 905
 906         /* Program the size of DFI into ILOAD_ATTR. */
 907         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
 908
 909         /*
 910          * Boot code of the firmware reads the ILOAD_BASE registers
 911          * to get to the start of the DFI in system memory.
 912          */
 913         address = tegra->fw.phys + sizeof(*header);
 914         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
 915         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
 916
 917         /* Set BOOTPATH to 1 in APMAP. */
 918         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
 919
 920         /* Invalidate L2IMEM. */
 921         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
 922
 923         /*
 924          * Initiate fetch of bootcode from system memory into L2IMEM.
 925          * Program bootcode location and size in system memory.
 926          */
 927         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
 928                                        IMEM_BLOCK_SIZE);
 929         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
 930                                         IMEM_BLOCK_SIZE);
 931         code_blocks = code_tag_blocks + code_size_blocks;
 932
 933         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
 934                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
 935                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
 936                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
 937         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
 938
 939         /* Trigger L2IMEM load operation. */
 940         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
 941                    XUSB_CSB_MP_L2IMEMOP_TRIG);
 942
 943         /* Setup Falcon auto-fill. */
 944         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
 945
 946         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
 947                         IMFILLRNG1_TAG_LO_SHIFT) |
 948                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
 949                         IMFILLRNG1_TAG_HI_SHIFT);
 950         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
 951
 952         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
 953
 954         /* wait for RESULT_VLD to get set */
 955 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
 956         err = readx_poll_timeout(tegra_csb_readl,
 957                                  XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
 958                                  value & L2IMEMOP_RESULT_VLD, 100, 10000);
 959         if (err < 0) {
 960                 dev_err(dev, "DMA controller not ready %#010x\n", value);
 961                 return err;
 962         }
 963 #undef tegra_csb_readl
 964
 965         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
 966                    XUSB_FALC_BOOTVEC);
 967
 968         /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
 969         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
 970
 971         timeout = jiffies + msecs_to_jiffies(200);
 972
 973         do {
 974                 value = readl(&op->status);
 975                 if ((value & STS_CNR) == 0)
 976                         break;
 977
 978                 usleep_range(1000, 2000);
 979         } while (time_is_after_jiffies(timeout));
 980
 981         value = readl(&op->status);
 982         if (value & STS_CNR) {
 983                 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
 984                 dev_err(dev, "XHCI controller not read: %#010x\n", value);
 985                 return -EIO;
 986         }
 987
 988         timestamp = le32_to_cpu(header->fwimg_created_time);
 989
 990         dev_info(dev, "Firmware timestamp: %ptTs UTC\n", &timestamp);
 991
 992         return 0;
 993 }
 994
 995 static void tegra_xusb_powerdomain_remove(struct device *dev,
 996                                           struct tegra_xusb *tegra)
 997 {
 998         if (!tegra->use_genpd)
 999                 return;
1000
1001         if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1002                 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1003         if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1004                 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1005 }
1006
1007 static int tegra_xusb_powerdomain_init(struct device *dev,
1008                                        struct tegra_xusb *tegra)
1009 {
1010         int err;
1011
1012         tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1013         if (IS_ERR(tegra->genpd_dev_host)) {
1014                 err = PTR_ERR(tegra->genpd_dev_host);
1015                 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1016                 return err;
1017         }
1018
1019         tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1020         if (IS_ERR(tegra->genpd_dev_ss)) {
1021                 err = PTR_ERR(tegra->genpd_dev_ss);
1022                 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1023                 return err;
1024         }
1025
1026         tegra->use_genpd = true;
1027
1028         return 0;
1029 }
1030
1031 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1032 {
1033         struct device *dev = tegra->dev;
1034         int rc;
1035
1036         if (tegra->use_genpd) {
1037                 rc = pm_runtime_get_sync(tegra->genpd_dev_ss);
1038                 if (rc < 0) {
1039                         dev_err(dev, "failed to enable XUSB SS partition\n");
1040                         return rc;
1041                 }
1042
1043                 rc = pm_runtime_get_sync(tegra->genpd_dev_host);
1044                 if (rc < 0) {
1045                         dev_err(dev, "failed to enable XUSB Host partition\n");
1046                         pm_runtime_put_sync(tegra->genpd_dev_ss);
1047                         return rc;
1048                 }
1049         } else {
1050                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1051                                                         tegra->ss_clk,
1052                                                         tegra->ss_rst);
1053                 if (rc < 0) {
1054                         dev_err(dev, "failed to enable XUSB SS partition\n");
1055                         return rc;
1056                 }
1057
1058                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1059                                                         tegra->host_clk,
1060                                                         tegra->host_rst);
1061                 if (rc < 0) {
1062                         dev_err(dev, "failed to enable XUSB Host partition\n");
1063                         tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1064                         return rc;
1065                 }
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1072 {
1073         struct device *dev = tegra->dev;
1074         int rc;
1075
1076         if (tegra->use_genpd) {
1077                 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1078                 if (rc < 0) {
1079                         dev_err(dev, "failed to disable XUSB Host partition\n");
1080                         return rc;
1081                 }
1082
1083                 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1084                 if (rc < 0) {
1085                         dev_err(dev, "failed to disable XUSB SS partition\n");
1086                         pm_runtime_get_sync(tegra->genpd_dev_host);
1087                         return rc;
1088                 }
1089         } else {
1090                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1091                 if (rc < 0) {
1092                         dev_err(dev, "failed to disable XUSB Host partition\n");
1093                         return rc;
1094                 }
1095
1096                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1097                 if (rc < 0) {
1098                         dev_err(dev, "failed to disable XUSB SS partition\n");
1099                         tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1100                                                           tegra->host_clk,
1101                                                           tegra->host_rst);
1102                         return rc;
1103                 }
1104         }
1105
1106         return 0;
1107 }
1108
1109 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1110 {
1111         struct tegra_xusb_mbox_msg msg;
1112         int err;
1113
1114         /* Enable firmware messages from controller. */
1115         msg.cmd = MBOX_CMD_MSG_ENABLED;
1116         msg.data = 0;
1117
1118         err = tegra_xusb_mbox_send(tegra, &msg);
1119         if (err < 0)
1120                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1121
1122         return err;
1123 }
1124
1125 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1126 {
1127         struct tegra_xusb *tegra = data;
1128
1129         mutex_lock(&tegra->lock);
1130
1131         if (tegra->suspended) {
1132                 mutex_unlock(&tegra->lock);
1133                 return IRQ_HANDLED;
1134         }
1135
1136         mutex_unlock(&tegra->lock);
1137
1138         pm_runtime_resume(tegra->dev);
1139
1140         return IRQ_HANDLED;
1141 }
1142
1143 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1144 {
1145         int err;
1146
1147         mutex_lock(&tegra->lock);
1148         err = __tegra_xusb_enable_firmware_messages(tegra);
1149         mutex_unlock(&tegra->lock);
1150
1151         return err;
1152 }
1153
1154 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1155                                                  bool set)
1156 {
1157         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1158         struct usb_hcd *hcd = main ?  xhci->main_hcd : xhci->shared_hcd;
1159         unsigned int wait = (!main && !set) ? 1000 : 10;
1160         u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1161         u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1162         u32 status;
1163         u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1164         u32 status_val = set ? stat_power : 0;
1165
1166         dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1167                 set ? "set" : "clear", main ? "HS" : "SS");
1168
1169         hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1170                                  NULL, 0);
1171
1172         do {
1173                 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1174                                         (char *) &status, sizeof(status));
1175                 if (status_val == (status & stat_power))
1176                         break;
1177
1178                 if (!main && !set)
1179                         usleep_range(600, 700);
1180                 else
1181                         usleep_range(10, 20);
1182         } while (--wait > 0);
1183
1184         if (status_val != (status & stat_power))
1185                 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1186                                                 set ? "set" : "clear",
1187                                                 main ? "HS" : "SS", status);
1188 }
1189
1190 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1191                                                                 int port)
1192 {
1193         unsigned int i, phy_count = 0;
1194
1195         for (i = 0; i < tegra->soc->num_types; i++) {
1196                 if (!strncmp(tegra->soc->phy_types[i].name, name,
1197                                                             strlen(name)))
1198                         return tegra->phys[phy_count+port];
1199
1200                 phy_count += tegra->soc->phy_types[i].num;
1201         }
1202
1203         return NULL;
1204 }
1205
1206 static void tegra_xhci_id_work(struct work_struct *work)
1207 {
1208         struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1209                                                 id_work);
1210         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1211         struct tegra_xusb_mbox_msg msg;
1212         struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1213                                                     tegra->otg_usb2_port);
1214         u32 status;
1215         int ret;
1216
1217         dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1218
1219         mutex_lock(&tegra->lock);
1220
1221         if (tegra->host_mode)
1222                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1223         else
1224                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1225
1226         mutex_unlock(&tegra->lock);
1227
1228         if (tegra->host_mode) {
1229                 /* switch to host mode */
1230                 if (tegra->otg_usb3_port >= 0) {
1231                         if (tegra->soc->otg_reset_sspi) {
1232                                 /* set PP=0 */
1233                                 tegra_xhci_hc_driver.hub_control(
1234                                         xhci->shared_hcd, GetPortStatus,
1235                                         0, tegra->otg_usb3_port+1,
1236                                         (char *) &status, sizeof(status));
1237                                 if (status & USB_SS_PORT_STAT_POWER)
1238                                         tegra_xhci_set_port_power(tegra, false,
1239                                                                   false);
1240
1241                                 /* reset OTG port SSPI */
1242                                 msg.cmd = MBOX_CMD_RESET_SSPI;
1243                                 msg.data = tegra->otg_usb3_port+1;
1244
1245                                 ret = tegra_xusb_mbox_send(tegra, &msg);
1246                                 if (ret < 0) {
1247                                         dev_info(tegra->dev,
1248                                                 "failed to RESET_SSPI %d\n",
1249                                                 ret);
1250                                 }
1251                         }
1252
1253                         tegra_xhci_set_port_power(tegra, false, true);
1254                 }
1255
1256                 tegra_xhci_set_port_power(tegra, true, true);
1257
1258         } else {
1259                 if (tegra->otg_usb3_port >= 0)
1260                         tegra_xhci_set_port_power(tegra, false, false);
1261
1262                 tegra_xhci_set_port_power(tegra, true, false);
1263         }
1264 }
1265
1266 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
1267 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1268 {
1269         return (tegra->usbphy[index] != NULL);
1270 }
1271
1272 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1273 {
1274         struct tegra_xusb_padctl *padctl = tegra->padctl;
1275         unsigned int i;
1276         int port;
1277
1278         for (i = 0; i < tegra->num_usb_phys; i++) {
1279                 if (is_usb2_otg_phy(tegra, i)) {
1280                         port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1281                         if ((port >= 0) && (index == (unsigned int)port))
1282                                 return true;
1283                 }
1284         }
1285
1286         return false;
1287 }
1288
1289 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1290 {
1291         if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1292                 return true;
1293
1294         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1295                 if (is_usb2_otg_phy(tegra, index))
1296                         return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1297                 else
1298                         return true;
1299         }
1300
1301         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1302                 if (is_usb3_otg_phy(tegra, index))
1303                         return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1304                 else
1305                         return true;
1306         }
1307
1308         return false;
1309 }
1310 #endif
1311
1312 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1313                                               struct usb_phy *usbphy)
1314 {
1315         unsigned int i;
1316
1317         for (i = 0; i < tegra->num_usb_phys; i++) {
1318                 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1319                         return i;
1320         }
1321
1322         return -1;
1323 }
1324
1325 static int tegra_xhci_id_notify(struct notifier_block *nb,
1326                                          unsigned long action, void *data)
1327 {
1328         struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1329                                                     id_nb);
1330         struct usb_phy *usbphy = (struct usb_phy *)data;
1331
1332         dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1333
1334         if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1335                 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1336                 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1337                         tegra->host_mode);
1338                 return NOTIFY_OK;
1339         }
1340
1341         tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1342         tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1343                                                         tegra->padctl,
1344                                                         tegra->otg_usb2_port);
1345
1346         tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1347
1348         schedule_work(&tegra->id_work);
1349
1350         return NOTIFY_OK;
1351 }
1352
1353 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1354 {
1355         unsigned int i;
1356
1357         tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1358                                    sizeof(*tegra->usbphy), GFP_KERNEL);
1359         if (!tegra->usbphy)
1360                 return -ENOMEM;
1361
1362         INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1363         tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1364         tegra->otg_usb2_port = -EINVAL;
1365         tegra->otg_usb3_port = -EINVAL;
1366
1367         for (i = 0; i < tegra->num_usb_phys; i++) {
1368                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1369
1370                 if (!phy)
1371                         continue;
1372
1373                 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1374                                                         phy->dev.of_node,
1375                                                         &tegra->id_nb);
1376                 if (!IS_ERR(tegra->usbphy[i])) {
1377                         dev_dbg(tegra->dev, "usbphy-%d registered", i);
1378                         otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1379                 } else {
1380                         /*
1381                          * usb-phy is optional, continue if its not available.
1382                          */
1383                         tegra->usbphy[i] = NULL;
1384                 }
1385         }
1386
1387         return 0;
1388 }
1389
1390 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1391 {
1392         unsigned int i;
1393
1394         cancel_work_sync(&tegra->id_work);
1395
1396         for (i = 0; i < tegra->num_usb_phys; i++)
1397                 if (tegra->usbphy[i])
1398                         otg_set_host(tegra->usbphy[i]->otg, NULL);
1399 }
1400
1401 static int tegra_xusb_probe(struct platform_device *pdev)
1402 {
1403         struct tegra_xusb *tegra;
1404         struct device_node *np;
1405         struct resource *regs;
1406         struct xhci_hcd *xhci;
1407         unsigned int i, j, k;
1408         struct phy *phy;
1409         int err;
1410
1411         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1412
1413         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1414         if (!tegra)
1415                 return -ENOMEM;
1416
1417         tegra->soc = of_device_get_match_data(&pdev->dev);
1418         mutex_init(&tegra->lock);
1419         tegra->dev = &pdev->dev;
1420
1421         err = tegra_xusb_init_context(tegra);
1422         if (err < 0)
1423                 return err;
1424
1425         tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
1426         if (IS_ERR(tegra->regs))
1427                 return PTR_ERR(tegra->regs);
1428
1429         tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1430         if (IS_ERR(tegra->fpci_base))
1431                 return PTR_ERR(tegra->fpci_base);
1432
1433         if (tegra->soc->has_ipfs) {
1434                 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1435                 if (IS_ERR(tegra->ipfs_base))
1436                         return PTR_ERR(tegra->ipfs_base);
1437         }
1438
1439         tegra->xhci_irq = platform_get_irq(pdev, 0);
1440         if (tegra->xhci_irq < 0)
1441                 return tegra->xhci_irq;
1442
1443         tegra->mbox_irq = platform_get_irq(pdev, 1);
1444         if (tegra->mbox_irq < 0)
1445                 return tegra->mbox_irq;
1446
1447         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1448         if (IS_ERR(tegra->padctl))
1449                 return PTR_ERR(tegra->padctl);
1450
1451         np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1452         if (!np) {
1453                 err = -ENODEV;
1454                 goto put_padctl;
1455         }
1456
1457         tegra->padctl_irq = of_irq_get(np, 0);
1458         if (tegra->padctl_irq <= 0) {
1459                 err = (tegra->padctl_irq == 0) ? -ENODEV : tegra->padctl_irq;
1460                 goto put_padctl;
1461         }
1462
1463         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1464         if (IS_ERR(tegra->host_clk)) {
1465                 err = PTR_ERR(tegra->host_clk);
1466                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1467                 goto put_padctl;
1468         }
1469
1470         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1471         if (IS_ERR(tegra->falcon_clk)) {
1472                 err = PTR_ERR(tegra->falcon_clk);
1473                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1474                 goto put_padctl;
1475         }
1476
1477         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1478         if (IS_ERR(tegra->ss_clk)) {
1479                 err = PTR_ERR(tegra->ss_clk);
1480                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1481                 goto put_padctl;
1482         }
1483
1484         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1485         if (IS_ERR(tegra->ss_src_clk)) {
1486                 err = PTR_ERR(tegra->ss_src_clk);
1487                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1488                 goto put_padctl;
1489         }
1490
1491         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1492         if (IS_ERR(tegra->hs_src_clk)) {
1493                 err = PTR_ERR(tegra->hs_src_clk);
1494                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1495                 goto put_padctl;
1496         }
1497
1498         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1499         if (IS_ERR(tegra->fs_src_clk)) {
1500                 err = PTR_ERR(tegra->fs_src_clk);
1501                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1502                 goto put_padctl;
1503         }
1504
1505         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1506         if (IS_ERR(tegra->pll_u_480m)) {
1507                 err = PTR_ERR(tegra->pll_u_480m);
1508                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1509                 goto put_padctl;
1510         }
1511
1512         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1513         if (IS_ERR(tegra->clk_m)) {
1514                 err = PTR_ERR(tegra->clk_m);
1515                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1516                 goto put_padctl;
1517         }
1518
1519         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1520         if (IS_ERR(tegra->pll_e)) {
1521                 err = PTR_ERR(tegra->pll_e);
1522                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1523                 goto put_padctl;
1524         }
1525
1526         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1527                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1528                                                          "xusb_host");
1529                 if (IS_ERR(tegra->host_rst)) {
1530                         err = PTR_ERR(tegra->host_rst);
1531                         dev_err(&pdev->dev,
1532                                 "failed to get xusb_host reset: %d\n", err);
1533                         goto put_padctl;
1534                 }
1535
1536                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1537                 if (IS_ERR(tegra->ss_rst)) {
1538                         err = PTR_ERR(tegra->ss_rst);
1539                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1540                                 err);
1541                         goto put_padctl;
1542                 }
1543         } else {
1544                 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1545                 if (err)
1546                         goto put_powerdomains;
1547         }
1548
1549         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1550                                        sizeof(*tegra->supplies), GFP_KERNEL);
1551         if (!tegra->supplies) {
1552                 err = -ENOMEM;
1553                 goto put_powerdomains;
1554         }
1555
1556         regulator_bulk_set_supply_names(tegra->supplies,
1557                                         tegra->soc->supply_names,
1558                                         tegra->soc->num_supplies);
1559
1560         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1561                                       tegra->supplies);
1562         if (err) {
1563                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1564                 goto put_powerdomains;
1565         }
1566
1567         for (i = 0; i < tegra->soc->num_types; i++) {
1568                 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1569                         tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1570                 tegra->num_phys += tegra->soc->phy_types[i].num;
1571         }
1572
1573         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1574                                    sizeof(*tegra->phys), GFP_KERNEL);
1575         if (!tegra->phys) {
1576                 err = -ENOMEM;
1577                 goto put_powerdomains;
1578         }
1579
1580         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1581                 char prop[8];
1582
1583                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1584                         snprintf(prop, sizeof(prop), "%s-%d",
1585                                  tegra->soc->phy_types[i].name, j);
1586
1587                         phy = devm_phy_optional_get(&pdev->dev, prop);
1588                         if (IS_ERR(phy)) {
1589                                 dev_err(&pdev->dev,
1590                                         "failed to get PHY %s: %ld\n", prop,
1591                                         PTR_ERR(phy));
1592                                 err = PTR_ERR(phy);
1593                                 goto put_powerdomains;
1594                         }
1595
1596                         tegra->phys[k++] = phy;
1597                 }
1598         }
1599
1600         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1601                                     dev_name(&pdev->dev));
1602         if (!tegra->hcd) {
1603                 err = -ENOMEM;
1604                 goto put_powerdomains;
1605         }
1606
1607         tegra->hcd->skip_phy_initialization = 1;
1608         tegra->hcd->regs = tegra->regs;
1609         tegra->hcd->rsrc_start = regs->start;
1610         tegra->hcd->rsrc_len = resource_size(regs);
1611
1612         /*
1613          * This must happen after usb_create_hcd(), because usb_create_hcd()
1614          * will overwrite the drvdata of the device with the hcd it creates.
1615          */
1616         platform_set_drvdata(pdev, tegra);
1617
1618         err = tegra_xusb_clk_enable(tegra);
1619         if (err) {
1620                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1621                 goto put_hcd;
1622         }
1623
1624         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1625         if (err) {
1626                 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1627                 goto disable_clk;
1628         }
1629
1630         err = tegra_xusb_phy_enable(tegra);
1631         if (err < 0) {
1632                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1633                 goto disable_regulator;
1634         }
1635
1636         /*
1637          * The XUSB Falcon microcontroller can only address 40 bits, so set
1638          * the DMA mask accordingly.
1639          */
1640         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1641         if (err < 0) {
1642                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1643                 goto disable_phy;
1644         }
1645
1646         err = tegra_xusb_request_firmware(tegra);
1647         if (err < 0) {
1648                 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1649                 goto disable_phy;
1650         }
1651
1652         err = tegra_xusb_unpowergate_partitions(tegra);
1653         if (err)
1654                 goto free_firmware;
1655
1656         tegra_xusb_config(tegra);
1657
1658         err = tegra_xusb_load_firmware(tegra);
1659         if (err < 0) {
1660                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1661                 goto powergate;
1662         }
1663
1664         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1665         if (err < 0) {
1666                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1667                 goto powergate;
1668         }
1669
1670         device_wakeup_enable(tegra->hcd->self.controller);
1671
1672         xhci = hcd_to_xhci(tegra->hcd);
1673
1674         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1675                                                  &pdev->dev,
1676                                                  dev_name(&pdev->dev),
1677                                                  tegra->hcd);
1678         if (!xhci->shared_hcd) {
1679                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1680                 err = -ENOMEM;
1681                 goto remove_usb2;
1682         }
1683
1684         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1685         if (err < 0) {
1686                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1687                 goto put_usb3;
1688         }
1689
1690         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1691                                         tegra_xusb_mbox_irq,
1692                                         tegra_xusb_mbox_thread, 0,
1693                                         dev_name(&pdev->dev), tegra);
1694         if (err < 0) {
1695                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1696                 goto remove_usb3;
1697         }
1698
1699         err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq, NULL, tegra_xusb_padctl_irq,
1700                                         IRQF_ONESHOT, dev_name(&pdev->dev), tegra);
1701         if (err < 0) {
1702                 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1703                 goto remove_usb3;
1704         }
1705
1706         err = tegra_xusb_enable_firmware_messages(tegra);
1707         if (err < 0) {
1708                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1709                 goto remove_usb3;
1710         }
1711
1712         err = tegra_xusb_init_usb_phy(tegra);
1713         if (err < 0) {
1714                 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1715                 goto remove_usb3;
1716         }
1717
1718         /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1719         device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1720         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1721         device_init_wakeup(tegra->dev, true);
1722
1723         pm_runtime_use_autosuspend(tegra->dev);
1724         pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1725         pm_runtime_mark_last_busy(tegra->dev);
1726         pm_runtime_set_active(tegra->dev);
1727         pm_runtime_enable(tegra->dev);
1728
1729         return 0;
1730
1731 remove_usb3:
1732         usb_remove_hcd(xhci->shared_hcd);
1733 put_usb3:
1734         usb_put_hcd(xhci->shared_hcd);
1735 remove_usb2:
1736         usb_remove_hcd(tegra->hcd);
1737 powergate:
1738         tegra_xusb_powergate_partitions(tegra);
1739 free_firmware:
1740         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1741                           tegra->fw.phys);
1742 disable_phy:
1743         tegra_xusb_phy_disable(tegra);
1744 disable_regulator:
1745         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1746 disable_clk:
1747         tegra_xusb_clk_disable(tegra);
1748 put_hcd:
1749         usb_put_hcd(tegra->hcd);
1750 put_powerdomains:
1751         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1752 put_padctl:
1753         of_node_put(np);
1754         tegra_xusb_padctl_put(tegra->padctl);
1755         return err;
1756 }
1757
1758 static int tegra_xusb_remove(struct platform_device *pdev)
1759 {
1760         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1761         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1762
1763         tegra_xusb_deinit_usb_phy(tegra);
1764
1765         pm_runtime_get_sync(&pdev->dev);
1766         usb_remove_hcd(xhci->shared_hcd);
1767         usb_put_hcd(xhci->shared_hcd);
1768         xhci->shared_hcd = NULL;
1769         usb_remove_hcd(tegra->hcd);
1770         usb_put_hcd(tegra->hcd);
1771
1772         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1773                           tegra->fw.phys);
1774
1775         pm_runtime_disable(&pdev->dev);
1776         pm_runtime_put(&pdev->dev);
1777
1778         tegra_xusb_powergate_partitions(tegra);
1779
1780         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1781
1782         tegra_xusb_phy_disable(tegra);
1783         tegra_xusb_clk_disable(tegra);
1784         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1785         tegra_xusb_padctl_put(tegra->padctl);
1786
1787         return 0;
1788 }
1789
1790 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1791 {
1792         struct device *dev = hub->hcd->self.controller;
1793         bool status = true;
1794         unsigned int i;
1795         u32 value;
1796
1797         for (i = 0; i < hub->num_ports; i++) {
1798                 value = readl(hub->ports[i]->addr);
1799                 if ((value & PORT_PE) == 0)
1800                         continue;
1801
1802                 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1803                         dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1804                                  hub->hcd->self.busnum, i + 1, value);
1805                         status = false;
1806                 }
1807         }
1808
1809         return status;
1810 }
1811
1812 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1813 {
1814         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1815         struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
1816         unsigned long flags;
1817         int err = 0;
1818
1819         if (bus_state->bus_suspended) {
1820                 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
1821                  * to U3 state, it takes 3ms to enter U3.
1822                  */
1823                 usleep_range(3000, 4000);
1824         }
1825
1826         spin_lock_irqsave(&xhci->lock, flags);
1827
1828         if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1829             !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1830                 err = -EBUSY;
1831
1832         spin_unlock_irqrestore(&xhci->lock, flags);
1833
1834         return err;
1835 }
1836
1837 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1838 {
1839         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1840         struct tegra_xusb_context *ctx = &tegra->context;
1841         unsigned int i;
1842
1843         if (soc->ipfs.num_offsets > 0) {
1844                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1845                         ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1846         }
1847
1848         if (soc->fpci.num_offsets > 0) {
1849                 for (i = 0; i < soc->fpci.num_offsets; i++)
1850                         ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1851         }
1852 }
1853
1854 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1855 {
1856         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1857         struct tegra_xusb_context *ctx = &tegra->context;
1858         unsigned int i;
1859
1860         if (soc->fpci.num_offsets > 0) {
1861                 for (i = 0; i < soc->fpci.num_offsets; i++)
1862                         fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1863         }
1864
1865         if (soc->ipfs.num_offsets > 0) {
1866                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1867                         ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1868         }
1869 }
1870
1871 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
1872 {
1873         if (DEV_LOWSPEED(portsc))
1874                 return USB_SPEED_LOW;
1875
1876         if (DEV_HIGHSPEED(portsc))
1877                 return USB_SPEED_HIGH;
1878
1879         if (DEV_FULLSPEED(portsc))
1880                 return USB_SPEED_FULL;
1881
1882         if (DEV_SUPERSPEED_ANY(portsc))
1883                 return USB_SPEED_SUPER;
1884
1885         return USB_SPEED_UNKNOWN;
1886 }
1887
1888 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
1889 {
1890         struct tegra_xusb_padctl *padctl = tegra->padctl;
1891         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1892         enum usb_device_speed speed;
1893         struct phy *phy;
1894         unsigned int index, offset;
1895         unsigned int i, j, k;
1896         struct xhci_hub *rhub;
1897         u32 portsc;
1898
1899         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1900                 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
1901                         rhub = &xhci->usb3_rhub;
1902                 else
1903                         rhub = &xhci->usb2_rhub;
1904
1905                 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
1906                         offset = tegra->soc->ports.usb2.count;
1907                 else
1908                         offset = 0;
1909
1910                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1911                         phy = tegra->phys[k++];
1912
1913                         if (!phy)
1914                                 continue;
1915
1916                         index = j + offset;
1917
1918                         if (index >= rhub->num_ports)
1919                                 continue;
1920
1921                         if (!is_host_mode_phy(tegra, i, j))
1922                                 continue;
1923
1924                         portsc = readl(rhub->ports[index]->addr);
1925                         speed = tegra_xhci_portsc_to_speed(tegra, portsc);
1926                         tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
1927                         tegra_xusb_padctl_enable_phy_wake(padctl, phy);
1928                 }
1929         }
1930 }
1931
1932 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
1933 {
1934         struct tegra_xusb_padctl *padctl = tegra->padctl;
1935         unsigned int i;
1936
1937         for (i = 0; i < tegra->num_phys; i++) {
1938                 if (!tegra->phys[i])
1939                         continue;
1940
1941                 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
1942         }
1943 }
1944
1945 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
1946 {
1947         struct tegra_xusb_padctl *padctl = tegra->padctl;
1948         unsigned int i;
1949
1950         for (i = 0; i < tegra->num_phys; i++) {
1951                 if (!tegra->phys[i])
1952                         continue;
1953
1954                 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
1955         }
1956 }
1957
1958 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime)
1959 {
1960         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1961         struct device *dev = tegra->dev;
1962         bool wakeup = runtime ? true : device_may_wakeup(dev);
1963         unsigned int i;
1964         int err;
1965         u32 usbcmd;
1966
1967         dev_dbg(dev, "entering ELPG\n");
1968
1969         usbcmd = readl(&xhci->op_regs->command);
1970         usbcmd &= ~CMD_EIE;
1971         writel(usbcmd, &xhci->op_regs->command);
1972
1973         err = tegra_xusb_check_ports(tegra);
1974         if (err < 0) {
1975                 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1976                 goto out;
1977         }
1978
1979         err = xhci_suspend(xhci, wakeup);
1980         if (err < 0) {
1981                 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
1982                 goto out;
1983         }
1984
1985         tegra_xusb_save_context(tegra);
1986
1987         if (wakeup)
1988                 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
1989
1990         tegra_xusb_powergate_partitions(tegra);
1991
1992         for (i = 0; i < tegra->num_phys; i++) {
1993                 if (!tegra->phys[i])
1994                         continue;
1995
1996                 phy_power_off(tegra->phys[i]);
1997                 if (!wakeup)
1998                         phy_exit(tegra->phys[i]);
1999         }
2000
2001         tegra_xusb_clk_disable(tegra);
2002
2003 out:
2004         if (!err)
2005                 dev_dbg(tegra->dev, "entering ELPG done\n");
2006         else {
2007                 usbcmd = readl(&xhci->op_regs->command);
2008                 usbcmd |= CMD_EIE;
2009                 writel(usbcmd, &xhci->op_regs->command);
2010
2011                 dev_dbg(tegra->dev, "entering ELPG failed\n");
2012                 pm_runtime_mark_last_busy(tegra->dev);
2013         }
2014
2015         return err;
2016 }
2017
2018 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime)
2019 {
2020         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2021         struct device *dev = tegra->dev;
2022         bool wakeup = runtime ? true : device_may_wakeup(dev);
2023         unsigned int i;
2024         u32 usbcmd;
2025         int err;
2026
2027         dev_dbg(dev, "exiting ELPG\n");
2028         pm_runtime_mark_last_busy(tegra->dev);
2029
2030         err = tegra_xusb_clk_enable(tegra);
2031         if (err < 0) {
2032                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2033                 goto out;
2034         }
2035
2036         err = tegra_xusb_unpowergate_partitions(tegra);
2037         if (err)
2038                 goto disable_clks;
2039
2040         if (wakeup)
2041                 tegra_xhci_disable_phy_wake(tegra);
2042
2043         for (i = 0; i < tegra->num_phys; i++) {
2044                 if (!tegra->phys[i])
2045                         continue;
2046
2047                 if (!wakeup)
2048                         phy_init(tegra->phys[i]);
2049
2050                 phy_power_on(tegra->phys[i]);
2051         }
2052
2053         tegra_xusb_config(tegra);
2054         tegra_xusb_restore_context(tegra);
2055
2056         err = tegra_xusb_load_firmware(tegra);
2057         if (err < 0) {
2058                 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2059                 goto disable_phy;
2060         }
2061
2062         err = __tegra_xusb_enable_firmware_messages(tegra);
2063         if (err < 0) {
2064                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2065                 goto disable_phy;
2066         }
2067
2068         if (wakeup)
2069                 tegra_xhci_disable_phy_sleepwalk(tegra);
2070
2071         err = xhci_resume(xhci, 0);
2072         if (err < 0) {
2073                 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2074                 goto disable_phy;
2075         }
2076
2077         usbcmd = readl(&xhci->op_regs->command);
2078         usbcmd |= CMD_EIE;
2079         writel(usbcmd, &xhci->op_regs->command);
2080
2081         goto out;
2082
2083 disable_phy:
2084         for (i = 0; i < tegra->num_phys; i++) {
2085                 if (!tegra->phys[i])
2086                         continue;
2087
2088                 phy_power_off(tegra->phys[i]);
2089                 if (!wakeup)
2090                         phy_exit(tegra->phys[i]);
2091         }
2092         tegra_xusb_powergate_partitions(tegra);
2093 disable_clks:
2094         tegra_xusb_clk_disable(tegra);
2095 out:
2096         if (!err)
2097                 dev_dbg(dev, "exiting ELPG done\n");
2098         else
2099                 dev_dbg(dev, "exiting ELPG failed\n");
2100
2101         return err;
2102 }
2103
2104 static __maybe_unused int tegra_xusb_suspend(struct device *dev)
2105 {
2106         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2107         int err;
2108
2109         synchronize_irq(tegra->mbox_irq);
2110
2111         mutex_lock(&tegra->lock);
2112
2113         if (pm_runtime_suspended(dev)) {
2114                 err = tegra_xusb_exit_elpg(tegra, true);
2115                 if (err < 0)
2116                         goto out;
2117         }
2118
2119         err = tegra_xusb_enter_elpg(tegra, false);
2120         if (err < 0) {
2121                 if (pm_runtime_suspended(dev)) {
2122                         pm_runtime_disable(dev);
2123                         pm_runtime_set_active(dev);
2124                         pm_runtime_enable(dev);
2125                 }
2126
2127                 goto out;
2128         }
2129
2130 out:
2131         if (!err) {
2132                 tegra->suspended = true;
2133                 pm_runtime_disable(dev);
2134
2135                 if (device_may_wakeup(dev)) {
2136                         if (enable_irq_wake(tegra->padctl_irq))
2137                                 dev_err(dev, "failed to enable padctl wakes\n");
2138                 }
2139         }
2140
2141         mutex_unlock(&tegra->lock);
2142
2143         return err;
2144 }
2145
2146 static __maybe_unused int tegra_xusb_resume(struct device *dev)
2147 {
2148         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2149         int err;
2150
2151         mutex_lock(&tegra->lock);
2152
2153         if (!tegra->suspended) {
2154                 mutex_unlock(&tegra->lock);
2155                 return 0;
2156         }
2157
2158         err = tegra_xusb_exit_elpg(tegra, false);
2159         if (err < 0) {
2160                 mutex_unlock(&tegra->lock);
2161                 return err;
2162         }
2163
2164         if (device_may_wakeup(dev)) {
2165                 if (disable_irq_wake(tegra->padctl_irq))
2166                         dev_err(dev, "failed to disable padctl wakes\n");
2167         }
2168         tegra->suspended = false;
2169         mutex_unlock(&tegra->lock);
2170
2171         pm_runtime_set_active(dev);
2172         pm_runtime_enable(dev);
2173
2174         return 0;
2175 }
2176
2177 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev)
2178 {
2179         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2180         int ret;
2181
2182         synchronize_irq(tegra->mbox_irq);
2183         mutex_lock(&tegra->lock);
2184         ret = tegra_xusb_enter_elpg(tegra, true);
2185         mutex_unlock(&tegra->lock);
2186
2187         return ret;
2188 }
2189
2190 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev)
2191 {
2192         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2193         int err;
2194
2195         mutex_lock(&tegra->lock);
2196         err = tegra_xusb_exit_elpg(tegra, true);
2197         mutex_unlock(&tegra->lock);
2198
2199         return err;
2200 }
2201
2202 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2203         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2204                            tegra_xusb_runtime_resume, NULL)
2205         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2206 };
2207
2208 static const char * const tegra124_supply_names[] = {
2209         "avddio-pex",
2210         "dvddio-pex",
2211         "avdd-usb",
2212         "hvdd-usb-ss",
2213 };
2214
2215 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2216         { .name = "usb3", .num = 2, },
2217         { .name = "usb2", .num = 3, },
2218         { .name = "hsic", .num = 2, },
2219 };
2220
2221 static const unsigned int tegra124_xusb_context_ipfs[] = {
2222         IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2223         IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2224         IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2225         IPFS_XUSB_HOST_MSI_VEC0_0,
2226         IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2227         IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2228         IPFS_XUSB_HOST_INTR_MASK_0,
2229         IPFS_XUSB_HOST_INTR_ENABLE_0,
2230         IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2231         IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2232         IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2233 };
2234
2235 static const unsigned int tegra124_xusb_context_fpci[] = {
2236         XUSB_CFG_ARU_CONTEXT_HS_PLS,
2237         XUSB_CFG_ARU_CONTEXT_FS_PLS,
2238         XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2239         XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2240         XUSB_CFG_ARU_CONTEXT,
2241         XUSB_CFG_AXI_CFG,
2242         XUSB_CFG_24,
2243         XUSB_CFG_16,
2244 };
2245
2246 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2247         .ipfs = {
2248                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2249                 .offsets = tegra124_xusb_context_ipfs,
2250         },
2251         .fpci = {
2252                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2253                 .offsets = tegra124_xusb_context_fpci,
2254         },
2255 };
2256
2257 static const struct tegra_xusb_soc tegra124_soc = {
2258         .firmware = "nvidia/tegra124/xusb.bin",
2259         .supply_names = tegra124_supply_names,
2260         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2261         .phy_types = tegra124_phy_types,
2262         .num_types = ARRAY_SIZE(tegra124_phy_types),
2263         .context = &tegra124_xusb_context,
2264         .ports = {
2265                 .usb2 = { .offset = 4, .count = 4, },
2266                 .hsic = { .offset = 6, .count = 2, },
2267                 .usb3 = { .offset = 0, .count = 2, },
2268         },
2269         .scale_ss_clock = true,
2270         .has_ipfs = true,
2271         .otg_reset_sspi = false,
2272         .mbox = {
2273                 .cmd = 0xe4,
2274                 .data_in = 0xe8,
2275                 .data_out = 0xec,
2276                 .owner = 0xf0,
2277         },
2278 };
2279 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2280
2281 static const char * const tegra210_supply_names[] = {
2282         "dvddio-pex",
2283         "hvddio-pex",
2284         "avdd-usb",
2285 };
2286
2287 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2288         { .name = "usb3", .num = 4, },
2289         { .name = "usb2", .num = 4, },
2290         { .name = "hsic", .num = 1, },
2291 };
2292
2293 static const struct tegra_xusb_soc tegra210_soc = {
2294         .firmware = "nvidia/tegra210/xusb.bin",
2295         .supply_names = tegra210_supply_names,
2296         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2297         .phy_types = tegra210_phy_types,
2298         .num_types = ARRAY_SIZE(tegra210_phy_types),
2299         .context = &tegra124_xusb_context,
2300         .ports = {
2301                 .usb2 = { .offset = 4, .count = 4, },
2302                 .hsic = { .offset = 8, .count = 1, },
2303                 .usb3 = { .offset = 0, .count = 4, },
2304         },
2305         .scale_ss_clock = false,
2306         .has_ipfs = true,
2307         .otg_reset_sspi = true,
2308         .mbox = {
2309                 .cmd = 0xe4,
2310                 .data_in = 0xe8,
2311                 .data_out = 0xec,
2312                 .owner = 0xf0,
2313         },
2314 };
2315 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2316
2317 static const char * const tegra186_supply_names[] = {
2318 };
2319 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2320
2321 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2322         { .name = "usb3", .num = 3, },
2323         { .name = "usb2", .num = 3, },
2324         { .name = "hsic", .num = 1, },
2325 };
2326
2327 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2328         .fpci = {
2329                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2330                 .offsets = tegra124_xusb_context_fpci,
2331         },
2332 };
2333
2334 static const struct tegra_xusb_soc tegra186_soc = {
2335         .firmware = "nvidia/tegra186/xusb.bin",
2336         .supply_names = tegra186_supply_names,
2337         .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2338         .phy_types = tegra186_phy_types,
2339         .num_types = ARRAY_SIZE(tegra186_phy_types),
2340         .context = &tegra186_xusb_context,
2341         .ports = {
2342                 .usb3 = { .offset = 0, .count = 3, },
2343                 .usb2 = { .offset = 3, .count = 3, },
2344                 .hsic = { .offset = 6, .count = 1, },
2345         },
2346         .scale_ss_clock = false,
2347         .has_ipfs = false,
2348         .otg_reset_sspi = false,
2349         .mbox = {
2350                 .cmd = 0xe4,
2351                 .data_in = 0xe8,
2352                 .data_out = 0xec,
2353                 .owner = 0xf0,
2354         },
2355         .lpm_support = true,
2356 };
2357
2358 static const char * const tegra194_supply_names[] = {
2359 };
2360
2361 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2362         { .name = "usb3", .num = 4, },
2363         { .name = "usb2", .num = 4, },
2364 };
2365
2366 static const struct tegra_xusb_soc tegra194_soc = {
2367         .firmware = "nvidia/tegra194/xusb.bin",
2368         .supply_names = tegra194_supply_names,
2369         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2370         .phy_types = tegra194_phy_types,
2371         .num_types = ARRAY_SIZE(tegra194_phy_types),
2372         .context = &tegra186_xusb_context,
2373         .ports = {
2374                 .usb3 = { .offset = 0, .count = 4, },
2375                 .usb2 = { .offset = 4, .count = 4, },
2376         },
2377         .scale_ss_clock = false,
2378         .has_ipfs = false,
2379         .otg_reset_sspi = false,
2380         .mbox = {
2381                 .cmd = 0x68,
2382                 .data_in = 0x6c,
2383                 .data_out = 0x70,
2384                 .owner = 0x74,
2385         },
2386         .lpm_support = true,
2387 };
2388 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2389
2390 static const struct of_device_id tegra_xusb_of_match[] = {
2391         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2392         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2393         { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2394         { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2395         { },
2396 };
2397 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2398
2399 static struct platform_driver tegra_xusb_driver = {
2400         .probe = tegra_xusb_probe,
2401         .remove = tegra_xusb_remove,
2402         .driver = {
2403                 .name = "tegra-xusb",
2404                 .pm = &tegra_xusb_pm_ops,
2405                 .of_match_table = tegra_xusb_of_match,
2406         },
2407 };
2408
2409 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2410 {
2411         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2412
2413         xhci->quirks |= XHCI_PLAT;
2414         if (tegra && tegra->soc->lpm_support)
2415                 xhci->quirks |= XHCI_LPM_SUPPORT;
2416 }
2417
2418 static int tegra_xhci_setup(struct usb_hcd *hcd)
2419 {
2420         return xhci_gen_setup(hcd, tegra_xhci_quirks);
2421 }
2422
2423 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2424         .reset = tegra_xhci_setup,
2425 };
2426
2427 static int __init tegra_xusb_init(void)
2428 {
2429         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2430
2431         return platform_driver_register(&tegra_xusb_driver);
2432 }
2433 module_init(tegra_xusb_init);
2434
2435 static void __exit tegra_xusb_exit(void)
2436 {
2437         platform_driver_unregister(&tegra_xusb_driver);
2438 }
2439 module_exit(tegra_xusb_exit);
2440
2441 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2442 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2443 MODULE_LICENSE("GPL v2");