1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
62 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
63 u32 field1, u32 field2,
64 u32 field3, u32 field4, bool command_must_succeed);
67 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
70 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
73 unsigned long segment_offset;
75 if (!seg || !trb || trb < seg->trbs)
78 segment_offset = trb - seg->trbs;
79 if (segment_offset >= TRBS_PER_SEGMENT)
81 return seg->dma + (segment_offset * sizeof(*trb));
84 static bool trb_is_noop(union xhci_trb *trb)
86 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
89 static bool trb_is_link(union xhci_trb *trb)
91 return TRB_TYPE_LINK_LE32(trb->link.control);
94 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
96 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
99 static bool last_trb_on_ring(struct xhci_ring *ring,
100 struct xhci_segment *seg, union xhci_trb *trb)
102 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
105 static bool link_trb_toggles_cycle(union xhci_trb *trb)
107 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
110 static bool last_td_in_urb(struct xhci_td *td)
112 struct urb_priv *urb_priv = td->urb->hcpriv;
114 return urb_priv->num_tds_done == urb_priv->num_tds;
117 static void inc_td_cnt(struct urb *urb)
119 struct urb_priv *urb_priv = urb->hcpriv;
121 urb_priv->num_tds_done++;
124 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
126 if (trb_is_link(trb)) {
127 /* unchain chained link TRBs */
128 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
130 trb->generic.field[0] = 0;
131 trb->generic.field[1] = 0;
132 trb->generic.field[2] = 0;
133 /* Preserve only the cycle bit of this TRB */
134 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
135 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
139 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
140 * TRB is in a new segment. This does not skip over link TRBs, and it does not
141 * effect the ring dequeue or enqueue pointers.
143 static void next_trb(struct xhci_hcd *xhci,
144 struct xhci_ring *ring,
145 struct xhci_segment **seg,
146 union xhci_trb **trb)
148 if (trb_is_link(*trb)) {
150 *trb = ((*seg)->trbs);
157 * See Cycle bit rules. SW is the consumer for the event ring only.
159 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
161 unsigned int link_trb_count = 0;
163 /* event ring doesn't have link trbs, check for last trb */
164 if (ring->type == TYPE_EVENT) {
165 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
169 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
170 ring->cycle_state ^= 1;
171 ring->deq_seg = ring->deq_seg->next;
172 ring->dequeue = ring->deq_seg->trbs;
176 /* All other rings have link trbs */
177 if (!trb_is_link(ring->dequeue)) {
178 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
179 xhci_warn(xhci, "Missing link TRB at end of segment\n");
182 ring->num_trbs_free++;
186 while (trb_is_link(ring->dequeue)) {
187 ring->deq_seg = ring->deq_seg->next;
188 ring->dequeue = ring->deq_seg->trbs;
190 if (link_trb_count++ > ring->num_segs) {
191 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
196 trace_xhci_inc_deq(ring);
202 * See Cycle bit rules. SW is the consumer for the event ring only.
204 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
205 * chain bit is set), then set the chain bit in all the following link TRBs.
206 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
207 * have their chain bit cleared (so that each Link TRB is a separate TD).
209 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
210 * set, but other sections talk about dealing with the chain bit set. This was
211 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
212 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
214 * @more_trbs_coming: Will you enqueue more TRBs before calling
215 * prepare_transfer()?
217 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
218 bool more_trbs_coming)
221 union xhci_trb *next;
222 unsigned int link_trb_count = 0;
224 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
225 /* If this is not event ring, there is one less usable TRB */
226 if (!trb_is_link(ring->enqueue))
227 ring->num_trbs_free--;
229 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
230 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
234 next = ++(ring->enqueue);
236 /* Update the dequeue pointer further if that was a link TRB */
237 while (trb_is_link(next)) {
240 * If the caller doesn't plan on enqueueing more TDs before
241 * ringing the doorbell, then we don't want to give the link TRB
242 * to the hardware just yet. We'll give the link TRB back in
243 * prepare_ring() just before we enqueue the TD at the top of
246 if (!chain && !more_trbs_coming)
249 /* If we're not dealing with 0.95 hardware or isoc rings on
250 * AMD 0.96 host, carry over the chain bit of the previous TRB
251 * (which may mean the chain bit is cleared).
253 if (!(ring->type == TYPE_ISOC &&
254 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
255 !xhci_link_trb_quirk(xhci)) {
256 next->link.control &= cpu_to_le32(~TRB_CHAIN);
257 next->link.control |= cpu_to_le32(chain);
259 /* Give this link TRB to the hardware */
261 next->link.control ^= cpu_to_le32(TRB_CYCLE);
263 /* Toggle the cycle bit after the last ring segment. */
264 if (link_trb_toggles_cycle(next))
265 ring->cycle_state ^= 1;
267 ring->enq_seg = ring->enq_seg->next;
268 ring->enqueue = ring->enq_seg->trbs;
269 next = ring->enqueue;
271 if (link_trb_count++ > ring->num_segs) {
272 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
277 trace_xhci_inc_enq(ring);
281 * Check to see if there's room to enqueue num_trbs on the ring and make sure
282 * enqueue pointer will not advance into dequeue segment. See rules above.
284 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
285 unsigned int num_trbs)
287 int num_trbs_in_deq_seg;
289 if (ring->num_trbs_free < num_trbs)
292 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
293 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
294 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
301 /* Ring the host controller doorbell after placing a command on the ring */
302 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
304 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
307 xhci_dbg(xhci, "// Ding dong!\n");
309 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
311 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
312 /* Flush PCI posted writes */
313 readl(&xhci->dba->doorbell[0]);
316 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
318 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
321 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
323 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
328 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
329 * If there are other commands waiting then restart the ring and kick the timer.
330 * This must be called with command ring stopped and xhci->lock held.
332 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
333 struct xhci_command *cur_cmd)
335 struct xhci_command *i_cmd;
337 /* Turn all aborted commands in list to no-ops, then restart */
338 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
340 if (i_cmd->status != COMP_COMMAND_ABORTED)
343 i_cmd->status = COMP_COMMAND_RING_STOPPED;
345 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
348 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
351 * caller waiting for completion is called when command
352 * completion event is received for these no-op commands
356 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
358 /* ring command ring doorbell to restart the command ring */
359 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
360 !(xhci->xhc_state & XHCI_STATE_DYING)) {
361 xhci->current_cmd = cur_cmd;
362 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
363 xhci_ring_cmd_db(xhci);
367 /* Must be called with xhci->lock held, releases and aquires lock back */
368 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
373 xhci_dbg(xhci, "Abort command ring\n");
375 reinit_completion(&xhci->cmd_ring_stop_completion);
377 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
378 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
379 &xhci->op_regs->cmd_ring);
381 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
382 * completion of the Command Abort operation. If CRR is not negated in 5
383 * seconds then driver handles it as if host died (-ENODEV).
384 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
385 * and try to recover a -ETIMEDOUT with a host controller reset.
387 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
388 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
390 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
396 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
397 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
398 * but the completion event in never sent. Wait 2 secs (arbitrary
399 * number) to handle those cases after negation of CMD_RING_RUNNING.
401 spin_unlock_irqrestore(&xhci->lock, flags);
402 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
403 msecs_to_jiffies(2000));
404 spin_lock_irqsave(&xhci->lock, flags);
406 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
407 xhci_cleanup_command_queue(xhci);
409 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
414 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
415 unsigned int slot_id,
416 unsigned int ep_index,
417 unsigned int stream_id)
419 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
420 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
421 unsigned int ep_state = ep->ep_state;
423 /* Don't ring the doorbell for this endpoint if there are pending
424 * cancellations because we don't want to interrupt processing.
425 * We don't want to restart any stream rings if there's a set dequeue
426 * pointer command pending because the device can choose to start any
427 * stream once the endpoint is on the HW schedule.
429 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
430 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
433 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
435 writel(DB_VALUE(ep_index, stream_id), db_addr);
436 /* flush the write */
440 /* Ring the doorbell for any rings with pending URBs */
441 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
442 unsigned int slot_id,
443 unsigned int ep_index)
445 unsigned int stream_id;
446 struct xhci_virt_ep *ep;
448 ep = &xhci->devs[slot_id]->eps[ep_index];
450 /* A ring has pending URBs if its TD list is not empty */
451 if (!(ep->ep_state & EP_HAS_STREAMS)) {
452 if (ep->ring && !(list_empty(&ep->ring->td_list)))
453 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
457 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
459 struct xhci_stream_info *stream_info = ep->stream_info;
460 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
461 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
466 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
467 unsigned int slot_id,
468 unsigned int ep_index)
470 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
473 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
474 unsigned int slot_id,
475 unsigned int ep_index)
477 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
478 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
481 if (ep_index >= EP_CTX_PER_DEV) {
482 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
485 if (!xhci->devs[slot_id]) {
486 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
490 return &xhci->devs[slot_id]->eps[ep_index];
493 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
494 struct xhci_virt_ep *ep,
495 unsigned int stream_id)
497 /* common case, no streams */
498 if (!(ep->ep_state & EP_HAS_STREAMS))
501 if (!ep->stream_info)
504 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
505 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
506 stream_id, ep->vdev->slot_id, ep->ep_index);
510 return ep->stream_info->stream_rings[stream_id];
513 /* Get the right ring for the given slot_id, ep_index and stream_id.
514 * If the endpoint supports streams, boundary check the URB's stream ID.
515 * If the endpoint doesn't support streams, return the singular endpoint ring.
517 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
518 unsigned int slot_id, unsigned int ep_index,
519 unsigned int stream_id)
521 struct xhci_virt_ep *ep;
523 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
527 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
532 * Get the hw dequeue pointer xHC stopped on, either directly from the
533 * endpoint context, or if streams are in use from the stream context.
534 * The returned hw_dequeue contains the lowest four bits with cycle state
535 * and possbile stream context type.
537 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
538 unsigned int ep_index, unsigned int stream_id)
540 struct xhci_ep_ctx *ep_ctx;
541 struct xhci_stream_ctx *st_ctx;
542 struct xhci_virt_ep *ep;
544 ep = &vdev->eps[ep_index];
546 if (ep->ep_state & EP_HAS_STREAMS) {
547 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
548 return le64_to_cpu(st_ctx->stream_ring);
550 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
551 return le64_to_cpu(ep_ctx->deq);
555 * Move the xHC's endpoint ring dequeue pointer past cur_td.
556 * Record the new state of the xHC's endpoint ring dequeue segment,
557 * dequeue pointer, stream id, and new consumer cycle state in state.
558 * Update our internal representation of the ring's dequeue pointer.
560 * We do this in three jumps:
561 * - First we update our new ring state to be the same as when the xHC stopped.
562 * - Then we traverse the ring to find the segment that contains
563 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
564 * any link TRBs with the toggle cycle bit set.
565 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
566 * if we've moved it past a link TRB with the toggle cycle bit set.
568 * Some of the uses of xhci_generic_trb are grotty, but if they're done
569 * with correct __le32 accesses they should work fine. Only users of this are
572 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
573 unsigned int slot_id, unsigned int ep_index,
574 unsigned int stream_id, struct xhci_td *cur_td,
575 struct xhci_dequeue_state *state)
577 struct xhci_virt_device *dev = xhci->devs[slot_id];
578 struct xhci_virt_ep *ep = &dev->eps[ep_index];
579 struct xhci_ring *ep_ring;
580 struct xhci_segment *new_seg;
581 union xhci_trb *new_deq;
584 bool cycle_found = false;
585 bool td_last_trb_found = false;
587 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
588 ep_index, stream_id);
590 xhci_warn(xhci, "WARN can't find new dequeue state "
591 "for invalid stream ID %u.\n",
596 * A cancelled TD can complete with a stall if HW cached the trb.
597 * In this case driver can't find cur_td, but if the ring is empty we
598 * can move the dequeue pointer to the current enqueue position.
601 if (list_empty(&ep_ring->td_list)) {
602 state->new_deq_seg = ep_ring->enq_seg;
603 state->new_deq_ptr = ep_ring->enqueue;
604 state->new_cycle_state = ep_ring->cycle_state;
607 xhci_warn(xhci, "Can't find new dequeue state, missing cur_td\n");
612 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
613 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
614 "Finding endpoint context");
616 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
617 new_seg = ep_ring->deq_seg;
618 new_deq = ep_ring->dequeue;
619 state->new_cycle_state = hw_dequeue & 0x1;
620 state->stream_id = stream_id;
623 * We want to find the pointer, segment and cycle state of the new trb
624 * (the one after current TD's last_trb). We know the cycle state at
625 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
629 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
630 == (dma_addr_t)(hw_dequeue & ~0xf)) {
632 if (td_last_trb_found)
635 if (new_deq == cur_td->last_trb)
636 td_last_trb_found = true;
638 if (cycle_found && trb_is_link(new_deq) &&
639 link_trb_toggles_cycle(new_deq))
640 state->new_cycle_state ^= 0x1;
642 next_trb(xhci, ep_ring, &new_seg, &new_deq);
644 /* Search wrapped around, bail out */
645 if (new_deq == ep->ring->dequeue) {
646 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
647 state->new_deq_seg = NULL;
648 state->new_deq_ptr = NULL;
652 } while (!cycle_found || !td_last_trb_found);
654 state->new_deq_seg = new_seg;
655 state->new_deq_ptr = new_deq;
658 /* Don't update the ring cycle state for the producer (us). */
659 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
660 "Cycle state = 0x%x", state->new_cycle_state);
662 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
663 "New dequeue segment = %p (virtual)",
665 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
666 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
667 "New dequeue pointer = 0x%llx (DMA)",
668 (unsigned long long) addr);
671 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
672 unsigned int slot_id, unsigned int ep_index,
673 unsigned int stream_id, struct xhci_td *td)
675 struct xhci_virt_device *dev = xhci->devs[slot_id];
676 struct xhci_virt_ep *ep = &dev->eps[ep_index];
677 struct xhci_ring *ep_ring;
678 struct xhci_command *cmd;
679 struct xhci_segment *new_seg;
680 union xhci_trb *new_deq;
684 bool cycle_found = false;
685 bool td_last_trb_found = false;
689 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
690 ep_index, stream_id);
692 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
697 * A cancelled TD can complete with a stall if HW cached the trb.
698 * In this case driver can't find td, but if the ring is empty we
699 * can move the dequeue pointer to the current enqueue position.
700 * We shouldn't hit this anymore as cached cancelled TRBs are given back
701 * after clearing the cache, but be on the safe side and keep it anyway
704 if (list_empty(&ep_ring->td_list)) {
705 new_seg = ep_ring->enq_seg;
706 new_deq = ep_ring->enqueue;
707 new_cycle = ep_ring->cycle_state;
708 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
711 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
716 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
717 new_seg = ep_ring->deq_seg;
718 new_deq = ep_ring->dequeue;
719 new_cycle = hw_dequeue & 0x1;
722 * We want to find the pointer, segment and cycle state of the new trb
723 * (the one after current TD's last_trb). We know the cycle state at
724 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
728 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
729 == (dma_addr_t)(hw_dequeue & ~0xf)) {
731 if (td_last_trb_found)
734 if (new_deq == td->last_trb)
735 td_last_trb_found = true;
737 if (cycle_found && trb_is_link(new_deq) &&
738 link_trb_toggles_cycle(new_deq))
741 next_trb(xhci, ep_ring, &new_seg, &new_deq);
743 /* Search wrapped around, bail out */
744 if (new_deq == ep->ring->dequeue) {
745 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
749 } while (!cycle_found || !td_last_trb_found);
753 /* Don't update the ring cycle state for the producer (us). */
754 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
756 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
757 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
761 if ((ep->ep_state & SET_DEQ_PENDING)) {
762 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
767 /* This function gets called from contexts where it cannot sleep */
768 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
770 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
775 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
776 ret = queue_command(xhci, cmd,
777 lower_32_bits(addr) | trb_sct | new_cycle,
779 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
780 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
782 xhci_free_command(xhci, cmd);
785 ep->queued_deq_seg = new_seg;
786 ep->queued_deq_ptr = new_deq;
788 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
789 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
791 /* Stop the TD queueing code from ringing the doorbell until
792 * this command completes. The HC won't set the dequeue pointer
793 * if the ring is running, and ringing the doorbell starts the
796 ep->ep_state |= SET_DEQ_PENDING;
797 xhci_ring_cmd_db(xhci);
801 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
802 * (The last TRB actually points to the ring enqueue pointer, which is not part
803 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
805 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
806 struct xhci_td *td, bool flip_cycle)
808 struct xhci_segment *seg = td->start_seg;
809 union xhci_trb *trb = td->first_trb;
812 trb_to_noop(trb, TRB_TR_NOOP);
814 /* flip cycle if asked to */
815 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
816 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
818 if (trb == td->last_trb)
821 next_trb(xhci, ep_ring, &seg, &trb);
825 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
826 struct xhci_virt_ep *ep)
828 ep->ep_state &= ~EP_STOP_CMD_PENDING;
829 /* Can't del_timer_sync in interrupt */
830 del_timer(&ep->stop_cmd_timer);
834 * Must be called with xhci->lock held in interrupt context,
835 * releases and re-acquires xhci->lock
837 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
838 struct xhci_td *cur_td, int status)
840 struct urb *urb = cur_td->urb;
841 struct urb_priv *urb_priv = urb->hcpriv;
842 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
844 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
845 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
846 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
847 if (xhci->quirks & XHCI_AMD_PLL_FIX)
848 usb_amd_quirk_pll_enable();
851 xhci_urb_free_priv(urb_priv);
852 usb_hcd_unlink_urb_from_ep(hcd, urb);
853 trace_xhci_urb_giveback(urb);
854 usb_hcd_giveback_urb(hcd, urb, status);
857 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
858 struct xhci_ring *ring, struct xhci_td *td)
860 struct device *dev = xhci_to_hcd(xhci)->self.controller;
861 struct xhci_segment *seg = td->bounce_seg;
862 struct urb *urb = td->urb;
865 if (!ring || !seg || !urb)
868 if (usb_urb_dir_out(urb)) {
869 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
874 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
876 /* for in tranfers we need to copy the data from bounce to sg */
877 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
878 seg->bounce_len, seg->bounce_offs);
879 if (len != seg->bounce_len)
880 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
881 len, seg->bounce_len);
883 seg->bounce_offs = 0;
886 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
887 struct xhci_ring *ep_ring, int status)
889 struct urb *urb = NULL;
891 /* Clean up the endpoint's TD list */
894 /* if a bounce buffer was used to align this td then unmap it */
895 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
897 /* Do one last check of the actual transfer length.
898 * If the host controller said we transferred more data than the buffer
899 * length, urb->actual_length will be a very big number (since it's
900 * unsigned). Play it safe and say we didn't transfer anything.
902 if (urb->actual_length > urb->transfer_buffer_length) {
903 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
904 urb->transfer_buffer_length, urb->actual_length);
905 urb->actual_length = 0;
908 /* TD might be removed from td_list if we are giving back a cancelled URB */
909 if (!list_empty(&td->td_list))
910 list_del_init(&td->td_list);
911 /* Giving back a cancelled URB, or if a slated TD completed anyway */
912 if (!list_empty(&td->cancelled_td_list))
913 list_del_init(&td->cancelled_td_list);
916 /* Giveback the urb when all the tds are completed */
917 if (last_td_in_urb(td)) {
918 if ((urb->actual_length != urb->transfer_buffer_length &&
919 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
920 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
921 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
922 urb, urb->actual_length,
923 urb->transfer_buffer_length, status);
925 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
926 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
928 xhci_giveback_urb_in_irq(xhci, td, status);
935 /* Complete the cancelled URBs we unlinked from td_list. */
936 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
938 struct xhci_ring *ring;
939 struct xhci_td *td, *tmp_td;
941 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
945 * Doesn't matter what we pass for status, since the core will
946 * just overwrite it (because the URB has been unlinked).
948 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
950 if (td->cancel_status == TD_CLEARED)
951 xhci_td_cleanup(ep->xhci, td, ring, 0);
953 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
958 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
959 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
961 struct xhci_command *command;
964 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
970 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
973 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
974 slot_id, ep_index, ret);
978 static void xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
979 struct xhci_virt_ep *ep, unsigned int stream_id,
981 enum xhci_ep_reset_type reset_type)
983 unsigned int slot_id = ep->vdev->slot_id;
987 * Avoid resetting endpoint if link is inactive. Can cause host hang.
988 * Device will be reset soon to recover the link so don't do anything
990 if (ep->vdev->flags & VDEV_PORT_ERROR)
993 ep->ep_state |= EP_HALTED;
995 /* add td to cancelled list and let reset ep handler take care of it */
996 if (reset_type == EP_HARD_RESET) {
997 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
998 if (td && list_empty(&td->cancelled_td_list)) {
999 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1000 td->cancel_status = TD_HALTED;
1004 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
1008 xhci_ring_cmd_db(xhci);
1012 * Fix up the ep ring first, so HW stops executing cancelled TDs.
1013 * We have the xHCI lock, so nothing can modify this list until we drop it.
1014 * We're also in the event handler, so we can't get re-interrupted if another
1015 * Stop Endpoint command completes.
1017 * only call this when ring is not in a running state
1020 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
1022 struct xhci_hcd *xhci;
1023 struct xhci_td *td = NULL;
1024 struct xhci_td *tmp_td = NULL;
1025 struct xhci_td *cached_td = NULL;
1026 struct xhci_ring *ring;
1028 unsigned int slot_id = ep->vdev->slot_id;
1033 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1034 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1035 "Removing canceled TD starting at 0x%llx (dma).",
1036 (unsigned long long)xhci_trb_virt_to_dma(
1037 td->start_seg, td->first_trb));
1038 list_del_init(&td->td_list);
1039 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1041 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1042 td->urb, td->urb->stream_id);
1046 * If ring stopped on the TD we need to cancel, then we have to
1047 * move the xHC endpoint ring dequeue pointer past this TD.
1049 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1050 td->urb->stream_id);
1053 if (trb_in_td(xhci, td->start_seg, td->first_trb,
1054 td->last_trb, hw_deq, false)) {
1055 switch (td->cancel_status) {
1056 case TD_CLEARED: /* TD is already no-op */
1057 case TD_CLEARING_CACHE: /* set TR deq command already queued */
1059 case TD_DIRTY: /* TD is cached, clear it */
1061 /* FIXME stream case, several stopped rings */
1066 td_to_noop(xhci, ring, td, false);
1067 td->cancel_status = TD_CLEARED;
1071 cached_td->cancel_status = TD_CLEARING_CACHE;
1073 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1074 cached_td->urb->stream_id,
1076 /* Failed to move past cached td, try just setting it noop */
1078 td_to_noop(xhci, ring, cached_td, false);
1079 cached_td->cancel_status = TD_CLEARED;
1087 * Returns the TD the endpoint ring halted on.
1088 * Only call for non-running rings without streams.
1090 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1095 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1096 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1098 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1099 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1100 td->last_trb, hw_deq, false))
1107 * When we get a command completion for a Stop Endpoint Command, we need to
1108 * unlink any cancelled TDs from the ring. There are two ways to do that:
1110 * 1. If the HW was in the middle of processing the TD that needs to be
1111 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1112 * in the TD with a Set Dequeue Pointer Command.
1113 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1114 * bit cleared) so that the HW will skip over them.
1116 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1117 union xhci_trb *trb, u32 comp_code)
1119 unsigned int ep_index;
1120 struct xhci_virt_ep *ep;
1121 struct xhci_ep_ctx *ep_ctx;
1122 struct xhci_td *td = NULL;
1123 enum xhci_ep_reset_type reset_type;
1124 struct xhci_command *command;
1126 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1127 if (!xhci->devs[slot_id])
1128 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1133 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1134 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1138 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1140 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1142 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1144 * If stop endpoint command raced with a halting endpoint we need to
1145 * reset the host side endpoint first.
1146 * If the TD we halted on isn't cancelled the TD should be given back
1147 * with a proper error code, and the ring dequeue moved past the TD.
1148 * If streams case we can't find hw_deq, or the TD we halted on so do a
1151 * Proper error code is unknown here, it would be -EPIPE if device side
1152 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1153 * We use -EPROTO, if device is stalled it should return a stall error on
1154 * next transfer, which then will return -EPIPE, and device side stall is
1155 * noted and cleared by class driver.
1157 switch (GET_EP_CTX_STATE(ep_ctx)) {
1158 case EP_STATE_HALTED:
1159 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1160 if (ep->ep_state & EP_HAS_STREAMS) {
1161 reset_type = EP_SOFT_RESET;
1163 reset_type = EP_HARD_RESET;
1164 td = find_halted_td(ep);
1166 td->status = -EPROTO;
1168 /* reset ep, reset handler cleans up cancelled tds */
1169 xhci_handle_halted_endpoint(xhci, ep, 0, td, reset_type);
1170 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1172 case EP_STATE_RUNNING:
1173 /* Race, HW handled stop ep cmd before ep was running */
1174 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1176 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1178 mod_timer(&ep->stop_cmd_timer,
1179 jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ);
1180 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1181 xhci_ring_cmd_db(xhci);
1188 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1189 xhci_invalidate_cancelled_tds(ep);
1190 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1192 /* Otherwise ring the doorbell(s) to restart queued transfers */
1193 xhci_giveback_invalidated_tds(ep);
1194 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1197 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1199 struct xhci_td *cur_td;
1200 struct xhci_td *tmp;
1202 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1203 list_del_init(&cur_td->td_list);
1205 if (!list_empty(&cur_td->cancelled_td_list))
1206 list_del_init(&cur_td->cancelled_td_list);
1208 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1210 inc_td_cnt(cur_td->urb);
1211 if (last_td_in_urb(cur_td))
1212 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1216 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1217 int slot_id, int ep_index)
1219 struct xhci_td *cur_td;
1220 struct xhci_td *tmp;
1221 struct xhci_virt_ep *ep;
1222 struct xhci_ring *ring;
1224 ep = &xhci->devs[slot_id]->eps[ep_index];
1225 if ((ep->ep_state & EP_HAS_STREAMS) ||
1226 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1229 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1231 ring = ep->stream_info->stream_rings[stream_id];
1235 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1236 "Killing URBs for slot ID %u, ep index %u, stream %u",
1237 slot_id, ep_index, stream_id);
1238 xhci_kill_ring_urbs(xhci, ring);
1244 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1245 "Killing URBs for slot ID %u, ep index %u",
1247 xhci_kill_ring_urbs(xhci, ring);
1250 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1251 cancelled_td_list) {
1252 list_del_init(&cur_td->cancelled_td_list);
1253 inc_td_cnt(cur_td->urb);
1255 if (last_td_in_urb(cur_td))
1256 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1261 * host controller died, register read returns 0xffffffff
1262 * Complete pending commands, mark them ABORTED.
1263 * URBs need to be given back as usb core might be waiting with device locks
1264 * held for the URBs to finish during device disconnect, blocking host remove.
1266 * Call with xhci->lock held.
1267 * lock is relased and re-acquired while giving back urb.
1269 void xhci_hc_died(struct xhci_hcd *xhci)
1273 if (xhci->xhc_state & XHCI_STATE_DYING)
1276 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1277 xhci->xhc_state |= XHCI_STATE_DYING;
1279 xhci_cleanup_command_queue(xhci);
1281 /* return any pending urbs, remove may be waiting for them */
1282 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1285 for (j = 0; j < 31; j++)
1286 xhci_kill_endpoint_urbs(xhci, i, j);
1289 /* inform usb core hc died if PCI remove isn't already handling it */
1290 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1291 usb_hc_died(xhci_to_hcd(xhci));
1294 /* Watchdog timer function for when a stop endpoint command fails to complete.
1295 * In this case, we assume the host controller is broken or dying or dead. The
1296 * host may still be completing some other events, so we have to be careful to
1297 * let the event ring handler and the URB dequeueing/enqueueing functions know
1298 * through xhci->state.
1300 * The timer may also fire if the host takes a very long time to respond to the
1301 * command, and the stop endpoint command completion handler cannot delete the
1302 * timer before the timer function is called. Another endpoint cancellation may
1303 * sneak in before the timer function can grab the lock, and that may queue
1304 * another stop endpoint command and add the timer back. So we cannot use a
1305 * simple flag to say whether there is a pending stop endpoint command for a
1306 * particular endpoint.
1308 * Instead we use a combination of that flag and checking if a new timer is
1311 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
1313 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
1314 struct xhci_hcd *xhci = ep->xhci;
1315 unsigned long flags;
1318 spin_lock_irqsave(&xhci->lock, flags);
1320 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1321 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1322 timer_pending(&ep->stop_cmd_timer)) {
1323 spin_unlock_irqrestore(&xhci->lock, flags);
1324 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1327 usbsts = readl(&xhci->op_regs->status);
1329 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1330 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(usbsts));
1332 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1337 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1338 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1339 * and try to recover a -ETIMEDOUT with a host controller reset
1343 spin_unlock_irqrestore(&xhci->lock, flags);
1344 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1345 "xHCI host controller is dead.");
1348 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1349 struct xhci_virt_device *dev,
1350 struct xhci_ring *ep_ring,
1351 unsigned int ep_index)
1353 union xhci_trb *dequeue_temp;
1354 int num_trbs_free_temp;
1355 bool revert = false;
1357 num_trbs_free_temp = ep_ring->num_trbs_free;
1358 dequeue_temp = ep_ring->dequeue;
1360 /* If we get two back-to-back stalls, and the first stalled transfer
1361 * ends just before a link TRB, the dequeue pointer will be left on
1362 * the link TRB by the code in the while loop. So we have to update
1363 * the dequeue pointer one segment further, or we'll jump off
1364 * the segment into la-la-land.
1366 if (trb_is_link(ep_ring->dequeue)) {
1367 ep_ring->deq_seg = ep_ring->deq_seg->next;
1368 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1371 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1372 /* We have more usable TRBs */
1373 ep_ring->num_trbs_free++;
1375 if (trb_is_link(ep_ring->dequeue)) {
1376 if (ep_ring->dequeue ==
1377 dev->eps[ep_index].queued_deq_ptr)
1379 ep_ring->deq_seg = ep_ring->deq_seg->next;
1380 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1382 if (ep_ring->dequeue == dequeue_temp) {
1389 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1390 ep_ring->num_trbs_free = num_trbs_free_temp;
1395 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1396 * we need to clear the set deq pending flag in the endpoint ring state, so that
1397 * the TD queueing code can ring the doorbell again. We also need to ring the
1398 * endpoint doorbell to restart the ring, but only if there aren't more
1399 * cancellations pending.
1401 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1402 union xhci_trb *trb, u32 cmd_comp_code)
1404 unsigned int ep_index;
1405 unsigned int stream_id;
1406 struct xhci_ring *ep_ring;
1407 struct xhci_virt_ep *ep;
1408 struct xhci_ep_ctx *ep_ctx;
1409 struct xhci_slot_ctx *slot_ctx;
1410 struct xhci_td *td, *tmp_td;
1412 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1413 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1414 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1418 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1420 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1422 /* XXX: Harmless??? */
1426 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1427 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1428 trace_xhci_handle_cmd_set_deq(slot_ctx);
1429 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1431 if (cmd_comp_code != COMP_SUCCESS) {
1432 unsigned int ep_state;
1433 unsigned int slot_state;
1435 switch (cmd_comp_code) {
1436 case COMP_TRB_ERROR:
1437 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1439 case COMP_CONTEXT_STATE_ERROR:
1440 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1441 ep_state = GET_EP_CTX_STATE(ep_ctx);
1442 slot_state = le32_to_cpu(slot_ctx->dev_state);
1443 slot_state = GET_SLOT_STATE(slot_state);
1444 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1445 "Slot state = %u, EP state = %u",
1446 slot_state, ep_state);
1448 case COMP_SLOT_NOT_ENABLED_ERROR:
1449 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1453 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1457 /* OK what do we do now? The endpoint state is hosed, and we
1458 * should never get to this point if the synchronization between
1459 * queueing, and endpoint state are correct. This might happen
1460 * if the device gets disconnected after we've finished
1461 * cancelling URBs, which might not be an error...
1465 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1466 if (ep->ep_state & EP_HAS_STREAMS) {
1467 struct xhci_stream_ctx *ctx =
1468 &ep->stream_info->stream_ctx_array[stream_id];
1469 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1471 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1473 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1474 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1475 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1476 ep->queued_deq_ptr) == deq) {
1477 /* Update the ring's dequeue segment and dequeue pointer
1478 * to reflect the new position.
1480 update_ring_for_set_deq_completion(xhci, ep->vdev,
1483 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1484 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1485 ep->queued_deq_seg, ep->queued_deq_ptr);
1488 /* HW cached TDs cleared from cache, give them back */
1489 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1490 cancelled_td_list) {
1491 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1492 if (td->cancel_status == TD_CLEARING_CACHE) {
1493 td->cancel_status = TD_CLEARED;
1494 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1498 ep->ep_state &= ~SET_DEQ_PENDING;
1499 ep->queued_deq_seg = NULL;
1500 ep->queued_deq_ptr = NULL;
1501 /* Restart any rings with pending URBs */
1502 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1505 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1506 union xhci_trb *trb, u32 cmd_comp_code)
1508 struct xhci_virt_ep *ep;
1509 struct xhci_ep_ctx *ep_ctx;
1510 unsigned int ep_index;
1512 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1513 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1517 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1518 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1520 /* This command will only fail if the endpoint wasn't halted,
1521 * but we don't care.
1523 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1524 "Ignoring reset ep completion code of %u", cmd_comp_code);
1526 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1527 xhci_invalidate_cancelled_tds(ep);
1529 if (xhci->quirks & XHCI_RESET_EP_QUIRK)
1530 xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw");
1531 /* Clear our internal halted state */
1532 ep->ep_state &= ~EP_HALTED;
1534 xhci_giveback_invalidated_tds(ep);
1536 /* if this was a soft reset, then restart */
1537 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1538 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1541 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1542 struct xhci_command *command, u32 cmd_comp_code)
1544 if (cmd_comp_code == COMP_SUCCESS)
1545 command->slot_id = slot_id;
1547 command->slot_id = 0;
1550 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1552 struct xhci_virt_device *virt_dev;
1553 struct xhci_slot_ctx *slot_ctx;
1555 virt_dev = xhci->devs[slot_id];
1559 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1560 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1562 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1563 /* Delete default control endpoint resources */
1564 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1565 xhci_free_virt_device(xhci, slot_id);
1568 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1571 struct xhci_virt_device *virt_dev;
1572 struct xhci_input_control_ctx *ctrl_ctx;
1573 struct xhci_ep_ctx *ep_ctx;
1574 unsigned int ep_index;
1575 unsigned int ep_state;
1576 u32 add_flags, drop_flags;
1579 * Configure endpoint commands can come from the USB core
1580 * configuration or alt setting changes, or because the HW
1581 * needed an extra configure endpoint command after a reset
1582 * endpoint command or streams were being configured.
1583 * If the command was for a halted endpoint, the xHCI driver
1584 * is not waiting on the configure endpoint command.
1586 virt_dev = xhci->devs[slot_id];
1589 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1591 xhci_warn(xhci, "Could not get input context, bad type.\n");
1595 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1596 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1597 /* Input ctx add_flags are the endpoint index plus one */
1598 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1600 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1601 trace_xhci_handle_cmd_config_ep(ep_ctx);
1603 /* A usb_set_interface() call directly after clearing a halted
1604 * condition may race on this quirky hardware. Not worth
1605 * worrying about, since this is prototype hardware. Not sure
1606 * if this will work for streams, but streams support was
1607 * untested on this prototype.
1609 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1610 ep_index != (unsigned int) -1 &&
1611 add_flags - SLOT_FLAG == drop_flags) {
1612 ep_state = virt_dev->eps[ep_index].ep_state;
1613 if (!(ep_state & EP_HALTED))
1615 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1616 "Completed config ep cmd - "
1617 "last ep index = %d, state = %d",
1618 ep_index, ep_state);
1619 /* Clear internal halted state and restart ring(s) */
1620 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1621 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1627 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1629 struct xhci_virt_device *vdev;
1630 struct xhci_slot_ctx *slot_ctx;
1632 vdev = xhci->devs[slot_id];
1635 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1636 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1639 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1641 struct xhci_virt_device *vdev;
1642 struct xhci_slot_ctx *slot_ctx;
1644 vdev = xhci->devs[slot_id];
1646 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1650 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1651 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1653 xhci_dbg(xhci, "Completed reset device command.\n");
1656 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1657 struct xhci_event_cmd *event)
1659 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1660 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1663 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1664 "NEC firmware version %2x.%02x",
1665 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1666 NEC_FW_MINOR(le32_to_cpu(event->status)));
1669 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1671 list_del(&cmd->cmd_list);
1673 if (cmd->completion) {
1674 cmd->status = status;
1675 complete(cmd->completion);
1681 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1683 struct xhci_command *cur_cmd, *tmp_cmd;
1684 xhci->current_cmd = NULL;
1685 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1686 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1689 void xhci_handle_command_timeout(struct work_struct *work)
1691 struct xhci_hcd *xhci;
1692 unsigned long flags;
1695 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1697 spin_lock_irqsave(&xhci->lock, flags);
1700 * If timeout work is pending, or current_cmd is NULL, it means we
1701 * raced with command completion. Command is handled so just return.
1703 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1704 spin_unlock_irqrestore(&xhci->lock, flags);
1707 /* mark this command to be cancelled */
1708 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1710 /* Make sure command ring is running before aborting it */
1711 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1712 if (hw_ring_state == ~(u64)0) {
1714 goto time_out_completed;
1717 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1718 (hw_ring_state & CMD_RING_RUNNING)) {
1719 /* Prevent new doorbell, and start command abort */
1720 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1721 xhci_dbg(xhci, "Command timeout\n");
1722 xhci_abort_cmd_ring(xhci, flags);
1723 goto time_out_completed;
1726 /* host removed. Bail out */
1727 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1728 xhci_dbg(xhci, "host removed, ring start fail?\n");
1729 xhci_cleanup_command_queue(xhci);
1731 goto time_out_completed;
1734 /* command timeout on stopped ring, ring can't be aborted */
1735 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1736 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1739 spin_unlock_irqrestore(&xhci->lock, flags);
1743 static void handle_cmd_completion(struct xhci_hcd *xhci,
1744 struct xhci_event_cmd *event)
1746 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1748 dma_addr_t cmd_dequeue_dma;
1750 union xhci_trb *cmd_trb;
1751 struct xhci_command *cmd;
1754 if (slot_id >= MAX_HC_SLOTS) {
1755 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1759 cmd_dma = le64_to_cpu(event->cmd_trb);
1760 cmd_trb = xhci->cmd_ring->dequeue;
1762 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1764 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1767 * Check whether the completion event is for our internal kept
1770 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1772 "ERROR mismatched command completion event\n");
1776 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1778 cancel_delayed_work(&xhci->cmd_timer);
1780 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1782 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1783 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1784 complete_all(&xhci->cmd_ring_stop_completion);
1788 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1790 "Command completion event does not match command\n");
1795 * Host aborted the command ring, check if the current command was
1796 * supposed to be aborted, otherwise continue normally.
1797 * The command ring is stopped now, but the xHC will issue a Command
1798 * Ring Stopped event which will cause us to restart it.
1800 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1801 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1802 if (cmd->status == COMP_COMMAND_ABORTED) {
1803 if (xhci->current_cmd == cmd)
1804 xhci->current_cmd = NULL;
1809 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1811 case TRB_ENABLE_SLOT:
1812 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1814 case TRB_DISABLE_SLOT:
1815 xhci_handle_cmd_disable_slot(xhci, slot_id);
1818 if (!cmd->completion)
1819 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1821 case TRB_EVAL_CONTEXT:
1824 xhci_handle_cmd_addr_dev(xhci, slot_id);
1827 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1828 le32_to_cpu(cmd_trb->generic.field[3])));
1829 if (!cmd->completion)
1830 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1834 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1835 le32_to_cpu(cmd_trb->generic.field[3])));
1836 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1839 /* Is this an aborted command turned to NO-OP? */
1840 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1841 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1844 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1845 le32_to_cpu(cmd_trb->generic.field[3])));
1846 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1849 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1850 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1852 slot_id = TRB_TO_SLOT_ID(
1853 le32_to_cpu(cmd_trb->generic.field[3]));
1854 xhci_handle_cmd_reset_dev(xhci, slot_id);
1856 case TRB_NEC_GET_FW:
1857 xhci_handle_cmd_nec_get_fw(xhci, event);
1860 /* Skip over unknown commands on the event ring */
1861 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1865 /* restart timer if this wasn't the last command */
1866 if (!list_is_singular(&xhci->cmd_list)) {
1867 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1868 struct xhci_command, cmd_list);
1869 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1870 } else if (xhci->current_cmd == cmd) {
1871 xhci->current_cmd = NULL;
1875 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1877 inc_deq(xhci, xhci->cmd_ring);
1880 static void handle_vendor_event(struct xhci_hcd *xhci,
1881 union xhci_trb *event, u32 trb_type)
1883 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1884 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1885 handle_cmd_completion(xhci, &event->event_cmd);
1888 static void handle_device_notification(struct xhci_hcd *xhci,
1889 union xhci_trb *event)
1892 struct usb_device *udev;
1894 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1895 if (!xhci->devs[slot_id]) {
1896 xhci_warn(xhci, "Device Notification event for "
1897 "unused slot %u\n", slot_id);
1901 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1903 udev = xhci->devs[slot_id]->udev;
1904 if (udev && udev->parent)
1905 usb_wakeup_notification(udev->parent, udev->portnum);
1909 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1911 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1912 * If a connection to a USB 1 device is followed by another connection
1913 * to a USB 2 device.
1915 * Reset the PHY after the USB device is disconnected if device speed
1916 * is less than HCD_USB3.
1917 * Retry the reset sequence max of 4 times checking the PLL lock status.
1920 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1922 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1924 u32 retry_count = 4;
1927 /* Assert PHY reset */
1928 writel(0x6F, hcd->regs + 0x1048);
1930 /* De-assert the PHY reset */
1931 writel(0x7F, hcd->regs + 0x1048);
1933 pll_lock_check = readl(hcd->regs + 0x1070);
1934 } while (!(pll_lock_check & 0x1) && --retry_count);
1937 static void handle_port_status(struct xhci_hcd *xhci,
1938 union xhci_trb *event)
1940 struct usb_hcd *hcd;
1942 u32 portsc, cmd_reg;
1945 unsigned int hcd_portnum;
1946 struct xhci_bus_state *bus_state;
1947 bool bogus_port_status = false;
1948 struct xhci_port *port;
1950 /* Port status change events always have a successful completion code */
1951 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1953 "WARN: xHC returned failed port status event\n");
1955 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1956 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1958 if ((port_id <= 0) || (port_id > max_ports)) {
1959 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1961 inc_deq(xhci, xhci->event_ring);
1965 port = &xhci->hw_ports[port_id - 1];
1966 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1967 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1969 bogus_port_status = true;
1973 /* We might get interrupts after shared_hcd is removed */
1974 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1975 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1976 bogus_port_status = true;
1980 hcd = port->rhub->hcd;
1981 bus_state = &port->rhub->bus_state;
1982 hcd_portnum = port->hcd_portnum;
1983 portsc = readl(port->addr);
1985 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1986 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1988 trace_xhci_handle_port_status(hcd_portnum, portsc);
1990 if (hcd->state == HC_STATE_SUSPENDED) {
1991 xhci_dbg(xhci, "resume root hub\n");
1992 usb_hcd_resume_root_hub(hcd);
1995 if (hcd->speed >= HCD_USB3 &&
1996 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1997 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1998 if (slot_id && xhci->devs[slot_id])
1999 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
2002 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
2003 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
2005 cmd_reg = readl(&xhci->op_regs->command);
2006 if (!(cmd_reg & CMD_RUN)) {
2007 xhci_warn(xhci, "xHC is not running.\n");
2011 if (DEV_SUPERSPEED_ANY(portsc)) {
2012 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
2013 /* Set a flag to say the port signaled remote wakeup,
2014 * so we can tell the difference between the end of
2015 * device and host initiated resume.
2017 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
2018 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2019 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2020 xhci_set_link_state(xhci, port, XDEV_U0);
2021 /* Need to wait until the next link state change
2022 * indicates the device is actually in U0.
2024 bogus_port_status = true;
2026 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
2027 xhci_dbg(xhci, "resume HS port %d\n", port_id);
2028 bus_state->resume_done[hcd_portnum] = jiffies +
2029 msecs_to_jiffies(USB_RESUME_TIMEOUT);
2030 set_bit(hcd_portnum, &bus_state->resuming_ports);
2031 /* Do the rest in GetPortStatus after resume time delay.
2032 * Avoid polling roothub status before that so that a
2033 * usb device auto-resume latency around ~40ms.
2035 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2036 mod_timer(&hcd->rh_timer,
2037 bus_state->resume_done[hcd_portnum]);
2038 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2039 bogus_port_status = true;
2043 if ((portsc & PORT_PLC) &&
2044 DEV_SUPERSPEED_ANY(portsc) &&
2045 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
2046 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
2047 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
2048 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
2049 complete(&bus_state->u3exit_done[hcd_portnum]);
2050 /* We've just brought the device into U0/1/2 through either the
2051 * Resume state after a device remote wakeup, or through the
2052 * U3Exit state after a host-initiated resume. If it's a device
2053 * initiated remote wake, don't pass up the link state change,
2054 * so the roothub behavior is consistent with external
2055 * USB 3.0 hub behavior.
2057 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
2058 if (slot_id && xhci->devs[slot_id])
2059 xhci_ring_device(xhci, slot_id);
2060 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
2061 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2062 usb_wakeup_notification(hcd->self.root_hub,
2064 bogus_port_status = true;
2070 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2071 * RExit to a disconnect state). If so, let the the driver know it's
2072 * out of the RExit state.
2074 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
2075 test_and_clear_bit(hcd_portnum,
2076 &bus_state->rexit_ports)) {
2077 complete(&bus_state->rexit_done[hcd_portnum]);
2078 bogus_port_status = true;
2082 if (hcd->speed < HCD_USB3) {
2083 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2084 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2085 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2086 xhci_cavium_reset_phy_quirk(xhci);
2090 /* Update event ring dequeue pointer before dropping the lock */
2091 inc_deq(xhci, xhci->event_ring);
2093 /* Don't make the USB core poll the roothub if we got a bad port status
2094 * change event. Besides, at that point we can't tell which roothub
2095 * (USB 2.0 or USB 3.0) to kick.
2097 if (bogus_port_status)
2101 * xHCI port-status-change events occur when the "or" of all the
2102 * status-change bits in the portsc register changes from 0 to 1.
2103 * New status changes won't cause an event if any other change
2104 * bits are still set. When an event occurs, switch over to
2105 * polling to avoid losing status changes.
2107 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
2108 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2109 spin_unlock(&xhci->lock);
2110 /* Pass this up to the core */
2111 usb_hcd_poll_rh_status(hcd);
2112 spin_lock(&xhci->lock);
2116 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2117 * at end_trb, which may be in another segment. If the suspect DMA address is a
2118 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2121 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2122 struct xhci_segment *start_seg,
2123 union xhci_trb *start_trb,
2124 union xhci_trb *end_trb,
2125 dma_addr_t suspect_dma,
2128 dma_addr_t start_dma;
2129 dma_addr_t end_seg_dma;
2130 dma_addr_t end_trb_dma;
2131 struct xhci_segment *cur_seg;
2133 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2134 cur_seg = start_seg;
2139 /* We may get an event for a Link TRB in the middle of a TD */
2140 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2141 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2142 /* If the end TRB isn't in this segment, this is set to 0 */
2143 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2147 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2148 (unsigned long long)suspect_dma,
2149 (unsigned long long)start_dma,
2150 (unsigned long long)end_trb_dma,
2151 (unsigned long long)cur_seg->dma,
2152 (unsigned long long)end_seg_dma);
2154 if (end_trb_dma > 0) {
2155 /* The end TRB is in this segment, so suspect should be here */
2156 if (start_dma <= end_trb_dma) {
2157 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2160 /* Case for one segment with
2161 * a TD wrapped around to the top
2163 if ((suspect_dma >= start_dma &&
2164 suspect_dma <= end_seg_dma) ||
2165 (suspect_dma >= cur_seg->dma &&
2166 suspect_dma <= end_trb_dma))
2171 /* Might still be somewhere in this segment */
2172 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2175 cur_seg = cur_seg->next;
2176 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2177 } while (cur_seg != start_seg);
2182 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2183 struct xhci_virt_ep *ep)
2186 * As part of low/full-speed endpoint-halt processing
2187 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2189 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2190 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2191 !(ep->ep_state & EP_CLEARING_TT)) {
2192 ep->ep_state |= EP_CLEARING_TT;
2193 td->urb->ep->hcpriv = td->urb->dev;
2194 if (usb_hub_clear_tt_buffer(td->urb))
2195 ep->ep_state &= ~EP_CLEARING_TT;
2199 /* Check if an error has halted the endpoint ring. The class driver will
2200 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2201 * However, a babble and other errors also halt the endpoint ring, and the class
2202 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2203 * Ring Dequeue Pointer command manually.
2205 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2206 struct xhci_ep_ctx *ep_ctx,
2207 unsigned int trb_comp_code)
2209 /* TRB completion codes that may require a manual halt cleanup */
2210 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2211 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2212 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2213 /* The 0.95 spec says a babbling control endpoint
2214 * is not halted. The 0.96 spec says it is. Some HW
2215 * claims to be 0.95 compliant, but it halts the control
2216 * endpoint anyway. Check if a babble halted the
2219 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2225 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2227 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2228 /* Vendor defined "informational" completion code,
2229 * treat as not-an-error.
2231 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2233 xhci_dbg(xhci, "Treating code as success.\n");
2239 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2240 struct xhci_transfer_event *event, struct xhci_virt_ep *ep)
2242 struct xhci_ep_ctx *ep_ctx;
2243 struct xhci_ring *ep_ring;
2246 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2247 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2248 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2250 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2251 trb_comp_code == COMP_STOPPED ||
2252 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
2253 /* The Endpoint Stop Command completion will take care of any
2254 * stopped TDs. A stopped TD may be restarted, so don't update
2255 * the ring dequeue pointer or take this TD off any lists yet.
2259 if (trb_comp_code == COMP_STALL_ERROR ||
2260 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2263 * xhci internal endpoint state will go to a "halt" state for
2264 * any stall, including default control pipe protocol stall.
2265 * To clear the host side halt we need to issue a reset endpoint
2266 * command, followed by a set dequeue command to move past the
2268 * Class drivers clear the device side halt from a functional
2269 * stall later. Hub TT buffer should only be cleared for FS/LS
2270 * devices behind HS hubs for functional stalls.
2272 if ((ep->ep_index != 0) || (trb_comp_code != COMP_STALL_ERROR))
2273 xhci_clear_hub_tt_buffer(xhci, td, ep);
2275 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2278 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2280 /* Update ring dequeue pointer */
2281 ep_ring->dequeue = td->last_trb;
2282 ep_ring->deq_seg = td->last_trb_seg;
2283 ep_ring->num_trbs_free += td->num_trbs - 1;
2284 inc_deq(xhci, ep_ring);
2287 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2290 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2291 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2292 union xhci_trb *stop_trb)
2295 union xhci_trb *trb = ring->dequeue;
2296 struct xhci_segment *seg = ring->deq_seg;
2298 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2299 if (!trb_is_noop(trb) && !trb_is_link(trb))
2300 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2306 * Process control tds, update urb status and actual_length.
2308 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2309 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2310 struct xhci_virt_ep *ep)
2312 struct xhci_ep_ctx *ep_ctx;
2314 u32 remaining, requested;
2317 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2318 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2319 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2320 requested = td->urb->transfer_buffer_length;
2321 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2323 switch (trb_comp_code) {
2325 if (trb_type != TRB_STATUS) {
2326 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2327 (trb_type == TRB_DATA) ? "data" : "setup");
2328 td->status = -ESHUTDOWN;
2333 case COMP_SHORT_PACKET:
2336 case COMP_STOPPED_SHORT_PACKET:
2337 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2338 td->urb->actual_length = remaining;
2340 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2345 td->urb->actual_length = 0;
2349 td->urb->actual_length = requested - remaining;
2352 td->urb->actual_length = requested;
2355 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2359 case COMP_STOPPED_LENGTH_INVALID:
2362 if (!xhci_requires_manual_halt_cleanup(xhci,
2363 ep_ctx, trb_comp_code))
2365 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2366 trb_comp_code, ep->ep_index);
2368 case COMP_STALL_ERROR:
2369 /* Did we transfer part of the data (middle) phase? */
2370 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2371 td->urb->actual_length = requested - remaining;
2372 else if (!td->urb_length_set)
2373 td->urb->actual_length = 0;
2377 /* stopped at setup stage, no data transferred */
2378 if (trb_type == TRB_SETUP)
2382 * if on data stage then update the actual_length of the URB and flag it
2383 * as set, so it won't be overwritten in the event for the last TRB.
2385 if (trb_type == TRB_DATA ||
2386 trb_type == TRB_NORMAL) {
2387 td->urb_length_set = true;
2388 td->urb->actual_length = requested - remaining;
2389 xhci_dbg(xhci, "Waiting for status stage event\n");
2393 /* at status stage */
2394 if (!td->urb_length_set)
2395 td->urb->actual_length = requested;
2398 return finish_td(xhci, td, event, ep);
2402 * Process isochronous tds, update urb packet status and actual_length.
2404 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2405 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2406 struct xhci_virt_ep *ep)
2408 struct urb_priv *urb_priv;
2410 struct usb_iso_packet_descriptor *frame;
2412 bool sum_trbs_for_length = false;
2413 u32 remaining, requested, ep_trb_len;
2414 int short_framestatus;
2416 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2417 urb_priv = td->urb->hcpriv;
2418 idx = urb_priv->num_tds_done;
2419 frame = &td->urb->iso_frame_desc[idx];
2420 requested = frame->length;
2421 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2422 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2423 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2426 /* handle completion code */
2427 switch (trb_comp_code) {
2430 frame->status = short_framestatus;
2431 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2432 sum_trbs_for_length = true;
2437 case COMP_SHORT_PACKET:
2438 frame->status = short_framestatus;
2439 sum_trbs_for_length = true;
2441 case COMP_BANDWIDTH_OVERRUN_ERROR:
2442 frame->status = -ECOMM;
2444 case COMP_ISOCH_BUFFER_OVERRUN:
2445 case COMP_BABBLE_DETECTED_ERROR:
2446 frame->status = -EOVERFLOW;
2448 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2449 case COMP_STALL_ERROR:
2450 frame->status = -EPROTO;
2452 case COMP_USB_TRANSACTION_ERROR:
2453 frame->status = -EPROTO;
2454 if (ep_trb != td->last_trb)
2458 sum_trbs_for_length = true;
2460 case COMP_STOPPED_SHORT_PACKET:
2461 /* field normally containing residue now contains tranferred */
2462 frame->status = short_framestatus;
2463 requested = remaining;
2465 case COMP_STOPPED_LENGTH_INVALID:
2470 sum_trbs_for_length = true;
2475 if (sum_trbs_for_length)
2476 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2477 ep_trb_len - remaining;
2479 frame->actual_length = requested;
2481 td->urb->actual_length += frame->actual_length;
2483 return finish_td(xhci, td, event, ep);
2486 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2487 struct xhci_virt_ep *ep, int status)
2489 struct urb_priv *urb_priv;
2490 struct usb_iso_packet_descriptor *frame;
2493 urb_priv = td->urb->hcpriv;
2494 idx = urb_priv->num_tds_done;
2495 frame = &td->urb->iso_frame_desc[idx];
2497 /* The transfer is partly done. */
2498 frame->status = -EXDEV;
2500 /* calc actual length */
2501 frame->actual_length = 0;
2503 /* Update ring dequeue pointer */
2504 ep->ring->dequeue = td->last_trb;
2505 ep->ring->deq_seg = td->last_trb_seg;
2506 ep->ring->num_trbs_free += td->num_trbs - 1;
2507 inc_deq(xhci, ep->ring);
2509 return xhci_td_cleanup(xhci, td, ep->ring, status);
2513 * Process bulk and interrupt tds, update urb status and actual_length.
2515 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2516 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2517 struct xhci_virt_ep *ep)
2519 struct xhci_slot_ctx *slot_ctx;
2520 struct xhci_ring *ep_ring;
2522 u32 remaining, requested, ep_trb_len;
2524 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2525 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2526 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2527 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2528 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2529 requested = td->urb->transfer_buffer_length;
2531 switch (trb_comp_code) {
2533 ep_ring->err_count = 0;
2534 /* handle success with untransferred data as short packet */
2535 if (ep_trb != td->last_trb || remaining) {
2536 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2537 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2538 td->urb->ep->desc.bEndpointAddress,
2539 requested, remaining);
2543 case COMP_SHORT_PACKET:
2544 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2545 td->urb->ep->desc.bEndpointAddress,
2546 requested, remaining);
2549 case COMP_STOPPED_SHORT_PACKET:
2550 td->urb->actual_length = remaining;
2552 case COMP_STOPPED_LENGTH_INVALID:
2553 /* stopped on ep trb with invalid length, exclude it */
2557 case COMP_USB_TRANSACTION_ERROR:
2558 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2559 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2564 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2572 if (ep_trb == td->last_trb)
2573 td->urb->actual_length = requested - remaining;
2575 td->urb->actual_length =
2576 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2577 ep_trb_len - remaining;
2579 if (remaining > requested) {
2580 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2582 td->urb->actual_length = 0;
2584 return finish_td(xhci, td, event, ep);
2588 * If this function returns an error condition, it means it got a Transfer
2589 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2590 * At this point, the host controller is probably hosed and should be reset.
2592 static int handle_tx_event(struct xhci_hcd *xhci,
2593 struct xhci_transfer_event *event)
2595 struct xhci_virt_ep *ep;
2596 struct xhci_ring *ep_ring;
2597 unsigned int slot_id;
2599 struct xhci_td *td = NULL;
2600 dma_addr_t ep_trb_dma;
2601 struct xhci_segment *ep_seg;
2602 union xhci_trb *ep_trb;
2603 int status = -EINPROGRESS;
2604 struct xhci_ep_ctx *ep_ctx;
2605 struct list_head *tmp;
2608 bool handling_skipped_tds = false;
2610 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2611 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2612 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2613 ep_trb_dma = le64_to_cpu(event->buffer);
2615 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2617 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2621 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2622 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2624 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2626 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2631 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2633 switch (trb_comp_code) {
2634 case COMP_STALL_ERROR:
2635 case COMP_USB_TRANSACTION_ERROR:
2636 case COMP_INVALID_STREAM_TYPE_ERROR:
2637 case COMP_INVALID_STREAM_ID_ERROR:
2638 xhci_handle_halted_endpoint(xhci, ep, 0, NULL,
2641 case COMP_RING_UNDERRUN:
2642 case COMP_RING_OVERRUN:
2643 case COMP_STOPPED_LENGTH_INVALID:
2646 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2652 /* Count current td numbers if ep->skip is set */
2654 list_for_each(tmp, &ep_ring->td_list)
2658 /* Look for common error cases */
2659 switch (trb_comp_code) {
2660 /* Skip codes that require special handling depending on
2664 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2666 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2667 ep_ring->last_td_was_short)
2668 trb_comp_code = COMP_SHORT_PACKET;
2670 xhci_warn_ratelimited(xhci,
2671 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2674 case COMP_SHORT_PACKET:
2676 /* Completion codes for endpoint stopped state */
2678 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2681 case COMP_STOPPED_LENGTH_INVALID:
2683 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2686 case COMP_STOPPED_SHORT_PACKET:
2688 "Stopped with short packet transfer detected for slot %u ep %u\n",
2691 /* Completion codes for endpoint halted state */
2692 case COMP_STALL_ERROR:
2693 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2695 ep->ep_state |= EP_HALTED;
2698 case COMP_SPLIT_TRANSACTION_ERROR:
2699 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2703 case COMP_USB_TRANSACTION_ERROR:
2704 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2708 case COMP_BABBLE_DETECTED_ERROR:
2709 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2711 status = -EOVERFLOW;
2713 /* Completion codes for endpoint error state */
2714 case COMP_TRB_ERROR:
2716 "WARN: TRB error for slot %u ep %u on endpoint\n",
2720 /* completion codes not indicating endpoint state change */
2721 case COMP_DATA_BUFFER_ERROR:
2723 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2727 case COMP_BANDWIDTH_OVERRUN_ERROR:
2729 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2732 case COMP_ISOCH_BUFFER_OVERRUN:
2734 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2737 case COMP_RING_UNDERRUN:
2739 * When the Isoch ring is empty, the xHC will generate
2740 * a Ring Overrun Event for IN Isoch endpoint or Ring
2741 * Underrun Event for OUT Isoch endpoint.
2743 xhci_dbg(xhci, "underrun event on endpoint\n");
2744 if (!list_empty(&ep_ring->td_list))
2745 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2746 "still with TDs queued?\n",
2747 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2750 case COMP_RING_OVERRUN:
2751 xhci_dbg(xhci, "overrun event on endpoint\n");
2752 if (!list_empty(&ep_ring->td_list))
2753 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2754 "still with TDs queued?\n",
2755 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2758 case COMP_MISSED_SERVICE_ERROR:
2760 * When encounter missed service error, one or more isoc tds
2761 * may be missed by xHC.
2762 * Set skip flag of the ep_ring; Complete the missed tds as
2763 * short transfer when process the ep_ring next time.
2767 "Miss service interval error for slot %u ep %u, set skip flag\n",
2770 case COMP_NO_PING_RESPONSE_ERROR:
2773 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2777 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2778 /* needs disable slot command to recover */
2780 "WARN: detect an incompatible device for slot %u ep %u",
2785 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2790 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2791 trb_comp_code, slot_id, ep_index);
2796 /* This TRB should be in the TD at the head of this ring's
2799 if (list_empty(&ep_ring->td_list)) {
2801 * Don't print wanings if it's due to a stopped endpoint
2802 * generating an extra completion event if the device
2803 * was suspended. Or, a event for the last TRB of a
2804 * short TD we already got a short event for.
2805 * The short TD is already removed from the TD list.
2808 if (!(trb_comp_code == COMP_STOPPED ||
2809 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2810 ep_ring->last_td_was_short)) {
2811 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2812 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2817 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2820 if (trb_comp_code == COMP_STALL_ERROR ||
2821 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2823 xhci_handle_halted_endpoint(xhci, ep,
2831 /* We've skipped all the TDs on the ep ring when ep->skip set */
2832 if (ep->skip && td_num == 0) {
2834 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2839 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2844 /* Is this a TRB in the currently executing TD? */
2845 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2846 td->last_trb, ep_trb_dma, false);
2849 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2850 * is not in the current TD pointed by ep_ring->dequeue because
2851 * that the hardware dequeue pointer still at the previous TRB
2852 * of the current TD. The previous TRB maybe a Link TD or the
2853 * last TRB of the previous TD. The command completion handle
2854 * will take care the rest.
2856 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2857 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2863 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2864 /* Some host controllers give a spurious
2865 * successful event after a short transfer.
2868 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2869 ep_ring->last_td_was_short) {
2870 ep_ring->last_td_was_short = false;
2873 /* HC is busted, give up! */
2875 "ERROR Transfer event TRB DMA ptr not "
2876 "part of current TD ep_index %d "
2877 "comp_code %u\n", ep_index,
2879 trb_in_td(xhci, ep_ring->deq_seg,
2880 ep_ring->dequeue, td->last_trb,
2885 skip_isoc_td(xhci, td, ep, status);
2888 if (trb_comp_code == COMP_SHORT_PACKET)
2889 ep_ring->last_td_was_short = true;
2891 ep_ring->last_td_was_short = false;
2895 "Found td. Clear skip flag for slot %u ep %u.\n",
2900 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2903 trace_xhci_handle_transfer(ep_ring,
2904 (struct xhci_generic_trb *) ep_trb);
2907 * No-op TRB could trigger interrupts in a case where
2908 * a URB was killed and a STALL_ERROR happens right
2909 * after the endpoint ring stopped. Reset the halted
2910 * endpoint. Otherwise, the endpoint remains stalled
2914 if (trb_is_noop(ep_trb)) {
2915 if (trb_comp_code == COMP_STALL_ERROR ||
2916 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2918 xhci_handle_halted_endpoint(xhci, ep,
2924 td->status = status;
2926 /* update the urb's actual_length and give back to the core */
2927 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2928 process_ctrl_td(xhci, td, ep_trb, event, ep);
2929 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2930 process_isoc_td(xhci, td, ep_trb, event, ep);
2932 process_bulk_intr_td(xhci, td, ep_trb, event, ep);
2934 handling_skipped_tds = ep->skip &&
2935 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2936 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2939 * Do not update event ring dequeue pointer if we're in a loop
2940 * processing missed tds.
2942 if (!handling_skipped_tds)
2943 inc_deq(xhci, xhci->event_ring);
2946 * If ep->skip is set, it means there are missed tds on the
2947 * endpoint ring need to take care of.
2948 * Process them as short transfer until reach the td pointed by
2951 } while (handling_skipped_tds);
2956 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2957 (unsigned long long) xhci_trb_virt_to_dma(
2958 xhci->event_ring->deq_seg,
2959 xhci->event_ring->dequeue),
2960 lower_32_bits(le64_to_cpu(event->buffer)),
2961 upper_32_bits(le64_to_cpu(event->buffer)),
2962 le32_to_cpu(event->transfer_len),
2963 le32_to_cpu(event->flags));
2968 * This function handles all OS-owned events on the event ring. It may drop
2969 * xhci->lock between event processing (e.g. to pass up port status changes).
2970 * Returns >0 for "possibly more events to process" (caller should call again),
2971 * otherwise 0 if done. In future, <0 returns should indicate error code.
2973 static int xhci_handle_event(struct xhci_hcd *xhci)
2975 union xhci_trb *event;
2976 int update_ptrs = 1;
2980 /* Event ring hasn't been allocated yet. */
2981 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2982 xhci_err(xhci, "ERROR event ring not ready\n");
2986 event = xhci->event_ring->dequeue;
2987 /* Does the HC or OS own the TRB? */
2988 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2989 xhci->event_ring->cycle_state)
2992 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2995 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2996 * speculative reads of the event's flags/data below.
2999 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
3000 /* FIXME: Handle more event types. */
3003 case TRB_COMPLETION:
3004 handle_cmd_completion(xhci, &event->event_cmd);
3006 case TRB_PORT_STATUS:
3007 handle_port_status(xhci, event);
3011 ret = handle_tx_event(xhci, &event->trans_event);
3016 handle_device_notification(xhci, event);
3019 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3020 handle_vendor_event(xhci, event, trb_type);
3022 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3024 /* Any of the above functions may drop and re-acquire the lock, so check
3025 * to make sure a watchdog timer didn't mark the host as non-responsive.
3027 if (xhci->xhc_state & XHCI_STATE_DYING) {
3028 xhci_dbg(xhci, "xHCI host dying, returning from "
3029 "event handler.\n");
3034 /* Update SW event ring dequeue pointer */
3035 inc_deq(xhci, xhci->event_ring);
3037 /* Are there more items on the event ring? Caller will call us again to
3044 * Update Event Ring Dequeue Pointer:
3045 * - When all events have finished
3046 * - To avoid "Event Ring Full Error" condition
3048 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3049 union xhci_trb *event_ring_deq)
3054 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3055 /* If necessary, update the HW's version of the event ring deq ptr. */
3056 if (event_ring_deq != xhci->event_ring->dequeue) {
3057 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
3058 xhci->event_ring->dequeue);
3060 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3062 * Per 4.9.4, Software writes to the ERDP register shall
3063 * always advance the Event Ring Dequeue Pointer value.
3065 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
3066 ((u64) deq & (u64) ~ERST_PTR_MASK))
3069 /* Update HC event ring dequeue pointer */
3070 temp_64 &= ERST_PTR_MASK;
3071 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3074 /* Clear the event handler busy flag (RW1C) */
3075 temp_64 |= ERST_EHB;
3076 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3080 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3081 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3082 * indicators of an event TRB error, but we check the status *first* to be safe.
3084 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3086 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3087 union xhci_trb *event_ring_deq;
3088 irqreturn_t ret = IRQ_NONE;
3089 unsigned long flags;
3094 spin_lock_irqsave(&xhci->lock, flags);
3095 /* Check if the xHC generated the interrupt, or the irq is shared */
3096 status = readl(&xhci->op_regs->status);
3097 if (status == ~(u32)0) {
3103 if (!(status & STS_EINT))
3106 if (status & STS_FATAL) {
3107 xhci_warn(xhci, "WARNING: Host System Error\n");
3114 * Clear the op reg interrupt status first,
3115 * so we can receive interrupts from other MSI-X interrupters.
3116 * Write 1 to clear the interrupt status.
3119 writel(status, &xhci->op_regs->status);
3121 if (!hcd->msi_enabled) {
3123 irq_pending = readl(&xhci->ir_set->irq_pending);
3124 irq_pending |= IMAN_IP;
3125 writel(irq_pending, &xhci->ir_set->irq_pending);
3128 if (xhci->xhc_state & XHCI_STATE_DYING ||
3129 xhci->xhc_state & XHCI_STATE_HALTED) {
3130 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3131 "Shouldn't IRQs be disabled?\n");
3132 /* Clear the event handler busy flag (RW1C);
3133 * the event ring should be empty.
3135 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3136 xhci_write_64(xhci, temp_64 | ERST_EHB,
3137 &xhci->ir_set->erst_dequeue);
3142 event_ring_deq = xhci->event_ring->dequeue;
3143 /* FIXME this should be a delayed service routine
3144 * that clears the EHB.
3146 while (xhci_handle_event(xhci) > 0) {
3147 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3149 xhci_update_erst_dequeue(xhci, event_ring_deq);
3153 xhci_update_erst_dequeue(xhci, event_ring_deq);
3157 spin_unlock_irqrestore(&xhci->lock, flags);
3162 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3164 return xhci_irq(hcd);
3167 /**** Endpoint Ring Operations ****/
3170 * Generic function for queueing a TRB on a ring.
3171 * The caller must have checked to make sure there's room on the ring.
3173 * @more_trbs_coming: Will you enqueue more TRBs before calling
3174 * prepare_transfer()?
3176 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3177 bool more_trbs_coming,
3178 u32 field1, u32 field2, u32 field3, u32 field4)
3180 struct xhci_generic_trb *trb;
3182 trb = &ring->enqueue->generic;
3183 trb->field[0] = cpu_to_le32(field1);
3184 trb->field[1] = cpu_to_le32(field2);
3185 trb->field[2] = cpu_to_le32(field3);
3186 /* make sure TRB is fully written before giving it to the controller */
3188 trb->field[3] = cpu_to_le32(field4);
3190 trace_xhci_queue_trb(ring, trb);
3192 inc_enq(xhci, ring, more_trbs_coming);
3196 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3197 * FIXME allocate segments if the ring is full.
3199 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3200 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3202 unsigned int num_trbs_needed;
3203 unsigned int link_trb_count = 0;
3205 /* Make sure the endpoint has been added to xHC schedule */
3207 case EP_STATE_DISABLED:
3209 * USB core changed config/interfaces without notifying us,
3210 * or hardware is reporting the wrong state.
3212 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3214 case EP_STATE_ERROR:
3215 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3216 /* FIXME event handling code for error needs to clear it */
3217 /* XXX not sure if this should be -ENOENT or not */
3219 case EP_STATE_HALTED:
3220 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3222 case EP_STATE_STOPPED:
3223 case EP_STATE_RUNNING:
3226 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3228 * FIXME issue Configure Endpoint command to try to get the HC
3229 * back into a known state.
3235 if (room_on_ring(xhci, ep_ring, num_trbs))
3238 if (ep_ring == xhci->cmd_ring) {
3239 xhci_err(xhci, "Do not support expand command ring\n");
3243 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3244 "ERROR no room on ep ring, try ring expansion");
3245 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3246 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3248 xhci_err(xhci, "Ring expansion failed\n");
3253 while (trb_is_link(ep_ring->enqueue)) {
3254 /* If we're not dealing with 0.95 hardware or isoc rings
3255 * on AMD 0.96 host, clear the chain bit.
3257 if (!xhci_link_trb_quirk(xhci) &&
3258 !(ep_ring->type == TYPE_ISOC &&
3259 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3260 ep_ring->enqueue->link.control &=
3261 cpu_to_le32(~TRB_CHAIN);
3263 ep_ring->enqueue->link.control |=
3264 cpu_to_le32(TRB_CHAIN);
3267 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3269 /* Toggle the cycle bit after the last ring segment. */
3270 if (link_trb_toggles_cycle(ep_ring->enqueue))
3271 ep_ring->cycle_state ^= 1;
3273 ep_ring->enq_seg = ep_ring->enq_seg->next;
3274 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3276 /* prevent infinite loop if all first trbs are link trbs */
3277 if (link_trb_count++ > ep_ring->num_segs) {
3278 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3283 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3284 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3291 static int prepare_transfer(struct xhci_hcd *xhci,
3292 struct xhci_virt_device *xdev,
3293 unsigned int ep_index,
3294 unsigned int stream_id,
3295 unsigned int num_trbs,
3297 unsigned int td_index,
3301 struct urb_priv *urb_priv;
3303 struct xhci_ring *ep_ring;
3304 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3306 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3309 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3314 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3315 num_trbs, mem_flags);
3319 urb_priv = urb->hcpriv;
3320 td = &urb_priv->td[td_index];
3322 INIT_LIST_HEAD(&td->td_list);
3323 INIT_LIST_HEAD(&td->cancelled_td_list);
3325 if (td_index == 0) {
3326 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3332 /* Add this TD to the tail of the endpoint ring's TD list */
3333 list_add_tail(&td->td_list, &ep_ring->td_list);
3334 td->start_seg = ep_ring->enq_seg;
3335 td->first_trb = ep_ring->enqueue;
3340 unsigned int count_trbs(u64 addr, u64 len)
3342 unsigned int num_trbs;
3344 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3352 static inline unsigned int count_trbs_needed(struct urb *urb)
3354 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3357 static unsigned int count_sg_trbs_needed(struct urb *urb)
3359 struct scatterlist *sg;
3360 unsigned int i, len, full_len, num_trbs = 0;
3362 full_len = urb->transfer_buffer_length;
3364 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3365 len = sg_dma_len(sg);
3366 num_trbs += count_trbs(sg_dma_address(sg), len);
3367 len = min_t(unsigned int, len, full_len);
3376 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3380 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3381 len = urb->iso_frame_desc[i].length;
3383 return count_trbs(addr, len);
3386 static void check_trb_math(struct urb *urb, int running_total)
3388 if (unlikely(running_total != urb->transfer_buffer_length))
3389 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3390 "queued %#x (%d), asked for %#x (%d)\n",
3392 urb->ep->desc.bEndpointAddress,
3393 running_total, running_total,
3394 urb->transfer_buffer_length,
3395 urb->transfer_buffer_length);
3398 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3399 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3400 struct xhci_generic_trb *start_trb)
3403 * Pass all the TRBs to the hardware at once and make sure this write
3408 start_trb->field[3] |= cpu_to_le32(start_cycle);
3410 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3411 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3414 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3415 struct xhci_ep_ctx *ep_ctx)
3420 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3421 ep_interval = urb->interval;
3423 /* Convert to microframes */
3424 if (urb->dev->speed == USB_SPEED_LOW ||
3425 urb->dev->speed == USB_SPEED_FULL)
3428 /* FIXME change this to a warning and a suggestion to use the new API
3429 * to set the polling interval (once the API is added).
3431 if (xhci_interval != ep_interval) {
3432 dev_dbg_ratelimited(&urb->dev->dev,
3433 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3434 ep_interval, ep_interval == 1 ? "" : "s",
3435 xhci_interval, xhci_interval == 1 ? "" : "s");
3436 urb->interval = xhci_interval;
3437 /* Convert back to frames for LS/FS devices */
3438 if (urb->dev->speed == USB_SPEED_LOW ||
3439 urb->dev->speed == USB_SPEED_FULL)
3445 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3446 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3447 * (comprised of sg list entries) can take several service intervals to
3450 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3451 struct urb *urb, int slot_id, unsigned int ep_index)
3453 struct xhci_ep_ctx *ep_ctx;
3455 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3456 check_interval(xhci, urb, ep_ctx);
3458 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3462 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3463 * packets remaining in the TD (*not* including this TRB).
3465 * Total TD packet count = total_packet_count =
3466 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3468 * Packets transferred up to and including this TRB = packets_transferred =
3469 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3471 * TD size = total_packet_count - packets_transferred
3473 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3474 * including this TRB, right shifted by 10
3476 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3477 * This is taken care of in the TRB_TD_SIZE() macro
3479 * The last TRB in a TD must have the TD size set to zero.
3481 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3482 int trb_buff_len, unsigned int td_total_len,
3483 struct urb *urb, bool more_trbs_coming)
3485 u32 maxp, total_packet_count;
3487 /* MTK xHCI 0.96 contains some features from 1.0 */
3488 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3489 return ((td_total_len - transferred) >> 10);
3491 /* One TRB with a zero-length data packet. */
3492 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3493 trb_buff_len == td_total_len)
3496 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3497 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3500 maxp = usb_endpoint_maxp(&urb->ep->desc);
3501 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3503 /* Queueing functions don't count the current TRB into transferred */
3504 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3508 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3509 u32 *trb_buff_len, struct xhci_segment *seg)
3511 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3512 unsigned int unalign;
3513 unsigned int max_pkt;
3517 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3518 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3520 /* we got lucky, last normal TRB data on segment is packet aligned */
3524 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3525 unalign, *trb_buff_len);
3527 /* is the last nornal TRB alignable by splitting it */
3528 if (*trb_buff_len > unalign) {
3529 *trb_buff_len -= unalign;
3530 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3535 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3536 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3537 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3539 new_buff_len = max_pkt - (enqd_len % max_pkt);
3541 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3542 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3544 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3545 if (usb_urb_dir_out(urb)) {
3546 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3547 seg->bounce_buf, new_buff_len, enqd_len);
3548 if (len != new_buff_len)
3550 "WARN Wrong bounce buffer write length: %zu != %d\n",
3552 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3553 max_pkt, DMA_TO_DEVICE);
3555 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3556 max_pkt, DMA_FROM_DEVICE);
3559 if (dma_mapping_error(dev, seg->bounce_dma)) {
3560 /* try without aligning. Some host controllers survive */
3561 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3564 *trb_buff_len = new_buff_len;
3565 seg->bounce_len = new_buff_len;
3566 seg->bounce_offs = enqd_len;
3568 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3573 /* This is very similar to what ehci-q.c qtd_fill() does */
3574 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3575 struct urb *urb, int slot_id, unsigned int ep_index)
3577 struct xhci_ring *ring;
3578 struct urb_priv *urb_priv;
3580 struct xhci_generic_trb *start_trb;
3581 struct scatterlist *sg = NULL;
3582 bool more_trbs_coming = true;
3583 bool need_zero_pkt = false;
3584 bool first_trb = true;
3585 unsigned int num_trbs;
3586 unsigned int start_cycle, num_sgs = 0;
3587 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3589 u32 field, length_field, remainder;
3590 u64 addr, send_addr;
3592 ring = xhci_urb_to_transfer_ring(xhci, urb);
3596 full_len = urb->transfer_buffer_length;
3597 /* If we have scatter/gather list, we use it. */
3598 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3599 num_sgs = urb->num_mapped_sgs;
3601 addr = (u64) sg_dma_address(sg);
3602 block_len = sg_dma_len(sg);
3603 num_trbs = count_sg_trbs_needed(urb);
3605 num_trbs = count_trbs_needed(urb);
3606 addr = (u64) urb->transfer_dma;
3607 block_len = full_len;
3609 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3610 ep_index, urb->stream_id,
3611 num_trbs, urb, 0, mem_flags);
3612 if (unlikely(ret < 0))
3615 urb_priv = urb->hcpriv;
3617 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3618 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3619 need_zero_pkt = true;
3621 td = &urb_priv->td[0];
3624 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3625 * until we've finished creating all the other TRBs. The ring's cycle
3626 * state may change as we enqueue the other TRBs, so save it too.
3628 start_trb = &ring->enqueue->generic;
3629 start_cycle = ring->cycle_state;
3632 /* Queue the TRBs, even if they are zero-length */
3633 for (enqd_len = 0; first_trb || enqd_len < full_len;
3634 enqd_len += trb_buff_len) {
3635 field = TRB_TYPE(TRB_NORMAL);
3637 /* TRB buffer should not cross 64KB boundaries */
3638 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3639 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3641 if (enqd_len + trb_buff_len > full_len)
3642 trb_buff_len = full_len - enqd_len;
3644 /* Don't change the cycle bit of the first TRB until later */
3647 if (start_cycle == 0)
3650 field |= ring->cycle_state;
3652 /* Chain all the TRBs together; clear the chain bit in the last
3653 * TRB to indicate it's the last TRB in the chain.
3655 if (enqd_len + trb_buff_len < full_len) {
3657 if (trb_is_link(ring->enqueue + 1)) {
3658 if (xhci_align_td(xhci, urb, enqd_len,
3661 send_addr = ring->enq_seg->bounce_dma;
3662 /* assuming TD won't span 2 segs */
3663 td->bounce_seg = ring->enq_seg;
3667 if (enqd_len + trb_buff_len >= full_len) {
3668 field &= ~TRB_CHAIN;
3670 more_trbs_coming = false;
3671 td->last_trb = ring->enqueue;
3672 td->last_trb_seg = ring->enq_seg;
3673 if (xhci_urb_suitable_for_idt(urb)) {
3674 memcpy(&send_addr, urb->transfer_buffer,
3676 le64_to_cpus(&send_addr);
3681 /* Only set interrupt on short packet for IN endpoints */
3682 if (usb_urb_dir_in(urb))
3685 /* Set the TRB length, TD size, and interrupter fields. */
3686 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3687 full_len, urb, more_trbs_coming);
3689 length_field = TRB_LEN(trb_buff_len) |
3690 TRB_TD_SIZE(remainder) |
3693 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3694 lower_32_bits(send_addr),
3695 upper_32_bits(send_addr),
3699 addr += trb_buff_len;
3700 sent_len = trb_buff_len;
3702 while (sg && sent_len >= block_len) {
3705 sent_len -= block_len;
3707 if (num_sgs != 0 && sg) {
3708 block_len = sg_dma_len(sg);
3709 addr = (u64) sg_dma_address(sg);
3713 block_len -= sent_len;
3717 if (need_zero_pkt) {
3718 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3719 ep_index, urb->stream_id,
3720 1, urb, 1, mem_flags);
3721 urb_priv->td[1].last_trb = ring->enqueue;
3722 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3723 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3724 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3725 urb_priv->td[1].num_trbs++;
3728 check_trb_math(urb, enqd_len);
3729 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3730 start_cycle, start_trb);
3734 /* Caller must have locked xhci->lock */
3735 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3736 struct urb *urb, int slot_id, unsigned int ep_index)
3738 struct xhci_ring *ep_ring;
3741 struct usb_ctrlrequest *setup;
3742 struct xhci_generic_trb *start_trb;
3745 struct urb_priv *urb_priv;
3748 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3753 * Need to copy setup packet into setup TRB, so we can't use the setup
3756 if (!urb->setup_packet)
3759 /* 1 TRB for setup, 1 for status */
3762 * Don't need to check if we need additional event data and normal TRBs,
3763 * since data in control transfers will never get bigger than 16MB
3764 * XXX: can we get a buffer that crosses 64KB boundaries?
3766 if (urb->transfer_buffer_length > 0)
3768 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3769 ep_index, urb->stream_id,
3770 num_trbs, urb, 0, mem_flags);
3774 urb_priv = urb->hcpriv;
3775 td = &urb_priv->td[0];
3776 td->num_trbs = num_trbs;
3779 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3780 * until we've finished creating all the other TRBs. The ring's cycle
3781 * state may change as we enqueue the other TRBs, so save it too.
3783 start_trb = &ep_ring->enqueue->generic;
3784 start_cycle = ep_ring->cycle_state;
3786 /* Queue setup TRB - see section 6.4.1.2.1 */
3787 /* FIXME better way to translate setup_packet into two u32 fields? */
3788 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3790 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3791 if (start_cycle == 0)
3794 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3795 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3796 if (urb->transfer_buffer_length > 0) {
3797 if (setup->bRequestType & USB_DIR_IN)
3798 field |= TRB_TX_TYPE(TRB_DATA_IN);
3800 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3804 queue_trb(xhci, ep_ring, true,
3805 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3806 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3807 TRB_LEN(8) | TRB_INTR_TARGET(0),
3808 /* Immediate data in pointer */
3811 /* If there's data, queue data TRBs */
3812 /* Only set interrupt on short packet for IN endpoints */
3813 if (usb_urb_dir_in(urb))
3814 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3816 field = TRB_TYPE(TRB_DATA);
3818 if (urb->transfer_buffer_length > 0) {
3819 u32 length_field, remainder;
3822 if (xhci_urb_suitable_for_idt(urb)) {
3823 memcpy(&addr, urb->transfer_buffer,
3824 urb->transfer_buffer_length);
3825 le64_to_cpus(&addr);
3828 addr = (u64) urb->transfer_dma;
3831 remainder = xhci_td_remainder(xhci, 0,
3832 urb->transfer_buffer_length,
3833 urb->transfer_buffer_length,
3835 length_field = TRB_LEN(urb->transfer_buffer_length) |
3836 TRB_TD_SIZE(remainder) |
3838 if (setup->bRequestType & USB_DIR_IN)
3839 field |= TRB_DIR_IN;
3840 queue_trb(xhci, ep_ring, true,
3841 lower_32_bits(addr),
3842 upper_32_bits(addr),
3844 field | ep_ring->cycle_state);
3847 /* Save the DMA address of the last TRB in the TD */
3848 td->last_trb = ep_ring->enqueue;
3849 td->last_trb_seg = ep_ring->enq_seg;
3851 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3852 /* If the device sent data, the status stage is an OUT transfer */
3853 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3857 queue_trb(xhci, ep_ring, false,
3861 /* Event on completion */
3862 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3864 giveback_first_trb(xhci, slot_id, ep_index, 0,
3865 start_cycle, start_trb);
3870 * The transfer burst count field of the isochronous TRB defines the number of
3871 * bursts that are required to move all packets in this TD. Only SuperSpeed
3872 * devices can burst up to bMaxBurst number of packets per service interval.
3873 * This field is zero based, meaning a value of zero in the field means one
3874 * burst. Basically, for everything but SuperSpeed devices, this field will be
3875 * zero. Only xHCI 1.0 host controllers support this field.
3877 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3878 struct urb *urb, unsigned int total_packet_count)
3880 unsigned int max_burst;
3882 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3885 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3886 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3890 * Returns the number of packets in the last "burst" of packets. This field is
3891 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3892 * the last burst packet count is equal to the total number of packets in the
3893 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3894 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3895 * contain 1 to (bMaxBurst + 1) packets.
3897 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3898 struct urb *urb, unsigned int total_packet_count)
3900 unsigned int max_burst;
3901 unsigned int residue;
3903 if (xhci->hci_version < 0x100)
3906 if (urb->dev->speed >= USB_SPEED_SUPER) {
3907 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3908 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3909 residue = total_packet_count % (max_burst + 1);
3910 /* If residue is zero, the last burst contains (max_burst + 1)
3911 * number of packets, but the TLBPC field is zero-based.
3917 if (total_packet_count == 0)
3919 return total_packet_count - 1;
3923 * Calculates Frame ID field of the isochronous TRB identifies the
3924 * target frame that the Interval associated with this Isochronous
3925 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3927 * Returns actual frame id on success, negative value on error.
3929 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3930 struct urb *urb, int index)
3932 int start_frame, ist, ret = 0;
3933 int start_frame_id, end_frame_id, current_frame_id;
3935 if (urb->dev->speed == USB_SPEED_LOW ||
3936 urb->dev->speed == USB_SPEED_FULL)
3937 start_frame = urb->start_frame + index * urb->interval;
3939 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3941 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3943 * If bit [3] of IST is cleared to '0', software can add a TRB no
3944 * later than IST[2:0] Microframes before that TRB is scheduled to
3946 * If bit [3] of IST is set to '1', software can add a TRB no later
3947 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3949 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3950 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3953 /* Software shall not schedule an Isoch TD with a Frame ID value that
3954 * is less than the Start Frame ID or greater than the End Frame ID,
3957 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3958 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3960 * Both the End Frame ID and Start Frame ID values are calculated
3961 * in microframes. When software determines the valid Frame ID value;
3962 * The End Frame ID value should be rounded down to the nearest Frame
3963 * boundary, and the Start Frame ID value should be rounded up to the
3964 * nearest Frame boundary.
3966 current_frame_id = readl(&xhci->run_regs->microframe_index);
3967 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3968 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3970 start_frame &= 0x7ff;
3971 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3972 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3974 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3975 __func__, index, readl(&xhci->run_regs->microframe_index),
3976 start_frame_id, end_frame_id, start_frame);
3978 if (start_frame_id < end_frame_id) {
3979 if (start_frame > end_frame_id ||
3980 start_frame < start_frame_id)
3982 } else if (start_frame_id > end_frame_id) {
3983 if ((start_frame > end_frame_id &&
3984 start_frame < start_frame_id))
3991 if (ret == -EINVAL || start_frame == start_frame_id) {
3992 start_frame = start_frame_id + 1;
3993 if (urb->dev->speed == USB_SPEED_LOW ||
3994 urb->dev->speed == USB_SPEED_FULL)
3995 urb->start_frame = start_frame;
3997 urb->start_frame = start_frame << 3;
4003 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4004 start_frame, current_frame_id, index,
4005 start_frame_id, end_frame_id);
4006 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4013 /* Check if we should generate event interrupt for a TD in an isoc URB */
4014 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
4016 if (xhci->hci_version < 0x100)
4018 /* always generate an event interrupt for the last TD */
4019 if (i == num_tds - 1)
4022 * If AVOID_BEI is set the host handles full event rings poorly,
4023 * generate an event at least every 8th TD to clear the event ring
4025 if (i && xhci->quirks & XHCI_AVOID_BEI)
4031 /* This is for isoc transfer */
4032 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4033 struct urb *urb, int slot_id, unsigned int ep_index)
4035 struct xhci_ring *ep_ring;
4036 struct urb_priv *urb_priv;
4038 int num_tds, trbs_per_td;
4039 struct xhci_generic_trb *start_trb;
4042 u32 field, length_field;
4043 int running_total, trb_buff_len, td_len, td_remain_len, ret;
4044 u64 start_addr, addr;
4046 bool more_trbs_coming;
4047 struct xhci_virt_ep *xep;
4050 xep = &xhci->devs[slot_id]->eps[ep_index];
4051 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4053 num_tds = urb->number_of_packets;
4055 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4058 start_addr = (u64) urb->transfer_dma;
4059 start_trb = &ep_ring->enqueue->generic;
4060 start_cycle = ep_ring->cycle_state;
4062 urb_priv = urb->hcpriv;
4063 /* Queue the TRBs for each TD, even if they are zero-length */
4064 for (i = 0; i < num_tds; i++) {
4065 unsigned int total_pkt_count, max_pkt;
4066 unsigned int burst_count, last_burst_pkt_count;
4071 addr = start_addr + urb->iso_frame_desc[i].offset;
4072 td_len = urb->iso_frame_desc[i].length;
4073 td_remain_len = td_len;
4074 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4075 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4077 /* A zero-length transfer still involves at least one packet. */
4078 if (total_pkt_count == 0)
4080 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4081 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4082 urb, total_pkt_count);
4084 trbs_per_td = count_isoc_trbs_needed(urb, i);
4086 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4087 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4093 td = &urb_priv->td[i];
4094 td->num_trbs = trbs_per_td;
4095 /* use SIA as default, if frame id is used overwrite it */
4096 sia_frame_id = TRB_SIA;
4097 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4098 HCC_CFC(xhci->hcc_params)) {
4099 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4101 sia_frame_id = TRB_FRAME_ID(frame_id);
4104 * Set isoc specific data for the first TRB in a TD.
4105 * Prevent HW from getting the TRBs by keeping the cycle state
4106 * inverted in the first TDs isoc TRB.
4108 field = TRB_TYPE(TRB_ISOC) |
4109 TRB_TLBPC(last_burst_pkt_count) |
4111 (i ? ep_ring->cycle_state : !start_cycle);
4113 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4114 if (!xep->use_extended_tbc)
4115 field |= TRB_TBC(burst_count);
4117 /* fill the rest of the TRB fields, and remaining normal TRBs */
4118 for (j = 0; j < trbs_per_td; j++) {
4121 /* only first TRB is isoc, overwrite otherwise */
4123 field = TRB_TYPE(TRB_NORMAL) |
4124 ep_ring->cycle_state;
4126 /* Only set interrupt on short packet for IN EPs */
4127 if (usb_urb_dir_in(urb))
4130 /* Set the chain bit for all except the last TRB */
4131 if (j < trbs_per_td - 1) {
4132 more_trbs_coming = true;
4135 more_trbs_coming = false;
4136 td->last_trb = ep_ring->enqueue;
4137 td->last_trb_seg = ep_ring->enq_seg;
4139 if (trb_block_event_intr(xhci, num_tds, i))
4142 /* Calculate TRB length */
4143 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4144 if (trb_buff_len > td_remain_len)
4145 trb_buff_len = td_remain_len;
4147 /* Set the TRB length, TD size, & interrupter fields. */
4148 remainder = xhci_td_remainder(xhci, running_total,
4149 trb_buff_len, td_len,
4150 urb, more_trbs_coming);
4152 length_field = TRB_LEN(trb_buff_len) |
4155 /* xhci 1.1 with ETE uses TD Size field for TBC */
4156 if (first_trb && xep->use_extended_tbc)
4157 length_field |= TRB_TD_SIZE_TBC(burst_count);
4159 length_field |= TRB_TD_SIZE(remainder);
4162 queue_trb(xhci, ep_ring, more_trbs_coming,
4163 lower_32_bits(addr),
4164 upper_32_bits(addr),
4167 running_total += trb_buff_len;
4169 addr += trb_buff_len;
4170 td_remain_len -= trb_buff_len;
4173 /* Check TD length */
4174 if (running_total != td_len) {
4175 xhci_err(xhci, "ISOC TD length unmatch\n");
4181 /* store the next frame id */
4182 if (HCC_CFC(xhci->hcc_params))
4183 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4185 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4186 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4187 usb_amd_quirk_pll_disable();
4189 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4191 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4192 start_cycle, start_trb);
4195 /* Clean up a partially enqueued isoc transfer. */
4197 for (i--; i >= 0; i--)
4198 list_del_init(&urb_priv->td[i].td_list);
4200 /* Use the first TD as a temporary variable to turn the TDs we've queued
4201 * into No-ops with a software-owned cycle bit. That way the hardware
4202 * won't accidentally start executing bogus TDs when we partially
4203 * overwrite them. td->first_trb and td->start_seg are already set.
4205 urb_priv->td[0].last_trb = ep_ring->enqueue;
4206 /* Every TRB except the first & last will have its cycle bit flipped. */
4207 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4209 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4210 ep_ring->enqueue = urb_priv->td[0].first_trb;
4211 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4212 ep_ring->cycle_state = start_cycle;
4213 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4214 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4219 * Check transfer ring to guarantee there is enough room for the urb.
4220 * Update ISO URB start_frame and interval.
4221 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4222 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4223 * Contiguous Frame ID is not supported by HC.
4225 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4226 struct urb *urb, int slot_id, unsigned int ep_index)
4228 struct xhci_virt_device *xdev;
4229 struct xhci_ring *ep_ring;
4230 struct xhci_ep_ctx *ep_ctx;
4232 int num_tds, num_trbs, i;
4234 struct xhci_virt_ep *xep;
4237 xdev = xhci->devs[slot_id];
4238 xep = &xhci->devs[slot_id]->eps[ep_index];
4239 ep_ring = xdev->eps[ep_index].ring;
4240 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4243 num_tds = urb->number_of_packets;
4244 for (i = 0; i < num_tds; i++)
4245 num_trbs += count_isoc_trbs_needed(urb, i);
4247 /* Check the ring to guarantee there is enough room for the whole urb.
4248 * Do not insert any td of the urb to the ring if the check failed.
4250 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4251 num_trbs, mem_flags);
4256 * Check interval value. This should be done before we start to
4257 * calculate the start frame value.
4259 check_interval(xhci, urb, ep_ctx);
4261 /* Calculate the start frame and put it in urb->start_frame. */
4262 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4263 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4264 urb->start_frame = xep->next_frame_id;
4265 goto skip_start_over;
4269 start_frame = readl(&xhci->run_regs->microframe_index);
4270 start_frame &= 0x3fff;
4272 * Round up to the next frame and consider the time before trb really
4273 * gets scheduled by hardare.
4275 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4276 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4278 start_frame += ist + XHCI_CFC_DELAY;
4279 start_frame = roundup(start_frame, 8);
4282 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4283 * is greate than 8 microframes.
4285 if (urb->dev->speed == USB_SPEED_LOW ||
4286 urb->dev->speed == USB_SPEED_FULL) {
4287 start_frame = roundup(start_frame, urb->interval << 3);
4288 urb->start_frame = start_frame >> 3;
4290 start_frame = roundup(start_frame, urb->interval);
4291 urb->start_frame = start_frame;
4295 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4297 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4300 /**** Command Ring Operations ****/
4302 /* Generic function for queueing a command TRB on the command ring.
4303 * Check to make sure there's room on the command ring for one command TRB.
4304 * Also check that there's room reserved for commands that must not fail.
4305 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4306 * then only check for the number of reserved spots.
4307 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4308 * because the command event handler may want to resubmit a failed command.
4310 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4311 u32 field1, u32 field2,
4312 u32 field3, u32 field4, bool command_must_succeed)
4314 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4317 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4318 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4319 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4323 if (!command_must_succeed)
4326 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4327 reserved_trbs, GFP_ATOMIC);
4329 xhci_err(xhci, "ERR: No room for command on command ring\n");
4330 if (command_must_succeed)
4331 xhci_err(xhci, "ERR: Reserved TRB counting for "
4332 "unfailable commands failed.\n");
4336 cmd->command_trb = xhci->cmd_ring->enqueue;
4338 /* if there are no other commands queued we start the timeout timer */
4339 if (list_empty(&xhci->cmd_list)) {
4340 xhci->current_cmd = cmd;
4341 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4344 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4346 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4347 field4 | xhci->cmd_ring->cycle_state);
4351 /* Queue a slot enable or disable request on the command ring */
4352 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4353 u32 trb_type, u32 slot_id)
4355 return queue_command(xhci, cmd, 0, 0, 0,
4356 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4359 /* Queue an address device command TRB */
4360 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4361 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4363 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4364 upper_32_bits(in_ctx_ptr), 0,
4365 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4366 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4369 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4370 u32 field1, u32 field2, u32 field3, u32 field4)
4372 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4375 /* Queue a reset device command TRB */
4376 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4379 return queue_command(xhci, cmd, 0, 0, 0,
4380 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4384 /* Queue a configure endpoint command TRB */
4385 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4386 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4387 u32 slot_id, bool command_must_succeed)
4389 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4390 upper_32_bits(in_ctx_ptr), 0,
4391 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4392 command_must_succeed);
4395 /* Queue an evaluate context command TRB */
4396 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4397 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4399 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4400 upper_32_bits(in_ctx_ptr), 0,
4401 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4402 command_must_succeed);
4406 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4407 * activity on an endpoint that is about to be suspended.
4409 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4410 int slot_id, unsigned int ep_index, int suspend)
4412 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4413 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4414 u32 type = TRB_TYPE(TRB_STOP_RING);
4415 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4417 return queue_command(xhci, cmd, 0, 0, 0,
4418 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4421 /* Set Transfer Ring Dequeue Pointer command */
4422 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4423 unsigned int slot_id, unsigned int ep_index,
4424 struct xhci_dequeue_state *deq_state)
4427 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4428 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4429 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4431 u32 type = TRB_TYPE(TRB_SET_DEQ);
4432 struct xhci_virt_ep *ep;
4433 struct xhci_command *cmd;
4436 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4437 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4438 deq_state->new_deq_seg,
4439 (unsigned long long)deq_state->new_deq_seg->dma,
4440 deq_state->new_deq_ptr,
4441 (unsigned long long)xhci_trb_virt_to_dma(
4442 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4443 deq_state->new_cycle_state);
4445 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4446 deq_state->new_deq_ptr);
4448 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4449 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4450 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4453 ep = &xhci->devs[slot_id]->eps[ep_index];
4454 if ((ep->ep_state & SET_DEQ_PENDING)) {
4455 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4456 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4460 /* This function gets called from contexts where it cannot sleep */
4461 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4465 ep->queued_deq_seg = deq_state->new_deq_seg;
4466 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4467 if (deq_state->stream_id)
4468 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4469 ret = queue_command(xhci, cmd,
4470 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4471 upper_32_bits(addr), trb_stream_id,
4472 trb_slot_id | trb_ep_index | type, false);
4474 xhci_free_command(xhci, cmd);
4478 /* Stop the TD queueing code from ringing the doorbell until
4479 * this command completes. The HC won't set the dequeue pointer
4480 * if the ring is running, and ringing the doorbell starts the
4483 ep->ep_state |= SET_DEQ_PENDING;
4486 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4487 int slot_id, unsigned int ep_index,
4488 enum xhci_ep_reset_type reset_type)
4490 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4491 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4492 u32 type = TRB_TYPE(TRB_RESET_EP);
4494 if (reset_type == EP_SOFT_RESET)
4497 return queue_command(xhci, cmd, 0, 0, 0,
4498 trb_slot_id | trb_ep_index | type, false);