drivers/usb/host/xhci-ring.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 /*
  12  * Ring initialization rules:
  13  * 1. Each segment is initialized to zero, except for link TRBs.
  14  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  15  *    Consumer Cycle State (CCS), depending on ring function.
  16  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  17  *
  18  * Ring behavior rules:
  19  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  20  *    least one free TRB in the ring.  This is useful if you want to turn that
  21  *    into a link TRB and expand the ring.
  22  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  23  *    link TRB, then load the pointer with the address in the link TRB.  If the
  24  *    link TRB had its toggle bit set, you may need to update the ring cycle
  25  *    state (see cycle bit rules).  You may have to do this multiple times
  26  *    until you reach a non-link TRB.
  27  * 3. A ring is full if enqueue++ (for the definition of increment above)
  28  *    equals the dequeue pointer.
  29  *
  30  * Cycle bit rules:
  31  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  32  *    in a link TRB, it must toggle the ring cycle state.
  33  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  34  *    in a link TRB, it must toggle the ring cycle state.
  35  *
  36  * Producer rules:
  37  * 1. Check if ring is full before you enqueue.
  38  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  39  *    Update enqueue pointer between each write (which may update the ring
  40  *    cycle state).
  41  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  42  *    and endpoint rings.  If HC is the producer for the event ring,
  43  *    and it generates an interrupt according to interrupt modulation rules.
  44  *
  45  * Consumer rules:
  46  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  47  *    the TRB is owned by the consumer.
  48  * 2. Update dequeue pointer (which may update the ring cycle state) and
  49  *    continue processing TRBs until you reach a TRB which is not owned by you.
  50  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  51  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  52  *   endpoint rings; it generates events on the event ring for these.
  53  */
  54
  55 #include <linux/scatterlist.h>
  56 #include <linux/slab.h>
  57 #include <linux/dma-mapping.h>
  58 #include "xhci.h"
  59 #include "xhci-trace.h"
  60
  61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
  62                          u32 field1, u32 field2,
  63                          u32 field3, u32 field4, bool command_must_succeed);
  64
  65 /*
  66  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  67  * address of the TRB.
  68  */
  69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  70                 union xhci_trb *trb)
  71 {
  72         unsigned long segment_offset;
  73
  74         if (!seg || !trb || trb < seg->trbs)
  75                 return 0;
  76         /* offset in TRBs */
  77         segment_offset = trb - seg->trbs;
  78         if (segment_offset >= TRBS_PER_SEGMENT)
  79                 return 0;
  80         return seg->dma + (segment_offset * sizeof(*trb));
  81 }
  82
  83 static bool trb_is_noop(union xhci_trb *trb)
  84 {
  85         return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
  86 }
  87
  88 static bool trb_is_link(union xhci_trb *trb)
  89 {
  90         return TRB_TYPE_LINK_LE32(trb->link.control);
  91 }
  92
  93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
  94 {
  95         return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
  96 }
  97
  98 static bool last_trb_on_ring(struct xhci_ring *ring,
  99                         struct xhci_segment *seg, union xhci_trb *trb)
 100 {
 101         return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
 102 }
 103
 104 static bool link_trb_toggles_cycle(union xhci_trb *trb)
 105 {
 106         return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 107 }
 108
 109 static bool last_td_in_urb(struct xhci_td *td)
 110 {
 111         struct urb_priv *urb_priv = td->urb->hcpriv;
 112
 113         return urb_priv->num_tds_done == urb_priv->num_tds;
 114 }
 115
 116 static void inc_td_cnt(struct urb *urb)
 117 {
 118         struct urb_priv *urb_priv = urb->hcpriv;
 119
 120         urb_priv->num_tds_done++;
 121 }
 122
 123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
 124 {
 125         if (trb_is_link(trb)) {
 126                 /* unchain chained link TRBs */
 127                 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
 128         } else {
 129                 trb->generic.field[0] = 0;
 130                 trb->generic.field[1] = 0;
 131                 trb->generic.field[2] = 0;
 132                 /* Preserve only the cycle bit of this TRB */
 133                 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 134                 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
 135         }
 136 }
 137
 138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 139  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 140  * effect the ring dequeue or enqueue pointers.
 141  */
 142 static void next_trb(struct xhci_hcd *xhci,
 143                 struct xhci_ring *ring,
 144                 struct xhci_segment **seg,
 145                 union xhci_trb **trb)
 146 {
 147         if (trb_is_link(*trb)) {
 148                 *seg = (*seg)->next;
 149                 *trb = ((*seg)->trbs);
 150         } else {
 151                 (*trb)++;
 152         }
 153 }
 154
 155 /*
 156  * See Cycle bit rules. SW is the consumer for the event ring only.
 157  */
 158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 159 {
 160         unsigned int link_trb_count = 0;
 161
 162         /* event ring doesn't have link trbs, check for last trb */
 163         if (ring->type == TYPE_EVENT) {
 164                 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 165                         ring->dequeue++;
 166                         goto out;
 167                 }
 168                 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
 169                         ring->cycle_state ^= 1;
 170                 ring->deq_seg = ring->deq_seg->next;
 171                 ring->dequeue = ring->deq_seg->trbs;
 172                 goto out;
 173         }
 174
 175         /* All other rings have link trbs */
 176         if (!trb_is_link(ring->dequeue)) {
 177                 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 178                         xhci_warn(xhci, "Missing link TRB at end of segment\n");
 179                 } else {
 180                         ring->dequeue++;
 181                         ring->num_trbs_free++;
 182                 }
 183         }
 184
 185         while (trb_is_link(ring->dequeue)) {
 186                 ring->deq_seg = ring->deq_seg->next;
 187                 ring->dequeue = ring->deq_seg->trbs;
 188
 189                 if (link_trb_count++ > ring->num_segs) {
 190                         xhci_warn(xhci, "Ring is an endless link TRB loop\n");
 191                         break;
 192                 }
 193         }
 194 out:
 195         trace_xhci_inc_deq(ring);
 196
 197         return;
 198 }
 199
 200 /*
 201  * See Cycle bit rules. SW is the consumer for the event ring only.
 202  *
 203  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 204  * chain bit is set), then set the chain bit in all the following link TRBs.
 205  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 206  * have their chain bit cleared (so that each Link TRB is a separate TD).
 207  *
 208  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 209  * set, but other sections talk about dealing with the chain bit set.  This was
 210  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 211  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 212  *
 213  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 214  *                      prepare_transfer()?
 215  */
 216 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 217                         bool more_trbs_coming)
 218 {
 219         u32 chain;
 220         union xhci_trb *next;
 221         unsigned int link_trb_count = 0;
 222
 223         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 224         /* If this is not event ring, there is one less usable TRB */
 225         if (!trb_is_link(ring->enqueue))
 226                 ring->num_trbs_free--;
 227
 228         if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
 229                 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
 230                 return;
 231         }
 232
 233         next = ++(ring->enqueue);
 234
 235         /* Update the dequeue pointer further if that was a link TRB */
 236         while (trb_is_link(next)) {
 237
 238                 /*
 239                  * If the caller doesn't plan on enqueueing more TDs before
 240                  * ringing the doorbell, then we don't want to give the link TRB
 241                  * to the hardware just yet. We'll give the link TRB back in
 242                  * prepare_ring() just before we enqueue the TD at the top of
 243                  * the ring.
 244                  */
 245                 if (!chain && !more_trbs_coming)
 246                         break;
 247
 248                 /* If we're not dealing with 0.95 hardware or isoc rings on
 249                  * AMD 0.96 host, carry over the chain bit of the previous TRB
 250                  * (which may mean the chain bit is cleared).
 251                  */
 252                 if (!(ring->type == TYPE_ISOC &&
 253                       (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
 254                     !xhci_link_trb_quirk(xhci)) {
 255                         next->link.control &= cpu_to_le32(~TRB_CHAIN);
 256                         next->link.control |= cpu_to_le32(chain);
 257                 }
 258                 /* Give this link TRB to the hardware */
 259                 wmb();
 260                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 261
 262                 /* Toggle the cycle bit after the last ring segment. */
 263                 if (link_trb_toggles_cycle(next))
 264                         ring->cycle_state ^= 1;
 265
 266                 ring->enq_seg = ring->enq_seg->next;
 267                 ring->enqueue = ring->enq_seg->trbs;
 268                 next = ring->enqueue;
 269
 270                 if (link_trb_count++ > ring->num_segs) {
 271                         xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
 272                         break;
 273                 }
 274         }
 275
 276         trace_xhci_inc_enq(ring);
 277 }
 278
 279 /*
 280  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 281  * enqueue pointer will not advance into dequeue segment. See rules above.
 282  */
 283 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 284                 unsigned int num_trbs)
 285 {
 286         int num_trbs_in_deq_seg;
 287
 288         if (ring->num_trbs_free < num_trbs)
 289                 return 0;
 290
 291         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 292                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 293                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 294                         return 0;
 295         }
 296
 297         return 1;
 298 }
 299
 300 /* Ring the host controller doorbell after placing a command on the ring */
 301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 302 {
 303         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 304                 return;
 305
 306         xhci_dbg(xhci, "// Ding dong!\n");
 307
 308         trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
 309
 310         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 311         /* Flush PCI posted writes */
 312         readl(&xhci->dba->doorbell[0]);
 313 }
 314
 315 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
 316 {
 317         return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
 318 }
 319
 320 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 321 {
 322         return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 323                                         cmd_list);
 324 }
 325
 326 /*
 327  * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 328  * If there are other commands waiting then restart the ring and kick the timer.
 329  * This must be called with command ring stopped and xhci->lock held.
 330  */
 331 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 332                                          struct xhci_command *cur_cmd)
 333 {
 334         struct xhci_command *i_cmd;
 335
 336         /* Turn all aborted commands in list to no-ops, then restart */
 337         list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 338
 339                 if (i_cmd->status != COMP_COMMAND_ABORTED)
 340                         continue;
 341
 342                 i_cmd->status = COMP_COMMAND_RING_STOPPED;
 343
 344                 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 345                          i_cmd->command_trb);
 346
 347                 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
 348
 349                 /*
 350                  * caller waiting for completion is called when command
 351                  *  completion event is received for these no-op commands
 352                  */
 353         }
 354
 355         xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 356
 357         /* ring command ring doorbell to restart the command ring */
 358         if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 359             !(xhci->xhc_state & XHCI_STATE_DYING)) {
 360                 xhci->current_cmd = cur_cmd;
 361                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
 362                 xhci_ring_cmd_db(xhci);
 363         }
 364 }
 365
 366 /* Must be called with xhci->lock held, releases and aquires lock back */
 367 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 368 {
 369         struct xhci_segment *new_seg    = xhci->cmd_ring->deq_seg;
 370         union xhci_trb *new_deq         = xhci->cmd_ring->dequeue;
 371         u64 crcr;
 372         int ret;
 373
 374         xhci_dbg(xhci, "Abort command ring\n");
 375
 376         reinit_completion(&xhci->cmd_ring_stop_completion);
 377
 378         /*
 379          * The control bits like command stop, abort are located in lower
 380          * dword of the command ring control register.
 381          * Some controllers require all 64 bits to be written to abort the ring.
 382          * Make sure the upper dword is valid, pointing to the next command,
 383          * avoiding corrupting the command ring pointer in case the command ring
 384          * is stopped by the time the upper dword is written.
 385          */
 386         next_trb(xhci, NULL, &new_seg, &new_deq);
 387         if (trb_is_link(new_deq))
 388                 next_trb(xhci, NULL, &new_seg, &new_deq);
 389
 390         crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
 391         xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
 392
 393         /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
 394          * completion of the Command Abort operation. If CRR is not negated in 5
 395          * seconds then driver handles it as if host died (-ENODEV).
 396          * In the future we should distinguish between -ENODEV and -ETIMEDOUT
 397          * and try to recover a -ETIMEDOUT with a host controller reset.
 398          */
 399         ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 400                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 401         if (ret < 0) {
 402                 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
 403                 xhci_halt(xhci);
 404                 xhci_hc_died(xhci);
 405                 return ret;
 406         }
 407         /*
 408          * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 409          * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 410          * but the completion event in never sent. Wait 2 secs (arbitrary
 411          * number) to handle those cases after negation of CMD_RING_RUNNING.
 412          */
 413         spin_unlock_irqrestore(&xhci->lock, flags);
 414         ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 415                                           msecs_to_jiffies(2000));
 416         spin_lock_irqsave(&xhci->lock, flags);
 417         if (!ret) {
 418                 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 419                 xhci_cleanup_command_queue(xhci);
 420         } else {
 421                 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 422         }
 423         return 0;
 424 }
 425
 426 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 427                 unsigned int slot_id,
 428                 unsigned int ep_index,
 429                 unsigned int stream_id)
 430 {
 431         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 432         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 433         unsigned int ep_state = ep->ep_state;
 434
 435         /* Don't ring the doorbell for this endpoint if there are pending
 436          * cancellations because we don't want to interrupt processing.
 437          * We don't want to restart any stream rings if there's a set dequeue
 438          * pointer command pending because the device can choose to start any
 439          * stream once the endpoint is on the HW schedule.
 440          */
 441         if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 442             (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
 443                 return;
 444
 445         trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
 446
 447         writel(DB_VALUE(ep_index, stream_id), db_addr);
 448         /* flush the write */
 449         readl(db_addr);
 450 }
 451
 452 /* Ring the doorbell for any rings with pending URBs */
 453 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 454                 unsigned int slot_id,
 455                 unsigned int ep_index)
 456 {
 457         unsigned int stream_id;
 458         struct xhci_virt_ep *ep;
 459
 460         ep = &xhci->devs[slot_id]->eps[ep_index];
 461
 462         /* A ring has pending URBs if its TD list is not empty */
 463         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 464                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 465                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 466                 return;
 467         }
 468
 469         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 470                         stream_id++) {
 471                 struct xhci_stream_info *stream_info = ep->stream_info;
 472                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 473                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 474                                                 stream_id);
 475         }
 476 }
 477
 478 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 479                 unsigned int slot_id,
 480                 unsigned int ep_index)
 481 {
 482         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 483 }
 484
 485 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
 486                                              unsigned int slot_id,
 487                                              unsigned int ep_index)
 488 {
 489         if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
 490                 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
 491                 return NULL;
 492         }
 493         if (ep_index >= EP_CTX_PER_DEV) {
 494                 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
 495                 return NULL;
 496         }
 497         if (!xhci->devs[slot_id]) {
 498                 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
 499                 return NULL;
 500         }
 501
 502         return &xhci->devs[slot_id]->eps[ep_index];
 503 }
 504
 505 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
 506                                               struct xhci_virt_ep *ep,
 507                                               unsigned int stream_id)
 508 {
 509         /* common case, no streams */
 510         if (!(ep->ep_state & EP_HAS_STREAMS))
 511                 return ep->ring;
 512
 513         if (!ep->stream_info)
 514                 return NULL;
 515
 516         if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
 517                 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
 518                           stream_id, ep->vdev->slot_id, ep->ep_index);
 519                 return NULL;
 520         }
 521
 522         return ep->stream_info->stream_rings[stream_id];
 523 }
 524
 525 /* Get the right ring for the given slot_id, ep_index and stream_id.
 526  * If the endpoint supports streams, boundary check the URB's stream ID.
 527  * If the endpoint doesn't support streams, return the singular endpoint ring.
 528  */
 529 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 530                 unsigned int slot_id, unsigned int ep_index,
 531                 unsigned int stream_id)
 532 {
 533         struct xhci_virt_ep *ep;
 534
 535         ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
 536         if (!ep)
 537                 return NULL;
 538
 539         return xhci_virt_ep_to_ring(xhci, ep, stream_id);
 540 }
 541
 542
 543 /*
 544  * Get the hw dequeue pointer xHC stopped on, either directly from the
 545  * endpoint context, or if streams are in use from the stream context.
 546  * The returned hw_dequeue contains the lowest four bits with cycle state
 547  * and possbile stream context type.
 548  */
 549 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
 550                            unsigned int ep_index, unsigned int stream_id)
 551 {
 552         struct xhci_ep_ctx *ep_ctx;
 553         struct xhci_stream_ctx *st_ctx;
 554         struct xhci_virt_ep *ep;
 555
 556         ep = &vdev->eps[ep_index];
 557
 558         if (ep->ep_state & EP_HAS_STREAMS) {
 559                 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
 560                 return le64_to_cpu(st_ctx->stream_ring);
 561         }
 562         ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 563         return le64_to_cpu(ep_ctx->deq);
 564 }
 565
 566 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
 567                                 unsigned int slot_id, unsigned int ep_index,
 568                                 unsigned int stream_id, struct xhci_td *td)
 569 {
 570         struct xhci_virt_device *dev = xhci->devs[slot_id];
 571         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 572         struct xhci_ring *ep_ring;
 573         struct xhci_command *cmd;
 574         struct xhci_segment *new_seg;
 575         struct xhci_segment *halted_seg = NULL;
 576         union xhci_trb *new_deq;
 577         int new_cycle;
 578         union xhci_trb *halted_trb;
 579         int index = 0;
 580         dma_addr_t addr;
 581         u64 hw_dequeue;
 582         bool cycle_found = false;
 583         bool td_last_trb_found = false;
 584         u32 trb_sct = 0;
 585         int ret;
 586
 587         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 588                         ep_index, stream_id);
 589         if (!ep_ring) {
 590                 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
 591                           stream_id);
 592                 return -ENODEV;
 593         }
 594         /*
 595          * A cancelled TD can complete with a stall if HW cached the trb.
 596          * In this case driver can't find td, but if the ring is empty we
 597          * can move the dequeue pointer to the current enqueue position.
 598          * We shouldn't hit this anymore as cached cancelled TRBs are given back
 599          * after clearing the cache, but be on the safe side and keep it anyway
 600          */
 601         if (!td) {
 602                 if (list_empty(&ep_ring->td_list)) {
 603                         new_seg = ep_ring->enq_seg;
 604                         new_deq = ep_ring->enqueue;
 605                         new_cycle = ep_ring->cycle_state;
 606                         xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
 607                         goto deq_found;
 608                 } else {
 609                         xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
 610                         return -EINVAL;
 611                 }
 612         }
 613
 614         hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
 615         new_seg = ep_ring->deq_seg;
 616         new_deq = ep_ring->dequeue;
 617
 618         /*
 619          * Quirk: xHC write-back of the DCS field in the hardware dequeue
 620          * pointer is wrong - use the cycle state of the TRB pointed to by
 621          * the dequeue pointer.
 622          */
 623         if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
 624             !(ep->ep_state & EP_HAS_STREAMS))
 625                 halted_seg = trb_in_td(xhci, td->start_seg,
 626                                        td->first_trb, td->last_trb,
 627                                        hw_dequeue & ~0xf, false);
 628         if (halted_seg) {
 629                 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
 630                          sizeof(*halted_trb);
 631                 halted_trb = &halted_seg->trbs[index];
 632                 new_cycle = halted_trb->generic.field[3] & 0x1;
 633                 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
 634                          (u8)(hw_dequeue & 0x1), index, new_cycle);
 635         } else {
 636                 new_cycle = hw_dequeue & 0x1;
 637         }
 638
 639         /*
 640          * We want to find the pointer, segment and cycle state of the new trb
 641          * (the one after current TD's last_trb). We know the cycle state at
 642          * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 643          * found.
 644          */
 645         do {
 646                 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 647                     == (dma_addr_t)(hw_dequeue & ~0xf)) {
 648                         cycle_found = true;
 649                         if (td_last_trb_found)
 650                                 break;
 651                 }
 652                 if (new_deq == td->last_trb)
 653                         td_last_trb_found = true;
 654
 655                 if (cycle_found && trb_is_link(new_deq) &&
 656                     link_trb_toggles_cycle(new_deq))
 657                         new_cycle ^= 0x1;
 658
 659                 next_trb(xhci, ep_ring, &new_seg, &new_deq);
 660
 661                 /* Search wrapped around, bail out */
 662                 if (new_deq == ep->ring->dequeue) {
 663                         xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 664                         return -EINVAL;
 665                 }
 666
 667         } while (!cycle_found || !td_last_trb_found);
 668
 669 deq_found:
 670
 671         /* Don't update the ring cycle state for the producer (us). */
 672         addr = xhci_trb_virt_to_dma(new_seg, new_deq);
 673         if (addr == 0) {
 674                 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
 675                 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
 676                 return -EINVAL;
 677         }
 678
 679         if ((ep->ep_state & SET_DEQ_PENDING)) {
 680                 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
 681                           &addr);
 682                 return -EBUSY;
 683         }
 684
 685         /* This function gets called from contexts where it cannot sleep */
 686         cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
 687         if (!cmd) {
 688                 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
 689                 return -ENOMEM;
 690         }
 691
 692         if (stream_id)
 693                 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
 694         ret = queue_command(xhci, cmd,
 695                 lower_32_bits(addr) | trb_sct | new_cycle,
 696                 upper_32_bits(addr),
 697                 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
 698                 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
 699         if (ret < 0) {
 700                 xhci_free_command(xhci, cmd);
 701                 return ret;
 702         }
 703         ep->queued_deq_seg = new_seg;
 704         ep->queued_deq_ptr = new_deq;
 705
 706         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 707                        "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
 708
 709         /* Stop the TD queueing code from ringing the doorbell until
 710          * this command completes.  The HC won't set the dequeue pointer
 711          * if the ring is running, and ringing the doorbell starts the
 712          * ring running.
 713          */
 714         ep->ep_state |= SET_DEQ_PENDING;
 715         xhci_ring_cmd_db(xhci);
 716         return 0;
 717 }
 718
 719 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 720  * (The last TRB actually points to the ring enqueue pointer, which is not part
 721  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 722  */
 723 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 724                        struct xhci_td *td, bool flip_cycle)
 725 {
 726         struct xhci_segment *seg        = td->start_seg;
 727         union xhci_trb *trb             = td->first_trb;
 728
 729         while (1) {
 730                 trb_to_noop(trb, TRB_TR_NOOP);
 731
 732                 /* flip cycle if asked to */
 733                 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
 734                         trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
 735
 736                 if (trb == td->last_trb)
 737                         break;
 738
 739                 next_trb(xhci, ep_ring, &seg, &trb);
 740         }
 741 }
 742
 743 /*
 744  * Must be called with xhci->lock held in interrupt context,
 745  * releases and re-acquires xhci->lock
 746  */
 747 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 748                                      struct xhci_td *cur_td, int status)
 749 {
 750         struct urb      *urb            = cur_td->urb;
 751         struct urb_priv *urb_priv       = urb->hcpriv;
 752         struct usb_hcd  *hcd            = bus_to_hcd(urb->dev->bus);
 753
 754         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 755                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 756                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 757                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
 758                                 usb_amd_quirk_pll_enable();
 759                 }
 760         }
 761         xhci_urb_free_priv(urb_priv);
 762         usb_hcd_unlink_urb_from_ep(hcd, urb);
 763         trace_xhci_urb_giveback(urb);
 764         usb_hcd_giveback_urb(hcd, urb, status);
 765 }
 766
 767 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 768                 struct xhci_ring *ring, struct xhci_td *td)
 769 {
 770         struct device *dev = xhci_to_hcd(xhci)->self.controller;
 771         struct xhci_segment *seg = td->bounce_seg;
 772         struct urb *urb = td->urb;
 773         size_t len;
 774
 775         if (!ring || !seg || !urb)
 776                 return;
 777
 778         if (usb_urb_dir_out(urb)) {
 779                 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 780                                  DMA_TO_DEVICE);
 781                 return;
 782         }
 783
 784         dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 785                          DMA_FROM_DEVICE);
 786         /* for in tranfers we need to copy the data from bounce to sg */
 787         if (urb->num_sgs) {
 788                 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
 789                                            seg->bounce_len, seg->bounce_offs);
 790                 if (len != seg->bounce_len)
 791                         xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
 792                                   len, seg->bounce_len);
 793         } else {
 794                 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
 795                        seg->bounce_len);
 796         }
 797         seg->bounce_len = 0;
 798         seg->bounce_offs = 0;
 799 }
 800
 801 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
 802                            struct xhci_ring *ep_ring, int status)
 803 {
 804         struct urb *urb = NULL;
 805
 806         /* Clean up the endpoint's TD list */
 807         urb = td->urb;
 808
 809         /* if a bounce buffer was used to align this td then unmap it */
 810         xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
 811
 812         /* Do one last check of the actual transfer length.
 813          * If the host controller said we transferred more data than the buffer
 814          * length, urb->actual_length will be a very big number (since it's
 815          * unsigned).  Play it safe and say we didn't transfer anything.
 816          */
 817         if (urb->actual_length > urb->transfer_buffer_length) {
 818                 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
 819                           urb->transfer_buffer_length, urb->actual_length);
 820                 urb->actual_length = 0;
 821                 status = 0;
 822         }
 823         /* TD might be removed from td_list if we are giving back a cancelled URB */
 824         if (!list_empty(&td->td_list))
 825                 list_del_init(&td->td_list);
 826         /* Giving back a cancelled URB, or if a slated TD completed anyway */
 827         if (!list_empty(&td->cancelled_td_list))
 828                 list_del_init(&td->cancelled_td_list);
 829
 830         inc_td_cnt(urb);
 831         /* Giveback the urb when all the tds are completed */
 832         if (last_td_in_urb(td)) {
 833                 if ((urb->actual_length != urb->transfer_buffer_length &&
 834                      (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
 835                     (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
 836                         xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
 837                                  urb, urb->actual_length,
 838                                  urb->transfer_buffer_length, status);
 839
 840                 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
 841                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
 842                         status = 0;
 843                 xhci_giveback_urb_in_irq(xhci, td, status);
 844         }
 845
 846         return 0;
 847 }
 848
 849
 850 /* Complete the cancelled URBs we unlinked from td_list. */
 851 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
 852 {
 853         struct xhci_ring *ring;
 854         struct xhci_td *td, *tmp_td;
 855
 856         list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
 857                                  cancelled_td_list) {
 858
 859                 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
 860
 861                 if (td->cancel_status == TD_CLEARED) {
 862                         xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
 863                                  __func__, td->urb);
 864                         xhci_td_cleanup(ep->xhci, td, ring, td->status);
 865                 } else {
 866                         xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
 867                                  __func__, td->urb, td->cancel_status);
 868                 }
 869                 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
 870                         return;
 871         }
 872 }
 873
 874 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
 875                                 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
 876 {
 877         struct xhci_command *command;
 878         int ret = 0;
 879
 880         command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
 881         if (!command) {
 882                 ret = -ENOMEM;
 883                 goto done;
 884         }
 885
 886         xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
 887                  (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
 888                  ep_index, slot_id);
 889
 890         ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
 891 done:
 892         if (ret)
 893                 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
 894                          slot_id, ep_index, ret);
 895         return ret;
 896 }
 897
 898 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
 899                                 struct xhci_virt_ep *ep,
 900                                 struct xhci_td *td,
 901                                 enum xhci_ep_reset_type reset_type)
 902 {
 903         unsigned int slot_id = ep->vdev->slot_id;
 904         int err;
 905
 906         /*
 907          * Avoid resetting endpoint if link is inactive. Can cause host hang.
 908          * Device will be reset soon to recover the link so don't do anything
 909          */
 910         if (ep->vdev->flags & VDEV_PORT_ERROR)
 911                 return -ENODEV;
 912
 913         /* add td to cancelled list and let reset ep handler take care of it */
 914         if (reset_type == EP_HARD_RESET) {
 915                 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
 916                 if (td && list_empty(&td->cancelled_td_list)) {
 917                         list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
 918                         td->cancel_status = TD_HALTED;
 919                 }
 920         }
 921
 922         if (ep->ep_state & EP_HALTED) {
 923                 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
 924                          ep->ep_index);
 925                 return 0;
 926         }
 927
 928         err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
 929         if (err)
 930                 return err;
 931
 932         ep->ep_state |= EP_HALTED;
 933
 934         xhci_ring_cmd_db(xhci);
 935
 936         return 0;
 937 }
 938
 939 /*
 940  * Fix up the ep ring first, so HW stops executing cancelled TDs.
 941  * We have the xHCI lock, so nothing can modify this list until we drop it.
 942  * We're also in the event handler, so we can't get re-interrupted if another
 943  * Stop Endpoint command completes.
 944  *
 945  * only call this when ring is not in a running state
 946  */
 947
 948 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
 949 {
 950         struct xhci_hcd         *xhci;
 951         struct xhci_td          *td = NULL;
 952         struct xhci_td          *tmp_td = NULL;
 953         struct xhci_td          *cached_td = NULL;
 954         struct xhci_ring        *ring;
 955         u64                     hw_deq;
 956         unsigned int            slot_id = ep->vdev->slot_id;
 957         int                     err;
 958
 959         xhci = ep->xhci;
 960
 961         list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
 962                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 963                                "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
 964                                (unsigned long long)xhci_trb_virt_to_dma(
 965                                        td->start_seg, td->first_trb),
 966                                td->urb->stream_id, td->urb);
 967                 list_del_init(&td->td_list);
 968                 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
 969                 if (!ring) {
 970                         xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
 971                                   td->urb, td->urb->stream_id);
 972                         continue;
 973                 }
 974                 /*
 975                  * If a ring stopped on the TD we need to cancel then we have to
 976                  * move the xHC endpoint ring dequeue pointer past this TD.
 977                  * Rings halted due to STALL may show hw_deq is past the stalled
 978                  * TD, but still require a set TR Deq command to flush xHC cache.
 979                  */
 980                 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
 981                                          td->urb->stream_id);
 982                 hw_deq &= ~0xf;
 983
 984                 if (td->cancel_status == TD_HALTED ||
 985                     trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
 986                         switch (td->cancel_status) {
 987                         case TD_CLEARED: /* TD is already no-op */
 988                         case TD_CLEARING_CACHE: /* set TR deq command already queued */
 989                                 break;
 990                         case TD_DIRTY: /* TD is cached, clear it */
 991                         case TD_HALTED:
 992                                 td->cancel_status = TD_CLEARING_CACHE;
 993                                 if (cached_td)
 994                                         /* FIXME  stream case, several stopped rings */
 995                                         xhci_dbg(xhci,
 996                                                  "Move dq past stream %u URB %p instead of stream %u URB %p\n",
 997                                                  td->urb->stream_id, td->urb,
 998                                                  cached_td->urb->stream_id, cached_td->urb);
 999                                 cached_td = td;
1000                                 break;
1001                         }
1002                 } else {
1003                         td_to_noop(xhci, ring, td, false);
1004                         td->cancel_status = TD_CLEARED;
1005                 }
1006         }
1007
1008         /* If there's no need to move the dequeue pointer then we're done */
1009         if (!cached_td)
1010                 return 0;
1011
1012         err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1013                                         cached_td->urb->stream_id,
1014                                         cached_td);
1015         if (err) {
1016                 /* Failed to move past cached td, just set cached TDs to no-op */
1017                 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1018                         if (td->cancel_status != TD_CLEARING_CACHE)
1019                                 continue;
1020                         xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1021                                  td->urb);
1022                         td_to_noop(xhci, ring, td, false);
1023                         td->cancel_status = TD_CLEARED;
1024                 }
1025         }
1026         return 0;
1027 }
1028
1029 /*
1030  * Returns the TD the endpoint ring halted on.
1031  * Only call for non-running rings without streams.
1032  */
1033 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1034 {
1035         struct xhci_td  *td;
1036         u64             hw_deq;
1037
1038         if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1039                 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1040                 hw_deq &= ~0xf;
1041                 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1042                 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1043                                 td->last_trb, hw_deq, false))
1044                         return td;
1045         }
1046         return NULL;
1047 }
1048
1049 /*
1050  * When we get a command completion for a Stop Endpoint Command, we need to
1051  * unlink any cancelled TDs from the ring.  There are two ways to do that:
1052  *
1053  *  1. If the HW was in the middle of processing the TD that needs to be
1054  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
1055  *     in the TD with a Set Dequeue Pointer Command.
1056  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1057  *     bit cleared) so that the HW will skip over them.
1058  */
1059 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1060                                     union xhci_trb *trb, u32 comp_code)
1061 {
1062         unsigned int ep_index;
1063         struct xhci_virt_ep *ep;
1064         struct xhci_ep_ctx *ep_ctx;
1065         struct xhci_td *td = NULL;
1066         enum xhci_ep_reset_type reset_type;
1067         struct xhci_command *command;
1068         int err;
1069
1070         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1071                 if (!xhci->devs[slot_id])
1072                         xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1073                                   slot_id);
1074                 return;
1075         }
1076
1077         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1078         ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1079         if (!ep)
1080                 return;
1081
1082         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1083
1084         trace_xhci_handle_cmd_stop_ep(ep_ctx);
1085
1086         if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1087         /*
1088          * If stop endpoint command raced with a halting endpoint we need to
1089          * reset the host side endpoint first.
1090          * If the TD we halted on isn't cancelled the TD should be given back
1091          * with a proper error code, and the ring dequeue moved past the TD.
1092          * If streams case we can't find hw_deq, or the TD we halted on so do a
1093          * soft reset.
1094          *
1095          * Proper error code is unknown here, it would be -EPIPE if device side
1096          * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1097          * We use -EPROTO, if device is stalled it should return a stall error on
1098          * next transfer, which then will return -EPIPE, and device side stall is
1099          * noted and cleared by class driver.
1100          */
1101                 switch (GET_EP_CTX_STATE(ep_ctx)) {
1102                 case EP_STATE_HALTED:
1103                         xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1104                         if (ep->ep_state & EP_HAS_STREAMS) {
1105                                 reset_type = EP_SOFT_RESET;
1106                         } else {
1107                                 reset_type = EP_HARD_RESET;
1108                                 td = find_halted_td(ep);
1109                                 if (td)
1110                                         td->status = -EPROTO;
1111                         }
1112                         /* reset ep, reset handler cleans up cancelled tds */
1113                         err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1114                         if (err)
1115                                 break;
1116                         ep->ep_state &= ~EP_STOP_CMD_PENDING;
1117                         return;
1118                 case EP_STATE_RUNNING:
1119                         /* Race, HW handled stop ep cmd before ep was running */
1120                         xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1121
1122                         command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1123                         if (!command) {
1124                                 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1125                                 return;
1126                         }
1127                         xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1128                         xhci_ring_cmd_db(xhci);
1129
1130                         return;
1131                 default:
1132                         break;
1133                 }
1134         }
1135
1136         /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1137         xhci_invalidate_cancelled_tds(ep);
1138         ep->ep_state &= ~EP_STOP_CMD_PENDING;
1139
1140         /* Otherwise ring the doorbell(s) to restart queued transfers */
1141         xhci_giveback_invalidated_tds(ep);
1142         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143 }
1144
1145 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1146 {
1147         struct xhci_td *cur_td;
1148         struct xhci_td *tmp;
1149
1150         list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1151                 list_del_init(&cur_td->td_list);
1152
1153                 if (!list_empty(&cur_td->cancelled_td_list))
1154                         list_del_init(&cur_td->cancelled_td_list);
1155
1156                 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1157
1158                 inc_td_cnt(cur_td->urb);
1159                 if (last_td_in_urb(cur_td))
1160                         xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1161         }
1162 }
1163
1164 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1165                 int slot_id, int ep_index)
1166 {
1167         struct xhci_td *cur_td;
1168         struct xhci_td *tmp;
1169         struct xhci_virt_ep *ep;
1170         struct xhci_ring *ring;
1171
1172         ep = &xhci->devs[slot_id]->eps[ep_index];
1173         if ((ep->ep_state & EP_HAS_STREAMS) ||
1174                         (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1175                 int stream_id;
1176
1177                 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1178                                 stream_id++) {
1179                         ring = ep->stream_info->stream_rings[stream_id];
1180                         if (!ring)
1181                                 continue;
1182
1183                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1184                                         "Killing URBs for slot ID %u, ep index %u, stream %u",
1185                                         slot_id, ep_index, stream_id);
1186                         xhci_kill_ring_urbs(xhci, ring);
1187                 }
1188         } else {
1189                 ring = ep->ring;
1190                 if (!ring)
1191                         return;
1192                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1193                                 "Killing URBs for slot ID %u, ep index %u",
1194                                 slot_id, ep_index);
1195                 xhci_kill_ring_urbs(xhci, ring);
1196         }
1197
1198         list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1199                         cancelled_td_list) {
1200                 list_del_init(&cur_td->cancelled_td_list);
1201                 inc_td_cnt(cur_td->urb);
1202
1203                 if (last_td_in_urb(cur_td))
1204                         xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1205         }
1206 }
1207
1208 /*
1209  * host controller died, register read returns 0xffffffff
1210  * Complete pending commands, mark them ABORTED.
1211  * URBs need to be given back as usb core might be waiting with device locks
1212  * held for the URBs to finish during device disconnect, blocking host remove.
1213  *
1214  * Call with xhci->lock held.
1215  * lock is relased and re-acquired while giving back urb.
1216  */
1217 void xhci_hc_died(struct xhci_hcd *xhci)
1218 {
1219         int i, j;
1220
1221         if (xhci->xhc_state & XHCI_STATE_DYING)
1222                 return;
1223
1224         xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1225         xhci->xhc_state |= XHCI_STATE_DYING;
1226
1227         xhci_cleanup_command_queue(xhci);
1228
1229         /* return any pending urbs, remove may be waiting for them */
1230         for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1231                 if (!xhci->devs[i])
1232                         continue;
1233                 for (j = 0; j < 31; j++)
1234                         xhci_kill_endpoint_urbs(xhci, i, j);
1235         }
1236
1237         /* inform usb core hc died if PCI remove isn't already handling it */
1238         if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1239                 usb_hc_died(xhci_to_hcd(xhci));
1240 }
1241
1242 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1243                 struct xhci_virt_device *dev,
1244                 struct xhci_ring *ep_ring,
1245                 unsigned int ep_index)
1246 {
1247         union xhci_trb *dequeue_temp;
1248         int num_trbs_free_temp;
1249         bool revert = false;
1250
1251         num_trbs_free_temp = ep_ring->num_trbs_free;
1252         dequeue_temp = ep_ring->dequeue;
1253
1254         /* If we get two back-to-back stalls, and the first stalled transfer
1255          * ends just before a link TRB, the dequeue pointer will be left on
1256          * the link TRB by the code in the while loop.  So we have to update
1257          * the dequeue pointer one segment further, or we'll jump off
1258          * the segment into la-la-land.
1259          */
1260         if (trb_is_link(ep_ring->dequeue)) {
1261                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1262                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1263         }
1264
1265         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1266                 /* We have more usable TRBs */
1267                 ep_ring->num_trbs_free++;
1268                 ep_ring->dequeue++;
1269                 if (trb_is_link(ep_ring->dequeue)) {
1270                         if (ep_ring->dequeue ==
1271                                         dev->eps[ep_index].queued_deq_ptr)
1272                                 break;
1273                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1274                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1275                 }
1276                 if (ep_ring->dequeue == dequeue_temp) {
1277                         revert = true;
1278                         break;
1279                 }
1280         }
1281
1282         if (revert) {
1283                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1284                 ep_ring->num_trbs_free = num_trbs_free_temp;
1285         }
1286 }
1287
1288 /*
1289  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1290  * we need to clear the set deq pending flag in the endpoint ring state, so that
1291  * the TD queueing code can ring the doorbell again.  We also need to ring the
1292  * endpoint doorbell to restart the ring, but only if there aren't more
1293  * cancellations pending.
1294  */
1295 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1296                 union xhci_trb *trb, u32 cmd_comp_code)
1297 {
1298         unsigned int ep_index;
1299         unsigned int stream_id;
1300         struct xhci_ring *ep_ring;
1301         struct xhci_virt_ep *ep;
1302         struct xhci_ep_ctx *ep_ctx;
1303         struct xhci_slot_ctx *slot_ctx;
1304         struct xhci_td *td, *tmp_td;
1305
1306         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1307         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1308         ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1309         if (!ep)
1310                 return;
1311
1312         ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1313         if (!ep_ring) {
1314                 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1315                                 stream_id);
1316                 /* XXX: Harmless??? */
1317                 goto cleanup;
1318         }
1319
1320         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1321         slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1322         trace_xhci_handle_cmd_set_deq(slot_ctx);
1323         trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1324
1325         if (cmd_comp_code != COMP_SUCCESS) {
1326                 unsigned int ep_state;
1327                 unsigned int slot_state;
1328
1329                 switch (cmd_comp_code) {
1330                 case COMP_TRB_ERROR:
1331                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1332                         break;
1333                 case COMP_CONTEXT_STATE_ERROR:
1334                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1335                         ep_state = GET_EP_CTX_STATE(ep_ctx);
1336                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1337                         slot_state = GET_SLOT_STATE(slot_state);
1338                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1339                                         "Slot state = %u, EP state = %u",
1340                                         slot_state, ep_state);
1341                         break;
1342                 case COMP_SLOT_NOT_ENABLED_ERROR:
1343                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1344                                         slot_id);
1345                         break;
1346                 default:
1347                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1348                                         cmd_comp_code);
1349                         break;
1350                 }
1351                 /* OK what do we do now?  The endpoint state is hosed, and we
1352                  * should never get to this point if the synchronization between
1353                  * queueing, and endpoint state are correct.  This might happen
1354                  * if the device gets disconnected after we've finished
1355                  * cancelling URBs, which might not be an error...
1356                  */
1357         } else {
1358                 u64 deq;
1359                 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1360                 if (ep->ep_state & EP_HAS_STREAMS) {
1361                         struct xhci_stream_ctx *ctx =
1362                                 &ep->stream_info->stream_ctx_array[stream_id];
1363                         deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1364                 } else {
1365                         deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1366                 }
1367                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1368                         "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1369                 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1370                                          ep->queued_deq_ptr) == deq) {
1371                         /* Update the ring's dequeue segment and dequeue pointer
1372                          * to reflect the new position.
1373                          */
1374                         update_ring_for_set_deq_completion(xhci, ep->vdev,
1375                                 ep_ring, ep_index);
1376                 } else {
1377                         xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1378                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1379                                   ep->queued_deq_seg, ep->queued_deq_ptr);
1380                 }
1381         }
1382         /* HW cached TDs cleared from cache, give them back */
1383         list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1384                                  cancelled_td_list) {
1385                 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1386                 if (td->cancel_status == TD_CLEARING_CACHE) {
1387                         td->cancel_status = TD_CLEARED;
1388                         xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1389                                  __func__, td->urb);
1390                         xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1391                 } else {
1392                         xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1393                                  __func__, td->urb, td->cancel_status);
1394                 }
1395         }
1396 cleanup:
1397         ep->ep_state &= ~SET_DEQ_PENDING;
1398         ep->queued_deq_seg = NULL;
1399         ep->queued_deq_ptr = NULL;
1400         /* Restart any rings with pending URBs */
1401         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1402 }
1403
1404 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1405                 union xhci_trb *trb, u32 cmd_comp_code)
1406 {
1407         struct xhci_virt_ep *ep;
1408         struct xhci_ep_ctx *ep_ctx;
1409         unsigned int ep_index;
1410
1411         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1412         ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1413         if (!ep)
1414                 return;
1415
1416         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1417         trace_xhci_handle_cmd_reset_ep(ep_ctx);
1418
1419         /* This command will only fail if the endpoint wasn't halted,
1420          * but we don't care.
1421          */
1422         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1423                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1424
1425         /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1426         xhci_invalidate_cancelled_tds(ep);
1427
1428         /* Clear our internal halted state */
1429         ep->ep_state &= ~EP_HALTED;
1430
1431         xhci_giveback_invalidated_tds(ep);
1432
1433         /* if this was a soft reset, then restart */
1434         if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1435                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1436 }
1437
1438 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1439                 struct xhci_command *command, u32 cmd_comp_code)
1440 {
1441         if (cmd_comp_code == COMP_SUCCESS)
1442                 command->slot_id = slot_id;
1443         else
1444                 command->slot_id = 0;
1445 }
1446
1447 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1448 {
1449         struct xhci_virt_device *virt_dev;
1450         struct xhci_slot_ctx *slot_ctx;
1451
1452         virt_dev = xhci->devs[slot_id];
1453         if (!virt_dev)
1454                 return;
1455
1456         slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1457         trace_xhci_handle_cmd_disable_slot(slot_ctx);
1458
1459         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1460                 /* Delete default control endpoint resources */
1461                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1462 }
1463
1464 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1465                 u32 cmd_comp_code)
1466 {
1467         struct xhci_virt_device *virt_dev;
1468         struct xhci_input_control_ctx *ctrl_ctx;
1469         struct xhci_ep_ctx *ep_ctx;
1470         unsigned int ep_index;
1471         u32 add_flags;
1472
1473         /*
1474          * Configure endpoint commands can come from the USB core configuration
1475          * or alt setting changes, or when streams were being configured.
1476          */
1477
1478         virt_dev = xhci->devs[slot_id];
1479         if (!virt_dev)
1480                 return;
1481         ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1482         if (!ctrl_ctx) {
1483                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1484                 return;
1485         }
1486
1487         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1488
1489         /* Input ctx add_flags are the endpoint index plus one */
1490         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1491
1492         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1493         trace_xhci_handle_cmd_config_ep(ep_ctx);
1494
1495         return;
1496 }
1497
1498 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1499 {
1500         struct xhci_virt_device *vdev;
1501         struct xhci_slot_ctx *slot_ctx;
1502
1503         vdev = xhci->devs[slot_id];
1504         if (!vdev)
1505                 return;
1506         slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1507         trace_xhci_handle_cmd_addr_dev(slot_ctx);
1508 }
1509
1510 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1511 {
1512         struct xhci_virt_device *vdev;
1513         struct xhci_slot_ctx *slot_ctx;
1514
1515         vdev = xhci->devs[slot_id];
1516         if (!vdev) {
1517                 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1518                           slot_id);
1519                 return;
1520         }
1521         slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1522         trace_xhci_handle_cmd_reset_dev(slot_ctx);
1523
1524         xhci_dbg(xhci, "Completed reset device command.\n");
1525 }
1526
1527 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1528                 struct xhci_event_cmd *event)
1529 {
1530         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1531                 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1532                 return;
1533         }
1534         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1535                         "NEC firmware version %2x.%02x",
1536                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1537                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1538 }
1539
1540 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1541 {
1542         list_del(&cmd->cmd_list);
1543
1544         if (cmd->completion) {
1545                 cmd->status = status;
1546                 complete(cmd->completion);
1547         } else {
1548                 kfree(cmd);
1549         }
1550 }
1551
1552 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1553 {
1554         struct xhci_command *cur_cmd, *tmp_cmd;
1555         xhci->current_cmd = NULL;
1556         list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1557                 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1558 }
1559
1560 void xhci_handle_command_timeout(struct work_struct *work)
1561 {
1562         struct xhci_hcd *xhci;
1563         unsigned long   flags;
1564         char            str[XHCI_MSG_MAX];
1565         u64             hw_ring_state;
1566         u32             cmd_field3;
1567         u32             usbsts;
1568
1569         xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1570
1571         spin_lock_irqsave(&xhci->lock, flags);
1572
1573         /*
1574          * If timeout work is pending, or current_cmd is NULL, it means we
1575          * raced with command completion. Command is handled so just return.
1576          */
1577         if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1578                 spin_unlock_irqrestore(&xhci->lock, flags);
1579                 return;
1580         }
1581
1582         cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1583         usbsts = readl(&xhci->op_regs->status);
1584         xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1585
1586         /* Bail out and tear down xhci if a stop endpoint command failed */
1587         if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1588                 struct xhci_virt_ep     *ep;
1589
1590                 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1591
1592                 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1593                                       TRB_TO_EP_INDEX(cmd_field3));
1594                 if (ep)
1595                         ep->ep_state &= ~EP_STOP_CMD_PENDING;
1596
1597                 xhci_halt(xhci);
1598                 xhci_hc_died(xhci);
1599                 goto time_out_completed;
1600         }
1601
1602         /* mark this command to be cancelled */
1603         xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1604
1605         /* Make sure command ring is running before aborting it */
1606         hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1607         if (hw_ring_state == ~(u64)0) {
1608                 xhci_hc_died(xhci);
1609                 goto time_out_completed;
1610         }
1611
1612         if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1613             (hw_ring_state & CMD_RING_RUNNING))  {
1614                 /* Prevent new doorbell, and start command abort */
1615                 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1616                 xhci_dbg(xhci, "Command timeout\n");
1617                 xhci_abort_cmd_ring(xhci, flags);
1618                 goto time_out_completed;
1619         }
1620
1621         /* host removed. Bail out */
1622         if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1623                 xhci_dbg(xhci, "host removed, ring start fail?\n");
1624                 xhci_cleanup_command_queue(xhci);
1625
1626                 goto time_out_completed;
1627         }
1628
1629         /* command timeout on stopped ring, ring can't be aborted */
1630         xhci_dbg(xhci, "Command timeout on stopped ring\n");
1631         xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1632
1633 time_out_completed:
1634         spin_unlock_irqrestore(&xhci->lock, flags);
1635         return;
1636 }
1637
1638 static void handle_cmd_completion(struct xhci_hcd *xhci,
1639                 struct xhci_event_cmd *event)
1640 {
1641         unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1642         u64 cmd_dma;
1643         dma_addr_t cmd_dequeue_dma;
1644         u32 cmd_comp_code;
1645         union xhci_trb *cmd_trb;
1646         struct xhci_command *cmd;
1647         u32 cmd_type;
1648
1649         if (slot_id >= MAX_HC_SLOTS) {
1650                 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1651                 return;
1652         }
1653
1654         cmd_dma = le64_to_cpu(event->cmd_trb);
1655         cmd_trb = xhci->cmd_ring->dequeue;
1656
1657         trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1658
1659         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1660                         cmd_trb);
1661         /*
1662          * Check whether the completion event is for our internal kept
1663          * command.
1664          */
1665         if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1666                 xhci_warn(xhci,
1667                           "ERROR mismatched command completion event\n");
1668                 return;
1669         }
1670
1671         cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1672
1673         cancel_delayed_work(&xhci->cmd_timer);
1674
1675         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1676
1677         /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1678         if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1679                 complete_all(&xhci->cmd_ring_stop_completion);
1680                 return;
1681         }
1682
1683         if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1684                 xhci_err(xhci,
1685                          "Command completion event does not match command\n");
1686                 return;
1687         }
1688
1689         /*
1690          * Host aborted the command ring, check if the current command was
1691          * supposed to be aborted, otherwise continue normally.
1692          * The command ring is stopped now, but the xHC will issue a Command
1693          * Ring Stopped event which will cause us to restart it.
1694          */
1695         if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1696                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1697                 if (cmd->status == COMP_COMMAND_ABORTED) {
1698                         if (xhci->current_cmd == cmd)
1699                                 xhci->current_cmd = NULL;
1700                         goto event_handled;
1701                 }
1702         }
1703
1704         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1705         switch (cmd_type) {
1706         case TRB_ENABLE_SLOT:
1707                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1708                 break;
1709         case TRB_DISABLE_SLOT:
1710                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1711                 break;
1712         case TRB_CONFIG_EP:
1713                 if (!cmd->completion)
1714                         xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1715                 break;
1716         case TRB_EVAL_CONTEXT:
1717                 break;
1718         case TRB_ADDR_DEV:
1719                 xhci_handle_cmd_addr_dev(xhci, slot_id);
1720                 break;
1721         case TRB_STOP_RING:
1722                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1723                                 le32_to_cpu(cmd_trb->generic.field[3])));
1724                 if (!cmd->completion)
1725                         xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1726                                                 cmd_comp_code);
1727                 break;
1728         case TRB_SET_DEQ:
1729                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1730                                 le32_to_cpu(cmd_trb->generic.field[3])));
1731                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1732                 break;
1733         case TRB_CMD_NOOP:
1734                 /* Is this an aborted command turned to NO-OP? */
1735                 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1736                         cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1737                 break;
1738         case TRB_RESET_EP:
1739                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1740                                 le32_to_cpu(cmd_trb->generic.field[3])));
1741                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1742                 break;
1743         case TRB_RESET_DEV:
1744                 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1745                  * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1746                  */
1747                 slot_id = TRB_TO_SLOT_ID(
1748                                 le32_to_cpu(cmd_trb->generic.field[3]));
1749                 xhci_handle_cmd_reset_dev(xhci, slot_id);
1750                 break;
1751         case TRB_NEC_GET_FW:
1752                 xhci_handle_cmd_nec_get_fw(xhci, event);
1753                 break;
1754         default:
1755                 /* Skip over unknown commands on the event ring */
1756                 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1757                 break;
1758         }
1759
1760         /* restart timer if this wasn't the last command */
1761         if (!list_is_singular(&xhci->cmd_list)) {
1762                 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1763                                                 struct xhci_command, cmd_list);
1764                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1765         } else if (xhci->current_cmd == cmd) {
1766                 xhci->current_cmd = NULL;
1767         }
1768
1769 event_handled:
1770         xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1771
1772         inc_deq(xhci, xhci->cmd_ring);
1773 }
1774
1775 static void handle_vendor_event(struct xhci_hcd *xhci,
1776                                 union xhci_trb *event, u32 trb_type)
1777 {
1778         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1779         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1780                 handle_cmd_completion(xhci, &event->event_cmd);
1781 }
1782
1783 static void handle_device_notification(struct xhci_hcd *xhci,
1784                 union xhci_trb *event)
1785 {
1786         u32 slot_id;
1787         struct usb_device *udev;
1788
1789         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1790         if (!xhci->devs[slot_id]) {
1791                 xhci_warn(xhci, "Device Notification event for "
1792                                 "unused slot %u\n", slot_id);
1793                 return;
1794         }
1795
1796         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1797                         slot_id);
1798         udev = xhci->devs[slot_id]->udev;
1799         if (udev && udev->parent)
1800                 usb_wakeup_notification(udev->parent, udev->portnum);
1801 }
1802
1803 /*
1804  * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1805  * Controller.
1806  * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1807  * If a connection to a USB 1 device is followed by another connection
1808  * to a USB 2 device.
1809  *
1810  * Reset the PHY after the USB device is disconnected if device speed
1811  * is less than HCD_USB3.
1812  * Retry the reset sequence max of 4 times checking the PLL lock status.
1813  *
1814  */
1815 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1816 {
1817         struct usb_hcd *hcd = xhci_to_hcd(xhci);
1818         u32 pll_lock_check;
1819         u32 retry_count = 4;
1820
1821         do {
1822                 /* Assert PHY reset */
1823                 writel(0x6F, hcd->regs + 0x1048);
1824                 udelay(10);
1825                 /* De-assert the PHY reset */
1826                 writel(0x7F, hcd->regs + 0x1048);
1827                 udelay(200);
1828                 pll_lock_check = readl(hcd->regs + 0x1070);
1829         } while (!(pll_lock_check & 0x1) && --retry_count);
1830 }
1831
1832 static void handle_port_status(struct xhci_hcd *xhci,
1833                 union xhci_trb *event)
1834 {
1835         struct usb_hcd *hcd;
1836         u32 port_id;
1837         u32 portsc, cmd_reg;
1838         int max_ports;
1839         int slot_id;
1840         unsigned int hcd_portnum;
1841         struct xhci_bus_state *bus_state;
1842         bool bogus_port_status = false;
1843         struct xhci_port *port;
1844
1845         /* Port status change events always have a successful completion code */
1846         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1847                 xhci_warn(xhci,
1848                           "WARN: xHC returned failed port status event\n");
1849
1850         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1851         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1852
1853         if ((port_id <= 0) || (port_id > max_ports)) {
1854                 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1855                           port_id);
1856                 inc_deq(xhci, xhci->event_ring);
1857                 return;
1858         }
1859
1860         port = &xhci->hw_ports[port_id - 1];
1861         if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1862                 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1863                           port_id);
1864                 bogus_port_status = true;
1865                 goto cleanup;
1866         }
1867
1868         /* We might get interrupts after shared_hcd is removed */
1869         if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1870                 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1871                 bogus_port_status = true;
1872                 goto cleanup;
1873         }
1874
1875         hcd = port->rhub->hcd;
1876         bus_state = &port->rhub->bus_state;
1877         hcd_portnum = port->hcd_portnum;
1878         portsc = readl(port->addr);
1879
1880         xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1881                  hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1882
1883         trace_xhci_handle_port_status(hcd_portnum, portsc);
1884
1885         if (hcd->state == HC_STATE_SUSPENDED) {
1886                 xhci_dbg(xhci, "resume root hub\n");
1887                 usb_hcd_resume_root_hub(hcd);
1888         }
1889
1890         if (hcd->speed >= HCD_USB3 &&
1891             (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1892                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1893                 if (slot_id && xhci->devs[slot_id])
1894                         xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1895         }
1896
1897         if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1898                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1899
1900                 cmd_reg = readl(&xhci->op_regs->command);
1901                 if (!(cmd_reg & CMD_RUN)) {
1902                         xhci_warn(xhci, "xHC is not running.\n");
1903                         goto cleanup;
1904                 }
1905
1906                 if (DEV_SUPERSPEED_ANY(portsc)) {
1907                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1908                         /* Set a flag to say the port signaled remote wakeup,
1909                          * so we can tell the difference between the end of
1910                          * device and host initiated resume.
1911                          */
1912                         bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1913                         xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1914                         usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1915                         xhci_set_link_state(xhci, port, XDEV_U0);
1916                         /* Need to wait until the next link state change
1917                          * indicates the device is actually in U0.
1918                          */
1919                         bogus_port_status = true;
1920                         goto cleanup;
1921                 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1922                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1923                         bus_state->resume_done[hcd_portnum] = jiffies +
1924                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1925                         set_bit(hcd_portnum, &bus_state->resuming_ports);
1926                         /* Do the rest in GetPortStatus after resume time delay.
1927                          * Avoid polling roothub status before that so that a
1928                          * usb device auto-resume latency around ~40ms.
1929                          */
1930                         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1931                         mod_timer(&hcd->rh_timer,
1932                                   bus_state->resume_done[hcd_portnum]);
1933                         usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1934                         bogus_port_status = true;
1935                 }
1936         }
1937
1938         if ((portsc & PORT_PLC) &&
1939             DEV_SUPERSPEED_ANY(portsc) &&
1940             ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1941              (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1942              (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1943                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1944                 complete(&bus_state->u3exit_done[hcd_portnum]);
1945                 /* We've just brought the device into U0/1/2 through either the
1946                  * Resume state after a device remote wakeup, or through the
1947                  * U3Exit state after a host-initiated resume.  If it's a device
1948                  * initiated remote wake, don't pass up the link state change,
1949                  * so the roothub behavior is consistent with external
1950                  * USB 3.0 hub behavior.
1951                  */
1952                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1953                 if (slot_id && xhci->devs[slot_id])
1954                         xhci_ring_device(xhci, slot_id);
1955                 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1956                         xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1957                         usb_wakeup_notification(hcd->self.root_hub,
1958                                         hcd_portnum + 1);
1959                         bogus_port_status = true;
1960                         goto cleanup;
1961                 }
1962         }
1963
1964         /*
1965          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1966          * RExit to a disconnect state).  If so, let the driver know it's
1967          * out of the RExit state.
1968          */
1969         if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1970                         test_and_clear_bit(hcd_portnum,
1971                                 &bus_state->rexit_ports)) {
1972                 complete(&bus_state->rexit_done[hcd_portnum]);
1973                 bogus_port_status = true;
1974                 goto cleanup;
1975         }
1976
1977         if (hcd->speed < HCD_USB3) {
1978                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1979                 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1980                     (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1981                         xhci_cavium_reset_phy_quirk(xhci);
1982         }
1983
1984 cleanup:
1985         /* Update event ring dequeue pointer before dropping the lock */
1986         inc_deq(xhci, xhci->event_ring);
1987
1988         /* Don't make the USB core poll the roothub if we got a bad port status
1989          * change event.  Besides, at that point we can't tell which roothub
1990          * (USB 2.0 or USB 3.0) to kick.
1991          */
1992         if (bogus_port_status)
1993                 return;
1994
1995         /*
1996          * xHCI port-status-change events occur when the "or" of all the
1997          * status-change bits in the portsc register changes from 0 to 1.
1998          * New status changes won't cause an event if any other change
1999          * bits are still set.  When an event occurs, switch over to
2000          * polling to avoid losing status changes.
2001          */
2002         xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2003                  __func__, hcd->self.busnum);
2004         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2005         spin_unlock(&xhci->lock);
2006         /* Pass this up to the core */
2007         usb_hcd_poll_rh_status(hcd);
2008         spin_lock(&xhci->lock);
2009 }
2010
2011 /*
2012  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2013  * at end_trb, which may be in another segment.  If the suspect DMA address is a
2014  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
2015  * returns 0.
2016  */
2017 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2018                 struct xhci_segment *start_seg,
2019                 union xhci_trb  *start_trb,
2020                 union xhci_trb  *end_trb,
2021                 dma_addr_t      suspect_dma,
2022                 bool            debug)
2023 {
2024         dma_addr_t start_dma;
2025         dma_addr_t end_seg_dma;
2026         dma_addr_t end_trb_dma;
2027         struct xhci_segment *cur_seg;
2028
2029         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2030         cur_seg = start_seg;
2031
2032         do {
2033                 if (start_dma == 0)
2034                         return NULL;
2035                 /* We may get an event for a Link TRB in the middle of a TD */
2036                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2037                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2038                 /* If the end TRB isn't in this segment, this is set to 0 */
2039                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2040
2041                 if (debug)
2042                         xhci_warn(xhci,
2043                                 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2044                                 (unsigned long long)suspect_dma,
2045                                 (unsigned long long)start_dma,
2046                                 (unsigned long long)end_trb_dma,
2047                                 (unsigned long long)cur_seg->dma,
2048                                 (unsigned long long)end_seg_dma);
2049
2050                 if (end_trb_dma > 0) {
2051                         /* The end TRB is in this segment, so suspect should be here */
2052                         if (start_dma <= end_trb_dma) {
2053                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2054                                         return cur_seg;
2055                         } else {
2056                                 /* Case for one segment with
2057                                  * a TD wrapped around to the top
2058                                  */
2059                                 if ((suspect_dma >= start_dma &&
2060                                                         suspect_dma <= end_seg_dma) ||
2061                                                 (suspect_dma >= cur_seg->dma &&
2062                                                  suspect_dma <= end_trb_dma))
2063                                         return cur_seg;
2064                         }
2065                         return NULL;
2066                 } else {
2067                         /* Might still be somewhere in this segment */
2068                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2069                                 return cur_seg;
2070                 }
2071                 cur_seg = cur_seg->next;
2072                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2073         } while (cur_seg != start_seg);
2074
2075         return NULL;
2076 }
2077
2078 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2079                 struct xhci_virt_ep *ep)
2080 {
2081         /*
2082          * As part of low/full-speed endpoint-halt processing
2083          * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2084          */
2085         if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2086             (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2087             !(ep->ep_state & EP_CLEARING_TT)) {
2088                 ep->ep_state |= EP_CLEARING_TT;
2089                 td->urb->ep->hcpriv = td->urb->dev;
2090                 if (usb_hub_clear_tt_buffer(td->urb))
2091                         ep->ep_state &= ~EP_CLEARING_TT;
2092         }
2093 }
2094
2095 /* Check if an error has halted the endpoint ring.  The class driver will
2096  * cleanup the halt for a non-default control endpoint if we indicate a stall.
2097  * However, a babble and other errors also halt the endpoint ring, and the class
2098  * driver won't clear the halt in that case, so we need to issue a Set Transfer
2099  * Ring Dequeue Pointer command manually.
2100  */
2101 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2102                 struct xhci_ep_ctx *ep_ctx,
2103                 unsigned int trb_comp_code)
2104 {
2105         /* TRB completion codes that may require a manual halt cleanup */
2106         if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2107                         trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2108                         trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2109                 /* The 0.95 spec says a babbling control endpoint
2110                  * is not halted. The 0.96 spec says it is.  Some HW
2111                  * claims to be 0.95 compliant, but it halts the control
2112                  * endpoint anyway.  Check if a babble halted the
2113                  * endpoint.
2114                  */
2115                 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2116                         return 1;
2117
2118         return 0;
2119 }
2120
2121 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2122 {
2123         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2124                 /* Vendor defined "informational" completion code,
2125                  * treat as not-an-error.
2126                  */
2127                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2128                                 trb_comp_code);
2129                 xhci_dbg(xhci, "Treating code as success.\n");
2130                 return 1;
2131         }
2132         return 0;
2133 }
2134
2135 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2136                      struct xhci_ring *ep_ring, struct xhci_td *td,
2137                      u32 trb_comp_code)
2138 {
2139         struct xhci_ep_ctx *ep_ctx;
2140
2141         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2142
2143         switch (trb_comp_code) {
2144         case COMP_STOPPED_LENGTH_INVALID:
2145         case COMP_STOPPED_SHORT_PACKET:
2146         case COMP_STOPPED:
2147                 /*
2148                  * The "Stop Endpoint" completion will take care of any
2149                  * stopped TDs. A stopped TD may be restarted, so don't update
2150                  * the ring dequeue pointer or take this TD off any lists yet.
2151                  */
2152                 return 0;
2153         case COMP_USB_TRANSACTION_ERROR:
2154         case COMP_BABBLE_DETECTED_ERROR:
2155         case COMP_SPLIT_TRANSACTION_ERROR:
2156                 /*
2157                  * If endpoint context state is not halted we might be
2158                  * racing with a reset endpoint command issued by a unsuccessful
2159                  * stop endpoint completion (context error). In that case the
2160                  * td should be on the cancelled list, and EP_HALTED flag set.
2161                  *
2162                  * Or then it's not halted due to the 0.95 spec stating that a
2163                  * babbling control endpoint should not halt. The 0.96 spec
2164                  * again says it should.  Some HW claims to be 0.95 compliant,
2165                  * but it halts the control endpoint anyway.
2166                  */
2167                 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2168                         /*
2169                          * If EP_HALTED is set and TD is on the cancelled list
2170                          * the TD and dequeue pointer will be handled by reset
2171                          * ep command completion
2172                          */
2173                         if ((ep->ep_state & EP_HALTED) &&
2174                             !list_empty(&td->cancelled_td_list)) {
2175                                 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2176                                          (unsigned long long)xhci_trb_virt_to_dma(
2177                                                  td->start_seg, td->first_trb));
2178                                 return 0;
2179                         }
2180                         /* endpoint not halted, don't reset it */
2181                         break;
2182                 }
2183                 /* Almost same procedure as for STALL_ERROR below */
2184                 xhci_clear_hub_tt_buffer(xhci, td, ep);
2185                 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2186                 return 0;
2187         case COMP_STALL_ERROR:
2188                 /*
2189                  * xhci internal endpoint state will go to a "halt" state for
2190                  * any stall, including default control pipe protocol stall.
2191                  * To clear the host side halt we need to issue a reset endpoint
2192                  * command, followed by a set dequeue command to move past the
2193                  * TD.
2194                  * Class drivers clear the device side halt from a functional
2195                  * stall later. Hub TT buffer should only be cleared for FS/LS
2196                  * devices behind HS hubs for functional stalls.
2197                  */
2198                 if (ep->ep_index != 0)
2199                         xhci_clear_hub_tt_buffer(xhci, td, ep);
2200
2201                 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2202
2203                 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2204         default:
2205                 break;
2206         }
2207
2208         /* Update ring dequeue pointer */
2209         ep_ring->dequeue = td->last_trb;
2210         ep_ring->deq_seg = td->last_trb_seg;
2211         ep_ring->num_trbs_free += td->num_trbs - 1;
2212         inc_deq(xhci, ep_ring);
2213
2214         return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2215 }
2216
2217 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2218 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2219                            union xhci_trb *stop_trb)
2220 {
2221         u32 sum;
2222         union xhci_trb *trb = ring->dequeue;
2223         struct xhci_segment *seg = ring->deq_seg;
2224
2225         for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2226                 if (!trb_is_noop(trb) && !trb_is_link(trb))
2227                         sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2228         }
2229         return sum;
2230 }
2231
2232 /*
2233  * Process control tds, update urb status and actual_length.
2234  */
2235 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2236                 struct xhci_ring *ep_ring,  struct xhci_td *td,
2237                            union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2238 {
2239         struct xhci_ep_ctx *ep_ctx;
2240         u32 trb_comp_code;
2241         u32 remaining, requested;
2242         u32 trb_type;
2243
2244         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2245         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2246         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2247         requested = td->urb->transfer_buffer_length;
2248         remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2249
2250         switch (trb_comp_code) {
2251         case COMP_SUCCESS:
2252                 if (trb_type != TRB_STATUS) {
2253                         xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2254                                   (trb_type == TRB_DATA) ? "data" : "setup");
2255                         td->status = -ESHUTDOWN;
2256                         break;
2257                 }
2258                 td->status = 0;
2259                 break;
2260         case COMP_SHORT_PACKET:
2261                 td->status = 0;
2262                 break;
2263         case COMP_STOPPED_SHORT_PACKET:
2264                 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2265                         td->urb->actual_length = remaining;
2266                 else
2267                         xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2268                 goto finish_td;
2269         case COMP_STOPPED:
2270                 switch (trb_type) {
2271                 case TRB_SETUP:
2272                         td->urb->actual_length = 0;
2273                         goto finish_td;
2274                 case TRB_DATA:
2275                 case TRB_NORMAL:
2276                         td->urb->actual_length = requested - remaining;
2277                         goto finish_td;
2278                 case TRB_STATUS:
2279                         td->urb->actual_length = requested;
2280                         goto finish_td;
2281                 default:
2282                         xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2283                                   trb_type);
2284                         goto finish_td;
2285                 }
2286         case COMP_STOPPED_LENGTH_INVALID:
2287                 goto finish_td;
2288         default:
2289                 if (!xhci_requires_manual_halt_cleanup(xhci,
2290                                                        ep_ctx, trb_comp_code))
2291                         break;
2292                 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2293                          trb_comp_code, ep->ep_index);
2294                 fallthrough;
2295         case COMP_STALL_ERROR:
2296                 /* Did we transfer part of the data (middle) phase? */
2297                 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2298                         td->urb->actual_length = requested - remaining;
2299                 else if (!td->urb_length_set)
2300                         td->urb->actual_length = 0;
2301                 goto finish_td;
2302         }
2303
2304         /* stopped at setup stage, no data transferred */
2305         if (trb_type == TRB_SETUP)
2306                 goto finish_td;
2307
2308         /*
2309          * if on data stage then update the actual_length of the URB and flag it
2310          * as set, so it won't be overwritten in the event for the last TRB.
2311          */
2312         if (trb_type == TRB_DATA ||
2313                 trb_type == TRB_NORMAL) {
2314                 td->urb_length_set = true;
2315                 td->urb->actual_length = requested - remaining;
2316                 xhci_dbg(xhci, "Waiting for status stage event\n");
2317                 return 0;
2318         }
2319
2320         /* at status stage */
2321         if (!td->urb_length_set)
2322                 td->urb->actual_length = requested;
2323
2324 finish_td:
2325         return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2326 }
2327
2328 /*
2329  * Process isochronous tds, update urb packet status and actual_length.
2330  */
2331 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2332                 struct xhci_ring *ep_ring, struct xhci_td *td,
2333                 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2334 {
2335         struct urb_priv *urb_priv;
2336         int idx;
2337         struct usb_iso_packet_descriptor *frame;
2338         u32 trb_comp_code;
2339         bool sum_trbs_for_length = false;
2340         u32 remaining, requested, ep_trb_len;
2341         int short_framestatus;
2342
2343         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2344         urb_priv = td->urb->hcpriv;
2345         idx = urb_priv->num_tds_done;
2346         frame = &td->urb->iso_frame_desc[idx];
2347         requested = frame->length;
2348         remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2349         ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2350         short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2351                 -EREMOTEIO : 0;
2352
2353         /* handle completion code */
2354         switch (trb_comp_code) {
2355         case COMP_SUCCESS:
2356                 if (remaining) {
2357                         frame->status = short_framestatus;
2358                         if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2359                                 sum_trbs_for_length = true;
2360                         break;
2361                 }
2362                 frame->status = 0;
2363                 break;
2364         case COMP_SHORT_PACKET:
2365                 frame->status = short_framestatus;
2366                 sum_trbs_for_length = true;
2367                 break;
2368         case COMP_BANDWIDTH_OVERRUN_ERROR:
2369                 frame->status = -ECOMM;
2370                 break;
2371         case COMP_ISOCH_BUFFER_OVERRUN:
2372         case COMP_BABBLE_DETECTED_ERROR:
2373                 frame->status = -EOVERFLOW;
2374                 break;
2375         case COMP_INCOMPATIBLE_DEVICE_ERROR:
2376         case COMP_STALL_ERROR:
2377                 frame->status = -EPROTO;
2378                 break;
2379         case COMP_USB_TRANSACTION_ERROR:
2380                 frame->status = -EPROTO;
2381                 if (ep_trb != td->last_trb)
2382                         return 0;
2383                 break;
2384         case COMP_STOPPED:
2385                 sum_trbs_for_length = true;
2386                 break;
2387         case COMP_STOPPED_SHORT_PACKET:
2388                 /* field normally containing residue now contains tranferred */
2389                 frame->status = short_framestatus;
2390                 requested = remaining;
2391                 break;
2392         case COMP_STOPPED_LENGTH_INVALID:
2393                 requested = 0;
2394                 remaining = 0;
2395                 break;
2396         default:
2397                 sum_trbs_for_length = true;
2398                 frame->status = -1;
2399                 break;
2400         }
2401
2402         if (sum_trbs_for_length)
2403                 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2404                         ep_trb_len - remaining;
2405         else
2406                 frame->actual_length = requested;
2407
2408         td->urb->actual_length += frame->actual_length;
2409
2410         return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2411 }
2412
2413 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2414                         struct xhci_virt_ep *ep, int status)
2415 {
2416         struct urb_priv *urb_priv;
2417         struct usb_iso_packet_descriptor *frame;
2418         int idx;
2419
2420         urb_priv = td->urb->hcpriv;
2421         idx = urb_priv->num_tds_done;
2422         frame = &td->urb->iso_frame_desc[idx];
2423
2424         /* The transfer is partly done. */
2425         frame->status = -EXDEV;
2426
2427         /* calc actual length */
2428         frame->actual_length = 0;
2429
2430         /* Update ring dequeue pointer */
2431         ep->ring->dequeue = td->last_trb;
2432         ep->ring->deq_seg = td->last_trb_seg;
2433         ep->ring->num_trbs_free += td->num_trbs - 1;
2434         inc_deq(xhci, ep->ring);
2435
2436         return xhci_td_cleanup(xhci, td, ep->ring, status);
2437 }
2438
2439 /*
2440  * Process bulk and interrupt tds, update urb status and actual_length.
2441  */
2442 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2443                 struct xhci_ring *ep_ring, struct xhci_td *td,
2444                 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2445 {
2446         struct xhci_slot_ctx *slot_ctx;
2447         u32 trb_comp_code;
2448         u32 remaining, requested, ep_trb_len;
2449
2450         slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2451         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2452         remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2453         ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2454         requested = td->urb->transfer_buffer_length;
2455
2456         switch (trb_comp_code) {
2457         case COMP_SUCCESS:
2458                 ep->err_count = 0;
2459                 /* handle success with untransferred data as short packet */
2460                 if (ep_trb != td->last_trb || remaining) {
2461                         xhci_warn(xhci, "WARN Successful completion on short TX\n");
2462                         xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2463                                  td->urb->ep->desc.bEndpointAddress,
2464                                  requested, remaining);
2465                 }
2466                 td->status = 0;
2467                 break;
2468         case COMP_SHORT_PACKET:
2469                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2470                          td->urb->ep->desc.bEndpointAddress,
2471                          requested, remaining);
2472                 td->status = 0;
2473                 break;
2474         case COMP_STOPPED_SHORT_PACKET:
2475                 td->urb->actual_length = remaining;
2476                 goto finish_td;
2477         case COMP_STOPPED_LENGTH_INVALID:
2478                 /* stopped on ep trb with invalid length, exclude it */
2479                 ep_trb_len      = 0;
2480                 remaining       = 0;
2481                 break;
2482         case COMP_USB_TRANSACTION_ERROR:
2483                 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2484                     (ep->err_count++ > MAX_SOFT_RETRY) ||
2485                     le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2486                         break;
2487
2488                 td->status = 0;
2489
2490                 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2491                 return 0;
2492         default:
2493                 /* do nothing */
2494                 break;
2495         }
2496
2497         if (ep_trb == td->last_trb)
2498                 td->urb->actual_length = requested - remaining;
2499         else
2500                 td->urb->actual_length =
2501                         sum_trb_lengths(xhci, ep_ring, ep_trb) +
2502                         ep_trb_len - remaining;
2503 finish_td:
2504         if (remaining > requested) {
2505                 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2506                           remaining);
2507                 td->urb->actual_length = 0;
2508         }
2509
2510         return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2511 }
2512
2513 /*
2514  * If this function returns an error condition, it means it got a Transfer
2515  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2516  * At this point, the host controller is probably hosed and should be reset.
2517  */
2518 static int handle_tx_event(struct xhci_hcd *xhci,
2519                 struct xhci_transfer_event *event)
2520 {
2521         struct xhci_virt_ep *ep;
2522         struct xhci_ring *ep_ring;
2523         unsigned int slot_id;
2524         int ep_index;
2525         struct xhci_td *td = NULL;
2526         dma_addr_t ep_trb_dma;
2527         struct xhci_segment *ep_seg;
2528         union xhci_trb *ep_trb;
2529         int status = -EINPROGRESS;
2530         struct xhci_ep_ctx *ep_ctx;
2531         struct list_head *tmp;
2532         u32 trb_comp_code;
2533         int td_num = 0;
2534         bool handling_skipped_tds = false;
2535
2536         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2537         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2538         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2539         ep_trb_dma = le64_to_cpu(event->buffer);
2540
2541         ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2542         if (!ep) {
2543                 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2544                 goto err_out;
2545         }
2546
2547         ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2548         ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2549
2550         if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2551                 xhci_err(xhci,
2552                          "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2553                           slot_id, ep_index);
2554                 goto err_out;
2555         }
2556
2557         /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2558         if (!ep_ring) {
2559                 switch (trb_comp_code) {
2560                 case COMP_STALL_ERROR:
2561                 case COMP_USB_TRANSACTION_ERROR:
2562                 case COMP_INVALID_STREAM_TYPE_ERROR:
2563                 case COMP_INVALID_STREAM_ID_ERROR:
2564                         xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2565                                  ep_index);
2566                         if (ep->err_count++ > MAX_SOFT_RETRY)
2567                                 xhci_handle_halted_endpoint(xhci, ep, NULL,
2568                                                             EP_HARD_RESET);
2569                         else
2570                                 xhci_handle_halted_endpoint(xhci, ep, NULL,
2571                                                             EP_SOFT_RESET);
2572                         goto cleanup;
2573                 case COMP_RING_UNDERRUN:
2574                 case COMP_RING_OVERRUN:
2575                 case COMP_STOPPED_LENGTH_INVALID:
2576                         goto cleanup;
2577                 default:
2578                         xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2579                                  slot_id, ep_index);
2580                         goto err_out;
2581                 }
2582         }
2583
2584         /* Count current td numbers if ep->skip is set */
2585         if (ep->skip) {
2586                 list_for_each(tmp, &ep_ring->td_list)
2587                         td_num++;
2588         }
2589
2590         /* Look for common error cases */
2591         switch (trb_comp_code) {
2592         /* Skip codes that require special handling depending on
2593          * transfer type
2594          */
2595         case COMP_SUCCESS:
2596                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2597                         break;
2598                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2599                     ep_ring->last_td_was_short)
2600                         trb_comp_code = COMP_SHORT_PACKET;
2601                 else
2602                         xhci_warn_ratelimited(xhci,
2603                                               "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2604                                               slot_id, ep_index);
2605                 break;
2606         case COMP_SHORT_PACKET:
2607                 break;
2608         /* Completion codes for endpoint stopped state */
2609         case COMP_STOPPED:
2610                 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2611                          slot_id, ep_index);
2612                 break;
2613         case COMP_STOPPED_LENGTH_INVALID:
2614                 xhci_dbg(xhci,
2615                          "Stopped on No-op or Link TRB for slot %u ep %u\n",
2616                          slot_id, ep_index);
2617                 break;
2618         case COMP_STOPPED_SHORT_PACKET:
2619                 xhci_dbg(xhci,
2620                          "Stopped with short packet transfer detected for slot %u ep %u\n",
2621                          slot_id, ep_index);
2622                 break;
2623         /* Completion codes for endpoint halted state */
2624         case COMP_STALL_ERROR:
2625                 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2626                          ep_index);
2627                 status = -EPIPE;
2628                 break;
2629         case COMP_SPLIT_TRANSACTION_ERROR:
2630                 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2631                          slot_id, ep_index);
2632                 status = -EPROTO;
2633                 break;
2634         case COMP_USB_TRANSACTION_ERROR:
2635                 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2636                          slot_id, ep_index);
2637                 status = -EPROTO;
2638                 break;
2639         case COMP_BABBLE_DETECTED_ERROR:
2640                 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2641                          slot_id, ep_index);
2642                 status = -EOVERFLOW;
2643                 break;
2644         /* Completion codes for endpoint error state */
2645         case COMP_TRB_ERROR:
2646                 xhci_warn(xhci,
2647                           "WARN: TRB error for slot %u ep %u on endpoint\n",
2648                           slot_id, ep_index);
2649                 status = -EILSEQ;
2650                 break;
2651         /* completion codes not indicating endpoint state change */
2652         case COMP_DATA_BUFFER_ERROR:
2653                 xhci_warn(xhci,
2654                           "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2655                           slot_id, ep_index);
2656                 status = -ENOSR;
2657                 break;
2658         case COMP_BANDWIDTH_OVERRUN_ERROR:
2659                 xhci_warn(xhci,
2660                           "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2661                           slot_id, ep_index);
2662                 break;
2663         case COMP_ISOCH_BUFFER_OVERRUN:
2664                 xhci_warn(xhci,
2665                           "WARN: buffer overrun event for slot %u ep %u on endpoint",
2666                           slot_id, ep_index);
2667                 break;
2668         case COMP_RING_UNDERRUN:
2669                 /*
2670                  * When the Isoch ring is empty, the xHC will generate
2671                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2672                  * Underrun Event for OUT Isoch endpoint.
2673                  */
2674                 xhci_dbg(xhci, "underrun event on endpoint\n");
2675                 if (!list_empty(&ep_ring->td_list))
2676                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2677                                         "still with TDs queued?\n",
2678                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2679                                  ep_index);
2680                 goto cleanup;
2681         case COMP_RING_OVERRUN:
2682                 xhci_dbg(xhci, "overrun event on endpoint\n");
2683                 if (!list_empty(&ep_ring->td_list))
2684                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2685                                         "still with TDs queued?\n",
2686                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2687                                  ep_index);
2688                 goto cleanup;
2689         case COMP_MISSED_SERVICE_ERROR:
2690                 /*
2691                  * When encounter missed service error, one or more isoc tds
2692                  * may be missed by xHC.
2693                  * Set skip flag of the ep_ring; Complete the missed tds as
2694                  * short transfer when process the ep_ring next time.
2695                  */
2696                 ep->skip = true;
2697                 xhci_dbg(xhci,
2698                          "Miss service interval error for slot %u ep %u, set skip flag\n",
2699                          slot_id, ep_index);
2700                 goto cleanup;
2701         case COMP_NO_PING_RESPONSE_ERROR:
2702                 ep->skip = true;
2703                 xhci_dbg(xhci,
2704                          "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2705                          slot_id, ep_index);
2706                 goto cleanup;
2707
2708         case COMP_INCOMPATIBLE_DEVICE_ERROR:
2709                 /* needs disable slot command to recover */
2710                 xhci_warn(xhci,
2711                           "WARN: detect an incompatible device for slot %u ep %u",
2712                           slot_id, ep_index);
2713                 status = -EPROTO;
2714                 break;
2715         default:
2716                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2717                         status = 0;
2718                         break;
2719                 }
2720                 xhci_warn(xhci,
2721                           "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2722                           trb_comp_code, slot_id, ep_index);
2723                 goto cleanup;
2724         }
2725
2726         do {
2727                 /* This TRB should be in the TD at the head of this ring's
2728                  * TD list.
2729                  */
2730                 if (list_empty(&ep_ring->td_list)) {
2731                         /*
2732                          * Don't print wanings if it's due to a stopped endpoint
2733                          * generating an extra completion event if the device
2734                          * was suspended. Or, a event for the last TRB of a
2735                          * short TD we already got a short event for.
2736                          * The short TD is already removed from the TD list.
2737                          */
2738
2739                         if (!(trb_comp_code == COMP_STOPPED ||
2740                               trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2741                               ep_ring->last_td_was_short)) {
2742                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2743                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2744                                                 ep_index);
2745                         }
2746                         if (ep->skip) {
2747                                 ep->skip = false;
2748                                 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2749                                          slot_id, ep_index);
2750                         }
2751                         if (trb_comp_code == COMP_STALL_ERROR ||
2752                             xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2753                                                               trb_comp_code)) {
2754                                 xhci_handle_halted_endpoint(xhci, ep, NULL,
2755                                                             EP_HARD_RESET);
2756                         }
2757                         goto cleanup;
2758                 }
2759
2760                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2761                 if (ep->skip && td_num == 0) {
2762                         ep->skip = false;
2763                         xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2764                                  slot_id, ep_index);
2765                         goto cleanup;
2766                 }
2767
2768                 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2769                                       td_list);
2770                 if (ep->skip)
2771                         td_num--;
2772
2773                 /* Is this a TRB in the currently executing TD? */
2774                 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2775                                 td->last_trb, ep_trb_dma, false);
2776
2777                 /*
2778                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2779                  * is not in the current TD pointed by ep_ring->dequeue because
2780                  * that the hardware dequeue pointer still at the previous TRB
2781                  * of the current TD. The previous TRB maybe a Link TD or the
2782                  * last TRB of the previous TD. The command completion handle
2783                  * will take care the rest.
2784                  */
2785                 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2786                            trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2787                         goto cleanup;
2788                 }
2789
2790                 if (!ep_seg) {
2791                         if (!ep->skip ||
2792                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2793                                 /* Some host controllers give a spurious
2794                                  * successful event after a short transfer.
2795                                  * Ignore it.
2796                                  */
2797                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2798                                                 ep_ring->last_td_was_short) {
2799                                         ep_ring->last_td_was_short = false;
2800                                         goto cleanup;
2801                                 }
2802                                 /* HC is busted, give up! */
2803                                 xhci_err(xhci,
2804                                         "ERROR Transfer event TRB DMA ptr not "
2805                                         "part of current TD ep_index %d "
2806                                         "comp_code %u\n", ep_index,
2807                                         trb_comp_code);
2808                                 trb_in_td(xhci, ep_ring->deq_seg,
2809                                           ep_ring->dequeue, td->last_trb,
2810                                           ep_trb_dma, true);
2811                                 return -ESHUTDOWN;
2812                         }
2813
2814                         skip_isoc_td(xhci, td, ep, status);
2815                         goto cleanup;
2816                 }
2817                 if (trb_comp_code == COMP_SHORT_PACKET)
2818                         ep_ring->last_td_was_short = true;
2819                 else
2820                         ep_ring->last_td_was_short = false;
2821
2822                 if (ep->skip) {
2823                         xhci_dbg(xhci,
2824                                  "Found td. Clear skip flag for slot %u ep %u.\n",
2825                                  slot_id, ep_index);
2826                         ep->skip = false;
2827                 }
2828
2829                 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2830                                                 sizeof(*ep_trb)];
2831
2832                 trace_xhci_handle_transfer(ep_ring,
2833                                 (struct xhci_generic_trb *) ep_trb);
2834
2835                 /*
2836                  * No-op TRB could trigger interrupts in a case where
2837                  * a URB was killed and a STALL_ERROR happens right
2838                  * after the endpoint ring stopped. Reset the halted
2839                  * endpoint. Otherwise, the endpoint remains stalled
2840                  * indefinitely.
2841                  */
2842
2843                 if (trb_is_noop(ep_trb)) {
2844                         if (trb_comp_code == COMP_STALL_ERROR ||
2845                             xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2846                                                               trb_comp_code))
2847                                 xhci_handle_halted_endpoint(xhci, ep, td,
2848                                                             EP_HARD_RESET);
2849                         goto cleanup;
2850                 }
2851
2852                 td->status = status;
2853
2854                 /* update the urb's actual_length and give back to the core */
2855                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2856                         process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2857                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2858                         process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2859                 else
2860                         process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2861 cleanup:
2862                 handling_skipped_tds = ep->skip &&
2863                         trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2864                         trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2865
2866                 /*
2867                  * Do not update event ring dequeue pointer if we're in a loop
2868                  * processing missed tds.
2869                  */
2870                 if (!handling_skipped_tds)
2871                         inc_deq(xhci, xhci->event_ring);
2872
2873         /*
2874          * If ep->skip is set, it means there are missed tds on the
2875          * endpoint ring need to take care of.
2876          * Process them as short transfer until reach the td pointed by
2877          * the event.
2878          */
2879         } while (handling_skipped_tds);
2880
2881         return 0;
2882
2883 err_out:
2884         xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2885                  (unsigned long long) xhci_trb_virt_to_dma(
2886                          xhci->event_ring->deq_seg,
2887                          xhci->event_ring->dequeue),
2888                  lower_32_bits(le64_to_cpu(event->buffer)),
2889                  upper_32_bits(le64_to_cpu(event->buffer)),
2890                  le32_to_cpu(event->transfer_len),
2891                  le32_to_cpu(event->flags));
2892         return -ENODEV;
2893 }
2894
2895 /*
2896  * This function handles all OS-owned events on the event ring.  It may drop
2897  * xhci->lock between event processing (e.g. to pass up port status changes).
2898  * Returns >0 for "possibly more events to process" (caller should call again),
2899  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2900  */
2901 static int xhci_handle_event(struct xhci_hcd *xhci)
2902 {
2903         union xhci_trb *event;
2904         int update_ptrs = 1;
2905         u32 trb_type;
2906         int ret;
2907
2908         /* Event ring hasn't been allocated yet. */
2909         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2910                 xhci_err(xhci, "ERROR event ring not ready\n");
2911                 return -ENOMEM;
2912         }
2913
2914         event = xhci->event_ring->dequeue;
2915         /* Does the HC or OS own the TRB? */
2916         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2917             xhci->event_ring->cycle_state)
2918                 return 0;
2919
2920         trace_xhci_handle_event(xhci->event_ring, &event->generic);
2921
2922         /*
2923          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2924          * speculative reads of the event's flags/data below.
2925          */
2926         rmb();
2927         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2928         /* FIXME: Handle more event types. */
2929
2930         switch (trb_type) {
2931         case TRB_COMPLETION:
2932                 handle_cmd_completion(xhci, &event->event_cmd);
2933                 break;
2934         case TRB_PORT_STATUS:
2935                 handle_port_status(xhci, event);
2936                 update_ptrs = 0;
2937                 break;
2938         case TRB_TRANSFER:
2939                 ret = handle_tx_event(xhci, &event->trans_event);
2940                 if (ret >= 0)
2941                         update_ptrs = 0;
2942                 break;
2943         case TRB_DEV_NOTE:
2944                 handle_device_notification(xhci, event);
2945                 break;
2946         default:
2947                 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2948                         handle_vendor_event(xhci, event, trb_type);
2949                 else
2950                         xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2951         }
2952         /* Any of the above functions may drop and re-acquire the lock, so check
2953          * to make sure a watchdog timer didn't mark the host as non-responsive.
2954          */
2955         if (xhci->xhc_state & XHCI_STATE_DYING) {
2956                 xhci_dbg(xhci, "xHCI host dying, returning from "
2957                                 "event handler.\n");
2958                 return 0;
2959         }
2960
2961         if (update_ptrs)
2962                 /* Update SW event ring dequeue pointer */
2963                 inc_deq(xhci, xhci->event_ring);
2964
2965         /* Are there more items on the event ring?  Caller will call us again to
2966          * check.
2967          */
2968         return 1;
2969 }
2970
2971 /*
2972  * Update Event Ring Dequeue Pointer:
2973  * - When all events have finished
2974  * - To avoid "Event Ring Full Error" condition
2975  */
2976 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2977                 union xhci_trb *event_ring_deq)
2978 {
2979         u64 temp_64;
2980         dma_addr_t deq;
2981
2982         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2983         /* If necessary, update the HW's version of the event ring deq ptr. */
2984         if (event_ring_deq != xhci->event_ring->dequeue) {
2985                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2986                                 xhci->event_ring->dequeue);
2987                 if (deq == 0)
2988                         xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2989                 /*
2990                  * Per 4.9.4, Software writes to the ERDP register shall
2991                  * always advance the Event Ring Dequeue Pointer value.
2992                  */
2993                 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2994                                 ((u64) deq & (u64) ~ERST_PTR_MASK))
2995                         return;
2996
2997                 /* Update HC event ring dequeue pointer */
2998                 temp_64 &= ERST_PTR_MASK;
2999                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3000         }
3001
3002         /* Clear the event handler busy flag (RW1C) */
3003         temp_64 |= ERST_EHB;
3004         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3005 }
3006
3007 /*
3008  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3009  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
3010  * indicators of an event TRB error, but we check the status *first* to be safe.
3011  */
3012 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3013 {
3014         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3015         union xhci_trb *event_ring_deq;
3016         irqreturn_t ret = IRQ_NONE;
3017         u64 temp_64;
3018         u32 status;
3019         int event_loop = 0;
3020
3021         spin_lock(&xhci->lock);
3022         /* Check if the xHC generated the interrupt, or the irq is shared */
3023         status = readl(&xhci->op_regs->status);
3024         if (status == ~(u32)0) {
3025                 xhci_hc_died(xhci);
3026                 ret = IRQ_HANDLED;
3027                 goto out;
3028         }
3029
3030         if (!(status & STS_EINT))
3031                 goto out;
3032
3033         if (status & STS_HCE) {
3034                 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3035                 goto out;
3036         }
3037
3038         if (status & STS_FATAL) {
3039                 xhci_warn(xhci, "WARNING: Host System Error\n");
3040                 xhci_halt(xhci);
3041                 ret = IRQ_HANDLED;
3042                 goto out;
3043         }
3044
3045         /*
3046          * Clear the op reg interrupt status first,
3047          * so we can receive interrupts from other MSI-X interrupters.
3048          * Write 1 to clear the interrupt status.
3049          */
3050         status |= STS_EINT;
3051         writel(status, &xhci->op_regs->status);
3052
3053         if (!hcd->msi_enabled) {
3054                 u32 irq_pending;
3055                 irq_pending = readl(&xhci->ir_set->irq_pending);
3056                 irq_pending |= IMAN_IP;
3057                 writel(irq_pending, &xhci->ir_set->irq_pending);
3058         }
3059
3060         if (xhci->xhc_state & XHCI_STATE_DYING ||
3061             xhci->xhc_state & XHCI_STATE_HALTED) {
3062                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3063                                 "Shouldn't IRQs be disabled?\n");
3064                 /* Clear the event handler busy flag (RW1C);
3065                  * the event ring should be empty.
3066                  */
3067                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3068                 xhci_write_64(xhci, temp_64 | ERST_EHB,
3069                                 &xhci->ir_set->erst_dequeue);
3070                 ret = IRQ_HANDLED;
3071                 goto out;
3072         }
3073
3074         event_ring_deq = xhci->event_ring->dequeue;
3075         /* FIXME this should be a delayed service routine
3076          * that clears the EHB.
3077          */
3078         while (xhci_handle_event(xhci) > 0) {
3079                 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3080                         continue;
3081                 xhci_update_erst_dequeue(xhci, event_ring_deq);
3082                 event_ring_deq = xhci->event_ring->dequeue;
3083
3084                 /* ring is half-full, force isoc trbs to interrupt more often */
3085                 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3086                         xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3087
3088                 event_loop = 0;
3089         }
3090
3091         xhci_update_erst_dequeue(xhci, event_ring_deq);
3092         ret = IRQ_HANDLED;
3093
3094 out:
3095         spin_unlock(&xhci->lock);
3096
3097         return ret;
3098 }
3099
3100 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3101 {
3102         return xhci_irq(hcd);
3103 }
3104
3105 /****           Endpoint Ring Operations        ****/
3106
3107 /*
3108  * Generic function for queueing a TRB on a ring.
3109  * The caller must have checked to make sure there's room on the ring.
3110  *
3111  * @more_trbs_coming:   Will you enqueue more TRBs before calling
3112  *                      prepare_transfer()?
3113  */
3114 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3115                 bool more_trbs_coming,
3116                 u32 field1, u32 field2, u32 field3, u32 field4)
3117 {
3118         struct xhci_generic_trb *trb;
3119
3120         trb = &ring->enqueue->generic;
3121         trb->field[0] = cpu_to_le32(field1);
3122         trb->field[1] = cpu_to_le32(field2);
3123         trb->field[2] = cpu_to_le32(field3);
3124         /* make sure TRB is fully written before giving it to the controller */
3125         wmb();
3126         trb->field[3] = cpu_to_le32(field4);
3127
3128         trace_xhci_queue_trb(ring, trb);
3129
3130         inc_enq(xhci, ring, more_trbs_coming);
3131 }
3132
3133 /*
3134  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3135  * FIXME allocate segments if the ring is full.
3136  */
3137 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3138                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3139 {
3140         unsigned int num_trbs_needed;
3141         unsigned int link_trb_count = 0;
3142
3143         /* Make sure the endpoint has been added to xHC schedule */
3144         switch (ep_state) {
3145         case EP_STATE_DISABLED:
3146                 /*
3147                  * USB core changed config/interfaces without notifying us,
3148                  * or hardware is reporting the wrong state.
3149                  */
3150                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3151                 return -ENOENT;
3152         case EP_STATE_ERROR:
3153                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3154                 /* FIXME event handling code for error needs to clear it */
3155                 /* XXX not sure if this should be -ENOENT or not */
3156                 return -EINVAL;
3157         case EP_STATE_HALTED:
3158                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3159                 break;
3160         case EP_STATE_STOPPED:
3161         case EP_STATE_RUNNING:
3162                 break;
3163         default:
3164                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3165                 /*
3166                  * FIXME issue Configure Endpoint command to try to get the HC
3167                  * back into a known state.
3168                  */
3169                 return -EINVAL;
3170         }
3171
3172         while (1) {
3173                 if (room_on_ring(xhci, ep_ring, num_trbs))
3174                         break;
3175
3176                 if (ep_ring == xhci->cmd_ring) {
3177                         xhci_err(xhci, "Do not support expand command ring\n");
3178                         return -ENOMEM;
3179                 }
3180
3181                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3182                                 "ERROR no room on ep ring, try ring expansion");
3183                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3184                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3185                                         mem_flags)) {
3186                         xhci_err(xhci, "Ring expansion failed\n");
3187                         return -ENOMEM;
3188                 }
3189         }
3190
3191         while (trb_is_link(ep_ring->enqueue)) {
3192                 /* If we're not dealing with 0.95 hardware or isoc rings
3193                  * on AMD 0.96 host, clear the chain bit.
3194                  */
3195                 if (!xhci_link_trb_quirk(xhci) &&
3196                     !(ep_ring->type == TYPE_ISOC &&
3197                       (xhci->quirks & XHCI_AMD_0x96_HOST)))
3198                         ep_ring->enqueue->link.control &=
3199                                 cpu_to_le32(~TRB_CHAIN);
3200                 else
3201                         ep_ring->enqueue->link.control |=
3202                                 cpu_to_le32(TRB_CHAIN);
3203
3204                 wmb();
3205                 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3206
3207                 /* Toggle the cycle bit after the last ring segment. */
3208                 if (link_trb_toggles_cycle(ep_ring->enqueue))
3209                         ep_ring->cycle_state ^= 1;
3210
3211                 ep_ring->enq_seg = ep_ring->enq_seg->next;
3212                 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3213
3214                 /* prevent infinite loop if all first trbs are link trbs */
3215                 if (link_trb_count++ > ep_ring->num_segs) {
3216                         xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3217                         return -EINVAL;
3218                 }
3219         }
3220
3221         if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3222                 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3223                 return -EINVAL;
3224         }
3225
3226         return 0;
3227 }
3228
3229 static int prepare_transfer(struct xhci_hcd *xhci,
3230                 struct xhci_virt_device *xdev,
3231                 unsigned int ep_index,
3232                 unsigned int stream_id,
3233                 unsigned int num_trbs,
3234                 struct urb *urb,
3235                 unsigned int td_index,
3236                 gfp_t mem_flags)
3237 {
3238         int ret;
3239         struct urb_priv *urb_priv;
3240         struct xhci_td  *td;
3241         struct xhci_ring *ep_ring;
3242         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3243
3244         ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3245                                               stream_id);
3246         if (!ep_ring) {
3247                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3248                                 stream_id);
3249                 return -EINVAL;
3250         }
3251
3252         ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3253                            num_trbs, mem_flags);
3254         if (ret)
3255                 return ret;
3256
3257         urb_priv = urb->hcpriv;
3258         td = &urb_priv->td[td_index];
3259
3260         INIT_LIST_HEAD(&td->td_list);
3261         INIT_LIST_HEAD(&td->cancelled_td_list);
3262
3263         if (td_index == 0) {
3264                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3265                 if (unlikely(ret))
3266                         return ret;
3267         }
3268
3269         td->urb = urb;
3270         /* Add this TD to the tail of the endpoint ring's TD list */
3271         list_add_tail(&td->td_list, &ep_ring->td_list);
3272         td->start_seg = ep_ring->enq_seg;
3273         td->first_trb = ep_ring->enqueue;
3274
3275         return 0;
3276 }
3277
3278 unsigned int count_trbs(u64 addr, u64 len)
3279 {
3280         unsigned int num_trbs;
3281
3282         num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3283                         TRB_MAX_BUFF_SIZE);
3284         if (num_trbs == 0)
3285                 num_trbs++;
3286
3287         return num_trbs;
3288 }
3289
3290 static inline unsigned int count_trbs_needed(struct urb *urb)
3291 {
3292         return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3293 }
3294
3295 static unsigned int count_sg_trbs_needed(struct urb *urb)
3296 {
3297         struct scatterlist *sg;
3298         unsigned int i, len, full_len, num_trbs = 0;
3299
3300         full_len = urb->transfer_buffer_length;
3301
3302         for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3303                 len = sg_dma_len(sg);
3304                 num_trbs += count_trbs(sg_dma_address(sg), len);
3305                 len = min_t(unsigned int, len, full_len);
3306                 full_len -= len;
3307                 if (full_len == 0)
3308                         break;
3309         }
3310
3311         return num_trbs;
3312 }
3313
3314 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3315 {
3316         u64 addr, len;
3317
3318         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3319         len = urb->iso_frame_desc[i].length;
3320
3321         return count_trbs(addr, len);
3322 }
3323
3324 static void check_trb_math(struct urb *urb, int running_total)
3325 {
3326         if (unlikely(running_total != urb->transfer_buffer_length))
3327                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3328                                 "queued %#x (%d), asked for %#x (%d)\n",
3329                                 __func__,
3330                                 urb->ep->desc.bEndpointAddress,
3331                                 running_total, running_total,
3332                                 urb->transfer_buffer_length,
3333                                 urb->transfer_buffer_length);
3334 }
3335
3336 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3337                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3338                 struct xhci_generic_trb *start_trb)
3339 {
3340         /*
3341          * Pass all the TRBs to the hardware at once and make sure this write
3342          * isn't reordered.
3343          */
3344         wmb();
3345         if (start_cycle)
3346                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3347         else
3348                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3349         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3350 }
3351
3352 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3353                                                 struct xhci_ep_ctx *ep_ctx)
3354 {
3355         int xhci_interval;
3356         int ep_interval;
3357
3358         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3359         ep_interval = urb->interval;
3360
3361         /* Convert to microframes */
3362         if (urb->dev->speed == USB_SPEED_LOW ||
3363                         urb->dev->speed == USB_SPEED_FULL)
3364                 ep_interval *= 8;
3365
3366         /* FIXME change this to a warning and a suggestion to use the new API
3367          * to set the polling interval (once the API is added).
3368          */
3369         if (xhci_interval != ep_interval) {
3370                 dev_dbg_ratelimited(&urb->dev->dev,
3371                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3372                                 ep_interval, ep_interval == 1 ? "" : "s",
3373                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3374                 urb->interval = xhci_interval;
3375                 /* Convert back to frames for LS/FS devices */
3376                 if (urb->dev->speed == USB_SPEED_LOW ||
3377                                 urb->dev->speed == USB_SPEED_FULL)
3378                         urb->interval /= 8;
3379         }
3380 }
3381
3382 /*
3383  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3384  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3385  * (comprised of sg list entries) can take several service intervals to
3386  * transmit.
3387  */
3388 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3389                 struct urb *urb, int slot_id, unsigned int ep_index)
3390 {
3391         struct xhci_ep_ctx *ep_ctx;
3392
3393         ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3394         check_interval(xhci, urb, ep_ctx);
3395
3396         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3397 }
3398
3399 /*
3400  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3401  * packets remaining in the TD (*not* including this TRB).
3402  *
3403  * Total TD packet count = total_packet_count =
3404  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3405  *
3406  * Packets transferred up to and including this TRB = packets_transferred =
3407  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3408  *
3409  * TD size = total_packet_count - packets_transferred
3410  *
3411  * For xHCI 0.96 and older, TD size field should be the remaining bytes
3412  * including this TRB, right shifted by 10
3413  *
3414  * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3415  * This is taken care of in the TRB_TD_SIZE() macro
3416  *
3417  * The last TRB in a TD must have the TD size set to zero.
3418  */
3419 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3420                               int trb_buff_len, unsigned int td_total_len,
3421                               struct urb *urb, bool more_trbs_coming)
3422 {
3423         u32 maxp, total_packet_count;
3424
3425         /* MTK xHCI 0.96 contains some features from 1.0 */
3426         if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3427                 return ((td_total_len - transferred) >> 10);
3428
3429         /* One TRB with a zero-length data packet. */
3430         if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3431             trb_buff_len == td_total_len)
3432                 return 0;
3433
3434         /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3435         if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3436                 trb_buff_len = 0;
3437
3438         maxp = usb_endpoint_maxp(&urb->ep->desc);
3439         total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3440
3441         /* Queueing functions don't count the current TRB into transferred */
3442         return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3443 }
3444
3445
3446 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3447                          u32 *trb_buff_len, struct xhci_segment *seg)
3448 {
3449         struct device *dev = xhci_to_hcd(xhci)->self.controller;
3450         unsigned int unalign;
3451         unsigned int max_pkt;
3452         u32 new_buff_len;
3453         size_t len;
3454
3455         max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3456         unalign = (enqd_len + *trb_buff_len) % max_pkt;
3457
3458         /* we got lucky, last normal TRB data on segment is packet aligned */
3459         if (unalign == 0)
3460                 return 0;
3461
3462         xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3463                  unalign, *trb_buff_len);
3464
3465         /* is the last nornal TRB alignable by splitting it */
3466         if (*trb_buff_len > unalign) {
3467                 *trb_buff_len -= unalign;
3468                 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3469                 return 0;
3470         }
3471
3472         /*
3473          * We want enqd_len + trb_buff_len to sum up to a number aligned to
3474          * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3475          * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3476          */
3477         new_buff_len = max_pkt - (enqd_len % max_pkt);
3478
3479         if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3480                 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3481
3482         /* create a max max_pkt sized bounce buffer pointed to by last trb */
3483         if (usb_urb_dir_out(urb)) {
3484                 if (urb->num_sgs) {
3485                         len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3486                                                  seg->bounce_buf, new_buff_len, enqd_len);
3487                         if (len != new_buff_len)
3488                                 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3489                                           len, new_buff_len);
3490                 } else {
3491                         memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3492                 }
3493
3494                 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3495                                                  max_pkt, DMA_TO_DEVICE);
3496         } else {
3497                 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3498                                                  max_pkt, DMA_FROM_DEVICE);
3499         }
3500
3501         if (dma_mapping_error(dev, seg->bounce_dma)) {
3502                 /* try without aligning. Some host controllers survive */
3503                 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3504                 return 0;
3505         }
3506         *trb_buff_len = new_buff_len;
3507         seg->bounce_len = new_buff_len;
3508         seg->bounce_offs = enqd_len;
3509
3510         xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3511
3512         return 1;
3513 }
3514
3515 /* This is very similar to what ehci-q.c qtd_fill() does */
3516 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3517                 struct urb *urb, int slot_id, unsigned int ep_index)
3518 {
3519         struct xhci_ring *ring;
3520         struct urb_priv *urb_priv;
3521         struct xhci_td *td;
3522         struct xhci_generic_trb *start_trb;
3523         struct scatterlist *sg = NULL;
3524         bool more_trbs_coming = true;
3525         bool need_zero_pkt = false;
3526         bool first_trb = true;
3527         unsigned int num_trbs;
3528         unsigned int start_cycle, num_sgs = 0;
3529         unsigned int enqd_len, block_len, trb_buff_len, full_len;
3530         int sent_len, ret;
3531         u32 field, length_field, remainder;
3532         u64 addr, send_addr;
3533
3534         ring = xhci_urb_to_transfer_ring(xhci, urb);
3535         if (!ring)
3536                 return -EINVAL;
3537
3538         full_len = urb->transfer_buffer_length;
3539         /* If we have scatter/gather list, we use it. */
3540         if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3541                 num_sgs = urb->num_mapped_sgs;
3542                 sg = urb->sg;
3543                 addr = (u64) sg_dma_address(sg);
3544                 block_len = sg_dma_len(sg);
3545                 num_trbs = count_sg_trbs_needed(urb);
3546         } else {
3547                 num_trbs = count_trbs_needed(urb);
3548                 addr = (u64) urb->transfer_dma;
3549                 block_len = full_len;
3550         }
3551         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3552                         ep_index, urb->stream_id,
3553                         num_trbs, urb, 0, mem_flags);
3554         if (unlikely(ret < 0))
3555                 return ret;
3556
3557         urb_priv = urb->hcpriv;
3558
3559         /* Deal with URB_ZERO_PACKET - need one more td/trb */
3560         if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3561                 need_zero_pkt = true;
3562
3563         td = &urb_priv->td[0];
3564
3565         /*
3566          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3567          * until we've finished creating all the other TRBs.  The ring's cycle
3568          * state may change as we enqueue the other TRBs, so save it too.
3569          */
3570         start_trb = &ring->enqueue->generic;
3571         start_cycle = ring->cycle_state;
3572         send_addr = addr;
3573
3574         /* Queue the TRBs, even if they are zero-length */
3575         for (enqd_len = 0; first_trb || enqd_len < full_len;
3576                         enqd_len += trb_buff_len) {
3577                 field = TRB_TYPE(TRB_NORMAL);
3578
3579                 /* TRB buffer should not cross 64KB boundaries */
3580                 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3581                 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3582
3583                 if (enqd_len + trb_buff_len > full_len)
3584                         trb_buff_len = full_len - enqd_len;
3585
3586                 /* Don't change the cycle bit of the first TRB until later */
3587                 if (first_trb) {
3588                         first_trb = false;
3589                         if (start_cycle == 0)
3590                                 field |= TRB_CYCLE;
3591                 } else
3592                         field |= ring->cycle_state;
3593
3594                 /* Chain all the TRBs together; clear the chain bit in the last
3595                  * TRB to indicate it's the last TRB in the chain.
3596                  */
3597                 if (enqd_len + trb_buff_len < full_len) {
3598                         field |= TRB_CHAIN;
3599                         if (trb_is_link(ring->enqueue + 1)) {
3600                                 if (xhci_align_td(xhci, urb, enqd_len,
3601                                                   &trb_buff_len,
3602                                                   ring->enq_seg)) {
3603                                         send_addr = ring->enq_seg->bounce_dma;
3604                                         /* assuming TD won't span 2 segs */
3605                                         td->bounce_seg = ring->enq_seg;
3606                                 }
3607                         }
3608                 }
3609                 if (enqd_len + trb_buff_len >= full_len) {
3610                         field &= ~TRB_CHAIN;
3611                         field |= TRB_IOC;
3612                         more_trbs_coming = false;
3613                         td->last_trb = ring->enqueue;
3614                         td->last_trb_seg = ring->enq_seg;
3615                         if (xhci_urb_suitable_for_idt(urb)) {
3616                                 memcpy(&send_addr, urb->transfer_buffer,
3617                                        trb_buff_len);
3618                                 le64_to_cpus(&send_addr);
3619                                 field |= TRB_IDT;
3620                         }
3621                 }
3622
3623                 /* Only set interrupt on short packet for IN endpoints */
3624                 if (usb_urb_dir_in(urb))
3625                         field |= TRB_ISP;
3626
3627                 /* Set the TRB length, TD size, and interrupter fields. */
3628                 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3629                                               full_len, urb, more_trbs_coming);
3630
3631                 length_field = TRB_LEN(trb_buff_len) |
3632                         TRB_TD_SIZE(remainder) |
3633                         TRB_INTR_TARGET(0);
3634
3635                 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3636                                 lower_32_bits(send_addr),
3637                                 upper_32_bits(send_addr),
3638                                 length_field,
3639                                 field);
3640                 td->num_trbs++;
3641                 addr += trb_buff_len;
3642                 sent_len = trb_buff_len;
3643
3644                 while (sg && sent_len >= block_len) {
3645                         /* New sg entry */
3646                         --num_sgs;
3647                         sent_len -= block_len;
3648                         sg = sg_next(sg);
3649                         if (num_sgs != 0 && sg) {
3650                                 block_len = sg_dma_len(sg);
3651                                 addr = (u64) sg_dma_address(sg);
3652                                 addr += sent_len;
3653                         }
3654                 }
3655                 block_len -= sent_len;
3656                 send_addr = addr;
3657         }
3658
3659         if (need_zero_pkt) {
3660                 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3661                                        ep_index, urb->stream_id,
3662                                        1, urb, 1, mem_flags);
3663                 urb_priv->td[1].last_trb = ring->enqueue;
3664                 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3665                 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3666                 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3667                 urb_priv->td[1].num_trbs++;
3668         }
3669
3670         check_trb_math(urb, enqd_len);
3671         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3672                         start_cycle, start_trb);
3673         return 0;
3674 }
3675
3676 /* Caller must have locked xhci->lock */
3677 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3678                 struct urb *urb, int slot_id, unsigned int ep_index)
3679 {
3680         struct xhci_ring *ep_ring;
3681         int num_trbs;
3682         int ret;
3683         struct usb_ctrlrequest *setup;
3684         struct xhci_generic_trb *start_trb;
3685         int start_cycle;
3686         u32 field;
3687         struct urb_priv *urb_priv;
3688         struct xhci_td *td;
3689
3690         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3691         if (!ep_ring)
3692                 return -EINVAL;
3693
3694         /*
3695          * Need to copy setup packet into setup TRB, so we can't use the setup
3696          * DMA address.
3697          */
3698         if (!urb->setup_packet)
3699                 return -EINVAL;
3700
3701         /* 1 TRB for setup, 1 for status */
3702         num_trbs = 2;
3703         /*
3704          * Don't need to check if we need additional event data and normal TRBs,
3705          * since data in control transfers will never get bigger than 16MB
3706          * XXX: can we get a buffer that crosses 64KB boundaries?
3707          */
3708         if (urb->transfer_buffer_length > 0)
3709                 num_trbs++;
3710         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3711                         ep_index, urb->stream_id,
3712                         num_trbs, urb, 0, mem_flags);
3713         if (ret < 0)
3714                 return ret;
3715
3716         urb_priv = urb->hcpriv;
3717         td = &urb_priv->td[0];
3718         td->num_trbs = num_trbs;
3719
3720         /*
3721          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3722          * until we've finished creating all the other TRBs.  The ring's cycle
3723          * state may change as we enqueue the other TRBs, so save it too.
3724          */
3725         start_trb = &ep_ring->enqueue->generic;
3726         start_cycle = ep_ring->cycle_state;
3727
3728         /* Queue setup TRB - see section 6.4.1.2.1 */
3729         /* FIXME better way to translate setup_packet into two u32 fields? */
3730         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3731         field = 0;
3732         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3733         if (start_cycle == 0)
3734                 field |= 0x1;
3735
3736         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3737         if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3738                 if (urb->transfer_buffer_length > 0) {
3739                         if (setup->bRequestType & USB_DIR_IN)
3740                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3741                         else
3742                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3743                 }
3744         }
3745
3746         queue_trb(xhci, ep_ring, true,
3747                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3748                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3749                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3750                   /* Immediate data in pointer */
3751                   field);
3752
3753         /* If there's data, queue data TRBs */
3754         /* Only set interrupt on short packet for IN endpoints */
3755         if (usb_urb_dir_in(urb))
3756                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3757         else
3758                 field = TRB_TYPE(TRB_DATA);
3759
3760         if (urb->transfer_buffer_length > 0) {
3761                 u32 length_field, remainder;
3762                 u64 addr;
3763
3764                 if (xhci_urb_suitable_for_idt(urb)) {
3765                         memcpy(&addr, urb->transfer_buffer,
3766                                urb->transfer_buffer_length);
3767                         le64_to_cpus(&addr);
3768                         field |= TRB_IDT;
3769                 } else {
3770                         addr = (u64) urb->transfer_dma;
3771                 }
3772
3773                 remainder = xhci_td_remainder(xhci, 0,
3774                                 urb->transfer_buffer_length,
3775                                 urb->transfer_buffer_length,
3776                                 urb, 1);
3777                 length_field = TRB_LEN(urb->transfer_buffer_length) |
3778                                 TRB_TD_SIZE(remainder) |
3779                                 TRB_INTR_TARGET(0);
3780                 if (setup->bRequestType & USB_DIR_IN)
3781                         field |= TRB_DIR_IN;
3782                 queue_trb(xhci, ep_ring, true,
3783                                 lower_32_bits(addr),
3784                                 upper_32_bits(addr),
3785                                 length_field,
3786                                 field | ep_ring->cycle_state);
3787         }
3788
3789         /* Save the DMA address of the last TRB in the TD */
3790         td->last_trb = ep_ring->enqueue;
3791         td->last_trb_seg = ep_ring->enq_seg;
3792
3793         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3794         /* If the device sent data, the status stage is an OUT transfer */
3795         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3796                 field = 0;
3797         else
3798                 field = TRB_DIR_IN;
3799         queue_trb(xhci, ep_ring, false,
3800                         0,
3801                         0,
3802                         TRB_INTR_TARGET(0),
3803                         /* Event on completion */
3804                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3805
3806         giveback_first_trb(xhci, slot_id, ep_index, 0,
3807                         start_cycle, start_trb);
3808         return 0;
3809 }
3810
3811 /*
3812  * The transfer burst count field of the isochronous TRB defines the number of
3813  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3814  * devices can burst up to bMaxBurst number of packets per service interval.
3815  * This field is zero based, meaning a value of zero in the field means one
3816  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3817  * zero.  Only xHCI 1.0 host controllers support this field.
3818  */
3819 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3820                 struct urb *urb, unsigned int total_packet_count)
3821 {
3822         unsigned int max_burst;
3823
3824         if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3825                 return 0;
3826
3827         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3828         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3829 }
3830
3831 /*
3832  * Returns the number of packets in the last "burst" of packets.  This field is
3833  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3834  * the last burst packet count is equal to the total number of packets in the
3835  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3836  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3837  * contain 1 to (bMaxBurst + 1) packets.
3838  */
3839 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3840                 struct urb *urb, unsigned int total_packet_count)
3841 {
3842         unsigned int max_burst;
3843         unsigned int residue;
3844
3845         if (xhci->hci_version < 0x100)
3846                 return 0;
3847
3848         if (urb->dev->speed >= USB_SPEED_SUPER) {
3849                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3850                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3851                 residue = total_packet_count % (max_burst + 1);
3852                 /* If residue is zero, the last burst contains (max_burst + 1)
3853                  * number of packets, but the TLBPC field is zero-based.
3854                  */
3855                 if (residue == 0)
3856                         return max_burst;
3857                 return residue - 1;
3858         }
3859         if (total_packet_count == 0)
3860                 return 0;
3861         return total_packet_count - 1;
3862 }
3863
3864 /*
3865  * Calculates Frame ID field of the isochronous TRB identifies the
3866  * target frame that the Interval associated with this Isochronous
3867  * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3868  *
3869  * Returns actual frame id on success, negative value on error.
3870  */
3871 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3872                 struct urb *urb, int index)
3873 {
3874         int start_frame, ist, ret = 0;
3875         int start_frame_id, end_frame_id, current_frame_id;
3876
3877         if (urb->dev->speed == USB_SPEED_LOW ||
3878                         urb->dev->speed == USB_SPEED_FULL)
3879                 start_frame = urb->start_frame + index * urb->interval;
3880         else
3881                 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3882
3883         /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3884          *
3885          * If bit [3] of IST is cleared to '0', software can add a TRB no
3886          * later than IST[2:0] Microframes before that TRB is scheduled to
3887          * be executed.
3888          * If bit [3] of IST is set to '1', software can add a TRB no later
3889          * than IST[2:0] Frames before that TRB is scheduled to be executed.
3890          */
3891         ist = HCS_IST(xhci->hcs_params2) & 0x7;
3892         if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3893                 ist <<= 3;
3894
3895         /* Software shall not schedule an Isoch TD with a Frame ID value that
3896          * is less than the Start Frame ID or greater than the End Frame ID,
3897          * where:
3898          *
3899          * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3900          * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3901          *
3902          * Both the End Frame ID and Start Frame ID values are calculated
3903          * in microframes. When software determines the valid Frame ID value;
3904          * The End Frame ID value should be rounded down to the nearest Frame
3905          * boundary, and the Start Frame ID value should be rounded up to the
3906          * nearest Frame boundary.
3907          */
3908         current_frame_id = readl(&xhci->run_regs->microframe_index);
3909         start_frame_id = roundup(current_frame_id + ist + 1, 8);
3910         end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3911
3912         start_frame &= 0x7ff;
3913         start_frame_id = (start_frame_id >> 3) & 0x7ff;
3914         end_frame_id = (end_frame_id >> 3) & 0x7ff;
3915
3916         xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3917                  __func__, index, readl(&xhci->run_regs->microframe_index),
3918                  start_frame_id, end_frame_id, start_frame);
3919
3920         if (start_frame_id < end_frame_id) {
3921                 if (start_frame > end_frame_id ||
3922                                 start_frame < start_frame_id)
3923                         ret = -EINVAL;
3924         } else if (start_frame_id > end_frame_id) {
3925                 if ((start_frame > end_frame_id &&
3926                                 start_frame < start_frame_id))
3927                         ret = -EINVAL;
3928         } else {
3929                         ret = -EINVAL;
3930         }
3931
3932         if (index == 0) {
3933                 if (ret == -EINVAL || start_frame == start_frame_id) {
3934                         start_frame = start_frame_id + 1;
3935                         if (urb->dev->speed == USB_SPEED_LOW ||
3936                                         urb->dev->speed == USB_SPEED_FULL)
3937                                 urb->start_frame = start_frame;
3938                         else
3939                                 urb->start_frame = start_frame << 3;
3940                         ret = 0;
3941                 }
3942         }
3943
3944         if (ret) {
3945                 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3946                                 start_frame, current_frame_id, index,
3947                                 start_frame_id, end_frame_id);
3948                 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3949                 return ret;
3950         }
3951
3952         return start_frame;
3953 }
3954
3955 /* Check if we should generate event interrupt for a TD in an isoc URB */
3956 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3957 {
3958         if (xhci->hci_version < 0x100)
3959                 return false;
3960         /* always generate an event interrupt for the last TD */
3961         if (i == num_tds - 1)
3962                 return false;
3963         /*
3964          * If AVOID_BEI is set the host handles full event rings poorly,
3965          * generate an event at least every 8th TD to clear the event ring
3966          */
3967         if (i && xhci->quirks & XHCI_AVOID_BEI)
3968                 return !!(i % xhci->isoc_bei_interval);
3969
3970         return true;
3971 }
3972
3973 /* This is for isoc transfer */
3974 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3975                 struct urb *urb, int slot_id, unsigned int ep_index)
3976 {
3977         struct xhci_ring *ep_ring;
3978         struct urb_priv *urb_priv;
3979         struct xhci_td *td;
3980         int num_tds, trbs_per_td;
3981         struct xhci_generic_trb *start_trb;
3982         bool first_trb;
3983         int start_cycle;
3984         u32 field, length_field;
3985         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3986         u64 start_addr, addr;
3987         int i, j;
3988         bool more_trbs_coming;
3989         struct xhci_virt_ep *xep;
3990         int frame_id;
3991
3992         xep = &xhci->devs[slot_id]->eps[ep_index];
3993         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3994
3995         num_tds = urb->number_of_packets;
3996         if (num_tds < 1) {
3997                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3998                 return -EINVAL;
3999         }
4000         start_addr = (u64) urb->transfer_dma;
4001         start_trb = &ep_ring->enqueue->generic;
4002         start_cycle = ep_ring->cycle_state;
4003
4004         urb_priv = urb->hcpriv;
4005         /* Queue the TRBs for each TD, even if they are zero-length */
4006         for (i = 0; i < num_tds; i++) {
4007                 unsigned int total_pkt_count, max_pkt;
4008                 unsigned int burst_count, last_burst_pkt_count;
4009                 u32 sia_frame_id;
4010
4011                 first_trb = true;
4012                 running_total = 0;
4013                 addr = start_addr + urb->iso_frame_desc[i].offset;
4014                 td_len = urb->iso_frame_desc[i].length;
4015                 td_remain_len = td_len;
4016                 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4017                 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4018
4019                 /* A zero-length transfer still involves at least one packet. */
4020                 if (total_pkt_count == 0)
4021                         total_pkt_count++;
4022                 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4023                 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4024                                                         urb, total_pkt_count);
4025
4026                 trbs_per_td = count_isoc_trbs_needed(urb, i);
4027
4028                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4029                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4030                 if (ret < 0) {
4031                         if (i == 0)
4032                                 return ret;
4033                         goto cleanup;
4034                 }
4035                 td = &urb_priv->td[i];
4036                 td->num_trbs = trbs_per_td;
4037                 /* use SIA as default, if frame id is used overwrite it */
4038                 sia_frame_id = TRB_SIA;
4039                 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4040                     HCC_CFC(xhci->hcc_params)) {
4041                         frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4042                         if (frame_id >= 0)
4043                                 sia_frame_id = TRB_FRAME_ID(frame_id);
4044                 }
4045                 /*
4046                  * Set isoc specific data for the first TRB in a TD.
4047                  * Prevent HW from getting the TRBs by keeping the cycle state
4048                  * inverted in the first TDs isoc TRB.
4049                  */
4050                 field = TRB_TYPE(TRB_ISOC) |
4051                         TRB_TLBPC(last_burst_pkt_count) |
4052                         sia_frame_id |
4053                         (i ? ep_ring->cycle_state : !start_cycle);
4054
4055                 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4056                 if (!xep->use_extended_tbc)
4057                         field |= TRB_TBC(burst_count);
4058
4059                 /* fill the rest of the TRB fields, and remaining normal TRBs */
4060                 for (j = 0; j < trbs_per_td; j++) {
4061                         u32 remainder = 0;
4062
4063                         /* only first TRB is isoc, overwrite otherwise */
4064                         if (!first_trb)
4065                                 field = TRB_TYPE(TRB_NORMAL) |
4066                                         ep_ring->cycle_state;
4067
4068                         /* Only set interrupt on short packet for IN EPs */
4069                         if (usb_urb_dir_in(urb))
4070                                 field |= TRB_ISP;
4071
4072                         /* Set the chain bit for all except the last TRB  */
4073                         if (j < trbs_per_td - 1) {
4074                                 more_trbs_coming = true;
4075                                 field |= TRB_CHAIN;
4076                         } else {
4077                                 more_trbs_coming = false;
4078                                 td->last_trb = ep_ring->enqueue;
4079                                 td->last_trb_seg = ep_ring->enq_seg;
4080                                 field |= TRB_IOC;
4081                                 if (trb_block_event_intr(xhci, num_tds, i))
4082                                         field |= TRB_BEI;
4083                         }
4084                         /* Calculate TRB length */
4085                         trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4086                         if (trb_buff_len > td_remain_len)
4087                                 trb_buff_len = td_remain_len;
4088
4089                         /* Set the TRB length, TD size, & interrupter fields. */
4090                         remainder = xhci_td_remainder(xhci, running_total,
4091                                                    trb_buff_len, td_len,
4092                                                    urb, more_trbs_coming);
4093
4094                         length_field = TRB_LEN(trb_buff_len) |
4095                                 TRB_INTR_TARGET(0);
4096
4097                         /* xhci 1.1 with ETE uses TD Size field for TBC */
4098                         if (first_trb && xep->use_extended_tbc)
4099                                 length_field |= TRB_TD_SIZE_TBC(burst_count);
4100                         else
4101                                 length_field |= TRB_TD_SIZE(remainder);
4102                         first_trb = false;
4103
4104                         queue_trb(xhci, ep_ring, more_trbs_coming,
4105                                 lower_32_bits(addr),
4106                                 upper_32_bits(addr),
4107                                 length_field,
4108                                 field);
4109                         running_total += trb_buff_len;
4110
4111                         addr += trb_buff_len;
4112                         td_remain_len -= trb_buff_len;
4113                 }
4114
4115                 /* Check TD length */
4116                 if (running_total != td_len) {
4117                         xhci_err(xhci, "ISOC TD length unmatch\n");
4118                         ret = -EINVAL;
4119                         goto cleanup;
4120                 }
4121         }
4122
4123         /* store the next frame id */
4124         if (HCC_CFC(xhci->hcc_params))
4125                 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4126
4127         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4128                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4129                         usb_amd_quirk_pll_disable();
4130         }
4131         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4132
4133         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4134                         start_cycle, start_trb);
4135         return 0;
4136 cleanup:
4137         /* Clean up a partially enqueued isoc transfer. */
4138
4139         for (i--; i >= 0; i--)
4140                 list_del_init(&urb_priv->td[i].td_list);
4141
4142         /* Use the first TD as a temporary variable to turn the TDs we've queued
4143          * into No-ops with a software-owned cycle bit. That way the hardware
4144          * won't accidentally start executing bogus TDs when we partially
4145          * overwrite them.  td->first_trb and td->start_seg are already set.
4146          */
4147         urb_priv->td[0].last_trb = ep_ring->enqueue;
4148         /* Every TRB except the first & last will have its cycle bit flipped. */
4149         td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4150
4151         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4152         ep_ring->enqueue = urb_priv->td[0].first_trb;
4153         ep_ring->enq_seg = urb_priv->td[0].start_seg;
4154         ep_ring->cycle_state = start_cycle;
4155         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4156         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4157         return ret;
4158 }
4159
4160 /*
4161  * Check transfer ring to guarantee there is enough room for the urb.
4162  * Update ISO URB start_frame and interval.
4163  * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4164  * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4165  * Contiguous Frame ID is not supported by HC.
4166  */
4167 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4168                 struct urb *urb, int slot_id, unsigned int ep_index)
4169 {
4170         struct xhci_virt_device *xdev;
4171         struct xhci_ring *ep_ring;
4172         struct xhci_ep_ctx *ep_ctx;
4173         int start_frame;
4174         int num_tds, num_trbs, i;
4175         int ret;
4176         struct xhci_virt_ep *xep;
4177         int ist;
4178
4179         xdev = xhci->devs[slot_id];
4180         xep = &xhci->devs[slot_id]->eps[ep_index];
4181         ep_ring = xdev->eps[ep_index].ring;
4182         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4183
4184         num_trbs = 0;
4185         num_tds = urb->number_of_packets;
4186         for (i = 0; i < num_tds; i++)
4187                 num_trbs += count_isoc_trbs_needed(urb, i);
4188
4189         /* Check the ring to guarantee there is enough room for the whole urb.
4190          * Do not insert any td of the urb to the ring if the check failed.
4191          */
4192         ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4193                            num_trbs, mem_flags);
4194         if (ret)
4195                 return ret;
4196
4197         /*
4198          * Check interval value. This should be done before we start to
4199          * calculate the start frame value.
4200          */
4201         check_interval(xhci, urb, ep_ctx);
4202
4203         /* Calculate the start frame and put it in urb->start_frame. */
4204         if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4205                 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4206                         urb->start_frame = xep->next_frame_id;
4207                         goto skip_start_over;
4208                 }
4209         }
4210
4211         start_frame = readl(&xhci->run_regs->microframe_index);
4212         start_frame &= 0x3fff;
4213         /*
4214          * Round up to the next frame and consider the time before trb really
4215          * gets scheduled by hardare.
4216          */
4217         ist = HCS_IST(xhci->hcs_params2) & 0x7;
4218         if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4219                 ist <<= 3;
4220         start_frame += ist + XHCI_CFC_DELAY;
4221         start_frame = roundup(start_frame, 8);
4222
4223         /*
4224          * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4225          * is greate than 8 microframes.
4226          */
4227         if (urb->dev->speed == USB_SPEED_LOW ||
4228                         urb->dev->speed == USB_SPEED_FULL) {
4229                 start_frame = roundup(start_frame, urb->interval << 3);
4230                 urb->start_frame = start_frame >> 3;
4231         } else {
4232                 start_frame = roundup(start_frame, urb->interval);
4233                 urb->start_frame = start_frame;
4234         }
4235
4236 skip_start_over:
4237         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4238
4239         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4240 }
4241
4242 /****           Command Ring Operations         ****/
4243
4244 /* Generic function for queueing a command TRB on the command ring.
4245  * Check to make sure there's room on the command ring for one command TRB.
4246  * Also check that there's room reserved for commands that must not fail.
4247  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4248  * then only check for the number of reserved spots.
4249  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4250  * because the command event handler may want to resubmit a failed command.
4251  */
4252 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4253                          u32 field1, u32 field2,
4254                          u32 field3, u32 field4, bool command_must_succeed)
4255 {
4256         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4257         int ret;
4258
4259         if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4260                 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4261                 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4262                 return -ESHUTDOWN;
4263         }
4264
4265         if (!command_must_succeed)
4266                 reserved_trbs++;
4267
4268         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4269                         reserved_trbs, GFP_ATOMIC);
4270         if (ret < 0) {
4271                 xhci_err(xhci, "ERR: No room for command on command ring\n");
4272                 if (command_must_succeed)
4273                         xhci_err(xhci, "ERR: Reserved TRB counting for "
4274                                         "unfailable commands failed.\n");
4275                 return ret;
4276         }
4277
4278         cmd->command_trb = xhci->cmd_ring->enqueue;
4279
4280         /* if there are no other commands queued we start the timeout timer */
4281         if (list_empty(&xhci->cmd_list)) {
4282                 xhci->current_cmd = cmd;
4283                 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4284         }
4285
4286         list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4287
4288         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4289                         field4 | xhci->cmd_ring->cycle_state);
4290         return 0;
4291 }
4292
4293 /* Queue a slot enable or disable request on the command ring */
4294 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4295                 u32 trb_type, u32 slot_id)
4296 {
4297         return queue_command(xhci, cmd, 0, 0, 0,
4298                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4299 }
4300
4301 /* Queue an address device command TRB */
4302 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4303                 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4304 {
4305         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4306                         upper_32_bits(in_ctx_ptr), 0,
4307                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4308                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4309 }
4310
4311 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4312                 u32 field1, u32 field2, u32 field3, u32 field4)
4313 {
4314         return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4315 }
4316
4317 /* Queue a reset device command TRB */
4318 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4319                 u32 slot_id)
4320 {
4321         return queue_command(xhci, cmd, 0, 0, 0,
4322                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4323                         false);
4324 }
4325
4326 /* Queue a configure endpoint command TRB */
4327 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4328                 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4329                 u32 slot_id, bool command_must_succeed)
4330 {
4331         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4332                         upper_32_bits(in_ctx_ptr), 0,
4333                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4334                         command_must_succeed);
4335 }
4336
4337 /* Queue an evaluate context command TRB */
4338 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4339                 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4340 {
4341         return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4342                         upper_32_bits(in_ctx_ptr), 0,
4343                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4344                         command_must_succeed);
4345 }
4346
4347 /*
4348  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4349  * activity on an endpoint that is about to be suspended.
4350  */
4351 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4352                              int slot_id, unsigned int ep_index, int suspend)
4353 {
4354         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4355         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4356         u32 type = TRB_TYPE(TRB_STOP_RING);
4357         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4358
4359         return queue_command(xhci, cmd, 0, 0, 0,
4360                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4361 }
4362
4363 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4364                         int slot_id, unsigned int ep_index,
4365                         enum xhci_ep_reset_type reset_type)
4366 {
4367         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4368         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4369         u32 type = TRB_TYPE(TRB_RESET_EP);
4370
4371         if (reset_type == EP_SOFT_RESET)
4372                 type |= TRB_TSP;
4373
4374         return queue_command(xhci, cmd, 0, 0, 0,
4375                         trb_slot_id | trb_ep_index | type, false);
4376 }