1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
307 struct xhci_command *i_cmd;
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
339 /* Must be called with xhci->lock held, releases and aquires lock back */
340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
345 xhci_dbg(xhci, "Abort command ring\n");
347 reinit_completion(&xhci->cmd_ring_stop_completion);
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
354 * completion of the Command Abort operation. If CRR is not negated in 5
355 * seconds then driver handles it as if host died (-ENODEV).
356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
357 * and try to recover a -ETIMEDOUT with a host controller reset.
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
370 * but the completion event in never sent. Wait 2 secs (arbitrary
371 * number) to handle those cases after negation of CMD_RING_RUNNING.
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
386 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
395 /* Don't ring the doorbell for this endpoint if there are pending
396 * cancellations because we don't want to interrupt processing.
397 * We don't want to restart any stream rings if there's a set dequeue
398 * pointer command pending because the device can choose to start any
399 * stream once the endpoint is on the HW schedule.
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED))
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405 /* The CPU has better things to do at this point than wait for a
406 * write-posting flush. It'll get there soon enough.
410 /* Ring the doorbell for any rings with pending URBs */
411 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
418 ep = &xhci->devs[slot_id]->eps[ep_index];
420 /* A ring has pending URBs if its TD list is not empty */
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
436 /* Get the right ring for the given slot_id, ep_index and stream_id.
437 * If the endpoint supports streams, boundary check the URB's stream ID.
438 * If the endpoint doesn't support streams, return the singular endpoint ring.
440 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
441 unsigned int slot_id, unsigned int ep_index,
442 unsigned int stream_id)
444 struct xhci_virt_ep *ep;
446 ep = &xhci->devs[slot_id]->eps[ep_index];
447 /* Common case: no streams */
448 if (!(ep->ep_state & EP_HAS_STREAMS))
451 if (stream_id == 0) {
453 "WARN: Slot ID %u, ep index %u has streams, "
454 "but URB has no stream ID.\n",
459 if (stream_id < ep->stream_info->num_streams)
460 return ep->stream_info->stream_rings[stream_id];
463 "WARN: Slot ID %u, ep index %u has "
464 "stream IDs 1 to %u allocated, "
465 "but stream ID %u is requested.\n",
467 ep->stream_info->num_streams - 1,
474 * Get the hw dequeue pointer xHC stopped on, either directly from the
475 * endpoint context, or if streams are in use from the stream context.
476 * The returned hw_dequeue contains the lowest four bits with cycle state
477 * and possbile stream context type.
479 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
480 unsigned int ep_index, unsigned int stream_id)
482 struct xhci_ep_ctx *ep_ctx;
483 struct xhci_stream_ctx *st_ctx;
484 struct xhci_virt_ep *ep;
486 ep = &vdev->eps[ep_index];
488 if (ep->ep_state & EP_HAS_STREAMS) {
489 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
490 return le64_to_cpu(st_ctx->stream_ring);
492 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
493 return le64_to_cpu(ep_ctx->deq);
497 * Move the xHC's endpoint ring dequeue pointer past cur_td.
498 * Record the new state of the xHC's endpoint ring dequeue segment,
499 * dequeue pointer, stream id, and new consumer cycle state in state.
500 * Update our internal representation of the ring's dequeue pointer.
502 * We do this in three jumps:
503 * - First we update our new ring state to be the same as when the xHC stopped.
504 * - Then we traverse the ring to find the segment that contains
505 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
506 * any link TRBs with the toggle cycle bit set.
507 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
508 * if we've moved it past a link TRB with the toggle cycle bit set.
510 * Some of the uses of xhci_generic_trb are grotty, but if they're done
511 * with correct __le32 accesses they should work fine. Only users of this are
514 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
515 unsigned int slot_id, unsigned int ep_index,
516 unsigned int stream_id, struct xhci_td *cur_td,
517 struct xhci_dequeue_state *state)
519 struct xhci_virt_device *dev = xhci->devs[slot_id];
520 struct xhci_virt_ep *ep = &dev->eps[ep_index];
521 struct xhci_ring *ep_ring;
522 struct xhci_segment *new_seg;
523 struct xhci_segment *halted_seg = NULL;
524 union xhci_trb *new_deq;
525 union xhci_trb *halted_trb;
529 bool cycle_found = false;
530 bool td_last_trb_found = false;
532 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
533 ep_index, stream_id);
535 xhci_warn(xhci, "WARN can't find new dequeue state "
536 "for invalid stream ID %u.\n",
540 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
541 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
542 "Finding endpoint context");
544 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
545 new_seg = ep_ring->deq_seg;
546 new_deq = ep_ring->dequeue;
549 * Quirk: xHC write-back of the DCS field in the hardware dequeue
550 * pointer is wrong - use the cycle state of the TRB pointed to by
551 * the dequeue pointer.
553 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
554 !(ep->ep_state & EP_HAS_STREAMS))
555 halted_seg = trb_in_td(xhci, cur_td->start_seg,
556 cur_td->first_trb, cur_td->last_trb,
557 hw_dequeue & ~0xf, false);
559 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
561 halted_trb = &halted_seg->trbs[index];
562 state->new_cycle_state = halted_trb->generic.field[3] & 0x1;
563 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
564 (u8)(hw_dequeue & 0x1), index,
565 state->new_cycle_state);
567 state->new_cycle_state = hw_dequeue & 0x1;
569 state->stream_id = stream_id;
572 * We want to find the pointer, segment and cycle state of the new trb
573 * (the one after current TD's last_trb). We know the cycle state at
574 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
578 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
579 == (dma_addr_t)(hw_dequeue & ~0xf)) {
581 if (td_last_trb_found)
584 if (new_deq == cur_td->last_trb)
585 td_last_trb_found = true;
587 if (cycle_found && trb_is_link(new_deq) &&
588 link_trb_toggles_cycle(new_deq))
589 state->new_cycle_state ^= 0x1;
591 next_trb(xhci, ep_ring, &new_seg, &new_deq);
593 /* Search wrapped around, bail out */
594 if (new_deq == ep->ring->dequeue) {
595 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
596 state->new_deq_seg = NULL;
597 state->new_deq_ptr = NULL;
601 } while (!cycle_found || !td_last_trb_found);
603 state->new_deq_seg = new_seg;
604 state->new_deq_ptr = new_deq;
606 /* Don't update the ring cycle state for the producer (us). */
607 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
608 "Cycle state = 0x%x", state->new_cycle_state);
610 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
611 "New dequeue segment = %p (virtual)",
613 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
614 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
615 "New dequeue pointer = 0x%llx (DMA)",
616 (unsigned long long) addr);
619 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
620 * (The last TRB actually points to the ring enqueue pointer, which is not part
621 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
623 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
624 struct xhci_td *td, bool flip_cycle)
626 struct xhci_segment *seg = td->start_seg;
627 union xhci_trb *trb = td->first_trb;
630 trb_to_noop(trb, TRB_TR_NOOP);
632 /* flip cycle if asked to */
633 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
634 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
636 if (trb == td->last_trb)
639 next_trb(xhci, ep_ring, &seg, &trb);
643 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
644 struct xhci_virt_ep *ep)
646 ep->ep_state &= ~EP_STOP_CMD_PENDING;
647 /* Can't del_timer_sync in interrupt */
648 del_timer(&ep->stop_cmd_timer);
652 * Must be called with xhci->lock held in interrupt context,
653 * releases and re-acquires xhci->lock
655 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
656 struct xhci_td *cur_td, int status)
658 struct urb *urb = cur_td->urb;
659 struct urb_priv *urb_priv = urb->hcpriv;
660 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
662 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
663 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
664 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
665 if (xhci->quirks & XHCI_AMD_PLL_FIX)
666 usb_amd_quirk_pll_enable();
669 xhci_urb_free_priv(urb_priv);
670 usb_hcd_unlink_urb_from_ep(hcd, urb);
671 spin_unlock(&xhci->lock);
672 trace_xhci_urb_giveback(urb);
673 usb_hcd_giveback_urb(hcd, urb, status);
674 spin_lock(&xhci->lock);
677 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
678 struct xhci_ring *ring, struct xhci_td *td)
680 struct device *dev = xhci_to_hcd(xhci)->self.controller;
681 struct xhci_segment *seg = td->bounce_seg;
682 struct urb *urb = td->urb;
685 if (!ring || !seg || !urb)
688 if (usb_urb_dir_out(urb)) {
689 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
694 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
696 /* for in tranfers we need to copy the data from bounce to sg */
697 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
698 seg->bounce_len, seg->bounce_offs);
699 if (len != seg->bounce_len)
700 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
701 len, seg->bounce_len);
703 seg->bounce_offs = 0;
707 * When we get a command completion for a Stop Endpoint Command, we need to
708 * unlink any cancelled TDs from the ring. There are two ways to do that:
710 * 1. If the HW was in the middle of processing the TD that needs to be
711 * cancelled, then we must move the ring's dequeue pointer past the last TRB
712 * in the TD with a Set Dequeue Pointer Command.
713 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
714 * bit cleared) so that the HW will skip over them.
716 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
717 union xhci_trb *trb, struct xhci_event_cmd *event)
719 unsigned int ep_index;
720 struct xhci_ring *ep_ring;
721 struct xhci_virt_ep *ep;
722 struct xhci_td *cur_td = NULL;
723 struct xhci_td *last_unlinked_td;
724 struct xhci_ep_ctx *ep_ctx;
725 struct xhci_virt_device *vdev;
727 struct xhci_dequeue_state deq_state;
729 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
730 if (!xhci->devs[slot_id])
731 xhci_warn(xhci, "Stop endpoint command "
732 "completion for disabled slot %u\n",
737 memset(&deq_state, 0, sizeof(deq_state));
738 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
740 vdev = xhci->devs[slot_id];
741 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
742 trace_xhci_handle_cmd_stop_ep(ep_ctx);
744 ep = &xhci->devs[slot_id]->eps[ep_index];
745 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
746 struct xhci_td, cancelled_td_list);
748 if (list_empty(&ep->cancelled_td_list)) {
749 xhci_stop_watchdog_timer_in_irq(xhci, ep);
750 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
754 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
755 * We have the xHCI lock, so nothing can modify this list until we drop
756 * it. We're also in the event handler, so we can't get re-interrupted
757 * if another Stop Endpoint command completes
759 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
760 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
761 "Removing canceled TD starting at 0x%llx (dma).",
762 (unsigned long long)xhci_trb_virt_to_dma(
763 cur_td->start_seg, cur_td->first_trb));
764 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
766 /* This shouldn't happen unless a driver is mucking
767 * with the stream ID after submission. This will
768 * leave the TD on the hardware ring, and the hardware
769 * will try to execute it, and may access a buffer
770 * that has already been freed. In the best case, the
771 * hardware will execute it, and the event handler will
772 * ignore the completion event for that TD, since it was
773 * removed from the td_list for that endpoint. In
774 * short, don't muck with the stream ID after
777 xhci_warn(xhci, "WARN Cancelled URB %p "
778 "has invalid stream ID %u.\n",
780 cur_td->urb->stream_id);
781 goto remove_finished_td;
784 * If we stopped on the TD we need to cancel, then we have to
785 * move the xHC endpoint ring dequeue pointer past this TD.
787 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
788 cur_td->urb->stream_id);
791 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
792 cur_td->last_trb, hw_deq, false)) {
793 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
794 cur_td->urb->stream_id,
797 td_to_noop(xhci, ep_ring, cur_td, false);
802 * The event handler won't see a completion for this TD anymore,
803 * so remove it from the endpoint ring's TD list. Keep it in
804 * the cancelled TD list for URB completion later.
806 list_del_init(&cur_td->td_list);
809 xhci_stop_watchdog_timer_in_irq(xhci, ep);
811 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
812 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
813 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
815 xhci_ring_cmd_db(xhci);
817 /* Otherwise ring the doorbell(s) to restart queued transfers */
818 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
822 * Drop the lock and complete the URBs in the cancelled TD list.
823 * New TDs to be cancelled might be added to the end of the list before
824 * we can complete all the URBs for the TDs we already unlinked.
825 * So stop when we've completed the URB for the last TD we unlinked.
828 cur_td = list_first_entry(&ep->cancelled_td_list,
829 struct xhci_td, cancelled_td_list);
830 list_del_init(&cur_td->cancelled_td_list);
832 /* Clean up the cancelled URB */
833 /* Doesn't matter what we pass for status, since the core will
834 * just overwrite it (because the URB has been unlinked).
836 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
837 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
838 inc_td_cnt(cur_td->urb);
839 if (last_td_in_urb(cur_td))
840 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
842 /* Stop processing the cancelled list if the watchdog timer is
845 if (xhci->xhc_state & XHCI_STATE_DYING)
847 } while (cur_td != last_unlinked_td);
849 /* Return to the event handler with xhci->lock re-acquired */
852 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
854 struct xhci_td *cur_td;
857 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
858 list_del_init(&cur_td->td_list);
860 if (!list_empty(&cur_td->cancelled_td_list))
861 list_del_init(&cur_td->cancelled_td_list);
863 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
865 inc_td_cnt(cur_td->urb);
866 if (last_td_in_urb(cur_td))
867 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
871 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
872 int slot_id, int ep_index)
874 struct xhci_td *cur_td;
876 struct xhci_virt_ep *ep;
877 struct xhci_ring *ring;
879 ep = &xhci->devs[slot_id]->eps[ep_index];
880 if ((ep->ep_state & EP_HAS_STREAMS) ||
881 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
884 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
886 ring = ep->stream_info->stream_rings[stream_id];
890 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
891 "Killing URBs for slot ID %u, ep index %u, stream %u",
892 slot_id, ep_index, stream_id);
893 xhci_kill_ring_urbs(xhci, ring);
899 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
900 "Killing URBs for slot ID %u, ep index %u",
902 xhci_kill_ring_urbs(xhci, ring);
905 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
907 list_del_init(&cur_td->cancelled_td_list);
908 inc_td_cnt(cur_td->urb);
910 if (last_td_in_urb(cur_td))
911 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
916 * host controller died, register read returns 0xffffffff
917 * Complete pending commands, mark them ABORTED.
918 * URBs need to be given back as usb core might be waiting with device locks
919 * held for the URBs to finish during device disconnect, blocking host remove.
921 * Call with xhci->lock held.
922 * lock is relased and re-acquired while giving back urb.
924 void xhci_hc_died(struct xhci_hcd *xhci)
928 if (xhci->xhc_state & XHCI_STATE_DYING)
931 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
932 xhci->xhc_state |= XHCI_STATE_DYING;
934 xhci_cleanup_command_queue(xhci);
936 /* return any pending urbs, remove may be waiting for them */
937 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
940 for (j = 0; j < 31; j++)
941 xhci_kill_endpoint_urbs(xhci, i, j);
944 /* inform usb core hc died if PCI remove isn't already handling it */
945 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
946 usb_hc_died(xhci_to_hcd(xhci));
949 /* Watchdog timer function for when a stop endpoint command fails to complete.
950 * In this case, we assume the host controller is broken or dying or dead. The
951 * host may still be completing some other events, so we have to be careful to
952 * let the event ring handler and the URB dequeueing/enqueueing functions know
953 * through xhci->state.
955 * The timer may also fire if the host takes a very long time to respond to the
956 * command, and the stop endpoint command completion handler cannot delete the
957 * timer before the timer function is called. Another endpoint cancellation may
958 * sneak in before the timer function can grab the lock, and that may queue
959 * another stop endpoint command and add the timer back. So we cannot use a
960 * simple flag to say whether there is a pending stop endpoint command for a
961 * particular endpoint.
963 * Instead we use a combination of that flag and checking if a new timer is
966 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
968 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
969 struct xhci_hcd *xhci = ep->xhci;
972 spin_lock_irqsave(&xhci->lock, flags);
974 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
975 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
976 timer_pending(&ep->stop_cmd_timer)) {
977 spin_unlock_irqrestore(&xhci->lock, flags);
978 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
982 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
983 ep->ep_state &= ~EP_STOP_CMD_PENDING;
988 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
989 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
990 * and try to recover a -ETIMEDOUT with a host controller reset
994 spin_unlock_irqrestore(&xhci->lock, flags);
995 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
996 "xHCI host controller is dead.");
999 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1000 struct xhci_virt_device *dev,
1001 struct xhci_ring *ep_ring,
1002 unsigned int ep_index)
1004 union xhci_trb *dequeue_temp;
1005 int num_trbs_free_temp;
1006 bool revert = false;
1008 num_trbs_free_temp = ep_ring->num_trbs_free;
1009 dequeue_temp = ep_ring->dequeue;
1011 /* If we get two back-to-back stalls, and the first stalled transfer
1012 * ends just before a link TRB, the dequeue pointer will be left on
1013 * the link TRB by the code in the while loop. So we have to update
1014 * the dequeue pointer one segment further, or we'll jump off
1015 * the segment into la-la-land.
1017 if (trb_is_link(ep_ring->dequeue)) {
1018 ep_ring->deq_seg = ep_ring->deq_seg->next;
1019 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1022 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1023 /* We have more usable TRBs */
1024 ep_ring->num_trbs_free++;
1026 if (trb_is_link(ep_ring->dequeue)) {
1027 if (ep_ring->dequeue ==
1028 dev->eps[ep_index].queued_deq_ptr)
1030 ep_ring->deq_seg = ep_ring->deq_seg->next;
1031 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1033 if (ep_ring->dequeue == dequeue_temp) {
1040 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1041 ep_ring->num_trbs_free = num_trbs_free_temp;
1046 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1047 * we need to clear the set deq pending flag in the endpoint ring state, so that
1048 * the TD queueing code can ring the doorbell again. We also need to ring the
1049 * endpoint doorbell to restart the ring, but only if there aren't more
1050 * cancellations pending.
1052 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1053 union xhci_trb *trb, u32 cmd_comp_code)
1055 unsigned int ep_index;
1056 unsigned int stream_id;
1057 struct xhci_ring *ep_ring;
1058 struct xhci_virt_device *dev;
1059 struct xhci_virt_ep *ep;
1060 struct xhci_ep_ctx *ep_ctx;
1061 struct xhci_slot_ctx *slot_ctx;
1063 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1064 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1065 dev = xhci->devs[slot_id];
1066 ep = &dev->eps[ep_index];
1068 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1070 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1072 /* XXX: Harmless??? */
1076 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078 trace_xhci_handle_cmd_set_deq(slot_ctx);
1079 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1081 if (cmd_comp_code != COMP_SUCCESS) {
1082 unsigned int ep_state;
1083 unsigned int slot_state;
1085 switch (cmd_comp_code) {
1086 case COMP_TRB_ERROR:
1087 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1089 case COMP_CONTEXT_STATE_ERROR:
1090 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1091 ep_state = GET_EP_CTX_STATE(ep_ctx);
1092 slot_state = le32_to_cpu(slot_ctx->dev_state);
1093 slot_state = GET_SLOT_STATE(slot_state);
1094 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1095 "Slot state = %u, EP state = %u",
1096 slot_state, ep_state);
1098 case COMP_SLOT_NOT_ENABLED_ERROR:
1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1103 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1107 /* OK what do we do now? The endpoint state is hosed, and we
1108 * should never get to this point if the synchronization between
1109 * queueing, and endpoint state are correct. This might happen
1110 * if the device gets disconnected after we've finished
1111 * cancelling URBs, which might not be an error...
1115 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1116 if (ep->ep_state & EP_HAS_STREAMS) {
1117 struct xhci_stream_ctx *ctx =
1118 &ep->stream_info->stream_ctx_array[stream_id];
1119 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1121 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1123 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1124 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1125 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1126 ep->queued_deq_ptr) == deq) {
1127 /* Update the ring's dequeue segment and dequeue pointer
1128 * to reflect the new position.
1130 update_ring_for_set_deq_completion(xhci, dev,
1133 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1134 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1135 ep->queued_deq_seg, ep->queued_deq_ptr);
1140 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1141 dev->eps[ep_index].queued_deq_seg = NULL;
1142 dev->eps[ep_index].queued_deq_ptr = NULL;
1143 /* Restart any rings with pending URBs */
1144 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1147 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1148 union xhci_trb *trb, u32 cmd_comp_code)
1150 struct xhci_virt_device *vdev;
1151 struct xhci_ep_ctx *ep_ctx;
1152 unsigned int ep_index;
1154 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1155 vdev = xhci->devs[slot_id];
1156 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1157 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1159 /* This command will only fail if the endpoint wasn't halted,
1160 * but we don't care.
1162 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1163 "Ignoring reset ep completion code of %u", cmd_comp_code);
1165 /* HW with the reset endpoint quirk needs to have a configure endpoint
1166 * command complete before the endpoint can be used. Queue that here
1167 * because the HW can't handle two commands being queued in a row.
1169 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1170 struct xhci_command *command;
1172 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1176 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1177 "Queueing configure endpoint command");
1178 xhci_queue_configure_endpoint(xhci, command,
1179 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1181 xhci_ring_cmd_db(xhci);
1183 /* Clear our internal halted state */
1184 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1188 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1189 struct xhci_command *command, u32 cmd_comp_code)
1191 if (cmd_comp_code == COMP_SUCCESS)
1192 command->slot_id = slot_id;
1194 command->slot_id = 0;
1197 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1199 struct xhci_virt_device *virt_dev;
1200 struct xhci_slot_ctx *slot_ctx;
1202 virt_dev = xhci->devs[slot_id];
1206 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1207 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1209 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1210 /* Delete default control endpoint resources */
1211 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1212 xhci_free_virt_device(xhci, slot_id);
1215 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1216 struct xhci_event_cmd *event, u32 cmd_comp_code)
1218 struct xhci_virt_device *virt_dev;
1219 struct xhci_input_control_ctx *ctrl_ctx;
1220 struct xhci_ep_ctx *ep_ctx;
1221 unsigned int ep_index;
1222 unsigned int ep_state;
1223 u32 add_flags, drop_flags;
1226 * Configure endpoint commands can come from the USB core
1227 * configuration or alt setting changes, or because the HW
1228 * needed an extra configure endpoint command after a reset
1229 * endpoint command or streams were being configured.
1230 * If the command was for a halted endpoint, the xHCI driver
1231 * is not waiting on the configure endpoint command.
1233 virt_dev = xhci->devs[slot_id];
1234 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1236 xhci_warn(xhci, "Could not get input context, bad type.\n");
1240 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1241 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1242 /* Input ctx add_flags are the endpoint index plus one */
1243 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1245 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1246 trace_xhci_handle_cmd_config_ep(ep_ctx);
1248 /* A usb_set_interface() call directly after clearing a halted
1249 * condition may race on this quirky hardware. Not worth
1250 * worrying about, since this is prototype hardware. Not sure
1251 * if this will work for streams, but streams support was
1252 * untested on this prototype.
1254 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1255 ep_index != (unsigned int) -1 &&
1256 add_flags - SLOT_FLAG == drop_flags) {
1257 ep_state = virt_dev->eps[ep_index].ep_state;
1258 if (!(ep_state & EP_HALTED))
1260 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1261 "Completed config ep cmd - "
1262 "last ep index = %d, state = %d",
1263 ep_index, ep_state);
1264 /* Clear internal halted state and restart ring(s) */
1265 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1266 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1272 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1274 struct xhci_virt_device *vdev;
1275 struct xhci_slot_ctx *slot_ctx;
1277 vdev = xhci->devs[slot_id];
1278 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1279 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1282 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1283 struct xhci_event_cmd *event)
1285 struct xhci_virt_device *vdev;
1286 struct xhci_slot_ctx *slot_ctx;
1288 vdev = xhci->devs[slot_id];
1289 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1290 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1292 xhci_dbg(xhci, "Completed reset device command.\n");
1293 if (!xhci->devs[slot_id])
1294 xhci_warn(xhci, "Reset device command completion "
1295 "for disabled slot %u\n", slot_id);
1298 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1299 struct xhci_event_cmd *event)
1301 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1302 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1305 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1306 "NEC firmware version %2x.%02x",
1307 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1308 NEC_FW_MINOR(le32_to_cpu(event->status)));
1311 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1313 list_del(&cmd->cmd_list);
1315 if (cmd->completion) {
1316 cmd->status = status;
1317 complete(cmd->completion);
1323 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1325 struct xhci_command *cur_cmd, *tmp_cmd;
1326 xhci->current_cmd = NULL;
1327 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1328 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1331 void xhci_handle_command_timeout(struct work_struct *work)
1333 struct xhci_hcd *xhci;
1334 unsigned long flags;
1337 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1339 spin_lock_irqsave(&xhci->lock, flags);
1342 * If timeout work is pending, or current_cmd is NULL, it means we
1343 * raced with command completion. Command is handled so just return.
1345 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1346 spin_unlock_irqrestore(&xhci->lock, flags);
1349 /* mark this command to be cancelled */
1350 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1352 /* Make sure command ring is running before aborting it */
1353 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1354 if (hw_ring_state == ~(u64)0) {
1356 goto time_out_completed;
1359 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1360 (hw_ring_state & CMD_RING_RUNNING)) {
1361 /* Prevent new doorbell, and start command abort */
1362 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1363 xhci_dbg(xhci, "Command timeout\n");
1364 xhci_abort_cmd_ring(xhci, flags);
1365 goto time_out_completed;
1368 /* host removed. Bail out */
1369 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1370 xhci_dbg(xhci, "host removed, ring start fail?\n");
1371 xhci_cleanup_command_queue(xhci);
1373 goto time_out_completed;
1376 /* command timeout on stopped ring, ring can't be aborted */
1377 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1378 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1381 spin_unlock_irqrestore(&xhci->lock, flags);
1385 static void handle_cmd_completion(struct xhci_hcd *xhci,
1386 struct xhci_event_cmd *event)
1388 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1390 dma_addr_t cmd_dequeue_dma;
1392 union xhci_trb *cmd_trb;
1393 struct xhci_command *cmd;
1396 cmd_dma = le64_to_cpu(event->cmd_trb);
1397 cmd_trb = xhci->cmd_ring->dequeue;
1399 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1401 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1404 * Check whether the completion event is for our internal kept
1407 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1409 "ERROR mismatched command completion event\n");
1413 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1415 cancel_delayed_work(&xhci->cmd_timer);
1417 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1419 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1420 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1421 complete_all(&xhci->cmd_ring_stop_completion);
1425 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1427 "Command completion event does not match command\n");
1432 * Host aborted the command ring, check if the current command was
1433 * supposed to be aborted, otherwise continue normally.
1434 * The command ring is stopped now, but the xHC will issue a Command
1435 * Ring Stopped event which will cause us to restart it.
1437 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1438 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1439 if (cmd->status == COMP_COMMAND_ABORTED) {
1440 if (xhci->current_cmd == cmd)
1441 xhci->current_cmd = NULL;
1446 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1448 case TRB_ENABLE_SLOT:
1449 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1451 case TRB_DISABLE_SLOT:
1452 xhci_handle_cmd_disable_slot(xhci, slot_id);
1455 if (!cmd->completion)
1456 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1459 case TRB_EVAL_CONTEXT:
1462 xhci_handle_cmd_addr_dev(xhci, slot_id);
1465 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1466 le32_to_cpu(cmd_trb->generic.field[3])));
1467 if (!cmd->completion)
1468 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1471 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1472 le32_to_cpu(cmd_trb->generic.field[3])));
1473 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1476 /* Is this an aborted command turned to NO-OP? */
1477 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1478 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1481 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1482 le32_to_cpu(cmd_trb->generic.field[3])));
1483 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1486 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1487 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1489 slot_id = TRB_TO_SLOT_ID(
1490 le32_to_cpu(cmd_trb->generic.field[3]));
1491 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1493 case TRB_NEC_GET_FW:
1494 xhci_handle_cmd_nec_get_fw(xhci, event);
1497 /* Skip over unknown commands on the event ring */
1498 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1502 /* restart timer if this wasn't the last command */
1503 if (!list_is_singular(&xhci->cmd_list)) {
1504 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1505 struct xhci_command, cmd_list);
1506 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1507 } else if (xhci->current_cmd == cmd) {
1508 xhci->current_cmd = NULL;
1512 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1514 inc_deq(xhci, xhci->cmd_ring);
1517 static void handle_vendor_event(struct xhci_hcd *xhci,
1518 union xhci_trb *event)
1522 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1523 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1524 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1525 handle_cmd_completion(xhci, &event->event_cmd);
1528 static void handle_device_notification(struct xhci_hcd *xhci,
1529 union xhci_trb *event)
1532 struct usb_device *udev;
1534 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1535 if (!xhci->devs[slot_id]) {
1536 xhci_warn(xhci, "Device Notification event for "
1537 "unused slot %u\n", slot_id);
1541 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1543 udev = xhci->devs[slot_id]->udev;
1544 if (udev && udev->parent)
1545 usb_wakeup_notification(udev->parent, udev->portnum);
1549 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1551 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1552 * If a connection to a USB 1 device is followed by another connection
1553 * to a USB 2 device.
1555 * Reset the PHY after the USB device is disconnected if device speed
1556 * is less than HCD_USB3.
1557 * Retry the reset sequence max of 4 times checking the PLL lock status.
1560 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1562 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1564 u32 retry_count = 4;
1567 /* Assert PHY reset */
1568 writel(0x6F, hcd->regs + 0x1048);
1570 /* De-assert the PHY reset */
1571 writel(0x7F, hcd->regs + 0x1048);
1573 pll_lock_check = readl(hcd->regs + 0x1070);
1574 } while (!(pll_lock_check & 0x1) && --retry_count);
1577 static void handle_port_status(struct xhci_hcd *xhci,
1578 union xhci_trb *event)
1580 struct usb_hcd *hcd;
1582 u32 portsc, cmd_reg;
1585 unsigned int hcd_portnum;
1586 struct xhci_bus_state *bus_state;
1587 bool bogus_port_status = false;
1588 struct xhci_port *port;
1590 /* Port status change events always have a successful completion code */
1591 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1593 "WARN: xHC returned failed port status event\n");
1595 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1596 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1598 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1599 if ((port_id <= 0) || (port_id > max_ports)) {
1600 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1601 inc_deq(xhci, xhci->event_ring);
1605 port = &xhci->hw_ports[port_id - 1];
1606 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1607 xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1608 bogus_port_status = true;
1612 /* We might get interrupts after shared_hcd is removed */
1613 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1614 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1615 bogus_port_status = true;
1619 hcd = port->rhub->hcd;
1620 bus_state = &xhci->bus_state[hcd_index(hcd)];
1621 hcd_portnum = port->hcd_portnum;
1622 portsc = readl(port->addr);
1624 trace_xhci_handle_port_status(hcd_portnum, portsc);
1626 if (hcd->state == HC_STATE_SUSPENDED) {
1627 xhci_dbg(xhci, "resume root hub\n");
1628 usb_hcd_resume_root_hub(hcd);
1631 if (hcd->speed >= HCD_USB3 &&
1632 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1633 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1634 if (slot_id && xhci->devs[slot_id])
1635 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1638 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1639 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1641 cmd_reg = readl(&xhci->op_regs->command);
1642 if (!(cmd_reg & CMD_RUN)) {
1643 xhci_warn(xhci, "xHC is not running.\n");
1647 if (DEV_SUPERSPEED_ANY(portsc)) {
1648 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1649 /* Set a flag to say the port signaled remote wakeup,
1650 * so we can tell the difference between the end of
1651 * device and host initiated resume.
1653 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1654 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1655 xhci_set_link_state(xhci, port, XDEV_U0);
1656 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1657 /* Need to wait until the next link state change
1658 * indicates the device is actually in U0.
1660 bogus_port_status = true;
1662 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1663 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1664 bus_state->resume_done[hcd_portnum] = jiffies +
1665 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1666 set_bit(hcd_portnum, &bus_state->resuming_ports);
1667 /* Do the rest in GetPortStatus after resume time delay.
1668 * Avoid polling roothub status before that so that a
1669 * usb device auto-resume latency around ~40ms.
1671 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1672 mod_timer(&hcd->rh_timer,
1673 bus_state->resume_done[hcd_portnum]);
1674 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1675 bogus_port_status = true;
1679 if ((portsc & PORT_PLC) &&
1680 DEV_SUPERSPEED_ANY(portsc) &&
1681 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1682 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1683 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1684 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1685 /* We've just brought the device into U0/1/2 through either the
1686 * Resume state after a device remote wakeup, or through the
1687 * U3Exit state after a host-initiated resume. If it's a device
1688 * initiated remote wake, don't pass up the link state change,
1689 * so the roothub behavior is consistent with external
1690 * USB 3.0 hub behavior.
1692 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1693 if (slot_id && xhci->devs[slot_id])
1694 xhci_ring_device(xhci, slot_id);
1695 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1696 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1697 usb_wakeup_notification(hcd->self.root_hub,
1699 bogus_port_status = true;
1705 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1706 * RExit to a disconnect state). If so, let the the driver know it's
1707 * out of the RExit state.
1709 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1710 test_and_clear_bit(hcd_portnum,
1711 &bus_state->rexit_ports)) {
1712 complete(&bus_state->rexit_done[hcd_portnum]);
1713 bogus_port_status = true;
1717 if (hcd->speed < HCD_USB3) {
1718 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1719 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1720 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1721 xhci_cavium_reset_phy_quirk(xhci);
1725 /* Update event ring dequeue pointer before dropping the lock */
1726 inc_deq(xhci, xhci->event_ring);
1728 /* Don't make the USB core poll the roothub if we got a bad port status
1729 * change event. Besides, at that point we can't tell which roothub
1730 * (USB 2.0 or USB 3.0) to kick.
1732 if (bogus_port_status)
1736 * xHCI port-status-change events occur when the "or" of all the
1737 * status-change bits in the portsc register changes from 0 to 1.
1738 * New status changes won't cause an event if any other change
1739 * bits are still set. When an event occurs, switch over to
1740 * polling to avoid losing status changes.
1742 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1743 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1744 spin_unlock(&xhci->lock);
1745 /* Pass this up to the core */
1746 usb_hcd_poll_rh_status(hcd);
1747 spin_lock(&xhci->lock);
1751 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1752 * at end_trb, which may be in another segment. If the suspect DMA address is a
1753 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1756 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1757 struct xhci_segment *start_seg,
1758 union xhci_trb *start_trb,
1759 union xhci_trb *end_trb,
1760 dma_addr_t suspect_dma,
1763 dma_addr_t start_dma;
1764 dma_addr_t end_seg_dma;
1765 dma_addr_t end_trb_dma;
1766 struct xhci_segment *cur_seg;
1768 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1769 cur_seg = start_seg;
1774 /* We may get an event for a Link TRB in the middle of a TD */
1775 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1776 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1777 /* If the end TRB isn't in this segment, this is set to 0 */
1778 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1782 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1783 (unsigned long long)suspect_dma,
1784 (unsigned long long)start_dma,
1785 (unsigned long long)end_trb_dma,
1786 (unsigned long long)cur_seg->dma,
1787 (unsigned long long)end_seg_dma);
1789 if (end_trb_dma > 0) {
1790 /* The end TRB is in this segment, so suspect should be here */
1791 if (start_dma <= end_trb_dma) {
1792 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1795 /* Case for one segment with
1796 * a TD wrapped around to the top
1798 if ((suspect_dma >= start_dma &&
1799 suspect_dma <= end_seg_dma) ||
1800 (suspect_dma >= cur_seg->dma &&
1801 suspect_dma <= end_trb_dma))
1806 /* Might still be somewhere in this segment */
1807 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1810 cur_seg = cur_seg->next;
1811 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1812 } while (cur_seg != start_seg);
1817 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1818 unsigned int slot_id, unsigned int ep_index,
1819 unsigned int stream_id, struct xhci_td *td,
1820 enum xhci_ep_reset_type reset_type)
1822 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1823 struct xhci_command *command;
1826 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1827 * Device will be reset soon to recover the link so don't do anything
1829 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1832 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1836 ep->ep_state |= EP_HALTED;
1838 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1840 if (reset_type == EP_HARD_RESET) {
1841 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1842 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1844 xhci_ring_cmd_db(xhci);
1847 /* Check if an error has halted the endpoint ring. The class driver will
1848 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1849 * However, a babble and other errors also halt the endpoint ring, and the class
1850 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1851 * Ring Dequeue Pointer command manually.
1853 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1854 struct xhci_ep_ctx *ep_ctx,
1855 unsigned int trb_comp_code)
1857 /* TRB completion codes that may require a manual halt cleanup */
1858 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1859 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1860 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1861 /* The 0.95 spec says a babbling control endpoint
1862 * is not halted. The 0.96 spec says it is. Some HW
1863 * claims to be 0.95 compliant, but it halts the control
1864 * endpoint anyway. Check if a babble halted the
1867 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1873 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1875 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1876 /* Vendor defined "informational" completion code,
1877 * treat as not-an-error.
1879 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1881 xhci_dbg(xhci, "Treating code as success.\n");
1887 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1888 struct xhci_ring *ep_ring, int *status)
1890 struct urb *urb = NULL;
1892 /* Clean up the endpoint's TD list */
1895 /* if a bounce buffer was used to align this td then unmap it */
1896 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1898 /* Do one last check of the actual transfer length.
1899 * If the host controller said we transferred more data than the buffer
1900 * length, urb->actual_length will be a very big number (since it's
1901 * unsigned). Play it safe and say we didn't transfer anything.
1903 if (urb->actual_length > urb->transfer_buffer_length) {
1904 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1905 urb->transfer_buffer_length, urb->actual_length);
1906 urb->actual_length = 0;
1909 list_del_init(&td->td_list);
1910 /* Was this TD slated to be cancelled but completed anyway? */
1911 if (!list_empty(&td->cancelled_td_list))
1912 list_del_init(&td->cancelled_td_list);
1915 /* Giveback the urb when all the tds are completed */
1916 if (last_td_in_urb(td)) {
1917 if ((urb->actual_length != urb->transfer_buffer_length &&
1918 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1919 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1920 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1921 urb, urb->actual_length,
1922 urb->transfer_buffer_length, *status);
1924 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1925 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1927 xhci_giveback_urb_in_irq(xhci, td, *status);
1933 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1934 struct xhci_transfer_event *event,
1935 struct xhci_virt_ep *ep, int *status)
1937 struct xhci_virt_device *xdev;
1938 struct xhci_ep_ctx *ep_ctx;
1939 struct xhci_ring *ep_ring;
1940 unsigned int slot_id;
1944 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1945 xdev = xhci->devs[slot_id];
1946 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1947 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1948 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1949 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1951 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1952 trb_comp_code == COMP_STOPPED ||
1953 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1954 /* The Endpoint Stop Command completion will take care of any
1955 * stopped TDs. A stopped TD may be restarted, so don't update
1956 * the ring dequeue pointer or take this TD off any lists yet.
1960 if (trb_comp_code == COMP_STALL_ERROR ||
1961 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1963 /* Issue a reset endpoint command to clear the host side
1964 * halt, followed by a set dequeue command to move the
1965 * dequeue pointer past the TD.
1966 * The class driver clears the device side halt later.
1968 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1969 ep_ring->stream_id, td, EP_HARD_RESET);
1971 /* Update ring dequeue pointer */
1972 while (ep_ring->dequeue != td->last_trb)
1973 inc_deq(xhci, ep_ring);
1974 inc_deq(xhci, ep_ring);
1977 return xhci_td_cleanup(xhci, td, ep_ring, status);
1980 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1981 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1982 union xhci_trb *stop_trb)
1985 union xhci_trb *trb = ring->dequeue;
1986 struct xhci_segment *seg = ring->deq_seg;
1988 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1989 if (!trb_is_noop(trb) && !trb_is_link(trb))
1990 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1996 * Process control tds, update urb status and actual_length.
1998 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1999 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2000 struct xhci_virt_ep *ep, int *status)
2002 struct xhci_virt_device *xdev;
2003 unsigned int slot_id;
2005 struct xhci_ep_ctx *ep_ctx;
2007 u32 remaining, requested;
2010 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2011 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2012 xdev = xhci->devs[slot_id];
2013 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2014 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2015 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2016 requested = td->urb->transfer_buffer_length;
2017 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2019 switch (trb_comp_code) {
2021 if (trb_type != TRB_STATUS) {
2022 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2023 (trb_type == TRB_DATA) ? "data" : "setup");
2024 *status = -ESHUTDOWN;
2029 case COMP_SHORT_PACKET:
2032 case COMP_STOPPED_SHORT_PACKET:
2033 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2034 td->urb->actual_length = remaining;
2036 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2041 td->urb->actual_length = 0;
2045 td->urb->actual_length = requested - remaining;
2048 td->urb->actual_length = requested;
2051 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2055 case COMP_STOPPED_LENGTH_INVALID:
2058 if (!xhci_requires_manual_halt_cleanup(xhci,
2059 ep_ctx, trb_comp_code))
2061 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2062 trb_comp_code, ep_index);
2063 /* else fall through */
2064 case COMP_STALL_ERROR:
2065 /* Did we transfer part of the data (middle) phase? */
2066 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2067 td->urb->actual_length = requested - remaining;
2068 else if (!td->urb_length_set)
2069 td->urb->actual_length = 0;
2073 /* stopped at setup stage, no data transferred */
2074 if (trb_type == TRB_SETUP)
2078 * if on data stage then update the actual_length of the URB and flag it
2079 * as set, so it won't be overwritten in the event for the last TRB.
2081 if (trb_type == TRB_DATA ||
2082 trb_type == TRB_NORMAL) {
2083 td->urb_length_set = true;
2084 td->urb->actual_length = requested - remaining;
2085 xhci_dbg(xhci, "Waiting for status stage event\n");
2089 /* at status stage */
2090 if (!td->urb_length_set)
2091 td->urb->actual_length = requested;
2094 return finish_td(xhci, td, event, ep, status);
2098 * Process isochronous tds, update urb packet status and actual_length.
2100 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2101 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2102 struct xhci_virt_ep *ep, int *status)
2104 struct xhci_ring *ep_ring;
2105 struct urb_priv *urb_priv;
2107 struct usb_iso_packet_descriptor *frame;
2109 bool sum_trbs_for_length = false;
2110 u32 remaining, requested, ep_trb_len;
2111 int short_framestatus;
2113 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2114 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2115 urb_priv = td->urb->hcpriv;
2116 idx = urb_priv->num_tds_done;
2117 frame = &td->urb->iso_frame_desc[idx];
2118 requested = frame->length;
2119 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2120 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2121 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2124 /* handle completion code */
2125 switch (trb_comp_code) {
2128 frame->status = short_framestatus;
2129 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2130 sum_trbs_for_length = true;
2135 case COMP_SHORT_PACKET:
2136 frame->status = short_framestatus;
2137 sum_trbs_for_length = true;
2139 case COMP_BANDWIDTH_OVERRUN_ERROR:
2140 frame->status = -ECOMM;
2142 case COMP_ISOCH_BUFFER_OVERRUN:
2143 case COMP_BABBLE_DETECTED_ERROR:
2144 frame->status = -EOVERFLOW;
2146 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2147 case COMP_STALL_ERROR:
2148 frame->status = -EPROTO;
2150 case COMP_USB_TRANSACTION_ERROR:
2151 frame->status = -EPROTO;
2152 if (ep_trb != td->last_trb)
2156 sum_trbs_for_length = true;
2158 case COMP_STOPPED_SHORT_PACKET:
2159 /* field normally containing residue now contains tranferred */
2160 frame->status = short_framestatus;
2161 requested = remaining;
2163 case COMP_STOPPED_LENGTH_INVALID:
2168 sum_trbs_for_length = true;
2173 if (sum_trbs_for_length)
2174 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2175 ep_trb_len - remaining;
2177 frame->actual_length = requested;
2179 td->urb->actual_length += frame->actual_length;
2181 return finish_td(xhci, td, event, ep, status);
2184 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2185 struct xhci_transfer_event *event,
2186 struct xhci_virt_ep *ep, int *status)
2188 struct xhci_ring *ep_ring;
2189 struct urb_priv *urb_priv;
2190 struct usb_iso_packet_descriptor *frame;
2193 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2194 urb_priv = td->urb->hcpriv;
2195 idx = urb_priv->num_tds_done;
2196 frame = &td->urb->iso_frame_desc[idx];
2198 /* The transfer is partly done. */
2199 frame->status = -EXDEV;
2201 /* calc actual length */
2202 frame->actual_length = 0;
2204 /* Update ring dequeue pointer */
2205 while (ep_ring->dequeue != td->last_trb)
2206 inc_deq(xhci, ep_ring);
2207 inc_deq(xhci, ep_ring);
2209 return xhci_td_cleanup(xhci, td, ep_ring, status);
2213 * Process bulk and interrupt tds, update urb status and actual_length.
2215 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2216 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2217 struct xhci_virt_ep *ep, int *status)
2219 struct xhci_ring *ep_ring;
2221 u32 remaining, requested, ep_trb_len;
2223 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2224 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2225 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2226 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2227 requested = td->urb->transfer_buffer_length;
2229 switch (trb_comp_code) {
2231 /* handle success with untransferred data as short packet */
2232 if (ep_trb != td->last_trb || remaining) {
2233 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2234 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2235 td->urb->ep->desc.bEndpointAddress,
2236 requested, remaining);
2240 case COMP_SHORT_PACKET:
2241 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2242 td->urb->ep->desc.bEndpointAddress,
2243 requested, remaining);
2246 case COMP_STOPPED_SHORT_PACKET:
2247 td->urb->actual_length = remaining;
2249 case COMP_STOPPED_LENGTH_INVALID:
2250 /* stopped on ep trb with invalid length, exclude it */
2259 if (ep_trb == td->last_trb)
2260 td->urb->actual_length = requested - remaining;
2262 td->urb->actual_length =
2263 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2264 ep_trb_len - remaining;
2266 if (remaining > requested) {
2267 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2269 td->urb->actual_length = 0;
2271 return finish_td(xhci, td, event, ep, status);
2275 * If this function returns an error condition, it means it got a Transfer
2276 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2277 * At this point, the host controller is probably hosed and should be reset.
2279 static int handle_tx_event(struct xhci_hcd *xhci,
2280 struct xhci_transfer_event *event)
2282 struct xhci_virt_device *xdev;
2283 struct xhci_virt_ep *ep;
2284 struct xhci_ring *ep_ring;
2285 unsigned int slot_id;
2287 struct xhci_td *td = NULL;
2288 dma_addr_t ep_trb_dma;
2289 struct xhci_segment *ep_seg;
2290 union xhci_trb *ep_trb;
2291 int status = -EINPROGRESS;
2292 struct xhci_ep_ctx *ep_ctx;
2293 struct list_head *tmp;
2296 bool handling_skipped_tds = false;
2298 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2299 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2300 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2301 ep_trb_dma = le64_to_cpu(event->buffer);
2303 xdev = xhci->devs[slot_id];
2305 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2310 ep = &xdev->eps[ep_index];
2311 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2312 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2314 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2316 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2321 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2323 switch (trb_comp_code) {
2324 case COMP_STALL_ERROR:
2325 case COMP_USB_TRANSACTION_ERROR:
2326 case COMP_INVALID_STREAM_TYPE_ERROR:
2327 case COMP_INVALID_STREAM_ID_ERROR:
2328 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2329 NULL, EP_SOFT_RESET);
2331 case COMP_RING_UNDERRUN:
2332 case COMP_RING_OVERRUN:
2333 case COMP_STOPPED_LENGTH_INVALID:
2336 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2342 /* Count current td numbers if ep->skip is set */
2344 list_for_each(tmp, &ep_ring->td_list)
2348 /* Look for common error cases */
2349 switch (trb_comp_code) {
2350 /* Skip codes that require special handling depending on
2354 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2356 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2357 ep_ring->last_td_was_short)
2358 trb_comp_code = COMP_SHORT_PACKET;
2360 xhci_warn_ratelimited(xhci,
2361 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2363 case COMP_SHORT_PACKET:
2365 /* Completion codes for endpoint stopped state */
2367 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2370 case COMP_STOPPED_LENGTH_INVALID:
2372 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2375 case COMP_STOPPED_SHORT_PACKET:
2377 "Stopped with short packet transfer detected for slot %u ep %u\n",
2380 /* Completion codes for endpoint halted state */
2381 case COMP_STALL_ERROR:
2382 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2384 ep->ep_state |= EP_HALTED;
2387 case COMP_SPLIT_TRANSACTION_ERROR:
2388 case COMP_USB_TRANSACTION_ERROR:
2389 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2393 case COMP_BABBLE_DETECTED_ERROR:
2394 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2396 status = -EOVERFLOW;
2398 /* Completion codes for endpoint error state */
2399 case COMP_TRB_ERROR:
2401 "WARN: TRB error for slot %u ep %u on endpoint\n",
2405 /* completion codes not indicating endpoint state change */
2406 case COMP_DATA_BUFFER_ERROR:
2408 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2412 case COMP_BANDWIDTH_OVERRUN_ERROR:
2414 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2417 case COMP_ISOCH_BUFFER_OVERRUN:
2419 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2422 case COMP_RING_UNDERRUN:
2424 * When the Isoch ring is empty, the xHC will generate
2425 * a Ring Overrun Event for IN Isoch endpoint or Ring
2426 * Underrun Event for OUT Isoch endpoint.
2428 xhci_dbg(xhci, "underrun event on endpoint\n");
2429 if (!list_empty(&ep_ring->td_list))
2430 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2431 "still with TDs queued?\n",
2432 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2435 case COMP_RING_OVERRUN:
2436 xhci_dbg(xhci, "overrun event on endpoint\n");
2437 if (!list_empty(&ep_ring->td_list))
2438 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2439 "still with TDs queued?\n",
2440 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2443 case COMP_MISSED_SERVICE_ERROR:
2445 * When encounter missed service error, one or more isoc tds
2446 * may be missed by xHC.
2447 * Set skip flag of the ep_ring; Complete the missed tds as
2448 * short transfer when process the ep_ring next time.
2452 "Miss service interval error for slot %u ep %u, set skip flag\n",
2455 case COMP_NO_PING_RESPONSE_ERROR:
2458 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2462 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2463 /* needs disable slot command to recover */
2465 "WARN: detect an incompatible device for slot %u ep %u",
2470 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2475 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2476 trb_comp_code, slot_id, ep_index);
2481 /* This TRB should be in the TD at the head of this ring's
2484 if (list_empty(&ep_ring->td_list)) {
2486 * Don't print wanings if it's due to a stopped endpoint
2487 * generating an extra completion event if the device
2488 * was suspended. Or, a event for the last TRB of a
2489 * short TD we already got a short event for.
2490 * The short TD is already removed from the TD list.
2493 if (!(trb_comp_code == COMP_STOPPED ||
2494 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2495 ep_ring->last_td_was_short)) {
2496 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2497 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2502 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2508 /* We've skipped all the TDs on the ep ring when ep->skip set */
2509 if (ep->skip && td_num == 0) {
2511 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2516 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2521 /* Is this a TRB in the currently executing TD? */
2522 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2523 td->last_trb, ep_trb_dma, false);
2526 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2527 * is not in the current TD pointed by ep_ring->dequeue because
2528 * that the hardware dequeue pointer still at the previous TRB
2529 * of the current TD. The previous TRB maybe a Link TD or the
2530 * last TRB of the previous TD. The command completion handle
2531 * will take care the rest.
2533 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2534 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2540 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2541 /* Some host controllers give a spurious
2542 * successful event after a short transfer.
2545 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2546 ep_ring->last_td_was_short) {
2547 ep_ring->last_td_was_short = false;
2550 /* HC is busted, give up! */
2552 "ERROR Transfer event TRB DMA ptr not "
2553 "part of current TD ep_index %d "
2554 "comp_code %u\n", ep_index,
2556 trb_in_td(xhci, ep_ring->deq_seg,
2557 ep_ring->dequeue, td->last_trb,
2562 skip_isoc_td(xhci, td, event, ep, &status);
2565 if (trb_comp_code == COMP_SHORT_PACKET)
2566 ep_ring->last_td_was_short = true;
2568 ep_ring->last_td_was_short = false;
2572 "Found td. Clear skip flag for slot %u ep %u.\n",
2577 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2580 trace_xhci_handle_transfer(ep_ring,
2581 (struct xhci_generic_trb *) ep_trb);
2584 * No-op TRB could trigger interrupts in a case where
2585 * a URB was killed and a STALL_ERROR happens right
2586 * after the endpoint ring stopped. Reset the halted
2587 * endpoint. Otherwise, the endpoint remains stalled
2590 if (trb_is_noop(ep_trb)) {
2591 if (trb_comp_code == COMP_STALL_ERROR ||
2592 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2594 xhci_cleanup_halted_endpoint(xhci, slot_id,
2601 /* update the urb's actual_length and give back to the core */
2602 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2603 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2604 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2605 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2607 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2610 handling_skipped_tds = ep->skip &&
2611 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2612 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2615 * Do not update event ring dequeue pointer if we're in a loop
2616 * processing missed tds.
2618 if (!handling_skipped_tds)
2619 inc_deq(xhci, xhci->event_ring);
2622 * If ep->skip is set, it means there are missed tds on the
2623 * endpoint ring need to take care of.
2624 * Process them as short transfer until reach the td pointed by
2627 } while (handling_skipped_tds);
2632 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2633 (unsigned long long) xhci_trb_virt_to_dma(
2634 xhci->event_ring->deq_seg,
2635 xhci->event_ring->dequeue),
2636 lower_32_bits(le64_to_cpu(event->buffer)),
2637 upper_32_bits(le64_to_cpu(event->buffer)),
2638 le32_to_cpu(event->transfer_len),
2639 le32_to_cpu(event->flags));
2644 * This function handles all OS-owned events on the event ring. It may drop
2645 * xhci->lock between event processing (e.g. to pass up port status changes).
2646 * Returns >0 for "possibly more events to process" (caller should call again),
2647 * otherwise 0 if done. In future, <0 returns should indicate error code.
2649 static int xhci_handle_event(struct xhci_hcd *xhci)
2651 union xhci_trb *event;
2652 int update_ptrs = 1;
2655 /* Event ring hasn't been allocated yet. */
2656 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2657 xhci_err(xhci, "ERROR event ring not ready\n");
2661 event = xhci->event_ring->dequeue;
2662 /* Does the HC or OS own the TRB? */
2663 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2664 xhci->event_ring->cycle_state)
2667 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2670 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2671 * speculative reads of the event's flags/data below.
2674 /* FIXME: Handle more event types. */
2675 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2676 case TRB_TYPE(TRB_COMPLETION):
2677 handle_cmd_completion(xhci, &event->event_cmd);
2679 case TRB_TYPE(TRB_PORT_STATUS):
2680 handle_port_status(xhci, event);
2683 case TRB_TYPE(TRB_TRANSFER):
2684 ret = handle_tx_event(xhci, &event->trans_event);
2688 case TRB_TYPE(TRB_DEV_NOTE):
2689 handle_device_notification(xhci, event);
2692 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2694 handle_vendor_event(xhci, event);
2696 xhci_warn(xhci, "ERROR unknown event type %d\n",
2698 le32_to_cpu(event->event_cmd.flags)));
2700 /* Any of the above functions may drop and re-acquire the lock, so check
2701 * to make sure a watchdog timer didn't mark the host as non-responsive.
2703 if (xhci->xhc_state & XHCI_STATE_DYING) {
2704 xhci_dbg(xhci, "xHCI host dying, returning from "
2705 "event handler.\n");
2710 /* Update SW event ring dequeue pointer */
2711 inc_deq(xhci, xhci->event_ring);
2713 /* Are there more items on the event ring? Caller will call us again to
2720 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2721 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2722 * indicators of an event TRB error, but we check the status *first* to be safe.
2724 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2726 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2727 union xhci_trb *event_ring_deq;
2728 irqreturn_t ret = IRQ_NONE;
2729 unsigned long flags;
2734 spin_lock_irqsave(&xhci->lock, flags);
2735 /* Check if the xHC generated the interrupt, or the irq is shared */
2736 status = readl(&xhci->op_regs->status);
2737 if (status == ~(u32)0) {
2743 if (!(status & STS_EINT))
2746 if (status & STS_FATAL) {
2747 xhci_warn(xhci, "WARNING: Host System Error\n");
2754 * Clear the op reg interrupt status first,
2755 * so we can receive interrupts from other MSI-X interrupters.
2756 * Write 1 to clear the interrupt status.
2759 writel(status, &xhci->op_regs->status);
2761 if (!hcd->msi_enabled) {
2763 irq_pending = readl(&xhci->ir_set->irq_pending);
2764 irq_pending |= IMAN_IP;
2765 writel(irq_pending, &xhci->ir_set->irq_pending);
2768 if (xhci->xhc_state & XHCI_STATE_DYING ||
2769 xhci->xhc_state & XHCI_STATE_HALTED) {
2770 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2771 "Shouldn't IRQs be disabled?\n");
2772 /* Clear the event handler busy flag (RW1C);
2773 * the event ring should be empty.
2775 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2776 xhci_write_64(xhci, temp_64 | ERST_EHB,
2777 &xhci->ir_set->erst_dequeue);
2782 event_ring_deq = xhci->event_ring->dequeue;
2783 /* FIXME this should be a delayed service routine
2784 * that clears the EHB.
2786 while (xhci_handle_event(xhci) > 0) {}
2788 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2789 /* If necessary, update the HW's version of the event ring deq ptr. */
2790 if (event_ring_deq != xhci->event_ring->dequeue) {
2791 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2792 xhci->event_ring->dequeue);
2794 xhci_warn(xhci, "WARN something wrong with SW event "
2795 "ring dequeue ptr.\n");
2796 /* Update HC event ring dequeue pointer */
2797 temp_64 &= ERST_PTR_MASK;
2798 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2801 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2802 temp_64 |= ERST_EHB;
2803 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2807 spin_unlock_irqrestore(&xhci->lock, flags);
2812 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2814 return xhci_irq(hcd);
2817 /**** Endpoint Ring Operations ****/
2820 * Generic function for queueing a TRB on a ring.
2821 * The caller must have checked to make sure there's room on the ring.
2823 * @more_trbs_coming: Will you enqueue more TRBs before calling
2824 * prepare_transfer()?
2826 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2827 bool more_trbs_coming,
2828 u32 field1, u32 field2, u32 field3, u32 field4)
2830 struct xhci_generic_trb *trb;
2832 trb = &ring->enqueue->generic;
2833 trb->field[0] = cpu_to_le32(field1);
2834 trb->field[1] = cpu_to_le32(field2);
2835 trb->field[2] = cpu_to_le32(field3);
2836 trb->field[3] = cpu_to_le32(field4);
2838 trace_xhci_queue_trb(ring, trb);
2840 inc_enq(xhci, ring, more_trbs_coming);
2844 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2845 * FIXME allocate segments if the ring is full.
2847 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2848 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2850 unsigned int num_trbs_needed;
2852 /* Make sure the endpoint has been added to xHC schedule */
2854 case EP_STATE_DISABLED:
2856 * USB core changed config/interfaces without notifying us,
2857 * or hardware is reporting the wrong state.
2859 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2861 case EP_STATE_ERROR:
2862 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2863 /* FIXME event handling code for error needs to clear it */
2864 /* XXX not sure if this should be -ENOENT or not */
2866 case EP_STATE_HALTED:
2867 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2868 case EP_STATE_STOPPED:
2869 case EP_STATE_RUNNING:
2872 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2874 * FIXME issue Configure Endpoint command to try to get the HC
2875 * back into a known state.
2881 if (room_on_ring(xhci, ep_ring, num_trbs))
2884 if (ep_ring == xhci->cmd_ring) {
2885 xhci_err(xhci, "Do not support expand command ring\n");
2889 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2890 "ERROR no room on ep ring, try ring expansion");
2891 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2892 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2894 xhci_err(xhci, "Ring expansion failed\n");
2899 while (trb_is_link(ep_ring->enqueue)) {
2900 /* If we're not dealing with 0.95 hardware or isoc rings
2901 * on AMD 0.96 host, clear the chain bit.
2903 if (!xhci_link_trb_quirk(xhci) &&
2904 !(ep_ring->type == TYPE_ISOC &&
2905 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2906 ep_ring->enqueue->link.control &=
2907 cpu_to_le32(~TRB_CHAIN);
2909 ep_ring->enqueue->link.control |=
2910 cpu_to_le32(TRB_CHAIN);
2913 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2915 /* Toggle the cycle bit after the last ring segment. */
2916 if (link_trb_toggles_cycle(ep_ring->enqueue))
2917 ep_ring->cycle_state ^= 1;
2919 ep_ring->enq_seg = ep_ring->enq_seg->next;
2920 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2925 static int prepare_transfer(struct xhci_hcd *xhci,
2926 struct xhci_virt_device *xdev,
2927 unsigned int ep_index,
2928 unsigned int stream_id,
2929 unsigned int num_trbs,
2931 unsigned int td_index,
2935 struct urb_priv *urb_priv;
2937 struct xhci_ring *ep_ring;
2938 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2940 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2942 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2947 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2948 num_trbs, mem_flags);
2952 urb_priv = urb->hcpriv;
2953 td = &urb_priv->td[td_index];
2955 INIT_LIST_HEAD(&td->td_list);
2956 INIT_LIST_HEAD(&td->cancelled_td_list);
2958 if (td_index == 0) {
2959 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2965 /* Add this TD to the tail of the endpoint ring's TD list */
2966 list_add_tail(&td->td_list, &ep_ring->td_list);
2967 td->start_seg = ep_ring->enq_seg;
2968 td->first_trb = ep_ring->enqueue;
2973 unsigned int count_trbs(u64 addr, u64 len)
2975 unsigned int num_trbs;
2977 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2985 static inline unsigned int count_trbs_needed(struct urb *urb)
2987 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2990 static unsigned int count_sg_trbs_needed(struct urb *urb)
2992 struct scatterlist *sg;
2993 unsigned int i, len, full_len, num_trbs = 0;
2995 full_len = urb->transfer_buffer_length;
2997 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2998 len = sg_dma_len(sg);
2999 num_trbs += count_trbs(sg_dma_address(sg), len);
3000 len = min_t(unsigned int, len, full_len);
3009 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3013 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3014 len = urb->iso_frame_desc[i].length;
3016 return count_trbs(addr, len);
3019 static void check_trb_math(struct urb *urb, int running_total)
3021 if (unlikely(running_total != urb->transfer_buffer_length))
3022 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3023 "queued %#x (%d), asked for %#x (%d)\n",
3025 urb->ep->desc.bEndpointAddress,
3026 running_total, running_total,
3027 urb->transfer_buffer_length,
3028 urb->transfer_buffer_length);
3031 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3032 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3033 struct xhci_generic_trb *start_trb)
3036 * Pass all the TRBs to the hardware at once and make sure this write
3041 start_trb->field[3] |= cpu_to_le32(start_cycle);
3043 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3044 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3047 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3048 struct xhci_ep_ctx *ep_ctx)
3053 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3054 ep_interval = urb->interval;
3056 /* Convert to microframes */
3057 if (urb->dev->speed == USB_SPEED_LOW ||
3058 urb->dev->speed == USB_SPEED_FULL)
3061 /* FIXME change this to a warning and a suggestion to use the new API
3062 * to set the polling interval (once the API is added).
3064 if (xhci_interval != ep_interval) {
3065 dev_dbg_ratelimited(&urb->dev->dev,
3066 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3067 ep_interval, ep_interval == 1 ? "" : "s",
3068 xhci_interval, xhci_interval == 1 ? "" : "s");
3069 urb->interval = xhci_interval;
3070 /* Convert back to frames for LS/FS devices */
3071 if (urb->dev->speed == USB_SPEED_LOW ||
3072 urb->dev->speed == USB_SPEED_FULL)
3078 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3079 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3080 * (comprised of sg list entries) can take several service intervals to
3083 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3084 struct urb *urb, int slot_id, unsigned int ep_index)
3086 struct xhci_ep_ctx *ep_ctx;
3088 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3089 check_interval(xhci, urb, ep_ctx);
3091 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3095 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3096 * packets remaining in the TD (*not* including this TRB).
3098 * Total TD packet count = total_packet_count =
3099 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3101 * Packets transferred up to and including this TRB = packets_transferred =
3102 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3104 * TD size = total_packet_count - packets_transferred
3106 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3107 * including this TRB, right shifted by 10
3109 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3110 * This is taken care of in the TRB_TD_SIZE() macro
3112 * The last TRB in a TD must have the TD size set to zero.
3114 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3115 int trb_buff_len, unsigned int td_total_len,
3116 struct urb *urb, bool more_trbs_coming)
3118 u32 maxp, total_packet_count;
3120 /* MTK xHCI 0.96 contains some features from 1.0 */
3121 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3122 return ((td_total_len - transferred) >> 10);
3124 /* One TRB with a zero-length data packet. */
3125 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3126 trb_buff_len == td_total_len)
3129 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3130 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3133 maxp = usb_endpoint_maxp(&urb->ep->desc);
3134 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3136 /* Queueing functions don't count the current TRB into transferred */
3137 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3141 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3142 u32 *trb_buff_len, struct xhci_segment *seg)
3144 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3145 unsigned int unalign;
3146 unsigned int max_pkt;
3150 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3151 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3153 /* we got lucky, last normal TRB data on segment is packet aligned */
3157 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3158 unalign, *trb_buff_len);
3160 /* is the last nornal TRB alignable by splitting it */
3161 if (*trb_buff_len > unalign) {
3162 *trb_buff_len -= unalign;
3163 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3168 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3169 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3170 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3172 new_buff_len = max_pkt - (enqd_len % max_pkt);
3174 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3175 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3177 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3178 if (usb_urb_dir_out(urb)) {
3179 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3180 seg->bounce_buf, new_buff_len, enqd_len);
3181 if (len != new_buff_len)
3183 "WARN Wrong bounce buffer write length: %zu != %d\n",
3185 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3186 max_pkt, DMA_TO_DEVICE);
3188 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3189 max_pkt, DMA_FROM_DEVICE);
3192 if (dma_mapping_error(dev, seg->bounce_dma)) {
3193 /* try without aligning. Some host controllers survive */
3194 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3197 *trb_buff_len = new_buff_len;
3198 seg->bounce_len = new_buff_len;
3199 seg->bounce_offs = enqd_len;
3201 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3206 /* This is very similar to what ehci-q.c qtd_fill() does */
3207 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3208 struct urb *urb, int slot_id, unsigned int ep_index)
3210 struct xhci_ring *ring;
3211 struct urb_priv *urb_priv;
3213 struct xhci_generic_trb *start_trb;
3214 struct scatterlist *sg = NULL;
3215 bool more_trbs_coming = true;
3216 bool need_zero_pkt = false;
3217 bool first_trb = true;
3218 unsigned int num_trbs;
3219 unsigned int start_cycle, num_sgs = 0;
3220 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3222 u32 field, length_field, remainder;
3223 u64 addr, send_addr;
3225 ring = xhci_urb_to_transfer_ring(xhci, urb);
3229 full_len = urb->transfer_buffer_length;
3230 /* If we have scatter/gather list, we use it. */
3232 num_sgs = urb->num_mapped_sgs;
3234 addr = (u64) sg_dma_address(sg);
3235 block_len = sg_dma_len(sg);
3236 num_trbs = count_sg_trbs_needed(urb);
3238 num_trbs = count_trbs_needed(urb);
3239 addr = (u64) urb->transfer_dma;
3240 block_len = full_len;
3242 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3243 ep_index, urb->stream_id,
3244 num_trbs, urb, 0, mem_flags);
3245 if (unlikely(ret < 0))
3248 urb_priv = urb->hcpriv;
3250 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3251 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3252 need_zero_pkt = true;
3254 td = &urb_priv->td[0];
3257 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3258 * until we've finished creating all the other TRBs. The ring's cycle
3259 * state may change as we enqueue the other TRBs, so save it too.
3261 start_trb = &ring->enqueue->generic;
3262 start_cycle = ring->cycle_state;
3265 /* Queue the TRBs, even if they are zero-length */
3266 for (enqd_len = 0; first_trb || enqd_len < full_len;
3267 enqd_len += trb_buff_len) {
3268 field = TRB_TYPE(TRB_NORMAL);
3270 /* TRB buffer should not cross 64KB boundaries */
3271 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3272 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3274 if (enqd_len + trb_buff_len > full_len)
3275 trb_buff_len = full_len - enqd_len;
3277 /* Don't change the cycle bit of the first TRB until later */
3280 if (start_cycle == 0)
3283 field |= ring->cycle_state;
3285 /* Chain all the TRBs together; clear the chain bit in the last
3286 * TRB to indicate it's the last TRB in the chain.
3288 if (enqd_len + trb_buff_len < full_len) {
3290 if (trb_is_link(ring->enqueue + 1)) {
3291 if (xhci_align_td(xhci, urb, enqd_len,
3294 send_addr = ring->enq_seg->bounce_dma;
3295 /* assuming TD won't span 2 segs */
3296 td->bounce_seg = ring->enq_seg;
3300 if (enqd_len + trb_buff_len >= full_len) {
3301 field &= ~TRB_CHAIN;
3303 more_trbs_coming = false;
3304 td->last_trb = ring->enqueue;
3307 /* Only set interrupt on short packet for IN endpoints */
3308 if (usb_urb_dir_in(urb))
3311 /* Set the TRB length, TD size, and interrupter fields. */
3312 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3313 full_len, urb, more_trbs_coming);
3315 length_field = TRB_LEN(trb_buff_len) |
3316 TRB_TD_SIZE(remainder) |
3319 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3320 lower_32_bits(send_addr),
3321 upper_32_bits(send_addr),
3325 addr += trb_buff_len;
3326 sent_len = trb_buff_len;
3328 while (sg && sent_len >= block_len) {
3331 sent_len -= block_len;
3334 block_len = sg_dma_len(sg);
3335 addr = (u64) sg_dma_address(sg);
3339 block_len -= sent_len;
3343 if (need_zero_pkt) {
3344 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3345 ep_index, urb->stream_id,
3346 1, urb, 1, mem_flags);
3347 urb_priv->td[1].last_trb = ring->enqueue;
3348 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3349 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3352 check_trb_math(urb, enqd_len);
3353 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3354 start_cycle, start_trb);
3358 /* Caller must have locked xhci->lock */
3359 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3360 struct urb *urb, int slot_id, unsigned int ep_index)
3362 struct xhci_ring *ep_ring;
3365 struct usb_ctrlrequest *setup;
3366 struct xhci_generic_trb *start_trb;
3369 struct urb_priv *urb_priv;
3372 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3377 * Need to copy setup packet into setup TRB, so we can't use the setup
3380 if (!urb->setup_packet)
3383 /* 1 TRB for setup, 1 for status */
3386 * Don't need to check if we need additional event data and normal TRBs,
3387 * since data in control transfers will never get bigger than 16MB
3388 * XXX: can we get a buffer that crosses 64KB boundaries?
3390 if (urb->transfer_buffer_length > 0)
3392 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3393 ep_index, urb->stream_id,
3394 num_trbs, urb, 0, mem_flags);
3398 urb_priv = urb->hcpriv;
3399 td = &urb_priv->td[0];
3402 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3403 * until we've finished creating all the other TRBs. The ring's cycle
3404 * state may change as we enqueue the other TRBs, so save it too.
3406 start_trb = &ep_ring->enqueue->generic;
3407 start_cycle = ep_ring->cycle_state;
3409 /* Queue setup TRB - see section 6.4.1.2.1 */
3410 /* FIXME better way to translate setup_packet into two u32 fields? */
3411 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3413 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3414 if (start_cycle == 0)
3417 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3418 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3419 if (urb->transfer_buffer_length > 0) {
3420 if (setup->bRequestType & USB_DIR_IN)
3421 field |= TRB_TX_TYPE(TRB_DATA_IN);
3423 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3427 queue_trb(xhci, ep_ring, true,
3428 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3429 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3430 TRB_LEN(8) | TRB_INTR_TARGET(0),
3431 /* Immediate data in pointer */
3434 /* If there's data, queue data TRBs */
3435 /* Only set interrupt on short packet for IN endpoints */
3436 if (usb_urb_dir_in(urb))
3437 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3439 field = TRB_TYPE(TRB_DATA);
3441 if (urb->transfer_buffer_length > 0) {
3442 u32 length_field, remainder;
3444 remainder = xhci_td_remainder(xhci, 0,
3445 urb->transfer_buffer_length,
3446 urb->transfer_buffer_length,
3448 length_field = TRB_LEN(urb->transfer_buffer_length) |
3449 TRB_TD_SIZE(remainder) |
3451 if (setup->bRequestType & USB_DIR_IN)
3452 field |= TRB_DIR_IN;
3453 queue_trb(xhci, ep_ring, true,
3454 lower_32_bits(urb->transfer_dma),
3455 upper_32_bits(urb->transfer_dma),
3457 field | ep_ring->cycle_state);
3460 /* Save the DMA address of the last TRB in the TD */
3461 td->last_trb = ep_ring->enqueue;
3463 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3464 /* If the device sent data, the status stage is an OUT transfer */
3465 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3469 queue_trb(xhci, ep_ring, false,
3473 /* Event on completion */
3474 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3476 giveback_first_trb(xhci, slot_id, ep_index, 0,
3477 start_cycle, start_trb);
3482 * The transfer burst count field of the isochronous TRB defines the number of
3483 * bursts that are required to move all packets in this TD. Only SuperSpeed
3484 * devices can burst up to bMaxBurst number of packets per service interval.
3485 * This field is zero based, meaning a value of zero in the field means one
3486 * burst. Basically, for everything but SuperSpeed devices, this field will be
3487 * zero. Only xHCI 1.0 host controllers support this field.
3489 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3490 struct urb *urb, unsigned int total_packet_count)
3492 unsigned int max_burst;
3494 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3497 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3498 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3502 * Returns the number of packets in the last "burst" of packets. This field is
3503 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3504 * the last burst packet count is equal to the total number of packets in the
3505 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3506 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3507 * contain 1 to (bMaxBurst + 1) packets.
3509 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3510 struct urb *urb, unsigned int total_packet_count)
3512 unsigned int max_burst;
3513 unsigned int residue;
3515 if (xhci->hci_version < 0x100)
3518 if (urb->dev->speed >= USB_SPEED_SUPER) {
3519 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3520 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3521 residue = total_packet_count % (max_burst + 1);
3522 /* If residue is zero, the last burst contains (max_burst + 1)
3523 * number of packets, but the TLBPC field is zero-based.
3529 if (total_packet_count == 0)
3531 return total_packet_count - 1;
3535 * Calculates Frame ID field of the isochronous TRB identifies the
3536 * target frame that the Interval associated with this Isochronous
3537 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3539 * Returns actual frame id on success, negative value on error.
3541 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3542 struct urb *urb, int index)
3544 int start_frame, ist, ret = 0;
3545 int start_frame_id, end_frame_id, current_frame_id;
3547 if (urb->dev->speed == USB_SPEED_LOW ||
3548 urb->dev->speed == USB_SPEED_FULL)
3549 start_frame = urb->start_frame + index * urb->interval;
3551 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3553 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3555 * If bit [3] of IST is cleared to '0', software can add a TRB no
3556 * later than IST[2:0] Microframes before that TRB is scheduled to
3558 * If bit [3] of IST is set to '1', software can add a TRB no later
3559 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3561 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3562 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3565 /* Software shall not schedule an Isoch TD with a Frame ID value that
3566 * is less than the Start Frame ID or greater than the End Frame ID,
3569 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3570 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3572 * Both the End Frame ID and Start Frame ID values are calculated
3573 * in microframes. When software determines the valid Frame ID value;
3574 * The End Frame ID value should be rounded down to the nearest Frame
3575 * boundary, and the Start Frame ID value should be rounded up to the
3576 * nearest Frame boundary.
3578 current_frame_id = readl(&xhci->run_regs->microframe_index);
3579 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3580 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3582 start_frame &= 0x7ff;
3583 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3584 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3586 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3587 __func__, index, readl(&xhci->run_regs->microframe_index),
3588 start_frame_id, end_frame_id, start_frame);
3590 if (start_frame_id < end_frame_id) {
3591 if (start_frame > end_frame_id ||
3592 start_frame < start_frame_id)
3594 } else if (start_frame_id > end_frame_id) {
3595 if ((start_frame > end_frame_id &&
3596 start_frame < start_frame_id))
3603 if (ret == -EINVAL || start_frame == start_frame_id) {
3604 start_frame = start_frame_id + 1;
3605 if (urb->dev->speed == USB_SPEED_LOW ||
3606 urb->dev->speed == USB_SPEED_FULL)
3607 urb->start_frame = start_frame;
3609 urb->start_frame = start_frame << 3;
3615 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3616 start_frame, current_frame_id, index,
3617 start_frame_id, end_frame_id);
3618 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3625 /* This is for isoc transfer */
3626 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3627 struct urb *urb, int slot_id, unsigned int ep_index)
3629 struct xhci_ring *ep_ring;
3630 struct urb_priv *urb_priv;
3632 int num_tds, trbs_per_td;
3633 struct xhci_generic_trb *start_trb;
3636 u32 field, length_field;
3637 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3638 u64 start_addr, addr;
3640 bool more_trbs_coming;
3641 struct xhci_virt_ep *xep;
3644 xep = &xhci->devs[slot_id]->eps[ep_index];
3645 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3647 num_tds = urb->number_of_packets;
3649 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3652 start_addr = (u64) urb->transfer_dma;
3653 start_trb = &ep_ring->enqueue->generic;
3654 start_cycle = ep_ring->cycle_state;
3656 urb_priv = urb->hcpriv;
3657 /* Queue the TRBs for each TD, even if they are zero-length */
3658 for (i = 0; i < num_tds; i++) {
3659 unsigned int total_pkt_count, max_pkt;
3660 unsigned int burst_count, last_burst_pkt_count;
3665 addr = start_addr + urb->iso_frame_desc[i].offset;
3666 td_len = urb->iso_frame_desc[i].length;
3667 td_remain_len = td_len;
3668 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3669 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3671 /* A zero-length transfer still involves at least one packet. */
3672 if (total_pkt_count == 0)
3674 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3675 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3676 urb, total_pkt_count);
3678 trbs_per_td = count_isoc_trbs_needed(urb, i);
3680 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3681 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3687 td = &urb_priv->td[i];
3689 /* use SIA as default, if frame id is used overwrite it */
3690 sia_frame_id = TRB_SIA;
3691 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3692 HCC_CFC(xhci->hcc_params)) {
3693 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3695 sia_frame_id = TRB_FRAME_ID(frame_id);
3698 * Set isoc specific data for the first TRB in a TD.
3699 * Prevent HW from getting the TRBs by keeping the cycle state
3700 * inverted in the first TDs isoc TRB.
3702 field = TRB_TYPE(TRB_ISOC) |
3703 TRB_TLBPC(last_burst_pkt_count) |
3705 (i ? ep_ring->cycle_state : !start_cycle);
3707 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3708 if (!xep->use_extended_tbc)
3709 field |= TRB_TBC(burst_count);
3711 /* fill the rest of the TRB fields, and remaining normal TRBs */
3712 for (j = 0; j < trbs_per_td; j++) {
3715 /* only first TRB is isoc, overwrite otherwise */
3717 field = TRB_TYPE(TRB_NORMAL) |
3718 ep_ring->cycle_state;
3720 /* Only set interrupt on short packet for IN EPs */
3721 if (usb_urb_dir_in(urb))
3724 /* Set the chain bit for all except the last TRB */
3725 if (j < trbs_per_td - 1) {
3726 more_trbs_coming = true;
3729 more_trbs_coming = false;
3730 td->last_trb = ep_ring->enqueue;
3732 /* set BEI, except for the last TD */
3733 if (xhci->hci_version >= 0x100 &&
3734 !(xhci->quirks & XHCI_AVOID_BEI) &&
3738 /* Calculate TRB length */
3739 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3740 if (trb_buff_len > td_remain_len)
3741 trb_buff_len = td_remain_len;
3743 /* Set the TRB length, TD size, & interrupter fields. */
3744 remainder = xhci_td_remainder(xhci, running_total,
3745 trb_buff_len, td_len,
3746 urb, more_trbs_coming);
3748 length_field = TRB_LEN(trb_buff_len) |
3751 /* xhci 1.1 with ETE uses TD Size field for TBC */
3752 if (first_trb && xep->use_extended_tbc)
3753 length_field |= TRB_TD_SIZE_TBC(burst_count);
3755 length_field |= TRB_TD_SIZE(remainder);
3758 queue_trb(xhci, ep_ring, more_trbs_coming,
3759 lower_32_bits(addr),
3760 upper_32_bits(addr),
3763 running_total += trb_buff_len;
3765 addr += trb_buff_len;
3766 td_remain_len -= trb_buff_len;
3769 /* Check TD length */
3770 if (running_total != td_len) {
3771 xhci_err(xhci, "ISOC TD length unmatch\n");
3777 /* store the next frame id */
3778 if (HCC_CFC(xhci->hcc_params))
3779 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3781 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3782 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3783 usb_amd_quirk_pll_disable();
3785 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3787 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3788 start_cycle, start_trb);
3791 /* Clean up a partially enqueued isoc transfer. */
3793 for (i--; i >= 0; i--)
3794 list_del_init(&urb_priv->td[i].td_list);
3796 /* Use the first TD as a temporary variable to turn the TDs we've queued
3797 * into No-ops with a software-owned cycle bit. That way the hardware
3798 * won't accidentally start executing bogus TDs when we partially
3799 * overwrite them. td->first_trb and td->start_seg are already set.
3801 urb_priv->td[0].last_trb = ep_ring->enqueue;
3802 /* Every TRB except the first & last will have its cycle bit flipped. */
3803 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3805 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3806 ep_ring->enqueue = urb_priv->td[0].first_trb;
3807 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3808 ep_ring->cycle_state = start_cycle;
3809 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3810 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3815 * Check transfer ring to guarantee there is enough room for the urb.
3816 * Update ISO URB start_frame and interval.
3817 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3818 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3819 * Contiguous Frame ID is not supported by HC.
3821 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3822 struct urb *urb, int slot_id, unsigned int ep_index)
3824 struct xhci_virt_device *xdev;
3825 struct xhci_ring *ep_ring;
3826 struct xhci_ep_ctx *ep_ctx;
3828 int num_tds, num_trbs, i;
3830 struct xhci_virt_ep *xep;
3833 xdev = xhci->devs[slot_id];
3834 xep = &xhci->devs[slot_id]->eps[ep_index];
3835 ep_ring = xdev->eps[ep_index].ring;
3836 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3839 num_tds = urb->number_of_packets;
3840 for (i = 0; i < num_tds; i++)
3841 num_trbs += count_isoc_trbs_needed(urb, i);
3843 /* Check the ring to guarantee there is enough room for the whole urb.
3844 * Do not insert any td of the urb to the ring if the check failed.
3846 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3847 num_trbs, mem_flags);
3852 * Check interval value. This should be done before we start to
3853 * calculate the start frame value.
3855 check_interval(xhci, urb, ep_ctx);
3857 /* Calculate the start frame and put it in urb->start_frame. */
3858 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3859 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3860 urb->start_frame = xep->next_frame_id;
3861 goto skip_start_over;
3865 start_frame = readl(&xhci->run_regs->microframe_index);
3866 start_frame &= 0x3fff;
3868 * Round up to the next frame and consider the time before trb really
3869 * gets scheduled by hardare.
3871 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3872 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3874 start_frame += ist + XHCI_CFC_DELAY;
3875 start_frame = roundup(start_frame, 8);
3878 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3879 * is greate than 8 microframes.
3881 if (urb->dev->speed == USB_SPEED_LOW ||
3882 urb->dev->speed == USB_SPEED_FULL) {
3883 start_frame = roundup(start_frame, urb->interval << 3);
3884 urb->start_frame = start_frame >> 3;
3886 start_frame = roundup(start_frame, urb->interval);
3887 urb->start_frame = start_frame;
3891 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3893 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3896 /**** Command Ring Operations ****/
3898 /* Generic function for queueing a command TRB on the command ring.
3899 * Check to make sure there's room on the command ring for one command TRB.
3900 * Also check that there's room reserved for commands that must not fail.
3901 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3902 * then only check for the number of reserved spots.
3903 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3904 * because the command event handler may want to resubmit a failed command.
3906 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3907 u32 field1, u32 field2,
3908 u32 field3, u32 field4, bool command_must_succeed)
3910 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3913 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3914 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3915 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3919 if (!command_must_succeed)
3922 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3923 reserved_trbs, GFP_ATOMIC);
3925 xhci_err(xhci, "ERR: No room for command on command ring\n");
3926 if (command_must_succeed)
3927 xhci_err(xhci, "ERR: Reserved TRB counting for "
3928 "unfailable commands failed.\n");
3932 cmd->command_trb = xhci->cmd_ring->enqueue;
3934 /* if there are no other commands queued we start the timeout timer */
3935 if (list_empty(&xhci->cmd_list)) {
3936 xhci->current_cmd = cmd;
3937 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3940 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3942 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3943 field4 | xhci->cmd_ring->cycle_state);
3947 /* Queue a slot enable or disable request on the command ring */
3948 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3949 u32 trb_type, u32 slot_id)
3951 return queue_command(xhci, cmd, 0, 0, 0,
3952 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3955 /* Queue an address device command TRB */
3956 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3957 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3959 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3960 upper_32_bits(in_ctx_ptr), 0,
3961 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3962 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3965 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3966 u32 field1, u32 field2, u32 field3, u32 field4)
3968 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3971 /* Queue a reset device command TRB */
3972 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3975 return queue_command(xhci, cmd, 0, 0, 0,
3976 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3980 /* Queue a configure endpoint command TRB */
3981 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3982 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3983 u32 slot_id, bool command_must_succeed)
3985 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3986 upper_32_bits(in_ctx_ptr), 0,
3987 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3988 command_must_succeed);
3991 /* Queue an evaluate context command TRB */
3992 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3993 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3995 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3996 upper_32_bits(in_ctx_ptr), 0,
3997 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3998 command_must_succeed);
4002 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4003 * activity on an endpoint that is about to be suspended.
4005 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4006 int slot_id, unsigned int ep_index, int suspend)
4008 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4009 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4010 u32 type = TRB_TYPE(TRB_STOP_RING);
4011 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4013 return queue_command(xhci, cmd, 0, 0, 0,
4014 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4017 /* Set Transfer Ring Dequeue Pointer command */
4018 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4019 unsigned int slot_id, unsigned int ep_index,
4020 struct xhci_dequeue_state *deq_state)
4023 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4024 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4025 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4027 u32 type = TRB_TYPE(TRB_SET_DEQ);
4028 struct xhci_virt_ep *ep;
4029 struct xhci_command *cmd;
4032 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4033 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4034 deq_state->new_deq_seg,
4035 (unsigned long long)deq_state->new_deq_seg->dma,
4036 deq_state->new_deq_ptr,
4037 (unsigned long long)xhci_trb_virt_to_dma(
4038 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4039 deq_state->new_cycle_state);
4041 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4042 deq_state->new_deq_ptr);
4044 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4045 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4046 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4049 ep = &xhci->devs[slot_id]->eps[ep_index];
4050 if ((ep->ep_state & SET_DEQ_PENDING)) {
4051 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4052 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4056 /* This function gets called from contexts where it cannot sleep */
4057 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4061 ep->queued_deq_seg = deq_state->new_deq_seg;
4062 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4063 if (deq_state->stream_id)
4064 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4065 ret = queue_command(xhci, cmd,
4066 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4067 upper_32_bits(addr), trb_stream_id,
4068 trb_slot_id | trb_ep_index | type, false);
4070 xhci_free_command(xhci, cmd);
4074 /* Stop the TD queueing code from ringing the doorbell until
4075 * this command completes. The HC won't set the dequeue pointer
4076 * if the ring is running, and ringing the doorbell starts the
4079 ep->ep_state |= SET_DEQ_PENDING;
4082 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4083 int slot_id, unsigned int ep_index,
4084 enum xhci_ep_reset_type reset_type)
4086 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4087 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4088 u32 type = TRB_TYPE(TRB_RESET_EP);
4090 if (reset_type == EP_SOFT_RESET)
4093 return queue_command(xhci, cmd, 0, 0, 0,
4094 trb_slot_id | trb_ep_index | type, false);