1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
307 struct xhci_command *i_cmd;
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
339 /* Must be called with xhci->lock held, releases and aquires lock back */
340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
345 xhci_dbg(xhci, "Abort command ring\n");
347 reinit_completion(&xhci->cmd_ring_stop_completion);
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
354 * completion of the Command Abort operation. If CRR is not negated in 5
355 * seconds then driver handles it as if host died (-ENODEV).
356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
357 * and try to recover a -ETIMEDOUT with a host controller reset.
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
370 * but the completion event in never sent. Wait 2 secs (arbitrary
371 * number) to handle those cases after negation of CMD_RING_RUNNING.
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
386 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
395 /* Don't ring the doorbell for this endpoint if there are pending
396 * cancellations because we don't want to interrupt processing.
397 * We don't want to restart any stream rings if there's a set dequeue
398 * pointer command pending because the device can choose to start any
399 * stream once the endpoint is on the HW schedule.
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED))
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405 /* The CPU has better things to do at this point than wait for a
406 * write-posting flush. It'll get there soon enough.
410 /* Ring the doorbell for any rings with pending URBs */
411 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
418 ep = &xhci->devs[slot_id]->eps[ep_index];
420 /* A ring has pending URBs if its TD list is not empty */
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
436 /* Get the right ring for the given slot_id, ep_index and stream_id.
437 * If the endpoint supports streams, boundary check the URB's stream ID.
438 * If the endpoint doesn't support streams, return the singular endpoint ring.
440 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
441 unsigned int slot_id, unsigned int ep_index,
442 unsigned int stream_id)
444 struct xhci_virt_ep *ep;
446 ep = &xhci->devs[slot_id]->eps[ep_index];
447 /* Common case: no streams */
448 if (!(ep->ep_state & EP_HAS_STREAMS))
451 if (stream_id == 0) {
453 "WARN: Slot ID %u, ep index %u has streams, "
454 "but URB has no stream ID.\n",
459 if (stream_id < ep->stream_info->num_streams)
460 return ep->stream_info->stream_rings[stream_id];
463 "WARN: Slot ID %u, ep index %u has "
464 "stream IDs 1 to %u allocated, "
465 "but stream ID %u is requested.\n",
467 ep->stream_info->num_streams - 1,
474 * Get the hw dequeue pointer xHC stopped on, either directly from the
475 * endpoint context, or if streams are in use from the stream context.
476 * The returned hw_dequeue contains the lowest four bits with cycle state
477 * and possbile stream context type.
479 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
480 unsigned int ep_index, unsigned int stream_id)
482 struct xhci_ep_ctx *ep_ctx;
483 struct xhci_stream_ctx *st_ctx;
484 struct xhci_virt_ep *ep;
486 ep = &vdev->eps[ep_index];
488 if (ep->ep_state & EP_HAS_STREAMS) {
489 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
490 return le64_to_cpu(st_ctx->stream_ring);
492 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
493 return le64_to_cpu(ep_ctx->deq);
497 * Move the xHC's endpoint ring dequeue pointer past cur_td.
498 * Record the new state of the xHC's endpoint ring dequeue segment,
499 * dequeue pointer, stream id, and new consumer cycle state in state.
500 * Update our internal representation of the ring's dequeue pointer.
502 * We do this in three jumps:
503 * - First we update our new ring state to be the same as when the xHC stopped.
504 * - Then we traverse the ring to find the segment that contains
505 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
506 * any link TRBs with the toggle cycle bit set.
507 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
508 * if we've moved it past a link TRB with the toggle cycle bit set.
510 * Some of the uses of xhci_generic_trb are grotty, but if they're done
511 * with correct __le32 accesses they should work fine. Only users of this are
514 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
515 unsigned int slot_id, unsigned int ep_index,
516 unsigned int stream_id, struct xhci_td *cur_td,
517 struct xhci_dequeue_state *state)
519 struct xhci_virt_device *dev = xhci->devs[slot_id];
520 struct xhci_virt_ep *ep = &dev->eps[ep_index];
521 struct xhci_ring *ep_ring;
522 struct xhci_segment *new_seg;
523 union xhci_trb *new_deq;
526 bool cycle_found = false;
527 bool td_last_trb_found = false;
529 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
530 ep_index, stream_id);
532 xhci_warn(xhci, "WARN can't find new dequeue state "
533 "for invalid stream ID %u.\n",
537 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
538 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
539 "Finding endpoint context");
541 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
542 new_seg = ep_ring->deq_seg;
543 new_deq = ep_ring->dequeue;
544 state->new_cycle_state = hw_dequeue & 0x1;
545 state->stream_id = stream_id;
548 * We want to find the pointer, segment and cycle state of the new trb
549 * (the one after current TD's last_trb). We know the cycle state at
550 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
554 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
555 == (dma_addr_t)(hw_dequeue & ~0xf)) {
557 if (td_last_trb_found)
560 if (new_deq == cur_td->last_trb)
561 td_last_trb_found = true;
563 if (cycle_found && trb_is_link(new_deq) &&
564 link_trb_toggles_cycle(new_deq))
565 state->new_cycle_state ^= 0x1;
567 next_trb(xhci, ep_ring, &new_seg, &new_deq);
569 /* Search wrapped around, bail out */
570 if (new_deq == ep->ring->dequeue) {
571 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
572 state->new_deq_seg = NULL;
573 state->new_deq_ptr = NULL;
577 } while (!cycle_found || !td_last_trb_found);
579 state->new_deq_seg = new_seg;
580 state->new_deq_ptr = new_deq;
582 /* Don't update the ring cycle state for the producer (us). */
583 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
584 "Cycle state = 0x%x", state->new_cycle_state);
586 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
587 "New dequeue segment = %p (virtual)",
589 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
591 "New dequeue pointer = 0x%llx (DMA)",
592 (unsigned long long) addr);
595 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
596 * (The last TRB actually points to the ring enqueue pointer, which is not part
597 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
599 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
600 struct xhci_td *td, bool flip_cycle)
602 struct xhci_segment *seg = td->start_seg;
603 union xhci_trb *trb = td->first_trb;
606 trb_to_noop(trb, TRB_TR_NOOP);
608 /* flip cycle if asked to */
609 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
610 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
612 if (trb == td->last_trb)
615 next_trb(xhci, ep_ring, &seg, &trb);
619 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
620 struct xhci_virt_ep *ep)
622 ep->ep_state &= ~EP_STOP_CMD_PENDING;
623 /* Can't del_timer_sync in interrupt */
624 del_timer(&ep->stop_cmd_timer);
628 * Must be called with xhci->lock held in interrupt context,
629 * releases and re-acquires xhci->lock
631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
632 struct xhci_td *cur_td, int status)
634 struct urb *urb = cur_td->urb;
635 struct urb_priv *urb_priv = urb->hcpriv;
636 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
638 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
639 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
640 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
641 if (xhci->quirks & XHCI_AMD_PLL_FIX)
642 usb_amd_quirk_pll_enable();
645 xhci_urb_free_priv(urb_priv);
646 usb_hcd_unlink_urb_from_ep(hcd, urb);
647 spin_unlock(&xhci->lock);
648 trace_xhci_urb_giveback(urb);
649 usb_hcd_giveback_urb(hcd, urb, status);
650 spin_lock(&xhci->lock);
653 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
654 struct xhci_ring *ring, struct xhci_td *td)
656 struct device *dev = xhci_to_hcd(xhci)->self.controller;
657 struct xhci_segment *seg = td->bounce_seg;
658 struct urb *urb = td->urb;
661 if (!ring || !seg || !urb)
664 if (usb_urb_dir_out(urb)) {
665 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
670 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
672 /* for in tranfers we need to copy the data from bounce to sg */
673 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
674 seg->bounce_len, seg->bounce_offs);
675 if (len != seg->bounce_len)
676 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
677 len, seg->bounce_len);
679 seg->bounce_offs = 0;
683 * When we get a command completion for a Stop Endpoint Command, we need to
684 * unlink any cancelled TDs from the ring. There are two ways to do that:
686 * 1. If the HW was in the middle of processing the TD that needs to be
687 * cancelled, then we must move the ring's dequeue pointer past the last TRB
688 * in the TD with a Set Dequeue Pointer Command.
689 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
690 * bit cleared) so that the HW will skip over them.
692 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
693 union xhci_trb *trb, struct xhci_event_cmd *event)
695 unsigned int ep_index;
696 struct xhci_ring *ep_ring;
697 struct xhci_virt_ep *ep;
698 struct xhci_td *cur_td = NULL;
699 struct xhci_td *last_unlinked_td;
700 struct xhci_ep_ctx *ep_ctx;
701 struct xhci_virt_device *vdev;
703 struct xhci_dequeue_state deq_state;
705 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
706 if (!xhci->devs[slot_id])
707 xhci_warn(xhci, "Stop endpoint command "
708 "completion for disabled slot %u\n",
713 memset(&deq_state, 0, sizeof(deq_state));
714 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
716 vdev = xhci->devs[slot_id];
717 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
718 trace_xhci_handle_cmd_stop_ep(ep_ctx);
720 ep = &xhci->devs[slot_id]->eps[ep_index];
721 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
722 struct xhci_td, cancelled_td_list);
724 if (list_empty(&ep->cancelled_td_list)) {
725 xhci_stop_watchdog_timer_in_irq(xhci, ep);
726 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
730 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
731 * We have the xHCI lock, so nothing can modify this list until we drop
732 * it. We're also in the event handler, so we can't get re-interrupted
733 * if another Stop Endpoint command completes
735 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
736 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
737 "Removing canceled TD starting at 0x%llx (dma).",
738 (unsigned long long)xhci_trb_virt_to_dma(
739 cur_td->start_seg, cur_td->first_trb));
740 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
742 /* This shouldn't happen unless a driver is mucking
743 * with the stream ID after submission. This will
744 * leave the TD on the hardware ring, and the hardware
745 * will try to execute it, and may access a buffer
746 * that has already been freed. In the best case, the
747 * hardware will execute it, and the event handler will
748 * ignore the completion event for that TD, since it was
749 * removed from the td_list for that endpoint. In
750 * short, don't muck with the stream ID after
753 xhci_warn(xhci, "WARN Cancelled URB %p "
754 "has invalid stream ID %u.\n",
756 cur_td->urb->stream_id);
757 goto remove_finished_td;
760 * If we stopped on the TD we need to cancel, then we have to
761 * move the xHC endpoint ring dequeue pointer past this TD.
763 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
764 cur_td->urb->stream_id);
767 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
768 cur_td->last_trb, hw_deq, false)) {
769 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
770 cur_td->urb->stream_id,
773 td_to_noop(xhci, ep_ring, cur_td, false);
778 * The event handler won't see a completion for this TD anymore,
779 * so remove it from the endpoint ring's TD list. Keep it in
780 * the cancelled TD list for URB completion later.
782 list_del_init(&cur_td->td_list);
785 xhci_stop_watchdog_timer_in_irq(xhci, ep);
787 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
788 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
789 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
791 xhci_ring_cmd_db(xhci);
793 /* Otherwise ring the doorbell(s) to restart queued transfers */
794 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
798 * Drop the lock and complete the URBs in the cancelled TD list.
799 * New TDs to be cancelled might be added to the end of the list before
800 * we can complete all the URBs for the TDs we already unlinked.
801 * So stop when we've completed the URB for the last TD we unlinked.
804 cur_td = list_first_entry(&ep->cancelled_td_list,
805 struct xhci_td, cancelled_td_list);
806 list_del_init(&cur_td->cancelled_td_list);
808 /* Clean up the cancelled URB */
809 /* Doesn't matter what we pass for status, since the core will
810 * just overwrite it (because the URB has been unlinked).
812 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
813 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
814 inc_td_cnt(cur_td->urb);
815 if (last_td_in_urb(cur_td))
816 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
818 /* Stop processing the cancelled list if the watchdog timer is
821 if (xhci->xhc_state & XHCI_STATE_DYING)
823 } while (cur_td != last_unlinked_td);
825 /* Return to the event handler with xhci->lock re-acquired */
828 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
830 struct xhci_td *cur_td;
833 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
834 list_del_init(&cur_td->td_list);
836 if (!list_empty(&cur_td->cancelled_td_list))
837 list_del_init(&cur_td->cancelled_td_list);
839 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
841 inc_td_cnt(cur_td->urb);
842 if (last_td_in_urb(cur_td))
843 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
847 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
848 int slot_id, int ep_index)
850 struct xhci_td *cur_td;
852 struct xhci_virt_ep *ep;
853 struct xhci_ring *ring;
855 ep = &xhci->devs[slot_id]->eps[ep_index];
856 if ((ep->ep_state & EP_HAS_STREAMS) ||
857 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
860 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
862 ring = ep->stream_info->stream_rings[stream_id];
866 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
867 "Killing URBs for slot ID %u, ep index %u, stream %u",
868 slot_id, ep_index, stream_id);
869 xhci_kill_ring_urbs(xhci, ring);
875 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
876 "Killing URBs for slot ID %u, ep index %u",
878 xhci_kill_ring_urbs(xhci, ring);
881 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
883 list_del_init(&cur_td->cancelled_td_list);
884 inc_td_cnt(cur_td->urb);
886 if (last_td_in_urb(cur_td))
887 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
892 * host controller died, register read returns 0xffffffff
893 * Complete pending commands, mark them ABORTED.
894 * URBs need to be given back as usb core might be waiting with device locks
895 * held for the URBs to finish during device disconnect, blocking host remove.
897 * Call with xhci->lock held.
898 * lock is relased and re-acquired while giving back urb.
900 void xhci_hc_died(struct xhci_hcd *xhci)
904 if (xhci->xhc_state & XHCI_STATE_DYING)
907 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
908 xhci->xhc_state |= XHCI_STATE_DYING;
910 xhci_cleanup_command_queue(xhci);
912 /* return any pending urbs, remove may be waiting for them */
913 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
916 for (j = 0; j < 31; j++)
917 xhci_kill_endpoint_urbs(xhci, i, j);
920 /* inform usb core hc died if PCI remove isn't already handling it */
921 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
922 usb_hc_died(xhci_to_hcd(xhci));
925 /* Watchdog timer function for when a stop endpoint command fails to complete.
926 * In this case, we assume the host controller is broken or dying or dead. The
927 * host may still be completing some other events, so we have to be careful to
928 * let the event ring handler and the URB dequeueing/enqueueing functions know
929 * through xhci->state.
931 * The timer may also fire if the host takes a very long time to respond to the
932 * command, and the stop endpoint command completion handler cannot delete the
933 * timer before the timer function is called. Another endpoint cancellation may
934 * sneak in before the timer function can grab the lock, and that may queue
935 * another stop endpoint command and add the timer back. So we cannot use a
936 * simple flag to say whether there is a pending stop endpoint command for a
937 * particular endpoint.
939 * Instead we use a combination of that flag and checking if a new timer is
942 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
944 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
945 struct xhci_hcd *xhci = ep->xhci;
948 spin_lock_irqsave(&xhci->lock, flags);
950 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
951 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
952 timer_pending(&ep->stop_cmd_timer)) {
953 spin_unlock_irqrestore(&xhci->lock, flags);
954 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
958 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
959 ep->ep_state &= ~EP_STOP_CMD_PENDING;
964 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
965 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
966 * and try to recover a -ETIMEDOUT with a host controller reset
970 spin_unlock_irqrestore(&xhci->lock, flags);
971 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
972 "xHCI host controller is dead.");
975 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
976 struct xhci_virt_device *dev,
977 struct xhci_ring *ep_ring,
978 unsigned int ep_index)
980 union xhci_trb *dequeue_temp;
981 int num_trbs_free_temp;
984 num_trbs_free_temp = ep_ring->num_trbs_free;
985 dequeue_temp = ep_ring->dequeue;
987 /* If we get two back-to-back stalls, and the first stalled transfer
988 * ends just before a link TRB, the dequeue pointer will be left on
989 * the link TRB by the code in the while loop. So we have to update
990 * the dequeue pointer one segment further, or we'll jump off
991 * the segment into la-la-land.
993 if (trb_is_link(ep_ring->dequeue)) {
994 ep_ring->deq_seg = ep_ring->deq_seg->next;
995 ep_ring->dequeue = ep_ring->deq_seg->trbs;
998 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
999 /* We have more usable TRBs */
1000 ep_ring->num_trbs_free++;
1002 if (trb_is_link(ep_ring->dequeue)) {
1003 if (ep_ring->dequeue ==
1004 dev->eps[ep_index].queued_deq_ptr)
1006 ep_ring->deq_seg = ep_ring->deq_seg->next;
1007 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1009 if (ep_ring->dequeue == dequeue_temp) {
1016 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1017 ep_ring->num_trbs_free = num_trbs_free_temp;
1022 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1023 * we need to clear the set deq pending flag in the endpoint ring state, so that
1024 * the TD queueing code can ring the doorbell again. We also need to ring the
1025 * endpoint doorbell to restart the ring, but only if there aren't more
1026 * cancellations pending.
1028 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1029 union xhci_trb *trb, u32 cmd_comp_code)
1031 unsigned int ep_index;
1032 unsigned int stream_id;
1033 struct xhci_ring *ep_ring;
1034 struct xhci_virt_device *dev;
1035 struct xhci_virt_ep *ep;
1036 struct xhci_ep_ctx *ep_ctx;
1037 struct xhci_slot_ctx *slot_ctx;
1039 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1040 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1041 dev = xhci->devs[slot_id];
1042 ep = &dev->eps[ep_index];
1044 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1046 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1048 /* XXX: Harmless??? */
1052 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1053 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1054 trace_xhci_handle_cmd_set_deq(slot_ctx);
1055 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1057 if (cmd_comp_code != COMP_SUCCESS) {
1058 unsigned int ep_state;
1059 unsigned int slot_state;
1061 switch (cmd_comp_code) {
1062 case COMP_TRB_ERROR:
1063 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1065 case COMP_CONTEXT_STATE_ERROR:
1066 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1067 ep_state = GET_EP_CTX_STATE(ep_ctx);
1068 slot_state = le32_to_cpu(slot_ctx->dev_state);
1069 slot_state = GET_SLOT_STATE(slot_state);
1070 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1071 "Slot state = %u, EP state = %u",
1072 slot_state, ep_state);
1074 case COMP_SLOT_NOT_ENABLED_ERROR:
1075 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1079 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1083 /* OK what do we do now? The endpoint state is hosed, and we
1084 * should never get to this point if the synchronization between
1085 * queueing, and endpoint state are correct. This might happen
1086 * if the device gets disconnected after we've finished
1087 * cancelling URBs, which might not be an error...
1091 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1092 if (ep->ep_state & EP_HAS_STREAMS) {
1093 struct xhci_stream_ctx *ctx =
1094 &ep->stream_info->stream_ctx_array[stream_id];
1095 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1097 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1099 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1100 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1101 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1102 ep->queued_deq_ptr) == deq) {
1103 /* Update the ring's dequeue segment and dequeue pointer
1104 * to reflect the new position.
1106 update_ring_for_set_deq_completion(xhci, dev,
1109 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1110 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1111 ep->queued_deq_seg, ep->queued_deq_ptr);
1116 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1117 dev->eps[ep_index].queued_deq_seg = NULL;
1118 dev->eps[ep_index].queued_deq_ptr = NULL;
1119 /* Restart any rings with pending URBs */
1120 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1123 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1124 union xhci_trb *trb, u32 cmd_comp_code)
1126 struct xhci_virt_device *vdev;
1127 struct xhci_ep_ctx *ep_ctx;
1128 unsigned int ep_index;
1130 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1131 vdev = xhci->devs[slot_id];
1132 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1133 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1135 /* This command will only fail if the endpoint wasn't halted,
1136 * but we don't care.
1138 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1139 "Ignoring reset ep completion code of %u", cmd_comp_code);
1141 /* HW with the reset endpoint quirk needs to have a configure endpoint
1142 * command complete before the endpoint can be used. Queue that here
1143 * because the HW can't handle two commands being queued in a row.
1145 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1146 struct xhci_command *command;
1148 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1153 "Queueing configure endpoint command");
1154 xhci_queue_configure_endpoint(xhci, command,
1155 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1157 xhci_ring_cmd_db(xhci);
1159 /* Clear our internal halted state */
1160 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1164 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1165 struct xhci_command *command, u32 cmd_comp_code)
1167 if (cmd_comp_code == COMP_SUCCESS)
1168 command->slot_id = slot_id;
1170 command->slot_id = 0;
1173 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1175 struct xhci_virt_device *virt_dev;
1176 struct xhci_slot_ctx *slot_ctx;
1178 virt_dev = xhci->devs[slot_id];
1182 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1183 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1185 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1186 /* Delete default control endpoint resources */
1187 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1188 xhci_free_virt_device(xhci, slot_id);
1191 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1192 struct xhci_event_cmd *event, u32 cmd_comp_code)
1194 struct xhci_virt_device *virt_dev;
1195 struct xhci_input_control_ctx *ctrl_ctx;
1196 struct xhci_ep_ctx *ep_ctx;
1197 unsigned int ep_index;
1198 unsigned int ep_state;
1199 u32 add_flags, drop_flags;
1202 * Configure endpoint commands can come from the USB core
1203 * configuration or alt setting changes, or because the HW
1204 * needed an extra configure endpoint command after a reset
1205 * endpoint command or streams were being configured.
1206 * If the command was for a halted endpoint, the xHCI driver
1207 * is not waiting on the configure endpoint command.
1209 virt_dev = xhci->devs[slot_id];
1210 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1212 xhci_warn(xhci, "Could not get input context, bad type.\n");
1216 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1217 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1218 /* Input ctx add_flags are the endpoint index plus one */
1219 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1221 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1222 trace_xhci_handle_cmd_config_ep(ep_ctx);
1224 /* A usb_set_interface() call directly after clearing a halted
1225 * condition may race on this quirky hardware. Not worth
1226 * worrying about, since this is prototype hardware. Not sure
1227 * if this will work for streams, but streams support was
1228 * untested on this prototype.
1230 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1231 ep_index != (unsigned int) -1 &&
1232 add_flags - SLOT_FLAG == drop_flags) {
1233 ep_state = virt_dev->eps[ep_index].ep_state;
1234 if (!(ep_state & EP_HALTED))
1236 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1237 "Completed config ep cmd - "
1238 "last ep index = %d, state = %d",
1239 ep_index, ep_state);
1240 /* Clear internal halted state and restart ring(s) */
1241 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1242 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1248 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1250 struct xhci_virt_device *vdev;
1251 struct xhci_slot_ctx *slot_ctx;
1253 vdev = xhci->devs[slot_id];
1254 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1255 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1258 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1259 struct xhci_event_cmd *event)
1261 struct xhci_virt_device *vdev;
1262 struct xhci_slot_ctx *slot_ctx;
1264 vdev = xhci->devs[slot_id];
1265 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1266 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1268 xhci_dbg(xhci, "Completed reset device command.\n");
1269 if (!xhci->devs[slot_id])
1270 xhci_warn(xhci, "Reset device command completion "
1271 "for disabled slot %u\n", slot_id);
1274 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1275 struct xhci_event_cmd *event)
1277 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1278 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1281 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1282 "NEC firmware version %2x.%02x",
1283 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1284 NEC_FW_MINOR(le32_to_cpu(event->status)));
1287 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1289 list_del(&cmd->cmd_list);
1291 if (cmd->completion) {
1292 cmd->status = status;
1293 complete(cmd->completion);
1299 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1301 struct xhci_command *cur_cmd, *tmp_cmd;
1302 xhci->current_cmd = NULL;
1303 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1304 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1307 void xhci_handle_command_timeout(struct work_struct *work)
1309 struct xhci_hcd *xhci;
1310 unsigned long flags;
1313 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1315 spin_lock_irqsave(&xhci->lock, flags);
1318 * If timeout work is pending, or current_cmd is NULL, it means we
1319 * raced with command completion. Command is handled so just return.
1321 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1322 spin_unlock_irqrestore(&xhci->lock, flags);
1325 /* mark this command to be cancelled */
1326 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1328 /* Make sure command ring is running before aborting it */
1329 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1330 if (hw_ring_state == ~(u64)0) {
1332 goto time_out_completed;
1335 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1336 (hw_ring_state & CMD_RING_RUNNING)) {
1337 /* Prevent new doorbell, and start command abort */
1338 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1339 xhci_dbg(xhci, "Command timeout\n");
1340 xhci_abort_cmd_ring(xhci, flags);
1341 goto time_out_completed;
1344 /* host removed. Bail out */
1345 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1346 xhci_dbg(xhci, "host removed, ring start fail?\n");
1347 xhci_cleanup_command_queue(xhci);
1349 goto time_out_completed;
1352 /* command timeout on stopped ring, ring can't be aborted */
1353 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1354 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1357 spin_unlock_irqrestore(&xhci->lock, flags);
1361 static void handle_cmd_completion(struct xhci_hcd *xhci,
1362 struct xhci_event_cmd *event)
1364 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1366 dma_addr_t cmd_dequeue_dma;
1368 union xhci_trb *cmd_trb;
1369 struct xhci_command *cmd;
1372 cmd_dma = le64_to_cpu(event->cmd_trb);
1373 cmd_trb = xhci->cmd_ring->dequeue;
1375 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1377 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1380 * Check whether the completion event is for our internal kept
1383 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1385 "ERROR mismatched command completion event\n");
1389 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1391 cancel_delayed_work(&xhci->cmd_timer);
1393 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1395 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1396 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1397 complete_all(&xhci->cmd_ring_stop_completion);
1401 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1403 "Command completion event does not match command\n");
1408 * Host aborted the command ring, check if the current command was
1409 * supposed to be aborted, otherwise continue normally.
1410 * The command ring is stopped now, but the xHC will issue a Command
1411 * Ring Stopped event which will cause us to restart it.
1413 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1414 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1415 if (cmd->status == COMP_COMMAND_ABORTED) {
1416 if (xhci->current_cmd == cmd)
1417 xhci->current_cmd = NULL;
1422 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1424 case TRB_ENABLE_SLOT:
1425 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1427 case TRB_DISABLE_SLOT:
1428 xhci_handle_cmd_disable_slot(xhci, slot_id);
1431 if (!cmd->completion)
1432 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1435 case TRB_EVAL_CONTEXT:
1438 xhci_handle_cmd_addr_dev(xhci, slot_id);
1441 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1442 le32_to_cpu(cmd_trb->generic.field[3])));
1443 if (!cmd->completion)
1444 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1447 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1448 le32_to_cpu(cmd_trb->generic.field[3])));
1449 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1452 /* Is this an aborted command turned to NO-OP? */
1453 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1454 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1457 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1458 le32_to_cpu(cmd_trb->generic.field[3])));
1459 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1462 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1463 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1465 slot_id = TRB_TO_SLOT_ID(
1466 le32_to_cpu(cmd_trb->generic.field[3]));
1467 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1469 case TRB_NEC_GET_FW:
1470 xhci_handle_cmd_nec_get_fw(xhci, event);
1473 /* Skip over unknown commands on the event ring */
1474 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1478 /* restart timer if this wasn't the last command */
1479 if (!list_is_singular(&xhci->cmd_list)) {
1480 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1481 struct xhci_command, cmd_list);
1482 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1483 } else if (xhci->current_cmd == cmd) {
1484 xhci->current_cmd = NULL;
1488 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1490 inc_deq(xhci, xhci->cmd_ring);
1493 static void handle_vendor_event(struct xhci_hcd *xhci,
1494 union xhci_trb *event)
1498 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1499 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1500 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1501 handle_cmd_completion(xhci, &event->event_cmd);
1504 static void handle_device_notification(struct xhci_hcd *xhci,
1505 union xhci_trb *event)
1508 struct usb_device *udev;
1510 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1511 if (!xhci->devs[slot_id]) {
1512 xhci_warn(xhci, "Device Notification event for "
1513 "unused slot %u\n", slot_id);
1517 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1519 udev = xhci->devs[slot_id]->udev;
1520 if (udev && udev->parent)
1521 usb_wakeup_notification(udev->parent, udev->portnum);
1525 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1527 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1528 * If a connection to a USB 1 device is followed by another connection
1529 * to a USB 2 device.
1531 * Reset the PHY after the USB device is disconnected if device speed
1532 * is less than HCD_USB3.
1533 * Retry the reset sequence max of 4 times checking the PLL lock status.
1536 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1538 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1540 u32 retry_count = 4;
1543 /* Assert PHY reset */
1544 writel(0x6F, hcd->regs + 0x1048);
1546 /* De-assert the PHY reset */
1547 writel(0x7F, hcd->regs + 0x1048);
1549 pll_lock_check = readl(hcd->regs + 0x1070);
1550 } while (!(pll_lock_check & 0x1) && --retry_count);
1553 static void handle_port_status(struct xhci_hcd *xhci,
1554 union xhci_trb *event)
1556 struct usb_hcd *hcd;
1558 u32 portsc, cmd_reg;
1561 unsigned int hcd_portnum;
1562 struct xhci_bus_state *bus_state;
1563 bool bogus_port_status = false;
1564 struct xhci_port *port;
1566 /* Port status change events always have a successful completion code */
1567 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1569 "WARN: xHC returned failed port status event\n");
1571 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1572 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1574 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1575 if ((port_id <= 0) || (port_id > max_ports)) {
1576 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1577 inc_deq(xhci, xhci->event_ring);
1581 port = &xhci->hw_ports[port_id - 1];
1582 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1583 xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1584 bogus_port_status = true;
1588 /* We might get interrupts after shared_hcd is removed */
1589 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1590 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1591 bogus_port_status = true;
1595 hcd = port->rhub->hcd;
1596 bus_state = &xhci->bus_state[hcd_index(hcd)];
1597 hcd_portnum = port->hcd_portnum;
1598 portsc = readl(port->addr);
1600 trace_xhci_handle_port_status(hcd_portnum, portsc);
1602 if (hcd->state == HC_STATE_SUSPENDED) {
1603 xhci_dbg(xhci, "resume root hub\n");
1604 usb_hcd_resume_root_hub(hcd);
1607 if (hcd->speed >= HCD_USB3 &&
1608 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1609 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1610 if (slot_id && xhci->devs[slot_id])
1611 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1614 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1615 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1617 cmd_reg = readl(&xhci->op_regs->command);
1618 if (!(cmd_reg & CMD_RUN)) {
1619 xhci_warn(xhci, "xHC is not running.\n");
1623 if (DEV_SUPERSPEED_ANY(portsc)) {
1624 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1625 /* Set a flag to say the port signaled remote wakeup,
1626 * so we can tell the difference between the end of
1627 * device and host initiated resume.
1629 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1630 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1631 xhci_set_link_state(xhci, port, XDEV_U0);
1632 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1633 /* Need to wait until the next link state change
1634 * indicates the device is actually in U0.
1636 bogus_port_status = true;
1638 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1639 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1640 bus_state->resume_done[hcd_portnum] = jiffies +
1641 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1642 set_bit(hcd_portnum, &bus_state->resuming_ports);
1643 /* Do the rest in GetPortStatus after resume time delay.
1644 * Avoid polling roothub status before that so that a
1645 * usb device auto-resume latency around ~40ms.
1647 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1648 mod_timer(&hcd->rh_timer,
1649 bus_state->resume_done[hcd_portnum]);
1650 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1651 bogus_port_status = true;
1655 if ((portsc & PORT_PLC) &&
1656 DEV_SUPERSPEED_ANY(portsc) &&
1657 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1658 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1659 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1660 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1661 /* We've just brought the device into U0/1/2 through either the
1662 * Resume state after a device remote wakeup, or through the
1663 * U3Exit state after a host-initiated resume. If it's a device
1664 * initiated remote wake, don't pass up the link state change,
1665 * so the roothub behavior is consistent with external
1666 * USB 3.0 hub behavior.
1668 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1669 if (slot_id && xhci->devs[slot_id])
1670 xhci_ring_device(xhci, slot_id);
1671 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1672 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1673 usb_wakeup_notification(hcd->self.root_hub,
1675 bogus_port_status = true;
1681 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1682 * RExit to a disconnect state). If so, let the the driver know it's
1683 * out of the RExit state.
1685 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1686 test_and_clear_bit(hcd_portnum,
1687 &bus_state->rexit_ports)) {
1688 complete(&bus_state->rexit_done[hcd_portnum]);
1689 bogus_port_status = true;
1693 if (hcd->speed < HCD_USB3) {
1694 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1695 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1696 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1697 xhci_cavium_reset_phy_quirk(xhci);
1701 /* Update event ring dequeue pointer before dropping the lock */
1702 inc_deq(xhci, xhci->event_ring);
1704 /* Don't make the USB core poll the roothub if we got a bad port status
1705 * change event. Besides, at that point we can't tell which roothub
1706 * (USB 2.0 or USB 3.0) to kick.
1708 if (bogus_port_status)
1712 * xHCI port-status-change events occur when the "or" of all the
1713 * status-change bits in the portsc register changes from 0 to 1.
1714 * New status changes won't cause an event if any other change
1715 * bits are still set. When an event occurs, switch over to
1716 * polling to avoid losing status changes.
1718 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1719 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1720 spin_unlock(&xhci->lock);
1721 /* Pass this up to the core */
1722 usb_hcd_poll_rh_status(hcd);
1723 spin_lock(&xhci->lock);
1727 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1728 * at end_trb, which may be in another segment. If the suspect DMA address is a
1729 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1732 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1733 struct xhci_segment *start_seg,
1734 union xhci_trb *start_trb,
1735 union xhci_trb *end_trb,
1736 dma_addr_t suspect_dma,
1739 dma_addr_t start_dma;
1740 dma_addr_t end_seg_dma;
1741 dma_addr_t end_trb_dma;
1742 struct xhci_segment *cur_seg;
1744 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1745 cur_seg = start_seg;
1750 /* We may get an event for a Link TRB in the middle of a TD */
1751 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1752 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1753 /* If the end TRB isn't in this segment, this is set to 0 */
1754 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1758 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1759 (unsigned long long)suspect_dma,
1760 (unsigned long long)start_dma,
1761 (unsigned long long)end_trb_dma,
1762 (unsigned long long)cur_seg->dma,
1763 (unsigned long long)end_seg_dma);
1765 if (end_trb_dma > 0) {
1766 /* The end TRB is in this segment, so suspect should be here */
1767 if (start_dma <= end_trb_dma) {
1768 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1771 /* Case for one segment with
1772 * a TD wrapped around to the top
1774 if ((suspect_dma >= start_dma &&
1775 suspect_dma <= end_seg_dma) ||
1776 (suspect_dma >= cur_seg->dma &&
1777 suspect_dma <= end_trb_dma))
1782 /* Might still be somewhere in this segment */
1783 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1786 cur_seg = cur_seg->next;
1787 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1788 } while (cur_seg != start_seg);
1793 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1794 unsigned int slot_id, unsigned int ep_index,
1795 unsigned int stream_id, struct xhci_td *td,
1796 enum xhci_ep_reset_type reset_type)
1798 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1799 struct xhci_command *command;
1802 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1803 * Device will be reset soon to recover the link so don't do anything
1805 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1808 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1812 ep->ep_state |= EP_HALTED;
1814 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1816 if (reset_type == EP_HARD_RESET) {
1817 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1818 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1820 xhci_ring_cmd_db(xhci);
1823 /* Check if an error has halted the endpoint ring. The class driver will
1824 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1825 * However, a babble and other errors also halt the endpoint ring, and the class
1826 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1827 * Ring Dequeue Pointer command manually.
1829 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1830 struct xhci_ep_ctx *ep_ctx,
1831 unsigned int trb_comp_code)
1833 /* TRB completion codes that may require a manual halt cleanup */
1834 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1835 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1836 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1837 /* The 0.95 spec says a babbling control endpoint
1838 * is not halted. The 0.96 spec says it is. Some HW
1839 * claims to be 0.95 compliant, but it halts the control
1840 * endpoint anyway. Check if a babble halted the
1843 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1849 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1851 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1852 /* Vendor defined "informational" completion code,
1853 * treat as not-an-error.
1855 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1857 xhci_dbg(xhci, "Treating code as success.\n");
1863 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1864 struct xhci_ring *ep_ring, int *status)
1866 struct urb *urb = NULL;
1868 /* Clean up the endpoint's TD list */
1871 /* if a bounce buffer was used to align this td then unmap it */
1872 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1874 /* Do one last check of the actual transfer length.
1875 * If the host controller said we transferred more data than the buffer
1876 * length, urb->actual_length will be a very big number (since it's
1877 * unsigned). Play it safe and say we didn't transfer anything.
1879 if (urb->actual_length > urb->transfer_buffer_length) {
1880 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1881 urb->transfer_buffer_length, urb->actual_length);
1882 urb->actual_length = 0;
1885 list_del_init(&td->td_list);
1886 /* Was this TD slated to be cancelled but completed anyway? */
1887 if (!list_empty(&td->cancelled_td_list))
1888 list_del_init(&td->cancelled_td_list);
1891 /* Giveback the urb when all the tds are completed */
1892 if (last_td_in_urb(td)) {
1893 if ((urb->actual_length != urb->transfer_buffer_length &&
1894 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1895 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1896 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1897 urb, urb->actual_length,
1898 urb->transfer_buffer_length, *status);
1900 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1901 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1903 xhci_giveback_urb_in_irq(xhci, td, *status);
1909 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1910 struct xhci_transfer_event *event,
1911 struct xhci_virt_ep *ep, int *status)
1913 struct xhci_virt_device *xdev;
1914 struct xhci_ep_ctx *ep_ctx;
1915 struct xhci_ring *ep_ring;
1916 unsigned int slot_id;
1920 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1921 xdev = xhci->devs[slot_id];
1922 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1923 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1924 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1925 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1927 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1928 trb_comp_code == COMP_STOPPED ||
1929 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1930 /* The Endpoint Stop Command completion will take care of any
1931 * stopped TDs. A stopped TD may be restarted, so don't update
1932 * the ring dequeue pointer or take this TD off any lists yet.
1936 if (trb_comp_code == COMP_STALL_ERROR ||
1937 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1939 /* Issue a reset endpoint command to clear the host side
1940 * halt, followed by a set dequeue command to move the
1941 * dequeue pointer past the TD.
1942 * The class driver clears the device side halt later.
1944 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1945 ep_ring->stream_id, td, EP_HARD_RESET);
1947 /* Update ring dequeue pointer */
1948 while (ep_ring->dequeue != td->last_trb)
1949 inc_deq(xhci, ep_ring);
1950 inc_deq(xhci, ep_ring);
1953 return xhci_td_cleanup(xhci, td, ep_ring, status);
1956 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1957 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1958 union xhci_trb *stop_trb)
1961 union xhci_trb *trb = ring->dequeue;
1962 struct xhci_segment *seg = ring->deq_seg;
1964 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1965 if (!trb_is_noop(trb) && !trb_is_link(trb))
1966 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1972 * Process control tds, update urb status and actual_length.
1974 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1975 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1976 struct xhci_virt_ep *ep, int *status)
1978 struct xhci_virt_device *xdev;
1979 unsigned int slot_id;
1981 struct xhci_ep_ctx *ep_ctx;
1983 u32 remaining, requested;
1986 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
1987 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1988 xdev = xhci->devs[slot_id];
1989 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1990 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1991 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1992 requested = td->urb->transfer_buffer_length;
1993 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1995 switch (trb_comp_code) {
1997 if (trb_type != TRB_STATUS) {
1998 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
1999 (trb_type == TRB_DATA) ? "data" : "setup");
2000 *status = -ESHUTDOWN;
2005 case COMP_SHORT_PACKET:
2008 case COMP_STOPPED_SHORT_PACKET:
2009 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2010 td->urb->actual_length = remaining;
2012 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2017 td->urb->actual_length = 0;
2021 td->urb->actual_length = requested - remaining;
2024 td->urb->actual_length = requested;
2027 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2031 case COMP_STOPPED_LENGTH_INVALID:
2034 if (!xhci_requires_manual_halt_cleanup(xhci,
2035 ep_ctx, trb_comp_code))
2037 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2038 trb_comp_code, ep_index);
2039 /* else fall through */
2040 case COMP_STALL_ERROR:
2041 /* Did we transfer part of the data (middle) phase? */
2042 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2043 td->urb->actual_length = requested - remaining;
2044 else if (!td->urb_length_set)
2045 td->urb->actual_length = 0;
2049 /* stopped at setup stage, no data transferred */
2050 if (trb_type == TRB_SETUP)
2054 * if on data stage then update the actual_length of the URB and flag it
2055 * as set, so it won't be overwritten in the event for the last TRB.
2057 if (trb_type == TRB_DATA ||
2058 trb_type == TRB_NORMAL) {
2059 td->urb_length_set = true;
2060 td->urb->actual_length = requested - remaining;
2061 xhci_dbg(xhci, "Waiting for status stage event\n");
2065 /* at status stage */
2066 if (!td->urb_length_set)
2067 td->urb->actual_length = requested;
2070 return finish_td(xhci, td, event, ep, status);
2074 * Process isochronous tds, update urb packet status and actual_length.
2076 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2077 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2078 struct xhci_virt_ep *ep, int *status)
2080 struct xhci_ring *ep_ring;
2081 struct urb_priv *urb_priv;
2083 struct usb_iso_packet_descriptor *frame;
2085 bool sum_trbs_for_length = false;
2086 u32 remaining, requested, ep_trb_len;
2087 int short_framestatus;
2089 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2090 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2091 urb_priv = td->urb->hcpriv;
2092 idx = urb_priv->num_tds_done;
2093 frame = &td->urb->iso_frame_desc[idx];
2094 requested = frame->length;
2095 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2096 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2097 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2100 /* handle completion code */
2101 switch (trb_comp_code) {
2104 frame->status = short_framestatus;
2105 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2106 sum_trbs_for_length = true;
2111 case COMP_SHORT_PACKET:
2112 frame->status = short_framestatus;
2113 sum_trbs_for_length = true;
2115 case COMP_BANDWIDTH_OVERRUN_ERROR:
2116 frame->status = -ECOMM;
2118 case COMP_ISOCH_BUFFER_OVERRUN:
2119 case COMP_BABBLE_DETECTED_ERROR:
2120 frame->status = -EOVERFLOW;
2122 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2123 case COMP_STALL_ERROR:
2124 frame->status = -EPROTO;
2126 case COMP_USB_TRANSACTION_ERROR:
2127 frame->status = -EPROTO;
2128 if (ep_trb != td->last_trb)
2132 sum_trbs_for_length = true;
2134 case COMP_STOPPED_SHORT_PACKET:
2135 /* field normally containing residue now contains tranferred */
2136 frame->status = short_framestatus;
2137 requested = remaining;
2139 case COMP_STOPPED_LENGTH_INVALID:
2144 sum_trbs_for_length = true;
2149 if (sum_trbs_for_length)
2150 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2151 ep_trb_len - remaining;
2153 frame->actual_length = requested;
2155 td->urb->actual_length += frame->actual_length;
2157 return finish_td(xhci, td, event, ep, status);
2160 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2161 struct xhci_transfer_event *event,
2162 struct xhci_virt_ep *ep, int *status)
2164 struct xhci_ring *ep_ring;
2165 struct urb_priv *urb_priv;
2166 struct usb_iso_packet_descriptor *frame;
2169 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2170 urb_priv = td->urb->hcpriv;
2171 idx = urb_priv->num_tds_done;
2172 frame = &td->urb->iso_frame_desc[idx];
2174 /* The transfer is partly done. */
2175 frame->status = -EXDEV;
2177 /* calc actual length */
2178 frame->actual_length = 0;
2180 /* Update ring dequeue pointer */
2181 while (ep_ring->dequeue != td->last_trb)
2182 inc_deq(xhci, ep_ring);
2183 inc_deq(xhci, ep_ring);
2185 return xhci_td_cleanup(xhci, td, ep_ring, status);
2189 * Process bulk and interrupt tds, update urb status and actual_length.
2191 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2192 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2193 struct xhci_virt_ep *ep, int *status)
2195 struct xhci_ring *ep_ring;
2197 u32 remaining, requested, ep_trb_len;
2199 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2200 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2201 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2202 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2203 requested = td->urb->transfer_buffer_length;
2205 switch (trb_comp_code) {
2207 /* handle success with untransferred data as short packet */
2208 if (ep_trb != td->last_trb || remaining) {
2209 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2210 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2211 td->urb->ep->desc.bEndpointAddress,
2212 requested, remaining);
2216 case COMP_SHORT_PACKET:
2217 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2218 td->urb->ep->desc.bEndpointAddress,
2219 requested, remaining);
2222 case COMP_STOPPED_SHORT_PACKET:
2223 td->urb->actual_length = remaining;
2225 case COMP_STOPPED_LENGTH_INVALID:
2226 /* stopped on ep trb with invalid length, exclude it */
2235 if (ep_trb == td->last_trb)
2236 td->urb->actual_length = requested - remaining;
2238 td->urb->actual_length =
2239 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2240 ep_trb_len - remaining;
2242 if (remaining > requested) {
2243 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2245 td->urb->actual_length = 0;
2247 return finish_td(xhci, td, event, ep, status);
2251 * If this function returns an error condition, it means it got a Transfer
2252 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2253 * At this point, the host controller is probably hosed and should be reset.
2255 static int handle_tx_event(struct xhci_hcd *xhci,
2256 struct xhci_transfer_event *event)
2258 struct xhci_virt_device *xdev;
2259 struct xhci_virt_ep *ep;
2260 struct xhci_ring *ep_ring;
2261 unsigned int slot_id;
2263 struct xhci_td *td = NULL;
2264 dma_addr_t ep_trb_dma;
2265 struct xhci_segment *ep_seg;
2266 union xhci_trb *ep_trb;
2267 int status = -EINPROGRESS;
2268 struct xhci_ep_ctx *ep_ctx;
2269 struct list_head *tmp;
2272 bool handling_skipped_tds = false;
2274 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2275 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2276 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2277 ep_trb_dma = le64_to_cpu(event->buffer);
2279 xdev = xhci->devs[slot_id];
2281 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2286 ep = &xdev->eps[ep_index];
2287 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2288 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2290 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2292 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2297 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2299 switch (trb_comp_code) {
2300 case COMP_STALL_ERROR:
2301 case COMP_USB_TRANSACTION_ERROR:
2302 case COMP_INVALID_STREAM_TYPE_ERROR:
2303 case COMP_INVALID_STREAM_ID_ERROR:
2304 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2305 NULL, EP_SOFT_RESET);
2307 case COMP_RING_UNDERRUN:
2308 case COMP_RING_OVERRUN:
2309 case COMP_STOPPED_LENGTH_INVALID:
2312 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2318 /* Count current td numbers if ep->skip is set */
2320 list_for_each(tmp, &ep_ring->td_list)
2324 /* Look for common error cases */
2325 switch (trb_comp_code) {
2326 /* Skip codes that require special handling depending on
2330 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2332 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2333 ep_ring->last_td_was_short)
2334 trb_comp_code = COMP_SHORT_PACKET;
2336 xhci_warn_ratelimited(xhci,
2337 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2339 case COMP_SHORT_PACKET:
2341 /* Completion codes for endpoint stopped state */
2343 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2346 case COMP_STOPPED_LENGTH_INVALID:
2348 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2351 case COMP_STOPPED_SHORT_PACKET:
2353 "Stopped with short packet transfer detected for slot %u ep %u\n",
2356 /* Completion codes for endpoint halted state */
2357 case COMP_STALL_ERROR:
2358 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2360 ep->ep_state |= EP_HALTED;
2363 case COMP_SPLIT_TRANSACTION_ERROR:
2364 case COMP_USB_TRANSACTION_ERROR:
2365 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2369 case COMP_BABBLE_DETECTED_ERROR:
2370 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2372 status = -EOVERFLOW;
2374 /* Completion codes for endpoint error state */
2375 case COMP_TRB_ERROR:
2377 "WARN: TRB error for slot %u ep %u on endpoint\n",
2381 /* completion codes not indicating endpoint state change */
2382 case COMP_DATA_BUFFER_ERROR:
2384 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2388 case COMP_BANDWIDTH_OVERRUN_ERROR:
2390 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2393 case COMP_ISOCH_BUFFER_OVERRUN:
2395 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2398 case COMP_RING_UNDERRUN:
2400 * When the Isoch ring is empty, the xHC will generate
2401 * a Ring Overrun Event for IN Isoch endpoint or Ring
2402 * Underrun Event for OUT Isoch endpoint.
2404 xhci_dbg(xhci, "underrun event on endpoint\n");
2405 if (!list_empty(&ep_ring->td_list))
2406 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2407 "still with TDs queued?\n",
2408 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2411 case COMP_RING_OVERRUN:
2412 xhci_dbg(xhci, "overrun event on endpoint\n");
2413 if (!list_empty(&ep_ring->td_list))
2414 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2415 "still with TDs queued?\n",
2416 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2419 case COMP_MISSED_SERVICE_ERROR:
2421 * When encounter missed service error, one or more isoc tds
2422 * may be missed by xHC.
2423 * Set skip flag of the ep_ring; Complete the missed tds as
2424 * short transfer when process the ep_ring next time.
2428 "Miss service interval error for slot %u ep %u, set skip flag\n",
2431 case COMP_NO_PING_RESPONSE_ERROR:
2434 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2438 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2439 /* needs disable slot command to recover */
2441 "WARN: detect an incompatible device for slot %u ep %u",
2446 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2451 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2452 trb_comp_code, slot_id, ep_index);
2457 /* This TRB should be in the TD at the head of this ring's
2460 if (list_empty(&ep_ring->td_list)) {
2462 * Don't print wanings if it's due to a stopped endpoint
2463 * generating an extra completion event if the device
2464 * was suspended. Or, a event for the last TRB of a
2465 * short TD we already got a short event for.
2466 * The short TD is already removed from the TD list.
2469 if (!(trb_comp_code == COMP_STOPPED ||
2470 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2471 ep_ring->last_td_was_short)) {
2472 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2473 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2478 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2484 /* We've skipped all the TDs on the ep ring when ep->skip set */
2485 if (ep->skip && td_num == 0) {
2487 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2492 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2497 /* Is this a TRB in the currently executing TD? */
2498 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2499 td->last_trb, ep_trb_dma, false);
2502 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2503 * is not in the current TD pointed by ep_ring->dequeue because
2504 * that the hardware dequeue pointer still at the previous TRB
2505 * of the current TD. The previous TRB maybe a Link TD or the
2506 * last TRB of the previous TD. The command completion handle
2507 * will take care the rest.
2509 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2510 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2516 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2517 /* Some host controllers give a spurious
2518 * successful event after a short transfer.
2521 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2522 ep_ring->last_td_was_short) {
2523 ep_ring->last_td_was_short = false;
2526 /* HC is busted, give up! */
2528 "ERROR Transfer event TRB DMA ptr not "
2529 "part of current TD ep_index %d "
2530 "comp_code %u\n", ep_index,
2532 trb_in_td(xhci, ep_ring->deq_seg,
2533 ep_ring->dequeue, td->last_trb,
2538 skip_isoc_td(xhci, td, event, ep, &status);
2541 if (trb_comp_code == COMP_SHORT_PACKET)
2542 ep_ring->last_td_was_short = true;
2544 ep_ring->last_td_was_short = false;
2548 "Found td. Clear skip flag for slot %u ep %u.\n",
2553 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2556 trace_xhci_handle_transfer(ep_ring,
2557 (struct xhci_generic_trb *) ep_trb);
2560 * No-op TRB could trigger interrupts in a case where
2561 * a URB was killed and a STALL_ERROR happens right
2562 * after the endpoint ring stopped. Reset the halted
2563 * endpoint. Otherwise, the endpoint remains stalled
2566 if (trb_is_noop(ep_trb)) {
2567 if (trb_comp_code == COMP_STALL_ERROR ||
2568 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2570 xhci_cleanup_halted_endpoint(xhci, slot_id,
2577 /* update the urb's actual_length and give back to the core */
2578 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2579 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2580 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2581 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2583 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2586 handling_skipped_tds = ep->skip &&
2587 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2588 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2591 * Do not update event ring dequeue pointer if we're in a loop
2592 * processing missed tds.
2594 if (!handling_skipped_tds)
2595 inc_deq(xhci, xhci->event_ring);
2598 * If ep->skip is set, it means there are missed tds on the
2599 * endpoint ring need to take care of.
2600 * Process them as short transfer until reach the td pointed by
2603 } while (handling_skipped_tds);
2608 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2609 (unsigned long long) xhci_trb_virt_to_dma(
2610 xhci->event_ring->deq_seg,
2611 xhci->event_ring->dequeue),
2612 lower_32_bits(le64_to_cpu(event->buffer)),
2613 upper_32_bits(le64_to_cpu(event->buffer)),
2614 le32_to_cpu(event->transfer_len),
2615 le32_to_cpu(event->flags));
2620 * This function handles all OS-owned events on the event ring. It may drop
2621 * xhci->lock between event processing (e.g. to pass up port status changes).
2622 * Returns >0 for "possibly more events to process" (caller should call again),
2623 * otherwise 0 if done. In future, <0 returns should indicate error code.
2625 static int xhci_handle_event(struct xhci_hcd *xhci)
2627 union xhci_trb *event;
2628 int update_ptrs = 1;
2631 /* Event ring hasn't been allocated yet. */
2632 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2633 xhci_err(xhci, "ERROR event ring not ready\n");
2637 event = xhci->event_ring->dequeue;
2638 /* Does the HC or OS own the TRB? */
2639 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2640 xhci->event_ring->cycle_state)
2643 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2646 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2647 * speculative reads of the event's flags/data below.
2650 /* FIXME: Handle more event types. */
2651 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2652 case TRB_TYPE(TRB_COMPLETION):
2653 handle_cmd_completion(xhci, &event->event_cmd);
2655 case TRB_TYPE(TRB_PORT_STATUS):
2656 handle_port_status(xhci, event);
2659 case TRB_TYPE(TRB_TRANSFER):
2660 ret = handle_tx_event(xhci, &event->trans_event);
2664 case TRB_TYPE(TRB_DEV_NOTE):
2665 handle_device_notification(xhci, event);
2668 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2670 handle_vendor_event(xhci, event);
2672 xhci_warn(xhci, "ERROR unknown event type %d\n",
2674 le32_to_cpu(event->event_cmd.flags)));
2676 /* Any of the above functions may drop and re-acquire the lock, so check
2677 * to make sure a watchdog timer didn't mark the host as non-responsive.
2679 if (xhci->xhc_state & XHCI_STATE_DYING) {
2680 xhci_dbg(xhci, "xHCI host dying, returning from "
2681 "event handler.\n");
2686 /* Update SW event ring dequeue pointer */
2687 inc_deq(xhci, xhci->event_ring);
2689 /* Are there more items on the event ring? Caller will call us again to
2696 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2697 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2698 * indicators of an event TRB error, but we check the status *first* to be safe.
2700 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2702 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2703 union xhci_trb *event_ring_deq;
2704 irqreturn_t ret = IRQ_NONE;
2705 unsigned long flags;
2710 spin_lock_irqsave(&xhci->lock, flags);
2711 /* Check if the xHC generated the interrupt, or the irq is shared */
2712 status = readl(&xhci->op_regs->status);
2713 if (status == ~(u32)0) {
2719 if (!(status & STS_EINT))
2722 if (status & STS_FATAL) {
2723 xhci_warn(xhci, "WARNING: Host System Error\n");
2730 * Clear the op reg interrupt status first,
2731 * so we can receive interrupts from other MSI-X interrupters.
2732 * Write 1 to clear the interrupt status.
2735 writel(status, &xhci->op_regs->status);
2737 if (!hcd->msi_enabled) {
2739 irq_pending = readl(&xhci->ir_set->irq_pending);
2740 irq_pending |= IMAN_IP;
2741 writel(irq_pending, &xhci->ir_set->irq_pending);
2744 if (xhci->xhc_state & XHCI_STATE_DYING ||
2745 xhci->xhc_state & XHCI_STATE_HALTED) {
2746 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2747 "Shouldn't IRQs be disabled?\n");
2748 /* Clear the event handler busy flag (RW1C);
2749 * the event ring should be empty.
2751 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2752 xhci_write_64(xhci, temp_64 | ERST_EHB,
2753 &xhci->ir_set->erst_dequeue);
2758 event_ring_deq = xhci->event_ring->dequeue;
2759 /* FIXME this should be a delayed service routine
2760 * that clears the EHB.
2762 while (xhci_handle_event(xhci) > 0) {}
2764 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2765 /* If necessary, update the HW's version of the event ring deq ptr. */
2766 if (event_ring_deq != xhci->event_ring->dequeue) {
2767 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2768 xhci->event_ring->dequeue);
2770 xhci_warn(xhci, "WARN something wrong with SW event "
2771 "ring dequeue ptr.\n");
2772 /* Update HC event ring dequeue pointer */
2773 temp_64 &= ERST_PTR_MASK;
2774 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2777 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2778 temp_64 |= ERST_EHB;
2779 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2783 spin_unlock_irqrestore(&xhci->lock, flags);
2788 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2790 return xhci_irq(hcd);
2793 /**** Endpoint Ring Operations ****/
2796 * Generic function for queueing a TRB on a ring.
2797 * The caller must have checked to make sure there's room on the ring.
2799 * @more_trbs_coming: Will you enqueue more TRBs before calling
2800 * prepare_transfer()?
2802 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2803 bool more_trbs_coming,
2804 u32 field1, u32 field2, u32 field3, u32 field4)
2806 struct xhci_generic_trb *trb;
2808 trb = &ring->enqueue->generic;
2809 trb->field[0] = cpu_to_le32(field1);
2810 trb->field[1] = cpu_to_le32(field2);
2811 trb->field[2] = cpu_to_le32(field3);
2812 trb->field[3] = cpu_to_le32(field4);
2814 trace_xhci_queue_trb(ring, trb);
2816 inc_enq(xhci, ring, more_trbs_coming);
2820 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2821 * FIXME allocate segments if the ring is full.
2823 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2824 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2826 unsigned int num_trbs_needed;
2828 /* Make sure the endpoint has been added to xHC schedule */
2830 case EP_STATE_DISABLED:
2832 * USB core changed config/interfaces without notifying us,
2833 * or hardware is reporting the wrong state.
2835 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2837 case EP_STATE_ERROR:
2838 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2839 /* FIXME event handling code for error needs to clear it */
2840 /* XXX not sure if this should be -ENOENT or not */
2842 case EP_STATE_HALTED:
2843 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2844 case EP_STATE_STOPPED:
2845 case EP_STATE_RUNNING:
2848 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2850 * FIXME issue Configure Endpoint command to try to get the HC
2851 * back into a known state.
2857 if (room_on_ring(xhci, ep_ring, num_trbs))
2860 if (ep_ring == xhci->cmd_ring) {
2861 xhci_err(xhci, "Do not support expand command ring\n");
2865 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2866 "ERROR no room on ep ring, try ring expansion");
2867 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2868 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2870 xhci_err(xhci, "Ring expansion failed\n");
2875 while (trb_is_link(ep_ring->enqueue)) {
2876 /* If we're not dealing with 0.95 hardware or isoc rings
2877 * on AMD 0.96 host, clear the chain bit.
2879 if (!xhci_link_trb_quirk(xhci) &&
2880 !(ep_ring->type == TYPE_ISOC &&
2881 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2882 ep_ring->enqueue->link.control &=
2883 cpu_to_le32(~TRB_CHAIN);
2885 ep_ring->enqueue->link.control |=
2886 cpu_to_le32(TRB_CHAIN);
2889 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2891 /* Toggle the cycle bit after the last ring segment. */
2892 if (link_trb_toggles_cycle(ep_ring->enqueue))
2893 ep_ring->cycle_state ^= 1;
2895 ep_ring->enq_seg = ep_ring->enq_seg->next;
2896 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2901 static int prepare_transfer(struct xhci_hcd *xhci,
2902 struct xhci_virt_device *xdev,
2903 unsigned int ep_index,
2904 unsigned int stream_id,
2905 unsigned int num_trbs,
2907 unsigned int td_index,
2911 struct urb_priv *urb_priv;
2913 struct xhci_ring *ep_ring;
2914 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2916 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2918 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2923 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2924 num_trbs, mem_flags);
2928 urb_priv = urb->hcpriv;
2929 td = &urb_priv->td[td_index];
2931 INIT_LIST_HEAD(&td->td_list);
2932 INIT_LIST_HEAD(&td->cancelled_td_list);
2934 if (td_index == 0) {
2935 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2941 /* Add this TD to the tail of the endpoint ring's TD list */
2942 list_add_tail(&td->td_list, &ep_ring->td_list);
2943 td->start_seg = ep_ring->enq_seg;
2944 td->first_trb = ep_ring->enqueue;
2949 unsigned int count_trbs(u64 addr, u64 len)
2951 unsigned int num_trbs;
2953 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2961 static inline unsigned int count_trbs_needed(struct urb *urb)
2963 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2966 static unsigned int count_sg_trbs_needed(struct urb *urb)
2968 struct scatterlist *sg;
2969 unsigned int i, len, full_len, num_trbs = 0;
2971 full_len = urb->transfer_buffer_length;
2973 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2974 len = sg_dma_len(sg);
2975 num_trbs += count_trbs(sg_dma_address(sg), len);
2976 len = min_t(unsigned int, len, full_len);
2985 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
2989 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2990 len = urb->iso_frame_desc[i].length;
2992 return count_trbs(addr, len);
2995 static void check_trb_math(struct urb *urb, int running_total)
2997 if (unlikely(running_total != urb->transfer_buffer_length))
2998 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2999 "queued %#x (%d), asked for %#x (%d)\n",
3001 urb->ep->desc.bEndpointAddress,
3002 running_total, running_total,
3003 urb->transfer_buffer_length,
3004 urb->transfer_buffer_length);
3007 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3008 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3009 struct xhci_generic_trb *start_trb)
3012 * Pass all the TRBs to the hardware at once and make sure this write
3017 start_trb->field[3] |= cpu_to_le32(start_cycle);
3019 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3020 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3023 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3024 struct xhci_ep_ctx *ep_ctx)
3029 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3030 ep_interval = urb->interval;
3032 /* Convert to microframes */
3033 if (urb->dev->speed == USB_SPEED_LOW ||
3034 urb->dev->speed == USB_SPEED_FULL)
3037 /* FIXME change this to a warning and a suggestion to use the new API
3038 * to set the polling interval (once the API is added).
3040 if (xhci_interval != ep_interval) {
3041 dev_dbg_ratelimited(&urb->dev->dev,
3042 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3043 ep_interval, ep_interval == 1 ? "" : "s",
3044 xhci_interval, xhci_interval == 1 ? "" : "s");
3045 urb->interval = xhci_interval;
3046 /* Convert back to frames for LS/FS devices */
3047 if (urb->dev->speed == USB_SPEED_LOW ||
3048 urb->dev->speed == USB_SPEED_FULL)
3054 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3055 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3056 * (comprised of sg list entries) can take several service intervals to
3059 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3060 struct urb *urb, int slot_id, unsigned int ep_index)
3062 struct xhci_ep_ctx *ep_ctx;
3064 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3065 check_interval(xhci, urb, ep_ctx);
3067 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3071 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3072 * packets remaining in the TD (*not* including this TRB).
3074 * Total TD packet count = total_packet_count =
3075 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3077 * Packets transferred up to and including this TRB = packets_transferred =
3078 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3080 * TD size = total_packet_count - packets_transferred
3082 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3083 * including this TRB, right shifted by 10
3085 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3086 * This is taken care of in the TRB_TD_SIZE() macro
3088 * The last TRB in a TD must have the TD size set to zero.
3090 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3091 int trb_buff_len, unsigned int td_total_len,
3092 struct urb *urb, bool more_trbs_coming)
3094 u32 maxp, total_packet_count;
3096 /* MTK xHCI 0.96 contains some features from 1.0 */
3097 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3098 return ((td_total_len - transferred) >> 10);
3100 /* One TRB with a zero-length data packet. */
3101 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3102 trb_buff_len == td_total_len)
3105 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3106 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3109 maxp = usb_endpoint_maxp(&urb->ep->desc);
3110 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3112 /* Queueing functions don't count the current TRB into transferred */
3113 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3117 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3118 u32 *trb_buff_len, struct xhci_segment *seg)
3120 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3121 unsigned int unalign;
3122 unsigned int max_pkt;
3126 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3127 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3129 /* we got lucky, last normal TRB data on segment is packet aligned */
3133 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3134 unalign, *trb_buff_len);
3136 /* is the last nornal TRB alignable by splitting it */
3137 if (*trb_buff_len > unalign) {
3138 *trb_buff_len -= unalign;
3139 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3144 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3145 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3146 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3148 new_buff_len = max_pkt - (enqd_len % max_pkt);
3150 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3151 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3153 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3154 if (usb_urb_dir_out(urb)) {
3155 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3156 seg->bounce_buf, new_buff_len, enqd_len);
3157 if (len != new_buff_len)
3159 "WARN Wrong bounce buffer write length: %zu != %d\n",
3161 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3162 max_pkt, DMA_TO_DEVICE);
3164 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3165 max_pkt, DMA_FROM_DEVICE);
3168 if (dma_mapping_error(dev, seg->bounce_dma)) {
3169 /* try without aligning. Some host controllers survive */
3170 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3173 *trb_buff_len = new_buff_len;
3174 seg->bounce_len = new_buff_len;
3175 seg->bounce_offs = enqd_len;
3177 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3182 /* This is very similar to what ehci-q.c qtd_fill() does */
3183 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3184 struct urb *urb, int slot_id, unsigned int ep_index)
3186 struct xhci_ring *ring;
3187 struct urb_priv *urb_priv;
3189 struct xhci_generic_trb *start_trb;
3190 struct scatterlist *sg = NULL;
3191 bool more_trbs_coming = true;
3192 bool need_zero_pkt = false;
3193 bool first_trb = true;
3194 unsigned int num_trbs;
3195 unsigned int start_cycle, num_sgs = 0;
3196 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3198 u32 field, length_field, remainder;
3199 u64 addr, send_addr;
3201 ring = xhci_urb_to_transfer_ring(xhci, urb);
3205 full_len = urb->transfer_buffer_length;
3206 /* If we have scatter/gather list, we use it. */
3208 num_sgs = urb->num_mapped_sgs;
3210 addr = (u64) sg_dma_address(sg);
3211 block_len = sg_dma_len(sg);
3212 num_trbs = count_sg_trbs_needed(urb);
3214 num_trbs = count_trbs_needed(urb);
3215 addr = (u64) urb->transfer_dma;
3216 block_len = full_len;
3218 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3219 ep_index, urb->stream_id,
3220 num_trbs, urb, 0, mem_flags);
3221 if (unlikely(ret < 0))
3224 urb_priv = urb->hcpriv;
3226 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3227 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3228 need_zero_pkt = true;
3230 td = &urb_priv->td[0];
3233 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3234 * until we've finished creating all the other TRBs. The ring's cycle
3235 * state may change as we enqueue the other TRBs, so save it too.
3237 start_trb = &ring->enqueue->generic;
3238 start_cycle = ring->cycle_state;
3241 /* Queue the TRBs, even if they are zero-length */
3242 for (enqd_len = 0; first_trb || enqd_len < full_len;
3243 enqd_len += trb_buff_len) {
3244 field = TRB_TYPE(TRB_NORMAL);
3246 /* TRB buffer should not cross 64KB boundaries */
3247 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3248 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3250 if (enqd_len + trb_buff_len > full_len)
3251 trb_buff_len = full_len - enqd_len;
3253 /* Don't change the cycle bit of the first TRB until later */
3256 if (start_cycle == 0)
3259 field |= ring->cycle_state;
3261 /* Chain all the TRBs together; clear the chain bit in the last
3262 * TRB to indicate it's the last TRB in the chain.
3264 if (enqd_len + trb_buff_len < full_len) {
3266 if (trb_is_link(ring->enqueue + 1)) {
3267 if (xhci_align_td(xhci, urb, enqd_len,
3270 send_addr = ring->enq_seg->bounce_dma;
3271 /* assuming TD won't span 2 segs */
3272 td->bounce_seg = ring->enq_seg;
3276 if (enqd_len + trb_buff_len >= full_len) {
3277 field &= ~TRB_CHAIN;
3279 more_trbs_coming = false;
3280 td->last_trb = ring->enqueue;
3283 /* Only set interrupt on short packet for IN endpoints */
3284 if (usb_urb_dir_in(urb))
3287 /* Set the TRB length, TD size, and interrupter fields. */
3288 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3289 full_len, urb, more_trbs_coming);
3291 length_field = TRB_LEN(trb_buff_len) |
3292 TRB_TD_SIZE(remainder) |
3295 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3296 lower_32_bits(send_addr),
3297 upper_32_bits(send_addr),
3301 addr += trb_buff_len;
3302 sent_len = trb_buff_len;
3304 while (sg && sent_len >= block_len) {
3307 sent_len -= block_len;
3310 block_len = sg_dma_len(sg);
3311 addr = (u64) sg_dma_address(sg);
3315 block_len -= sent_len;
3319 if (need_zero_pkt) {
3320 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3321 ep_index, urb->stream_id,
3322 1, urb, 1, mem_flags);
3323 urb_priv->td[1].last_trb = ring->enqueue;
3324 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3325 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3328 check_trb_math(urb, enqd_len);
3329 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3330 start_cycle, start_trb);
3334 /* Caller must have locked xhci->lock */
3335 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3336 struct urb *urb, int slot_id, unsigned int ep_index)
3338 struct xhci_ring *ep_ring;
3341 struct usb_ctrlrequest *setup;
3342 struct xhci_generic_trb *start_trb;
3345 struct urb_priv *urb_priv;
3348 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3353 * Need to copy setup packet into setup TRB, so we can't use the setup
3356 if (!urb->setup_packet)
3359 /* 1 TRB for setup, 1 for status */
3362 * Don't need to check if we need additional event data and normal TRBs,
3363 * since data in control transfers will never get bigger than 16MB
3364 * XXX: can we get a buffer that crosses 64KB boundaries?
3366 if (urb->transfer_buffer_length > 0)
3368 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3369 ep_index, urb->stream_id,
3370 num_trbs, urb, 0, mem_flags);
3374 urb_priv = urb->hcpriv;
3375 td = &urb_priv->td[0];
3378 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3379 * until we've finished creating all the other TRBs. The ring's cycle
3380 * state may change as we enqueue the other TRBs, so save it too.
3382 start_trb = &ep_ring->enqueue->generic;
3383 start_cycle = ep_ring->cycle_state;
3385 /* Queue setup TRB - see section 6.4.1.2.1 */
3386 /* FIXME better way to translate setup_packet into two u32 fields? */
3387 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3389 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3390 if (start_cycle == 0)
3393 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3394 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3395 if (urb->transfer_buffer_length > 0) {
3396 if (setup->bRequestType & USB_DIR_IN)
3397 field |= TRB_TX_TYPE(TRB_DATA_IN);
3399 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3403 queue_trb(xhci, ep_ring, true,
3404 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3405 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3406 TRB_LEN(8) | TRB_INTR_TARGET(0),
3407 /* Immediate data in pointer */
3410 /* If there's data, queue data TRBs */
3411 /* Only set interrupt on short packet for IN endpoints */
3412 if (usb_urb_dir_in(urb))
3413 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3415 field = TRB_TYPE(TRB_DATA);
3417 if (urb->transfer_buffer_length > 0) {
3418 u32 length_field, remainder;
3420 remainder = xhci_td_remainder(xhci, 0,
3421 urb->transfer_buffer_length,
3422 urb->transfer_buffer_length,
3424 length_field = TRB_LEN(urb->transfer_buffer_length) |
3425 TRB_TD_SIZE(remainder) |
3427 if (setup->bRequestType & USB_DIR_IN)
3428 field |= TRB_DIR_IN;
3429 queue_trb(xhci, ep_ring, true,
3430 lower_32_bits(urb->transfer_dma),
3431 upper_32_bits(urb->transfer_dma),
3433 field | ep_ring->cycle_state);
3436 /* Save the DMA address of the last TRB in the TD */
3437 td->last_trb = ep_ring->enqueue;
3439 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3440 /* If the device sent data, the status stage is an OUT transfer */
3441 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3445 queue_trb(xhci, ep_ring, false,
3449 /* Event on completion */
3450 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3452 giveback_first_trb(xhci, slot_id, ep_index, 0,
3453 start_cycle, start_trb);
3458 * The transfer burst count field of the isochronous TRB defines the number of
3459 * bursts that are required to move all packets in this TD. Only SuperSpeed
3460 * devices can burst up to bMaxBurst number of packets per service interval.
3461 * This field is zero based, meaning a value of zero in the field means one
3462 * burst. Basically, for everything but SuperSpeed devices, this field will be
3463 * zero. Only xHCI 1.0 host controllers support this field.
3465 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3466 struct urb *urb, unsigned int total_packet_count)
3468 unsigned int max_burst;
3470 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3473 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3474 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3478 * Returns the number of packets in the last "burst" of packets. This field is
3479 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3480 * the last burst packet count is equal to the total number of packets in the
3481 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3482 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3483 * contain 1 to (bMaxBurst + 1) packets.
3485 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3486 struct urb *urb, unsigned int total_packet_count)
3488 unsigned int max_burst;
3489 unsigned int residue;
3491 if (xhci->hci_version < 0x100)
3494 if (urb->dev->speed >= USB_SPEED_SUPER) {
3495 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3496 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3497 residue = total_packet_count % (max_burst + 1);
3498 /* If residue is zero, the last burst contains (max_burst + 1)
3499 * number of packets, but the TLBPC field is zero-based.
3505 if (total_packet_count == 0)
3507 return total_packet_count - 1;
3511 * Calculates Frame ID field of the isochronous TRB identifies the
3512 * target frame that the Interval associated with this Isochronous
3513 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3515 * Returns actual frame id on success, negative value on error.
3517 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3518 struct urb *urb, int index)
3520 int start_frame, ist, ret = 0;
3521 int start_frame_id, end_frame_id, current_frame_id;
3523 if (urb->dev->speed == USB_SPEED_LOW ||
3524 urb->dev->speed == USB_SPEED_FULL)
3525 start_frame = urb->start_frame + index * urb->interval;
3527 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3529 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3531 * If bit [3] of IST is cleared to '0', software can add a TRB no
3532 * later than IST[2:0] Microframes before that TRB is scheduled to
3534 * If bit [3] of IST is set to '1', software can add a TRB no later
3535 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3537 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3538 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3541 /* Software shall not schedule an Isoch TD with a Frame ID value that
3542 * is less than the Start Frame ID or greater than the End Frame ID,
3545 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3546 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3548 * Both the End Frame ID and Start Frame ID values are calculated
3549 * in microframes. When software determines the valid Frame ID value;
3550 * The End Frame ID value should be rounded down to the nearest Frame
3551 * boundary, and the Start Frame ID value should be rounded up to the
3552 * nearest Frame boundary.
3554 current_frame_id = readl(&xhci->run_regs->microframe_index);
3555 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3556 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3558 start_frame &= 0x7ff;
3559 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3560 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3562 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3563 __func__, index, readl(&xhci->run_regs->microframe_index),
3564 start_frame_id, end_frame_id, start_frame);
3566 if (start_frame_id < end_frame_id) {
3567 if (start_frame > end_frame_id ||
3568 start_frame < start_frame_id)
3570 } else if (start_frame_id > end_frame_id) {
3571 if ((start_frame > end_frame_id &&
3572 start_frame < start_frame_id))
3579 if (ret == -EINVAL || start_frame == start_frame_id) {
3580 start_frame = start_frame_id + 1;
3581 if (urb->dev->speed == USB_SPEED_LOW ||
3582 urb->dev->speed == USB_SPEED_FULL)
3583 urb->start_frame = start_frame;
3585 urb->start_frame = start_frame << 3;
3591 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3592 start_frame, current_frame_id, index,
3593 start_frame_id, end_frame_id);
3594 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3601 /* This is for isoc transfer */
3602 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3603 struct urb *urb, int slot_id, unsigned int ep_index)
3605 struct xhci_ring *ep_ring;
3606 struct urb_priv *urb_priv;
3608 int num_tds, trbs_per_td;
3609 struct xhci_generic_trb *start_trb;
3612 u32 field, length_field;
3613 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3614 u64 start_addr, addr;
3616 bool more_trbs_coming;
3617 struct xhci_virt_ep *xep;
3620 xep = &xhci->devs[slot_id]->eps[ep_index];
3621 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3623 num_tds = urb->number_of_packets;
3625 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3628 start_addr = (u64) urb->transfer_dma;
3629 start_trb = &ep_ring->enqueue->generic;
3630 start_cycle = ep_ring->cycle_state;
3632 urb_priv = urb->hcpriv;
3633 /* Queue the TRBs for each TD, even if they are zero-length */
3634 for (i = 0; i < num_tds; i++) {
3635 unsigned int total_pkt_count, max_pkt;
3636 unsigned int burst_count, last_burst_pkt_count;
3641 addr = start_addr + urb->iso_frame_desc[i].offset;
3642 td_len = urb->iso_frame_desc[i].length;
3643 td_remain_len = td_len;
3644 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3645 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3647 /* A zero-length transfer still involves at least one packet. */
3648 if (total_pkt_count == 0)
3650 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3651 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3652 urb, total_pkt_count);
3654 trbs_per_td = count_isoc_trbs_needed(urb, i);
3656 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3657 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3663 td = &urb_priv->td[i];
3665 /* use SIA as default, if frame id is used overwrite it */
3666 sia_frame_id = TRB_SIA;
3667 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3668 HCC_CFC(xhci->hcc_params)) {
3669 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3671 sia_frame_id = TRB_FRAME_ID(frame_id);
3674 * Set isoc specific data for the first TRB in a TD.
3675 * Prevent HW from getting the TRBs by keeping the cycle state
3676 * inverted in the first TDs isoc TRB.
3678 field = TRB_TYPE(TRB_ISOC) |
3679 TRB_TLBPC(last_burst_pkt_count) |
3681 (i ? ep_ring->cycle_state : !start_cycle);
3683 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3684 if (!xep->use_extended_tbc)
3685 field |= TRB_TBC(burst_count);
3687 /* fill the rest of the TRB fields, and remaining normal TRBs */
3688 for (j = 0; j < trbs_per_td; j++) {
3691 /* only first TRB is isoc, overwrite otherwise */
3693 field = TRB_TYPE(TRB_NORMAL) |
3694 ep_ring->cycle_state;
3696 /* Only set interrupt on short packet for IN EPs */
3697 if (usb_urb_dir_in(urb))
3700 /* Set the chain bit for all except the last TRB */
3701 if (j < trbs_per_td - 1) {
3702 more_trbs_coming = true;
3705 more_trbs_coming = false;
3706 td->last_trb = ep_ring->enqueue;
3708 /* set BEI, except for the last TD */
3709 if (xhci->hci_version >= 0x100 &&
3710 !(xhci->quirks & XHCI_AVOID_BEI) &&
3714 /* Calculate TRB length */
3715 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3716 if (trb_buff_len > td_remain_len)
3717 trb_buff_len = td_remain_len;
3719 /* Set the TRB length, TD size, & interrupter fields. */
3720 remainder = xhci_td_remainder(xhci, running_total,
3721 trb_buff_len, td_len,
3722 urb, more_trbs_coming);
3724 length_field = TRB_LEN(trb_buff_len) |
3727 /* xhci 1.1 with ETE uses TD Size field for TBC */
3728 if (first_trb && xep->use_extended_tbc)
3729 length_field |= TRB_TD_SIZE_TBC(burst_count);
3731 length_field |= TRB_TD_SIZE(remainder);
3734 queue_trb(xhci, ep_ring, more_trbs_coming,
3735 lower_32_bits(addr),
3736 upper_32_bits(addr),
3739 running_total += trb_buff_len;
3741 addr += trb_buff_len;
3742 td_remain_len -= trb_buff_len;
3745 /* Check TD length */
3746 if (running_total != td_len) {
3747 xhci_err(xhci, "ISOC TD length unmatch\n");
3753 /* store the next frame id */
3754 if (HCC_CFC(xhci->hcc_params))
3755 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3757 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3758 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3759 usb_amd_quirk_pll_disable();
3761 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3763 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3764 start_cycle, start_trb);
3767 /* Clean up a partially enqueued isoc transfer. */
3769 for (i--; i >= 0; i--)
3770 list_del_init(&urb_priv->td[i].td_list);
3772 /* Use the first TD as a temporary variable to turn the TDs we've queued
3773 * into No-ops with a software-owned cycle bit. That way the hardware
3774 * won't accidentally start executing bogus TDs when we partially
3775 * overwrite them. td->first_trb and td->start_seg are already set.
3777 urb_priv->td[0].last_trb = ep_ring->enqueue;
3778 /* Every TRB except the first & last will have its cycle bit flipped. */
3779 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3781 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3782 ep_ring->enqueue = urb_priv->td[0].first_trb;
3783 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3784 ep_ring->cycle_state = start_cycle;
3785 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3786 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3791 * Check transfer ring to guarantee there is enough room for the urb.
3792 * Update ISO URB start_frame and interval.
3793 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3794 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3795 * Contiguous Frame ID is not supported by HC.
3797 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3798 struct urb *urb, int slot_id, unsigned int ep_index)
3800 struct xhci_virt_device *xdev;
3801 struct xhci_ring *ep_ring;
3802 struct xhci_ep_ctx *ep_ctx;
3804 int num_tds, num_trbs, i;
3806 struct xhci_virt_ep *xep;
3809 xdev = xhci->devs[slot_id];
3810 xep = &xhci->devs[slot_id]->eps[ep_index];
3811 ep_ring = xdev->eps[ep_index].ring;
3812 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3815 num_tds = urb->number_of_packets;
3816 for (i = 0; i < num_tds; i++)
3817 num_trbs += count_isoc_trbs_needed(urb, i);
3819 /* Check the ring to guarantee there is enough room for the whole urb.
3820 * Do not insert any td of the urb to the ring if the check failed.
3822 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3823 num_trbs, mem_flags);
3828 * Check interval value. This should be done before we start to
3829 * calculate the start frame value.
3831 check_interval(xhci, urb, ep_ctx);
3833 /* Calculate the start frame and put it in urb->start_frame. */
3834 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3835 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3836 urb->start_frame = xep->next_frame_id;
3837 goto skip_start_over;
3841 start_frame = readl(&xhci->run_regs->microframe_index);
3842 start_frame &= 0x3fff;
3844 * Round up to the next frame and consider the time before trb really
3845 * gets scheduled by hardare.
3847 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3848 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3850 start_frame += ist + XHCI_CFC_DELAY;
3851 start_frame = roundup(start_frame, 8);
3854 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3855 * is greate than 8 microframes.
3857 if (urb->dev->speed == USB_SPEED_LOW ||
3858 urb->dev->speed == USB_SPEED_FULL) {
3859 start_frame = roundup(start_frame, urb->interval << 3);
3860 urb->start_frame = start_frame >> 3;
3862 start_frame = roundup(start_frame, urb->interval);
3863 urb->start_frame = start_frame;
3867 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3869 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3872 /**** Command Ring Operations ****/
3874 /* Generic function for queueing a command TRB on the command ring.
3875 * Check to make sure there's room on the command ring for one command TRB.
3876 * Also check that there's room reserved for commands that must not fail.
3877 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3878 * then only check for the number of reserved spots.
3879 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3880 * because the command event handler may want to resubmit a failed command.
3882 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3883 u32 field1, u32 field2,
3884 u32 field3, u32 field4, bool command_must_succeed)
3886 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3889 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3890 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3891 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3895 if (!command_must_succeed)
3898 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3899 reserved_trbs, GFP_ATOMIC);
3901 xhci_err(xhci, "ERR: No room for command on command ring\n");
3902 if (command_must_succeed)
3903 xhci_err(xhci, "ERR: Reserved TRB counting for "
3904 "unfailable commands failed.\n");
3908 cmd->command_trb = xhci->cmd_ring->enqueue;
3910 /* if there are no other commands queued we start the timeout timer */
3911 if (list_empty(&xhci->cmd_list)) {
3912 xhci->current_cmd = cmd;
3913 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3916 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3918 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3919 field4 | xhci->cmd_ring->cycle_state);
3923 /* Queue a slot enable or disable request on the command ring */
3924 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3925 u32 trb_type, u32 slot_id)
3927 return queue_command(xhci, cmd, 0, 0, 0,
3928 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3931 /* Queue an address device command TRB */
3932 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3933 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3935 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3936 upper_32_bits(in_ctx_ptr), 0,
3937 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3938 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3941 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3942 u32 field1, u32 field2, u32 field3, u32 field4)
3944 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3947 /* Queue a reset device command TRB */
3948 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3951 return queue_command(xhci, cmd, 0, 0, 0,
3952 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3956 /* Queue a configure endpoint command TRB */
3957 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3958 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3959 u32 slot_id, bool command_must_succeed)
3961 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3962 upper_32_bits(in_ctx_ptr), 0,
3963 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3964 command_must_succeed);
3967 /* Queue an evaluate context command TRB */
3968 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3969 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3971 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3972 upper_32_bits(in_ctx_ptr), 0,
3973 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3974 command_must_succeed);
3978 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3979 * activity on an endpoint that is about to be suspended.
3981 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3982 int slot_id, unsigned int ep_index, int suspend)
3984 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3985 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3986 u32 type = TRB_TYPE(TRB_STOP_RING);
3987 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3989 return queue_command(xhci, cmd, 0, 0, 0,
3990 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3993 /* Set Transfer Ring Dequeue Pointer command */
3994 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3995 unsigned int slot_id, unsigned int ep_index,
3996 struct xhci_dequeue_state *deq_state)
3999 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4000 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4001 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4003 u32 type = TRB_TYPE(TRB_SET_DEQ);
4004 struct xhci_virt_ep *ep;
4005 struct xhci_command *cmd;
4008 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4009 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4010 deq_state->new_deq_seg,
4011 (unsigned long long)deq_state->new_deq_seg->dma,
4012 deq_state->new_deq_ptr,
4013 (unsigned long long)xhci_trb_virt_to_dma(
4014 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4015 deq_state->new_cycle_state);
4017 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4018 deq_state->new_deq_ptr);
4020 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4021 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4022 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4025 ep = &xhci->devs[slot_id]->eps[ep_index];
4026 if ((ep->ep_state & SET_DEQ_PENDING)) {
4027 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4028 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4032 /* This function gets called from contexts where it cannot sleep */
4033 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4037 ep->queued_deq_seg = deq_state->new_deq_seg;
4038 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4039 if (deq_state->stream_id)
4040 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4041 ret = queue_command(xhci, cmd,
4042 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4043 upper_32_bits(addr), trb_stream_id,
4044 trb_slot_id | trb_ep_index | type, false);
4046 xhci_free_command(xhci, cmd);
4050 /* Stop the TD queueing code from ringing the doorbell until
4051 * this command completes. The HC won't set the dequeue pointer
4052 * if the ring is running, and ringing the doorbell starts the
4055 ep->ep_state |= SET_DEQ_PENDING;
4058 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4059 int slot_id, unsigned int ep_index,
4060 enum xhci_ep_reset_type reset_type)
4062 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4063 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4064 u32 type = TRB_TYPE(TRB_RESET_EP);
4066 if (reset_type == EP_SOFT_RESET)
4069 return queue_command(xhci, cmd, 0, 0, 0,
4070 trb_slot_id | trb_ep_index | type, false);