1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
155 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
157 unsigned int link_trb_count = 0;
159 /* event ring doesn't have link trbs, check for last trb */
160 if (ring->type == TYPE_EVENT) {
161 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
166 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 /* All other rings have link trbs */
173 if (!trb_is_link(ring->dequeue)) {
174 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
175 xhci_warn(xhci, "Missing link TRB at end of segment\n");
178 ring->num_trbs_free++;
182 while (trb_is_link(ring->dequeue)) {
183 ring->deq_seg = ring->deq_seg->next;
184 ring->dequeue = ring->deq_seg->trbs;
186 if (link_trb_count++ > ring->num_segs) {
187 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
192 trace_xhci_inc_deq(ring);
198 * See Cycle bit rules. SW is the consumer for the event ring only.
200 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
201 * chain bit is set), then set the chain bit in all the following link TRBs.
202 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
203 * have their chain bit cleared (so that each Link TRB is a separate TD).
205 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
206 * set, but other sections talk about dealing with the chain bit set. This was
207 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
208 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
210 * @more_trbs_coming: Will you enqueue more TRBs before calling
211 * prepare_transfer()?
213 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
214 bool more_trbs_coming)
217 union xhci_trb *next;
218 unsigned int link_trb_count = 0;
220 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
221 /* If this is not event ring, there is one less usable TRB */
222 if (!trb_is_link(ring->enqueue))
223 ring->num_trbs_free--;
225 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
226 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
230 next = ++(ring->enqueue);
232 /* Update the dequeue pointer further if that was a link TRB */
233 while (trb_is_link(next)) {
236 * If the caller doesn't plan on enqueueing more TDs before
237 * ringing the doorbell, then we don't want to give the link TRB
238 * to the hardware just yet. We'll give the link TRB back in
239 * prepare_ring() just before we enqueue the TD at the top of
242 if (!chain && !more_trbs_coming)
245 /* If we're not dealing with 0.95 hardware or isoc rings on
246 * AMD 0.96 host, carry over the chain bit of the previous TRB
247 * (which may mean the chain bit is cleared).
249 if (!(ring->type == TYPE_ISOC &&
250 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
251 !xhci_link_trb_quirk(xhci)) {
252 next->link.control &= cpu_to_le32(~TRB_CHAIN);
253 next->link.control |= cpu_to_le32(chain);
255 /* Give this link TRB to the hardware */
257 next->link.control ^= cpu_to_le32(TRB_CYCLE);
259 /* Toggle the cycle bit after the last ring segment. */
260 if (link_trb_toggles_cycle(next))
261 ring->cycle_state ^= 1;
263 ring->enq_seg = ring->enq_seg->next;
264 ring->enqueue = ring->enq_seg->trbs;
265 next = ring->enqueue;
267 if (link_trb_count++ > ring->num_segs) {
268 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
273 trace_xhci_inc_enq(ring);
277 * Check to see if there's room to enqueue num_trbs on the ring and make sure
278 * enqueue pointer will not advance into dequeue segment. See rules above.
280 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
281 unsigned int num_trbs)
283 int num_trbs_in_deq_seg;
285 if (ring->num_trbs_free < num_trbs)
288 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
289 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
290 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
297 /* Ring the host controller doorbell after placing a command on the ring */
298 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
300 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
303 xhci_dbg(xhci, "// Ding dong!\n");
305 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
307 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
308 /* Flush PCI posted writes */
309 readl(&xhci->dba->doorbell[0]);
312 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
314 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
317 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
319 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
324 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
325 * If there are other commands waiting then restart the ring and kick the timer.
326 * This must be called with command ring stopped and xhci->lock held.
328 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
329 struct xhci_command *cur_cmd)
331 struct xhci_command *i_cmd;
333 /* Turn all aborted commands in list to no-ops, then restart */
334 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
336 if (i_cmd->status != COMP_COMMAND_ABORTED)
339 i_cmd->status = COMP_COMMAND_RING_STOPPED;
341 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
344 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
347 * caller waiting for completion is called when command
348 * completion event is received for these no-op commands
352 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
354 /* ring command ring doorbell to restart the command ring */
355 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
356 !(xhci->xhc_state & XHCI_STATE_DYING)) {
357 xhci->current_cmd = cur_cmd;
358 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
359 xhci_ring_cmd_db(xhci);
363 /* Must be called with xhci->lock held, releases and aquires lock back */
364 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
369 xhci_dbg(xhci, "Abort command ring\n");
371 reinit_completion(&xhci->cmd_ring_stop_completion);
373 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
374 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
375 &xhci->op_regs->cmd_ring);
377 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
378 * completion of the Command Abort operation. If CRR is not negated in 5
379 * seconds then driver handles it as if host died (-ENODEV).
380 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
381 * and try to recover a -ETIMEDOUT with a host controller reset.
383 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
384 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
386 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
392 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
393 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
394 * but the completion event in never sent. Wait 2 secs (arbitrary
395 * number) to handle those cases after negation of CMD_RING_RUNNING.
397 spin_unlock_irqrestore(&xhci->lock, flags);
398 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
399 msecs_to_jiffies(2000));
400 spin_lock_irqsave(&xhci->lock, flags);
402 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
403 xhci_cleanup_command_queue(xhci);
405 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
410 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
411 unsigned int slot_id,
412 unsigned int ep_index,
413 unsigned int stream_id)
415 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
416 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
417 unsigned int ep_state = ep->ep_state;
419 /* Don't ring the doorbell for this endpoint if there are pending
420 * cancellations because we don't want to interrupt processing.
421 * We don't want to restart any stream rings if there's a set dequeue
422 * pointer command pending because the device can choose to start any
423 * stream once the endpoint is on the HW schedule.
425 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
426 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
429 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
431 writel(DB_VALUE(ep_index, stream_id), db_addr);
432 /* flush the write */
436 /* Ring the doorbell for any rings with pending URBs */
437 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
438 unsigned int slot_id,
439 unsigned int ep_index)
441 unsigned int stream_id;
442 struct xhci_virt_ep *ep;
444 ep = &xhci->devs[slot_id]->eps[ep_index];
446 /* A ring has pending URBs if its TD list is not empty */
447 if (!(ep->ep_state & EP_HAS_STREAMS)) {
448 if (ep->ring && !(list_empty(&ep->ring->td_list)))
449 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
453 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
455 struct xhci_stream_info *stream_info = ep->stream_info;
456 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
457 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
462 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
463 unsigned int slot_id,
464 unsigned int ep_index)
466 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
469 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
470 unsigned int slot_id,
471 unsigned int ep_index)
473 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
474 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
477 if (ep_index >= EP_CTX_PER_DEV) {
478 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
481 if (!xhci->devs[slot_id]) {
482 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
486 return &xhci->devs[slot_id]->eps[ep_index];
489 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
490 struct xhci_virt_ep *ep,
491 unsigned int stream_id)
493 /* common case, no streams */
494 if (!(ep->ep_state & EP_HAS_STREAMS))
497 if (!ep->stream_info)
500 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
501 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
502 stream_id, ep->vdev->slot_id, ep->ep_index);
506 return ep->stream_info->stream_rings[stream_id];
509 /* Get the right ring for the given slot_id, ep_index and stream_id.
510 * If the endpoint supports streams, boundary check the URB's stream ID.
511 * If the endpoint doesn't support streams, return the singular endpoint ring.
513 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
514 unsigned int slot_id, unsigned int ep_index,
515 unsigned int stream_id)
517 struct xhci_virt_ep *ep;
519 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
523 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
528 * Get the hw dequeue pointer xHC stopped on, either directly from the
529 * endpoint context, or if streams are in use from the stream context.
530 * The returned hw_dequeue contains the lowest four bits with cycle state
531 * and possbile stream context type.
533 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
534 unsigned int ep_index, unsigned int stream_id)
536 struct xhci_ep_ctx *ep_ctx;
537 struct xhci_stream_ctx *st_ctx;
538 struct xhci_virt_ep *ep;
540 ep = &vdev->eps[ep_index];
542 if (ep->ep_state & EP_HAS_STREAMS) {
543 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
544 return le64_to_cpu(st_ctx->stream_ring);
546 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
547 return le64_to_cpu(ep_ctx->deq);
551 * Move the xHC's endpoint ring dequeue pointer past cur_td.
552 * Record the new state of the xHC's endpoint ring dequeue segment,
553 * dequeue pointer, stream id, and new consumer cycle state in state.
554 * Update our internal representation of the ring's dequeue pointer.
556 * We do this in three jumps:
557 * - First we update our new ring state to be the same as when the xHC stopped.
558 * - Then we traverse the ring to find the segment that contains
559 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
560 * any link TRBs with the toggle cycle bit set.
561 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
562 * if we've moved it past a link TRB with the toggle cycle bit set.
564 * Some of the uses of xhci_generic_trb are grotty, but if they're done
565 * with correct __le32 accesses they should work fine. Only users of this are
568 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
569 unsigned int slot_id, unsigned int ep_index,
570 unsigned int stream_id, struct xhci_td *cur_td,
571 struct xhci_dequeue_state *state)
573 struct xhci_virt_device *dev = xhci->devs[slot_id];
574 struct xhci_virt_ep *ep = &dev->eps[ep_index];
575 struct xhci_ring *ep_ring;
576 struct xhci_segment *new_seg;
577 union xhci_trb *new_deq;
580 bool cycle_found = false;
581 bool td_last_trb_found = false;
583 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
584 ep_index, stream_id);
586 xhci_warn(xhci, "WARN can't find new dequeue state "
587 "for invalid stream ID %u.\n",
592 * A cancelled TD can complete with a stall if HW cached the trb.
593 * In this case driver can't find cur_td, but if the ring is empty we
594 * can move the dequeue pointer to the current enqueue position.
597 if (list_empty(&ep_ring->td_list)) {
598 state->new_deq_seg = ep_ring->enq_seg;
599 state->new_deq_ptr = ep_ring->enqueue;
600 state->new_cycle_state = ep_ring->cycle_state;
603 xhci_warn(xhci, "Can't find new dequeue state, missing cur_td\n");
608 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
609 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
610 "Finding endpoint context");
612 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
613 new_seg = ep_ring->deq_seg;
614 new_deq = ep_ring->dequeue;
615 state->new_cycle_state = hw_dequeue & 0x1;
616 state->stream_id = stream_id;
619 * We want to find the pointer, segment and cycle state of the new trb
620 * (the one after current TD's last_trb). We know the cycle state at
621 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
625 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
626 == (dma_addr_t)(hw_dequeue & ~0xf)) {
628 if (td_last_trb_found)
631 if (new_deq == cur_td->last_trb)
632 td_last_trb_found = true;
634 if (cycle_found && trb_is_link(new_deq) &&
635 link_trb_toggles_cycle(new_deq))
636 state->new_cycle_state ^= 0x1;
638 next_trb(xhci, ep_ring, &new_seg, &new_deq);
640 /* Search wrapped around, bail out */
641 if (new_deq == ep->ring->dequeue) {
642 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
643 state->new_deq_seg = NULL;
644 state->new_deq_ptr = NULL;
648 } while (!cycle_found || !td_last_trb_found);
650 state->new_deq_seg = new_seg;
651 state->new_deq_ptr = new_deq;
654 /* Don't update the ring cycle state for the producer (us). */
655 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
656 "Cycle state = 0x%x", state->new_cycle_state);
658 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
659 "New dequeue segment = %p (virtual)",
661 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
662 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
663 "New dequeue pointer = 0x%llx (DMA)",
664 (unsigned long long) addr);
667 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
668 * (The last TRB actually points to the ring enqueue pointer, which is not part
669 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
671 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
672 struct xhci_td *td, bool flip_cycle)
674 struct xhci_segment *seg = td->start_seg;
675 union xhci_trb *trb = td->first_trb;
678 trb_to_noop(trb, TRB_TR_NOOP);
680 /* flip cycle if asked to */
681 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
682 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
684 if (trb == td->last_trb)
687 next_trb(xhci, ep_ring, &seg, &trb);
691 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
692 struct xhci_virt_ep *ep)
694 ep->ep_state &= ~EP_STOP_CMD_PENDING;
695 /* Can't del_timer_sync in interrupt */
696 del_timer(&ep->stop_cmd_timer);
700 * Must be called with xhci->lock held in interrupt context,
701 * releases and re-acquires xhci->lock
703 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
704 struct xhci_td *cur_td, int status)
706 struct urb *urb = cur_td->urb;
707 struct urb_priv *urb_priv = urb->hcpriv;
708 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
710 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
711 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
712 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
713 if (xhci->quirks & XHCI_AMD_PLL_FIX)
714 usb_amd_quirk_pll_enable();
717 xhci_urb_free_priv(urb_priv);
718 usb_hcd_unlink_urb_from_ep(hcd, urb);
719 trace_xhci_urb_giveback(urb);
720 usb_hcd_giveback_urb(hcd, urb, status);
723 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
724 struct xhci_ring *ring, struct xhci_td *td)
726 struct device *dev = xhci_to_hcd(xhci)->self.controller;
727 struct xhci_segment *seg = td->bounce_seg;
728 struct urb *urb = td->urb;
731 if (!ring || !seg || !urb)
734 if (usb_urb_dir_out(urb)) {
735 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
740 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
742 /* for in tranfers we need to copy the data from bounce to sg */
743 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
744 seg->bounce_len, seg->bounce_offs);
745 if (len != seg->bounce_len)
746 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
747 len, seg->bounce_len);
749 seg->bounce_offs = 0;
752 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
753 struct xhci_ring *ep_ring, int *status)
755 struct urb *urb = NULL;
757 /* Clean up the endpoint's TD list */
760 /* if a bounce buffer was used to align this td then unmap it */
761 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
763 /* Do one last check of the actual transfer length.
764 * If the host controller said we transferred more data than the buffer
765 * length, urb->actual_length will be a very big number (since it's
766 * unsigned). Play it safe and say we didn't transfer anything.
768 if (urb->actual_length > urb->transfer_buffer_length) {
769 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
770 urb->transfer_buffer_length, urb->actual_length);
771 urb->actual_length = 0;
774 /* TD might be removed from td_list if we are giving back a cancelled URB */
775 if (!list_empty(&td->td_list))
776 list_del_init(&td->td_list);
777 /* Giving back a cancelled URB, or if a slated TD completed anyway */
778 if (!list_empty(&td->cancelled_td_list))
779 list_del_init(&td->cancelled_td_list);
782 /* Giveback the urb when all the tds are completed */
783 if (last_td_in_urb(td)) {
784 if ((urb->actual_length != urb->transfer_buffer_length &&
785 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
786 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
787 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
788 urb, urb->actual_length,
789 urb->transfer_buffer_length, *status);
791 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
792 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
794 xhci_giveback_urb_in_irq(xhci, td, *status);
800 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
801 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
803 struct xhci_command *command;
806 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
812 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
815 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
816 slot_id, ep_index, ret);
821 * When we get a command completion for a Stop Endpoint Command, we need to
822 * unlink any cancelled TDs from the ring. There are two ways to do that:
824 * 1. If the HW was in the middle of processing the TD that needs to be
825 * cancelled, then we must move the ring's dequeue pointer past the last TRB
826 * in the TD with a Set Dequeue Pointer Command.
827 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
828 * bit cleared) so that the HW will skip over them.
830 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
833 unsigned int ep_index;
834 struct xhci_ring *ep_ring;
835 struct xhci_virt_ep *ep;
836 struct xhci_td *cur_td = NULL;
837 struct xhci_td *last_unlinked_td;
838 struct xhci_ep_ctx *ep_ctx;
839 struct xhci_virt_device *vdev;
841 struct xhci_dequeue_state deq_state;
843 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
844 if (!xhci->devs[slot_id])
845 xhci_warn(xhci, "Stop endpoint command "
846 "completion for disabled slot %u\n",
851 memset(&deq_state, 0, sizeof(deq_state));
852 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
854 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
859 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
860 trace_xhci_handle_cmd_stop_ep(ep_ctx);
862 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
863 struct xhci_td, cancelled_td_list);
865 if (list_empty(&ep->cancelled_td_list)) {
866 xhci_stop_watchdog_timer_in_irq(xhci, ep);
867 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
871 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
872 * We have the xHCI lock, so nothing can modify this list until we drop
873 * it. We're also in the event handler, so we can't get re-interrupted
874 * if another Stop Endpoint command completes
876 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
877 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
878 "Removing canceled TD starting at 0x%llx (dma).",
879 (unsigned long long)xhci_trb_virt_to_dma(
880 cur_td->start_seg, cur_td->first_trb));
881 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
883 /* This shouldn't happen unless a driver is mucking
884 * with the stream ID after submission. This will
885 * leave the TD on the hardware ring, and the hardware
886 * will try to execute it, and may access a buffer
887 * that has already been freed. In the best case, the
888 * hardware will execute it, and the event handler will
889 * ignore the completion event for that TD, since it was
890 * removed from the td_list for that endpoint. In
891 * short, don't muck with the stream ID after
894 xhci_warn(xhci, "WARN Cancelled URB %p "
895 "has invalid stream ID %u.\n",
897 cur_td->urb->stream_id);
898 goto remove_finished_td;
901 * If we stopped on the TD we need to cancel, then we have to
902 * move the xHC endpoint ring dequeue pointer past this TD.
904 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
905 cur_td->urb->stream_id);
908 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
909 cur_td->last_trb, hw_deq, false)) {
910 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
911 cur_td->urb->stream_id,
914 td_to_noop(xhci, ep_ring, cur_td, false);
919 * The event handler won't see a completion for this TD anymore,
920 * so remove it from the endpoint ring's TD list. Keep it in
921 * the cancelled TD list for URB completion later.
923 list_del_init(&cur_td->td_list);
926 xhci_stop_watchdog_timer_in_irq(xhci, ep);
928 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
929 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
930 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
932 xhci_ring_cmd_db(xhci);
934 /* Otherwise ring the doorbell(s) to restart queued transfers */
935 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
939 * Drop the lock and complete the URBs in the cancelled TD list.
940 * New TDs to be cancelled might be added to the end of the list before
941 * we can complete all the URBs for the TDs we already unlinked.
942 * So stop when we've completed the URB for the last TD we unlinked.
945 cur_td = list_first_entry(&ep->cancelled_td_list,
946 struct xhci_td, cancelled_td_list);
947 list_del_init(&cur_td->cancelled_td_list);
949 /* Doesn't matter what we pass for status, since the core will
950 * just overwrite it (because the URB has been unlinked).
952 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
953 xhci_td_cleanup(xhci, cur_td, ep_ring, 0);
955 /* Stop processing the cancelled list if the watchdog timer is
958 if (xhci->xhc_state & XHCI_STATE_DYING)
960 } while (cur_td != last_unlinked_td);
962 /* Return to the event handler with xhci->lock re-acquired */
965 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
967 struct xhci_td *cur_td;
970 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
971 list_del_init(&cur_td->td_list);
973 if (!list_empty(&cur_td->cancelled_td_list))
974 list_del_init(&cur_td->cancelled_td_list);
976 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
978 inc_td_cnt(cur_td->urb);
979 if (last_td_in_urb(cur_td))
980 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
984 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
985 int slot_id, int ep_index)
987 struct xhci_td *cur_td;
989 struct xhci_virt_ep *ep;
990 struct xhci_ring *ring;
992 ep = &xhci->devs[slot_id]->eps[ep_index];
993 if ((ep->ep_state & EP_HAS_STREAMS) ||
994 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
997 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
999 ring = ep->stream_info->stream_rings[stream_id];
1003 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1004 "Killing URBs for slot ID %u, ep index %u, stream %u",
1005 slot_id, ep_index, stream_id);
1006 xhci_kill_ring_urbs(xhci, ring);
1012 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1013 "Killing URBs for slot ID %u, ep index %u",
1015 xhci_kill_ring_urbs(xhci, ring);
1018 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1019 cancelled_td_list) {
1020 list_del_init(&cur_td->cancelled_td_list);
1021 inc_td_cnt(cur_td->urb);
1023 if (last_td_in_urb(cur_td))
1024 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1029 * host controller died, register read returns 0xffffffff
1030 * Complete pending commands, mark them ABORTED.
1031 * URBs need to be given back as usb core might be waiting with device locks
1032 * held for the URBs to finish during device disconnect, blocking host remove.
1034 * Call with xhci->lock held.
1035 * lock is relased and re-acquired while giving back urb.
1037 void xhci_hc_died(struct xhci_hcd *xhci)
1041 if (xhci->xhc_state & XHCI_STATE_DYING)
1044 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1045 xhci->xhc_state |= XHCI_STATE_DYING;
1047 xhci_cleanup_command_queue(xhci);
1049 /* return any pending urbs, remove may be waiting for them */
1050 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1053 for (j = 0; j < 31; j++)
1054 xhci_kill_endpoint_urbs(xhci, i, j);
1057 /* inform usb core hc died if PCI remove isn't already handling it */
1058 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1059 usb_hc_died(xhci_to_hcd(xhci));
1062 /* Watchdog timer function for when a stop endpoint command fails to complete.
1063 * In this case, we assume the host controller is broken or dying or dead. The
1064 * host may still be completing some other events, so we have to be careful to
1065 * let the event ring handler and the URB dequeueing/enqueueing functions know
1066 * through xhci->state.
1068 * The timer may also fire if the host takes a very long time to respond to the
1069 * command, and the stop endpoint command completion handler cannot delete the
1070 * timer before the timer function is called. Another endpoint cancellation may
1071 * sneak in before the timer function can grab the lock, and that may queue
1072 * another stop endpoint command and add the timer back. So we cannot use a
1073 * simple flag to say whether there is a pending stop endpoint command for a
1074 * particular endpoint.
1076 * Instead we use a combination of that flag and checking if a new timer is
1079 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
1081 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
1082 struct xhci_hcd *xhci = ep->xhci;
1083 unsigned long flags;
1086 spin_lock_irqsave(&xhci->lock, flags);
1088 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1089 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1090 timer_pending(&ep->stop_cmd_timer)) {
1091 spin_unlock_irqrestore(&xhci->lock, flags);
1092 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1095 usbsts = readl(&xhci->op_regs->status);
1097 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1098 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(usbsts));
1100 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1105 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1106 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1107 * and try to recover a -ETIMEDOUT with a host controller reset
1111 spin_unlock_irqrestore(&xhci->lock, flags);
1112 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1113 "xHCI host controller is dead.");
1116 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1117 struct xhci_virt_device *dev,
1118 struct xhci_ring *ep_ring,
1119 unsigned int ep_index)
1121 union xhci_trb *dequeue_temp;
1122 int num_trbs_free_temp;
1123 bool revert = false;
1125 num_trbs_free_temp = ep_ring->num_trbs_free;
1126 dequeue_temp = ep_ring->dequeue;
1128 /* If we get two back-to-back stalls, and the first stalled transfer
1129 * ends just before a link TRB, the dequeue pointer will be left on
1130 * the link TRB by the code in the while loop. So we have to update
1131 * the dequeue pointer one segment further, or we'll jump off
1132 * the segment into la-la-land.
1134 if (trb_is_link(ep_ring->dequeue)) {
1135 ep_ring->deq_seg = ep_ring->deq_seg->next;
1136 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1139 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1140 /* We have more usable TRBs */
1141 ep_ring->num_trbs_free++;
1143 if (trb_is_link(ep_ring->dequeue)) {
1144 if (ep_ring->dequeue ==
1145 dev->eps[ep_index].queued_deq_ptr)
1147 ep_ring->deq_seg = ep_ring->deq_seg->next;
1148 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1150 if (ep_ring->dequeue == dequeue_temp) {
1157 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1158 ep_ring->num_trbs_free = num_trbs_free_temp;
1163 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1164 * we need to clear the set deq pending flag in the endpoint ring state, so that
1165 * the TD queueing code can ring the doorbell again. We also need to ring the
1166 * endpoint doorbell to restart the ring, but only if there aren't more
1167 * cancellations pending.
1169 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1170 union xhci_trb *trb, u32 cmd_comp_code)
1172 unsigned int ep_index;
1173 unsigned int stream_id;
1174 struct xhci_ring *ep_ring;
1175 struct xhci_virt_ep *ep;
1176 struct xhci_ep_ctx *ep_ctx;
1177 struct xhci_slot_ctx *slot_ctx;
1179 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1180 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1181 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1185 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1187 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1189 /* XXX: Harmless??? */
1193 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1194 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1195 trace_xhci_handle_cmd_set_deq(slot_ctx);
1196 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1198 if (cmd_comp_code != COMP_SUCCESS) {
1199 unsigned int ep_state;
1200 unsigned int slot_state;
1202 switch (cmd_comp_code) {
1203 case COMP_TRB_ERROR:
1204 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1206 case COMP_CONTEXT_STATE_ERROR:
1207 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1208 ep_state = GET_EP_CTX_STATE(ep_ctx);
1209 slot_state = le32_to_cpu(slot_ctx->dev_state);
1210 slot_state = GET_SLOT_STATE(slot_state);
1211 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1212 "Slot state = %u, EP state = %u",
1213 slot_state, ep_state);
1215 case COMP_SLOT_NOT_ENABLED_ERROR:
1216 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1220 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1224 /* OK what do we do now? The endpoint state is hosed, and we
1225 * should never get to this point if the synchronization between
1226 * queueing, and endpoint state are correct. This might happen
1227 * if the device gets disconnected after we've finished
1228 * cancelling URBs, which might not be an error...
1232 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1233 if (ep->ep_state & EP_HAS_STREAMS) {
1234 struct xhci_stream_ctx *ctx =
1235 &ep->stream_info->stream_ctx_array[stream_id];
1236 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1238 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1240 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1241 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1242 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1243 ep->queued_deq_ptr) == deq) {
1244 /* Update the ring's dequeue segment and dequeue pointer
1245 * to reflect the new position.
1247 update_ring_for_set_deq_completion(xhci, ep->vdev,
1250 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1251 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1252 ep->queued_deq_seg, ep->queued_deq_ptr);
1257 ep->ep_state &= ~SET_DEQ_PENDING;
1258 ep->queued_deq_seg = NULL;
1259 ep->queued_deq_ptr = NULL;
1260 /* Restart any rings with pending URBs */
1261 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1264 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1265 union xhci_trb *trb, u32 cmd_comp_code)
1267 struct xhci_virt_ep *ep;
1268 struct xhci_ep_ctx *ep_ctx;
1269 unsigned int ep_index;
1271 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1272 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1276 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1277 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1279 /* This command will only fail if the endpoint wasn't halted,
1280 * but we don't care.
1282 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1283 "Ignoring reset ep completion code of %u", cmd_comp_code);
1285 /* HW with the reset endpoint quirk needs to have a configure endpoint
1286 * command complete before the endpoint can be used. Queue that here
1287 * because the HW can't handle two commands being queued in a row.
1289 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1290 struct xhci_command *command;
1292 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1296 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1297 "Queueing configure endpoint command");
1298 xhci_queue_configure_endpoint(xhci, command,
1299 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1301 xhci_ring_cmd_db(xhci);
1303 /* Clear our internal halted state */
1304 ep->ep_state &= ~EP_HALTED;
1307 /* if this was a soft reset, then restart */
1308 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1309 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1312 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1313 struct xhci_command *command, u32 cmd_comp_code)
1315 if (cmd_comp_code == COMP_SUCCESS)
1316 command->slot_id = slot_id;
1318 command->slot_id = 0;
1321 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1323 struct xhci_virt_device *virt_dev;
1324 struct xhci_slot_ctx *slot_ctx;
1326 virt_dev = xhci->devs[slot_id];
1330 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1331 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1333 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1334 /* Delete default control endpoint resources */
1335 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1336 xhci_free_virt_device(xhci, slot_id);
1339 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1342 struct xhci_virt_device *virt_dev;
1343 struct xhci_input_control_ctx *ctrl_ctx;
1344 struct xhci_ep_ctx *ep_ctx;
1345 unsigned int ep_index;
1346 unsigned int ep_state;
1347 u32 add_flags, drop_flags;
1350 * Configure endpoint commands can come from the USB core
1351 * configuration or alt setting changes, or because the HW
1352 * needed an extra configure endpoint command after a reset
1353 * endpoint command or streams were being configured.
1354 * If the command was for a halted endpoint, the xHCI driver
1355 * is not waiting on the configure endpoint command.
1357 virt_dev = xhci->devs[slot_id];
1360 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1362 xhci_warn(xhci, "Could not get input context, bad type.\n");
1366 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1367 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1368 /* Input ctx add_flags are the endpoint index plus one */
1369 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1371 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1372 trace_xhci_handle_cmd_config_ep(ep_ctx);
1374 /* A usb_set_interface() call directly after clearing a halted
1375 * condition may race on this quirky hardware. Not worth
1376 * worrying about, since this is prototype hardware. Not sure
1377 * if this will work for streams, but streams support was
1378 * untested on this prototype.
1380 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1381 ep_index != (unsigned int) -1 &&
1382 add_flags - SLOT_FLAG == drop_flags) {
1383 ep_state = virt_dev->eps[ep_index].ep_state;
1384 if (!(ep_state & EP_HALTED))
1386 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1387 "Completed config ep cmd - "
1388 "last ep index = %d, state = %d",
1389 ep_index, ep_state);
1390 /* Clear internal halted state and restart ring(s) */
1391 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1392 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1398 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1400 struct xhci_virt_device *vdev;
1401 struct xhci_slot_ctx *slot_ctx;
1403 vdev = xhci->devs[slot_id];
1406 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1407 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1410 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1412 struct xhci_virt_device *vdev;
1413 struct xhci_slot_ctx *slot_ctx;
1415 vdev = xhci->devs[slot_id];
1417 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1421 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1422 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1424 xhci_dbg(xhci, "Completed reset device command.\n");
1427 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1428 struct xhci_event_cmd *event)
1430 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1431 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1434 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1435 "NEC firmware version %2x.%02x",
1436 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1437 NEC_FW_MINOR(le32_to_cpu(event->status)));
1440 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1442 list_del(&cmd->cmd_list);
1444 if (cmd->completion) {
1445 cmd->status = status;
1446 complete(cmd->completion);
1452 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1454 struct xhci_command *cur_cmd, *tmp_cmd;
1455 xhci->current_cmd = NULL;
1456 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1457 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1460 void xhci_handle_command_timeout(struct work_struct *work)
1462 struct xhci_hcd *xhci;
1463 unsigned long flags;
1466 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1468 spin_lock_irqsave(&xhci->lock, flags);
1471 * If timeout work is pending, or current_cmd is NULL, it means we
1472 * raced with command completion. Command is handled so just return.
1474 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1475 spin_unlock_irqrestore(&xhci->lock, flags);
1478 /* mark this command to be cancelled */
1479 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1481 /* Make sure command ring is running before aborting it */
1482 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1483 if (hw_ring_state == ~(u64)0) {
1485 goto time_out_completed;
1488 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1489 (hw_ring_state & CMD_RING_RUNNING)) {
1490 /* Prevent new doorbell, and start command abort */
1491 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1492 xhci_dbg(xhci, "Command timeout\n");
1493 xhci_abort_cmd_ring(xhci, flags);
1494 goto time_out_completed;
1497 /* host removed. Bail out */
1498 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1499 xhci_dbg(xhci, "host removed, ring start fail?\n");
1500 xhci_cleanup_command_queue(xhci);
1502 goto time_out_completed;
1505 /* command timeout on stopped ring, ring can't be aborted */
1506 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1507 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1510 spin_unlock_irqrestore(&xhci->lock, flags);
1514 static void handle_cmd_completion(struct xhci_hcd *xhci,
1515 struct xhci_event_cmd *event)
1517 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1519 dma_addr_t cmd_dequeue_dma;
1521 union xhci_trb *cmd_trb;
1522 struct xhci_command *cmd;
1525 if (slot_id >= MAX_HC_SLOTS) {
1526 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1530 cmd_dma = le64_to_cpu(event->cmd_trb);
1531 cmd_trb = xhci->cmd_ring->dequeue;
1533 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1535 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1538 * Check whether the completion event is for our internal kept
1541 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1543 "ERROR mismatched command completion event\n");
1547 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1549 cancel_delayed_work(&xhci->cmd_timer);
1551 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1553 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1554 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1555 complete_all(&xhci->cmd_ring_stop_completion);
1559 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1561 "Command completion event does not match command\n");
1566 * Host aborted the command ring, check if the current command was
1567 * supposed to be aborted, otherwise continue normally.
1568 * The command ring is stopped now, but the xHC will issue a Command
1569 * Ring Stopped event which will cause us to restart it.
1571 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1572 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1573 if (cmd->status == COMP_COMMAND_ABORTED) {
1574 if (xhci->current_cmd == cmd)
1575 xhci->current_cmd = NULL;
1580 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1582 case TRB_ENABLE_SLOT:
1583 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1585 case TRB_DISABLE_SLOT:
1586 xhci_handle_cmd_disable_slot(xhci, slot_id);
1589 if (!cmd->completion)
1590 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1592 case TRB_EVAL_CONTEXT:
1595 xhci_handle_cmd_addr_dev(xhci, slot_id);
1598 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1599 le32_to_cpu(cmd_trb->generic.field[3])));
1600 if (!cmd->completion)
1601 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb);
1604 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1605 le32_to_cpu(cmd_trb->generic.field[3])));
1606 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1609 /* Is this an aborted command turned to NO-OP? */
1610 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1611 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1614 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1615 le32_to_cpu(cmd_trb->generic.field[3])));
1616 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1619 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1620 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1622 slot_id = TRB_TO_SLOT_ID(
1623 le32_to_cpu(cmd_trb->generic.field[3]));
1624 xhci_handle_cmd_reset_dev(xhci, slot_id);
1626 case TRB_NEC_GET_FW:
1627 xhci_handle_cmd_nec_get_fw(xhci, event);
1630 /* Skip over unknown commands on the event ring */
1631 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1635 /* restart timer if this wasn't the last command */
1636 if (!list_is_singular(&xhci->cmd_list)) {
1637 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1638 struct xhci_command, cmd_list);
1639 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1640 } else if (xhci->current_cmd == cmd) {
1641 xhci->current_cmd = NULL;
1645 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1647 inc_deq(xhci, xhci->cmd_ring);
1650 static void handle_vendor_event(struct xhci_hcd *xhci,
1651 union xhci_trb *event, u32 trb_type)
1653 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1654 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1655 handle_cmd_completion(xhci, &event->event_cmd);
1658 static void handle_device_notification(struct xhci_hcd *xhci,
1659 union xhci_trb *event)
1662 struct usb_device *udev;
1664 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1665 if (!xhci->devs[slot_id]) {
1666 xhci_warn(xhci, "Device Notification event for "
1667 "unused slot %u\n", slot_id);
1671 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1673 udev = xhci->devs[slot_id]->udev;
1674 if (udev && udev->parent)
1675 usb_wakeup_notification(udev->parent, udev->portnum);
1679 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1681 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1682 * If a connection to a USB 1 device is followed by another connection
1683 * to a USB 2 device.
1685 * Reset the PHY after the USB device is disconnected if device speed
1686 * is less than HCD_USB3.
1687 * Retry the reset sequence max of 4 times checking the PLL lock status.
1690 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1692 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1694 u32 retry_count = 4;
1697 /* Assert PHY reset */
1698 writel(0x6F, hcd->regs + 0x1048);
1700 /* De-assert the PHY reset */
1701 writel(0x7F, hcd->regs + 0x1048);
1703 pll_lock_check = readl(hcd->regs + 0x1070);
1704 } while (!(pll_lock_check & 0x1) && --retry_count);
1707 static void handle_port_status(struct xhci_hcd *xhci,
1708 union xhci_trb *event)
1710 struct usb_hcd *hcd;
1712 u32 portsc, cmd_reg;
1715 unsigned int hcd_portnum;
1716 struct xhci_bus_state *bus_state;
1717 bool bogus_port_status = false;
1718 struct xhci_port *port;
1720 /* Port status change events always have a successful completion code */
1721 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1723 "WARN: xHC returned failed port status event\n");
1725 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1726 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1728 if ((port_id <= 0) || (port_id > max_ports)) {
1729 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1731 inc_deq(xhci, xhci->event_ring);
1735 port = &xhci->hw_ports[port_id - 1];
1736 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1737 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1739 bogus_port_status = true;
1743 /* We might get interrupts after shared_hcd is removed */
1744 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1745 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1746 bogus_port_status = true;
1750 hcd = port->rhub->hcd;
1751 bus_state = &port->rhub->bus_state;
1752 hcd_portnum = port->hcd_portnum;
1753 portsc = readl(port->addr);
1755 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1756 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1758 trace_xhci_handle_port_status(hcd_portnum, portsc);
1760 if (hcd->state == HC_STATE_SUSPENDED) {
1761 xhci_dbg(xhci, "resume root hub\n");
1762 usb_hcd_resume_root_hub(hcd);
1765 if (hcd->speed >= HCD_USB3 &&
1766 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1767 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1768 if (slot_id && xhci->devs[slot_id])
1769 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1772 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1773 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1775 cmd_reg = readl(&xhci->op_regs->command);
1776 if (!(cmd_reg & CMD_RUN)) {
1777 xhci_warn(xhci, "xHC is not running.\n");
1781 if (DEV_SUPERSPEED_ANY(portsc)) {
1782 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1783 /* Set a flag to say the port signaled remote wakeup,
1784 * so we can tell the difference between the end of
1785 * device and host initiated resume.
1787 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1788 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1789 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1790 xhci_set_link_state(xhci, port, XDEV_U0);
1791 /* Need to wait until the next link state change
1792 * indicates the device is actually in U0.
1794 bogus_port_status = true;
1796 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1797 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1798 bus_state->resume_done[hcd_portnum] = jiffies +
1799 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1800 set_bit(hcd_portnum, &bus_state->resuming_ports);
1801 /* Do the rest in GetPortStatus after resume time delay.
1802 * Avoid polling roothub status before that so that a
1803 * usb device auto-resume latency around ~40ms.
1805 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1806 mod_timer(&hcd->rh_timer,
1807 bus_state->resume_done[hcd_portnum]);
1808 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1809 bogus_port_status = true;
1813 if ((portsc & PORT_PLC) &&
1814 DEV_SUPERSPEED_ANY(portsc) &&
1815 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1816 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1817 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1818 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1819 complete(&bus_state->u3exit_done[hcd_portnum]);
1820 /* We've just brought the device into U0/1/2 through either the
1821 * Resume state after a device remote wakeup, or through the
1822 * U3Exit state after a host-initiated resume. If it's a device
1823 * initiated remote wake, don't pass up the link state change,
1824 * so the roothub behavior is consistent with external
1825 * USB 3.0 hub behavior.
1827 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1828 if (slot_id && xhci->devs[slot_id])
1829 xhci_ring_device(xhci, slot_id);
1830 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1831 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1832 usb_wakeup_notification(hcd->self.root_hub,
1834 bogus_port_status = true;
1840 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1841 * RExit to a disconnect state). If so, let the the driver know it's
1842 * out of the RExit state.
1844 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1845 test_and_clear_bit(hcd_portnum,
1846 &bus_state->rexit_ports)) {
1847 complete(&bus_state->rexit_done[hcd_portnum]);
1848 bogus_port_status = true;
1852 if (hcd->speed < HCD_USB3) {
1853 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1854 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1855 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1856 xhci_cavium_reset_phy_quirk(xhci);
1860 /* Update event ring dequeue pointer before dropping the lock */
1861 inc_deq(xhci, xhci->event_ring);
1863 /* Don't make the USB core poll the roothub if we got a bad port status
1864 * change event. Besides, at that point we can't tell which roothub
1865 * (USB 2.0 or USB 3.0) to kick.
1867 if (bogus_port_status)
1871 * xHCI port-status-change events occur when the "or" of all the
1872 * status-change bits in the portsc register changes from 0 to 1.
1873 * New status changes won't cause an event if any other change
1874 * bits are still set. When an event occurs, switch over to
1875 * polling to avoid losing status changes.
1877 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1878 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1879 spin_unlock(&xhci->lock);
1880 /* Pass this up to the core */
1881 usb_hcd_poll_rh_status(hcd);
1882 spin_lock(&xhci->lock);
1886 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1887 * at end_trb, which may be in another segment. If the suspect DMA address is a
1888 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1891 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1892 struct xhci_segment *start_seg,
1893 union xhci_trb *start_trb,
1894 union xhci_trb *end_trb,
1895 dma_addr_t suspect_dma,
1898 dma_addr_t start_dma;
1899 dma_addr_t end_seg_dma;
1900 dma_addr_t end_trb_dma;
1901 struct xhci_segment *cur_seg;
1903 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1904 cur_seg = start_seg;
1909 /* We may get an event for a Link TRB in the middle of a TD */
1910 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1911 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1912 /* If the end TRB isn't in this segment, this is set to 0 */
1913 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1917 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1918 (unsigned long long)suspect_dma,
1919 (unsigned long long)start_dma,
1920 (unsigned long long)end_trb_dma,
1921 (unsigned long long)cur_seg->dma,
1922 (unsigned long long)end_seg_dma);
1924 if (end_trb_dma > 0) {
1925 /* The end TRB is in this segment, so suspect should be here */
1926 if (start_dma <= end_trb_dma) {
1927 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1930 /* Case for one segment with
1931 * a TD wrapped around to the top
1933 if ((suspect_dma >= start_dma &&
1934 suspect_dma <= end_seg_dma) ||
1935 (suspect_dma >= cur_seg->dma &&
1936 suspect_dma <= end_trb_dma))
1941 /* Might still be somewhere in this segment */
1942 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1945 cur_seg = cur_seg->next;
1946 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1947 } while (cur_seg != start_seg);
1952 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1953 struct xhci_virt_ep *ep)
1956 * As part of low/full-speed endpoint-halt processing
1957 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1959 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1960 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1961 !(ep->ep_state & EP_CLEARING_TT)) {
1962 ep->ep_state |= EP_CLEARING_TT;
1963 td->urb->ep->hcpriv = td->urb->dev;
1964 if (usb_hub_clear_tt_buffer(td->urb))
1965 ep->ep_state &= ~EP_CLEARING_TT;
1969 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1970 struct xhci_virt_ep *ep, unsigned int stream_id,
1972 enum xhci_ep_reset_type reset_type)
1974 unsigned int slot_id = ep->vdev->slot_id;
1978 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1979 * Device will be reset soon to recover the link so don't do anything
1981 if (ep->vdev->flags & VDEV_PORT_ERROR)
1984 ep->ep_state |= EP_HALTED;
1986 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
1990 if (reset_type == EP_HARD_RESET) {
1991 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1992 xhci_cleanup_stalled_ring(xhci, slot_id, ep->ep_index, stream_id,
1995 xhci_ring_cmd_db(xhci);
1998 /* Check if an error has halted the endpoint ring. The class driver will
1999 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2000 * However, a babble and other errors also halt the endpoint ring, and the class
2001 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2002 * Ring Dequeue Pointer command manually.
2004 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2005 struct xhci_ep_ctx *ep_ctx,
2006 unsigned int trb_comp_code)
2008 /* TRB completion codes that may require a manual halt cleanup */
2009 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2010 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2011 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2012 /* The 0.95 spec says a babbling control endpoint
2013 * is not halted. The 0.96 spec says it is. Some HW
2014 * claims to be 0.95 compliant, but it halts the control
2015 * endpoint anyway. Check if a babble halted the
2018 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2024 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2026 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2027 /* Vendor defined "informational" completion code,
2028 * treat as not-an-error.
2030 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2032 xhci_dbg(xhci, "Treating code as success.\n");
2038 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2039 struct xhci_transfer_event *event,
2040 struct xhci_virt_ep *ep, int *status)
2042 struct xhci_ep_ctx *ep_ctx;
2043 struct xhci_ring *ep_ring;
2046 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2047 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2048 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2050 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2051 trb_comp_code == COMP_STOPPED ||
2052 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
2053 /* The Endpoint Stop Command completion will take care of any
2054 * stopped TDs. A stopped TD may be restarted, so don't update
2055 * the ring dequeue pointer or take this TD off any lists yet.
2059 if (trb_comp_code == COMP_STALL_ERROR ||
2060 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2063 * xhci internal endpoint state will go to a "halt" state for
2064 * any stall, including default control pipe protocol stall.
2065 * To clear the host side halt we need to issue a reset endpoint
2066 * command, followed by a set dequeue command to move past the
2068 * Class drivers clear the device side halt from a functional
2069 * stall later. Hub TT buffer should only be cleared for FS/LS
2070 * devices behind HS hubs for functional stalls.
2072 if ((ep->ep_index != 0) || (trb_comp_code != COMP_STALL_ERROR))
2073 xhci_clear_hub_tt_buffer(xhci, td, ep);
2074 xhci_cleanup_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2077 /* Update ring dequeue pointer */
2078 ep_ring->dequeue = td->last_trb;
2079 ep_ring->deq_seg = td->last_trb_seg;
2080 ep_ring->num_trbs_free += td->num_trbs - 1;
2081 inc_deq(xhci, ep_ring);
2084 return xhci_td_cleanup(xhci, td, ep_ring, status);
2087 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2088 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2089 union xhci_trb *stop_trb)
2092 union xhci_trb *trb = ring->dequeue;
2093 struct xhci_segment *seg = ring->deq_seg;
2095 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2096 if (!trb_is_noop(trb) && !trb_is_link(trb))
2097 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2103 * Process control tds, update urb status and actual_length.
2105 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2106 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2107 struct xhci_virt_ep *ep, int *status)
2109 struct xhci_ep_ctx *ep_ctx;
2111 u32 remaining, requested;
2114 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2115 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2116 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2117 requested = td->urb->transfer_buffer_length;
2118 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2120 switch (trb_comp_code) {
2122 if (trb_type != TRB_STATUS) {
2123 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2124 (trb_type == TRB_DATA) ? "data" : "setup");
2125 *status = -ESHUTDOWN;
2130 case COMP_SHORT_PACKET:
2133 case COMP_STOPPED_SHORT_PACKET:
2134 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2135 td->urb->actual_length = remaining;
2137 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2142 td->urb->actual_length = 0;
2146 td->urb->actual_length = requested - remaining;
2149 td->urb->actual_length = requested;
2152 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2156 case COMP_STOPPED_LENGTH_INVALID:
2159 if (!xhci_requires_manual_halt_cleanup(xhci,
2160 ep_ctx, trb_comp_code))
2162 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2163 trb_comp_code, ep->ep_index);
2165 case COMP_STALL_ERROR:
2166 /* Did we transfer part of the data (middle) phase? */
2167 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2168 td->urb->actual_length = requested - remaining;
2169 else if (!td->urb_length_set)
2170 td->urb->actual_length = 0;
2174 /* stopped at setup stage, no data transferred */
2175 if (trb_type == TRB_SETUP)
2179 * if on data stage then update the actual_length of the URB and flag it
2180 * as set, so it won't be overwritten in the event for the last TRB.
2182 if (trb_type == TRB_DATA ||
2183 trb_type == TRB_NORMAL) {
2184 td->urb_length_set = true;
2185 td->urb->actual_length = requested - remaining;
2186 xhci_dbg(xhci, "Waiting for status stage event\n");
2190 /* at status stage */
2191 if (!td->urb_length_set)
2192 td->urb->actual_length = requested;
2195 return finish_td(xhci, td, event, ep, status);
2199 * Process isochronous tds, update urb packet status and actual_length.
2201 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2202 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2203 struct xhci_virt_ep *ep, int *status)
2205 struct urb_priv *urb_priv;
2207 struct usb_iso_packet_descriptor *frame;
2209 bool sum_trbs_for_length = false;
2210 u32 remaining, requested, ep_trb_len;
2211 int short_framestatus;
2213 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2214 urb_priv = td->urb->hcpriv;
2215 idx = urb_priv->num_tds_done;
2216 frame = &td->urb->iso_frame_desc[idx];
2217 requested = frame->length;
2218 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2219 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2220 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2223 /* handle completion code */
2224 switch (trb_comp_code) {
2227 frame->status = short_framestatus;
2228 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2229 sum_trbs_for_length = true;
2234 case COMP_SHORT_PACKET:
2235 frame->status = short_framestatus;
2236 sum_trbs_for_length = true;
2238 case COMP_BANDWIDTH_OVERRUN_ERROR:
2239 frame->status = -ECOMM;
2241 case COMP_ISOCH_BUFFER_OVERRUN:
2242 case COMP_BABBLE_DETECTED_ERROR:
2243 frame->status = -EOVERFLOW;
2245 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2246 case COMP_STALL_ERROR:
2247 frame->status = -EPROTO;
2249 case COMP_USB_TRANSACTION_ERROR:
2250 frame->status = -EPROTO;
2251 if (ep_trb != td->last_trb)
2255 sum_trbs_for_length = true;
2257 case COMP_STOPPED_SHORT_PACKET:
2258 /* field normally containing residue now contains tranferred */
2259 frame->status = short_framestatus;
2260 requested = remaining;
2262 case COMP_STOPPED_LENGTH_INVALID:
2267 sum_trbs_for_length = true;
2272 if (sum_trbs_for_length)
2273 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2274 ep_trb_len - remaining;
2276 frame->actual_length = requested;
2278 td->urb->actual_length += frame->actual_length;
2280 return finish_td(xhci, td, event, ep, status);
2283 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2284 struct xhci_virt_ep *ep, int *status)
2286 struct urb_priv *urb_priv;
2287 struct usb_iso_packet_descriptor *frame;
2290 urb_priv = td->urb->hcpriv;
2291 idx = urb_priv->num_tds_done;
2292 frame = &td->urb->iso_frame_desc[idx];
2294 /* The transfer is partly done. */
2295 frame->status = -EXDEV;
2297 /* calc actual length */
2298 frame->actual_length = 0;
2300 /* Update ring dequeue pointer */
2301 ep->ring->dequeue = td->last_trb;
2302 ep->ring->deq_seg = td->last_trb_seg;
2303 ep->ring->num_trbs_free += td->num_trbs - 1;
2304 inc_deq(xhci, ep->ring);
2306 return xhci_td_cleanup(xhci, td, ep->ring, status);
2310 * Process bulk and interrupt tds, update urb status and actual_length.
2312 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2313 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2314 struct xhci_virt_ep *ep, int *status)
2316 struct xhci_slot_ctx *slot_ctx;
2317 struct xhci_ring *ep_ring;
2319 u32 remaining, requested, ep_trb_len;
2321 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2322 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2323 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2324 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2325 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2326 requested = td->urb->transfer_buffer_length;
2328 switch (trb_comp_code) {
2330 ep_ring->err_count = 0;
2331 /* handle success with untransferred data as short packet */
2332 if (ep_trb != td->last_trb || remaining) {
2333 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2334 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2335 td->urb->ep->desc.bEndpointAddress,
2336 requested, remaining);
2340 case COMP_SHORT_PACKET:
2341 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2342 td->urb->ep->desc.bEndpointAddress,
2343 requested, remaining);
2346 case COMP_STOPPED_SHORT_PACKET:
2347 td->urb->actual_length = remaining;
2349 case COMP_STOPPED_LENGTH_INVALID:
2350 /* stopped on ep trb with invalid length, exclude it */
2354 case COMP_USB_TRANSACTION_ERROR:
2355 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2356 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2359 xhci_cleanup_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2367 if (ep_trb == td->last_trb)
2368 td->urb->actual_length = requested - remaining;
2370 td->urb->actual_length =
2371 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2372 ep_trb_len - remaining;
2374 if (remaining > requested) {
2375 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2377 td->urb->actual_length = 0;
2379 return finish_td(xhci, td, event, ep, status);
2383 * If this function returns an error condition, it means it got a Transfer
2384 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2385 * At this point, the host controller is probably hosed and should be reset.
2387 static int handle_tx_event(struct xhci_hcd *xhci,
2388 struct xhci_transfer_event *event)
2390 struct xhci_virt_ep *ep;
2391 struct xhci_ring *ep_ring;
2392 unsigned int slot_id;
2394 struct xhci_td *td = NULL;
2395 dma_addr_t ep_trb_dma;
2396 struct xhci_segment *ep_seg;
2397 union xhci_trb *ep_trb;
2398 int status = -EINPROGRESS;
2399 struct xhci_ep_ctx *ep_ctx;
2400 struct list_head *tmp;
2403 bool handling_skipped_tds = false;
2405 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2406 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2407 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2408 ep_trb_dma = le64_to_cpu(event->buffer);
2410 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2412 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2416 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2417 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2419 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2421 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2426 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2428 switch (trb_comp_code) {
2429 case COMP_STALL_ERROR:
2430 case COMP_USB_TRANSACTION_ERROR:
2431 case COMP_INVALID_STREAM_TYPE_ERROR:
2432 case COMP_INVALID_STREAM_ID_ERROR:
2433 xhci_cleanup_halted_endpoint(xhci, ep, 0, NULL,
2436 case COMP_RING_UNDERRUN:
2437 case COMP_RING_OVERRUN:
2438 case COMP_STOPPED_LENGTH_INVALID:
2441 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2447 /* Count current td numbers if ep->skip is set */
2449 list_for_each(tmp, &ep_ring->td_list)
2453 /* Look for common error cases */
2454 switch (trb_comp_code) {
2455 /* Skip codes that require special handling depending on
2459 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2461 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2462 ep_ring->last_td_was_short)
2463 trb_comp_code = COMP_SHORT_PACKET;
2465 xhci_warn_ratelimited(xhci,
2466 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2469 case COMP_SHORT_PACKET:
2471 /* Completion codes for endpoint stopped state */
2473 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2476 case COMP_STOPPED_LENGTH_INVALID:
2478 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2481 case COMP_STOPPED_SHORT_PACKET:
2483 "Stopped with short packet transfer detected for slot %u ep %u\n",
2486 /* Completion codes for endpoint halted state */
2487 case COMP_STALL_ERROR:
2488 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2490 ep->ep_state |= EP_HALTED;
2493 case COMP_SPLIT_TRANSACTION_ERROR:
2494 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2498 case COMP_USB_TRANSACTION_ERROR:
2499 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2503 case COMP_BABBLE_DETECTED_ERROR:
2504 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2506 status = -EOVERFLOW;
2508 /* Completion codes for endpoint error state */
2509 case COMP_TRB_ERROR:
2511 "WARN: TRB error for slot %u ep %u on endpoint\n",
2515 /* completion codes not indicating endpoint state change */
2516 case COMP_DATA_BUFFER_ERROR:
2518 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2522 case COMP_BANDWIDTH_OVERRUN_ERROR:
2524 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2527 case COMP_ISOCH_BUFFER_OVERRUN:
2529 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2532 case COMP_RING_UNDERRUN:
2534 * When the Isoch ring is empty, the xHC will generate
2535 * a Ring Overrun Event for IN Isoch endpoint or Ring
2536 * Underrun Event for OUT Isoch endpoint.
2538 xhci_dbg(xhci, "underrun event on endpoint\n");
2539 if (!list_empty(&ep_ring->td_list))
2540 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2541 "still with TDs queued?\n",
2542 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2545 case COMP_RING_OVERRUN:
2546 xhci_dbg(xhci, "overrun event on endpoint\n");
2547 if (!list_empty(&ep_ring->td_list))
2548 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2549 "still with TDs queued?\n",
2550 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2553 case COMP_MISSED_SERVICE_ERROR:
2555 * When encounter missed service error, one or more isoc tds
2556 * may be missed by xHC.
2557 * Set skip flag of the ep_ring; Complete the missed tds as
2558 * short transfer when process the ep_ring next time.
2562 "Miss service interval error for slot %u ep %u, set skip flag\n",
2565 case COMP_NO_PING_RESPONSE_ERROR:
2568 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2572 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2573 /* needs disable slot command to recover */
2575 "WARN: detect an incompatible device for slot %u ep %u",
2580 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2585 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2586 trb_comp_code, slot_id, ep_index);
2591 /* This TRB should be in the TD at the head of this ring's
2594 if (list_empty(&ep_ring->td_list)) {
2596 * Don't print wanings if it's due to a stopped endpoint
2597 * generating an extra completion event if the device
2598 * was suspended. Or, a event for the last TRB of a
2599 * short TD we already got a short event for.
2600 * The short TD is already removed from the TD list.
2603 if (!(trb_comp_code == COMP_STOPPED ||
2604 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2605 ep_ring->last_td_was_short)) {
2606 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2607 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2612 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2615 if (trb_comp_code == COMP_STALL_ERROR ||
2616 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2618 xhci_cleanup_halted_endpoint(xhci, ep,
2626 /* We've skipped all the TDs on the ep ring when ep->skip set */
2627 if (ep->skip && td_num == 0) {
2629 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2634 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2639 /* Is this a TRB in the currently executing TD? */
2640 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2641 td->last_trb, ep_trb_dma, false);
2644 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2645 * is not in the current TD pointed by ep_ring->dequeue because
2646 * that the hardware dequeue pointer still at the previous TRB
2647 * of the current TD. The previous TRB maybe a Link TD or the
2648 * last TRB of the previous TD. The command completion handle
2649 * will take care the rest.
2651 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2652 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2658 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2659 /* Some host controllers give a spurious
2660 * successful event after a short transfer.
2663 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2664 ep_ring->last_td_was_short) {
2665 ep_ring->last_td_was_short = false;
2668 /* HC is busted, give up! */
2670 "ERROR Transfer event TRB DMA ptr not "
2671 "part of current TD ep_index %d "
2672 "comp_code %u\n", ep_index,
2674 trb_in_td(xhci, ep_ring->deq_seg,
2675 ep_ring->dequeue, td->last_trb,
2680 skip_isoc_td(xhci, td, ep, &status);
2683 if (trb_comp_code == COMP_SHORT_PACKET)
2684 ep_ring->last_td_was_short = true;
2686 ep_ring->last_td_was_short = false;
2690 "Found td. Clear skip flag for slot %u ep %u.\n",
2695 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2698 trace_xhci_handle_transfer(ep_ring,
2699 (struct xhci_generic_trb *) ep_trb);
2702 * No-op TRB could trigger interrupts in a case where
2703 * a URB was killed and a STALL_ERROR happens right
2704 * after the endpoint ring stopped. Reset the halted
2705 * endpoint. Otherwise, the endpoint remains stalled
2708 if (trb_is_noop(ep_trb)) {
2709 if (trb_comp_code == COMP_STALL_ERROR ||
2710 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2712 xhci_cleanup_halted_endpoint(xhci, ep,
2718 /* update the urb's actual_length and give back to the core */
2719 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2720 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2721 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2722 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2724 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2727 handling_skipped_tds = ep->skip &&
2728 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2729 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2732 * Do not update event ring dequeue pointer if we're in a loop
2733 * processing missed tds.
2735 if (!handling_skipped_tds)
2736 inc_deq(xhci, xhci->event_ring);
2739 * If ep->skip is set, it means there are missed tds on the
2740 * endpoint ring need to take care of.
2741 * Process them as short transfer until reach the td pointed by
2744 } while (handling_skipped_tds);
2749 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2750 (unsigned long long) xhci_trb_virt_to_dma(
2751 xhci->event_ring->deq_seg,
2752 xhci->event_ring->dequeue),
2753 lower_32_bits(le64_to_cpu(event->buffer)),
2754 upper_32_bits(le64_to_cpu(event->buffer)),
2755 le32_to_cpu(event->transfer_len),
2756 le32_to_cpu(event->flags));
2761 * This function handles all OS-owned events on the event ring. It may drop
2762 * xhci->lock between event processing (e.g. to pass up port status changes).
2763 * Returns >0 for "possibly more events to process" (caller should call again),
2764 * otherwise 0 if done. In future, <0 returns should indicate error code.
2766 static int xhci_handle_event(struct xhci_hcd *xhci)
2768 union xhci_trb *event;
2769 int update_ptrs = 1;
2773 /* Event ring hasn't been allocated yet. */
2774 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2775 xhci_err(xhci, "ERROR event ring not ready\n");
2779 event = xhci->event_ring->dequeue;
2780 /* Does the HC or OS own the TRB? */
2781 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2782 xhci->event_ring->cycle_state)
2785 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2788 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2789 * speculative reads of the event's flags/data below.
2792 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2793 /* FIXME: Handle more event types. */
2796 case TRB_COMPLETION:
2797 handle_cmd_completion(xhci, &event->event_cmd);
2799 case TRB_PORT_STATUS:
2800 handle_port_status(xhci, event);
2804 ret = handle_tx_event(xhci, &event->trans_event);
2809 handle_device_notification(xhci, event);
2812 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2813 handle_vendor_event(xhci, event, trb_type);
2815 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2817 /* Any of the above functions may drop and re-acquire the lock, so check
2818 * to make sure a watchdog timer didn't mark the host as non-responsive.
2820 if (xhci->xhc_state & XHCI_STATE_DYING) {
2821 xhci_dbg(xhci, "xHCI host dying, returning from "
2822 "event handler.\n");
2827 /* Update SW event ring dequeue pointer */
2828 inc_deq(xhci, xhci->event_ring);
2830 /* Are there more items on the event ring? Caller will call us again to
2837 * Update Event Ring Dequeue Pointer:
2838 * - When all events have finished
2839 * - To avoid "Event Ring Full Error" condition
2841 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2842 union xhci_trb *event_ring_deq)
2847 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2848 /* If necessary, update the HW's version of the event ring deq ptr. */
2849 if (event_ring_deq != xhci->event_ring->dequeue) {
2850 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2851 xhci->event_ring->dequeue);
2853 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2855 * Per 4.9.4, Software writes to the ERDP register shall
2856 * always advance the Event Ring Dequeue Pointer value.
2858 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2859 ((u64) deq & (u64) ~ERST_PTR_MASK))
2862 /* Update HC event ring dequeue pointer */
2863 temp_64 &= ERST_PTR_MASK;
2864 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2867 /* Clear the event handler busy flag (RW1C) */
2868 temp_64 |= ERST_EHB;
2869 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2873 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2874 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2875 * indicators of an event TRB error, but we check the status *first* to be safe.
2877 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2879 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2880 union xhci_trb *event_ring_deq;
2881 irqreturn_t ret = IRQ_NONE;
2882 unsigned long flags;
2887 spin_lock_irqsave(&xhci->lock, flags);
2888 /* Check if the xHC generated the interrupt, or the irq is shared */
2889 status = readl(&xhci->op_regs->status);
2890 if (status == ~(u32)0) {
2896 if (!(status & STS_EINT))
2899 if (status & STS_FATAL) {
2900 xhci_warn(xhci, "WARNING: Host System Error\n");
2907 * Clear the op reg interrupt status first,
2908 * so we can receive interrupts from other MSI-X interrupters.
2909 * Write 1 to clear the interrupt status.
2912 writel(status, &xhci->op_regs->status);
2914 if (!hcd->msi_enabled) {
2916 irq_pending = readl(&xhci->ir_set->irq_pending);
2917 irq_pending |= IMAN_IP;
2918 writel(irq_pending, &xhci->ir_set->irq_pending);
2921 if (xhci->xhc_state & XHCI_STATE_DYING ||
2922 xhci->xhc_state & XHCI_STATE_HALTED) {
2923 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2924 "Shouldn't IRQs be disabled?\n");
2925 /* Clear the event handler busy flag (RW1C);
2926 * the event ring should be empty.
2928 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2929 xhci_write_64(xhci, temp_64 | ERST_EHB,
2930 &xhci->ir_set->erst_dequeue);
2935 event_ring_deq = xhci->event_ring->dequeue;
2936 /* FIXME this should be a delayed service routine
2937 * that clears the EHB.
2939 while (xhci_handle_event(xhci) > 0) {
2940 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2942 xhci_update_erst_dequeue(xhci, event_ring_deq);
2946 xhci_update_erst_dequeue(xhci, event_ring_deq);
2950 spin_unlock_irqrestore(&xhci->lock, flags);
2955 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2957 return xhci_irq(hcd);
2960 /**** Endpoint Ring Operations ****/
2963 * Generic function for queueing a TRB on a ring.
2964 * The caller must have checked to make sure there's room on the ring.
2966 * @more_trbs_coming: Will you enqueue more TRBs before calling
2967 * prepare_transfer()?
2969 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2970 bool more_trbs_coming,
2971 u32 field1, u32 field2, u32 field3, u32 field4)
2973 struct xhci_generic_trb *trb;
2975 trb = &ring->enqueue->generic;
2976 trb->field[0] = cpu_to_le32(field1);
2977 trb->field[1] = cpu_to_le32(field2);
2978 trb->field[2] = cpu_to_le32(field3);
2979 /* make sure TRB is fully written before giving it to the controller */
2981 trb->field[3] = cpu_to_le32(field4);
2983 trace_xhci_queue_trb(ring, trb);
2985 inc_enq(xhci, ring, more_trbs_coming);
2989 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2990 * FIXME allocate segments if the ring is full.
2992 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2993 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2995 unsigned int num_trbs_needed;
2996 unsigned int link_trb_count = 0;
2998 /* Make sure the endpoint has been added to xHC schedule */
3000 case EP_STATE_DISABLED:
3002 * USB core changed config/interfaces without notifying us,
3003 * or hardware is reporting the wrong state.
3005 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3007 case EP_STATE_ERROR:
3008 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3009 /* FIXME event handling code for error needs to clear it */
3010 /* XXX not sure if this should be -ENOENT or not */
3012 case EP_STATE_HALTED:
3013 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3015 case EP_STATE_STOPPED:
3016 case EP_STATE_RUNNING:
3019 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3021 * FIXME issue Configure Endpoint command to try to get the HC
3022 * back into a known state.
3028 if (room_on_ring(xhci, ep_ring, num_trbs))
3031 if (ep_ring == xhci->cmd_ring) {
3032 xhci_err(xhci, "Do not support expand command ring\n");
3036 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3037 "ERROR no room on ep ring, try ring expansion");
3038 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3039 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3041 xhci_err(xhci, "Ring expansion failed\n");
3046 while (trb_is_link(ep_ring->enqueue)) {
3047 /* If we're not dealing with 0.95 hardware or isoc rings
3048 * on AMD 0.96 host, clear the chain bit.
3050 if (!xhci_link_trb_quirk(xhci) &&
3051 !(ep_ring->type == TYPE_ISOC &&
3052 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3053 ep_ring->enqueue->link.control &=
3054 cpu_to_le32(~TRB_CHAIN);
3056 ep_ring->enqueue->link.control |=
3057 cpu_to_le32(TRB_CHAIN);
3060 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3062 /* Toggle the cycle bit after the last ring segment. */
3063 if (link_trb_toggles_cycle(ep_ring->enqueue))
3064 ep_ring->cycle_state ^= 1;
3066 ep_ring->enq_seg = ep_ring->enq_seg->next;
3067 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3069 /* prevent infinite loop if all first trbs are link trbs */
3070 if (link_trb_count++ > ep_ring->num_segs) {
3071 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3076 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3077 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3084 static int prepare_transfer(struct xhci_hcd *xhci,
3085 struct xhci_virt_device *xdev,
3086 unsigned int ep_index,
3087 unsigned int stream_id,
3088 unsigned int num_trbs,
3090 unsigned int td_index,
3094 struct urb_priv *urb_priv;
3096 struct xhci_ring *ep_ring;
3097 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3099 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3102 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3107 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3108 num_trbs, mem_flags);
3112 urb_priv = urb->hcpriv;
3113 td = &urb_priv->td[td_index];
3115 INIT_LIST_HEAD(&td->td_list);
3116 INIT_LIST_HEAD(&td->cancelled_td_list);
3118 if (td_index == 0) {
3119 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3125 /* Add this TD to the tail of the endpoint ring's TD list */
3126 list_add_tail(&td->td_list, &ep_ring->td_list);
3127 td->start_seg = ep_ring->enq_seg;
3128 td->first_trb = ep_ring->enqueue;
3133 unsigned int count_trbs(u64 addr, u64 len)
3135 unsigned int num_trbs;
3137 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3145 static inline unsigned int count_trbs_needed(struct urb *urb)
3147 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3150 static unsigned int count_sg_trbs_needed(struct urb *urb)
3152 struct scatterlist *sg;
3153 unsigned int i, len, full_len, num_trbs = 0;
3155 full_len = urb->transfer_buffer_length;
3157 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3158 len = sg_dma_len(sg);
3159 num_trbs += count_trbs(sg_dma_address(sg), len);
3160 len = min_t(unsigned int, len, full_len);
3169 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3173 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3174 len = urb->iso_frame_desc[i].length;
3176 return count_trbs(addr, len);
3179 static void check_trb_math(struct urb *urb, int running_total)
3181 if (unlikely(running_total != urb->transfer_buffer_length))
3182 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3183 "queued %#x (%d), asked for %#x (%d)\n",
3185 urb->ep->desc.bEndpointAddress,
3186 running_total, running_total,
3187 urb->transfer_buffer_length,
3188 urb->transfer_buffer_length);
3191 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3192 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3193 struct xhci_generic_trb *start_trb)
3196 * Pass all the TRBs to the hardware at once and make sure this write
3201 start_trb->field[3] |= cpu_to_le32(start_cycle);
3203 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3204 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3207 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3208 struct xhci_ep_ctx *ep_ctx)
3213 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3214 ep_interval = urb->interval;
3216 /* Convert to microframes */
3217 if (urb->dev->speed == USB_SPEED_LOW ||
3218 urb->dev->speed == USB_SPEED_FULL)
3221 /* FIXME change this to a warning and a suggestion to use the new API
3222 * to set the polling interval (once the API is added).
3224 if (xhci_interval != ep_interval) {
3225 dev_dbg_ratelimited(&urb->dev->dev,
3226 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3227 ep_interval, ep_interval == 1 ? "" : "s",
3228 xhci_interval, xhci_interval == 1 ? "" : "s");
3229 urb->interval = xhci_interval;
3230 /* Convert back to frames for LS/FS devices */
3231 if (urb->dev->speed == USB_SPEED_LOW ||
3232 urb->dev->speed == USB_SPEED_FULL)
3238 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3239 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3240 * (comprised of sg list entries) can take several service intervals to
3243 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3244 struct urb *urb, int slot_id, unsigned int ep_index)
3246 struct xhci_ep_ctx *ep_ctx;
3248 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3249 check_interval(xhci, urb, ep_ctx);
3251 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3255 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3256 * packets remaining in the TD (*not* including this TRB).
3258 * Total TD packet count = total_packet_count =
3259 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3261 * Packets transferred up to and including this TRB = packets_transferred =
3262 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3264 * TD size = total_packet_count - packets_transferred
3266 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3267 * including this TRB, right shifted by 10
3269 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3270 * This is taken care of in the TRB_TD_SIZE() macro
3272 * The last TRB in a TD must have the TD size set to zero.
3274 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3275 int trb_buff_len, unsigned int td_total_len,
3276 struct urb *urb, bool more_trbs_coming)
3278 u32 maxp, total_packet_count;
3280 /* MTK xHCI 0.96 contains some features from 1.0 */
3281 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3282 return ((td_total_len - transferred) >> 10);
3284 /* One TRB with a zero-length data packet. */
3285 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3286 trb_buff_len == td_total_len)
3289 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3290 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3293 maxp = usb_endpoint_maxp(&urb->ep->desc);
3294 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3296 /* Queueing functions don't count the current TRB into transferred */
3297 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3301 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3302 u32 *trb_buff_len, struct xhci_segment *seg)
3304 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3305 unsigned int unalign;
3306 unsigned int max_pkt;
3310 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3311 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3313 /* we got lucky, last normal TRB data on segment is packet aligned */
3317 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3318 unalign, *trb_buff_len);
3320 /* is the last nornal TRB alignable by splitting it */
3321 if (*trb_buff_len > unalign) {
3322 *trb_buff_len -= unalign;
3323 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3328 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3329 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3330 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3332 new_buff_len = max_pkt - (enqd_len % max_pkt);
3334 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3335 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3337 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3338 if (usb_urb_dir_out(urb)) {
3339 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3340 seg->bounce_buf, new_buff_len, enqd_len);
3341 if (len != new_buff_len)
3343 "WARN Wrong bounce buffer write length: %zu != %d\n",
3345 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3346 max_pkt, DMA_TO_DEVICE);
3348 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3349 max_pkt, DMA_FROM_DEVICE);
3352 if (dma_mapping_error(dev, seg->bounce_dma)) {
3353 /* try without aligning. Some host controllers survive */
3354 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3357 *trb_buff_len = new_buff_len;
3358 seg->bounce_len = new_buff_len;
3359 seg->bounce_offs = enqd_len;
3361 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3366 /* This is very similar to what ehci-q.c qtd_fill() does */
3367 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3368 struct urb *urb, int slot_id, unsigned int ep_index)
3370 struct xhci_ring *ring;
3371 struct urb_priv *urb_priv;
3373 struct xhci_generic_trb *start_trb;
3374 struct scatterlist *sg = NULL;
3375 bool more_trbs_coming = true;
3376 bool need_zero_pkt = false;
3377 bool first_trb = true;
3378 unsigned int num_trbs;
3379 unsigned int start_cycle, num_sgs = 0;
3380 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3382 u32 field, length_field, remainder;
3383 u64 addr, send_addr;
3385 ring = xhci_urb_to_transfer_ring(xhci, urb);
3389 full_len = urb->transfer_buffer_length;
3390 /* If we have scatter/gather list, we use it. */
3391 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3392 num_sgs = urb->num_mapped_sgs;
3394 addr = (u64) sg_dma_address(sg);
3395 block_len = sg_dma_len(sg);
3396 num_trbs = count_sg_trbs_needed(urb);
3398 num_trbs = count_trbs_needed(urb);
3399 addr = (u64) urb->transfer_dma;
3400 block_len = full_len;
3402 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3403 ep_index, urb->stream_id,
3404 num_trbs, urb, 0, mem_flags);
3405 if (unlikely(ret < 0))
3408 urb_priv = urb->hcpriv;
3410 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3411 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3412 need_zero_pkt = true;
3414 td = &urb_priv->td[0];
3417 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3418 * until we've finished creating all the other TRBs. The ring's cycle
3419 * state may change as we enqueue the other TRBs, so save it too.
3421 start_trb = &ring->enqueue->generic;
3422 start_cycle = ring->cycle_state;
3425 /* Queue the TRBs, even if they are zero-length */
3426 for (enqd_len = 0; first_trb || enqd_len < full_len;
3427 enqd_len += trb_buff_len) {
3428 field = TRB_TYPE(TRB_NORMAL);
3430 /* TRB buffer should not cross 64KB boundaries */
3431 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3432 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3434 if (enqd_len + trb_buff_len > full_len)
3435 trb_buff_len = full_len - enqd_len;
3437 /* Don't change the cycle bit of the first TRB until later */
3440 if (start_cycle == 0)
3443 field |= ring->cycle_state;
3445 /* Chain all the TRBs together; clear the chain bit in the last
3446 * TRB to indicate it's the last TRB in the chain.
3448 if (enqd_len + trb_buff_len < full_len) {
3450 if (trb_is_link(ring->enqueue + 1)) {
3451 if (xhci_align_td(xhci, urb, enqd_len,
3454 send_addr = ring->enq_seg->bounce_dma;
3455 /* assuming TD won't span 2 segs */
3456 td->bounce_seg = ring->enq_seg;
3460 if (enqd_len + trb_buff_len >= full_len) {
3461 field &= ~TRB_CHAIN;
3463 more_trbs_coming = false;
3464 td->last_trb = ring->enqueue;
3465 td->last_trb_seg = ring->enq_seg;
3466 if (xhci_urb_suitable_for_idt(urb)) {
3467 memcpy(&send_addr, urb->transfer_buffer,
3469 le64_to_cpus(&send_addr);
3474 /* Only set interrupt on short packet for IN endpoints */
3475 if (usb_urb_dir_in(urb))
3478 /* Set the TRB length, TD size, and interrupter fields. */
3479 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3480 full_len, urb, more_trbs_coming);
3482 length_field = TRB_LEN(trb_buff_len) |
3483 TRB_TD_SIZE(remainder) |
3486 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3487 lower_32_bits(send_addr),
3488 upper_32_bits(send_addr),
3492 addr += trb_buff_len;
3493 sent_len = trb_buff_len;
3495 while (sg && sent_len >= block_len) {
3498 sent_len -= block_len;
3500 if (num_sgs != 0 && sg) {
3501 block_len = sg_dma_len(sg);
3502 addr = (u64) sg_dma_address(sg);
3506 block_len -= sent_len;
3510 if (need_zero_pkt) {
3511 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3512 ep_index, urb->stream_id,
3513 1, urb, 1, mem_flags);
3514 urb_priv->td[1].last_trb = ring->enqueue;
3515 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3516 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3517 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3518 urb_priv->td[1].num_trbs++;
3521 check_trb_math(urb, enqd_len);
3522 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3523 start_cycle, start_trb);
3527 /* Caller must have locked xhci->lock */
3528 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3529 struct urb *urb, int slot_id, unsigned int ep_index)
3531 struct xhci_ring *ep_ring;
3534 struct usb_ctrlrequest *setup;
3535 struct xhci_generic_trb *start_trb;
3538 struct urb_priv *urb_priv;
3541 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3546 * Need to copy setup packet into setup TRB, so we can't use the setup
3549 if (!urb->setup_packet)
3552 /* 1 TRB for setup, 1 for status */
3555 * Don't need to check if we need additional event data and normal TRBs,
3556 * since data in control transfers will never get bigger than 16MB
3557 * XXX: can we get a buffer that crosses 64KB boundaries?
3559 if (urb->transfer_buffer_length > 0)
3561 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3562 ep_index, urb->stream_id,
3563 num_trbs, urb, 0, mem_flags);
3567 urb_priv = urb->hcpriv;
3568 td = &urb_priv->td[0];
3569 td->num_trbs = num_trbs;
3572 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3573 * until we've finished creating all the other TRBs. The ring's cycle
3574 * state may change as we enqueue the other TRBs, so save it too.
3576 start_trb = &ep_ring->enqueue->generic;
3577 start_cycle = ep_ring->cycle_state;
3579 /* Queue setup TRB - see section 6.4.1.2.1 */
3580 /* FIXME better way to translate setup_packet into two u32 fields? */
3581 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3583 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3584 if (start_cycle == 0)
3587 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3588 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3589 if (urb->transfer_buffer_length > 0) {
3590 if (setup->bRequestType & USB_DIR_IN)
3591 field |= TRB_TX_TYPE(TRB_DATA_IN);
3593 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3597 queue_trb(xhci, ep_ring, true,
3598 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3599 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3600 TRB_LEN(8) | TRB_INTR_TARGET(0),
3601 /* Immediate data in pointer */
3604 /* If there's data, queue data TRBs */
3605 /* Only set interrupt on short packet for IN endpoints */
3606 if (usb_urb_dir_in(urb))
3607 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3609 field = TRB_TYPE(TRB_DATA);
3611 if (urb->transfer_buffer_length > 0) {
3612 u32 length_field, remainder;
3615 if (xhci_urb_suitable_for_idt(urb)) {
3616 memcpy(&addr, urb->transfer_buffer,
3617 urb->transfer_buffer_length);
3618 le64_to_cpus(&addr);
3621 addr = (u64) urb->transfer_dma;
3624 remainder = xhci_td_remainder(xhci, 0,
3625 urb->transfer_buffer_length,
3626 urb->transfer_buffer_length,
3628 length_field = TRB_LEN(urb->transfer_buffer_length) |
3629 TRB_TD_SIZE(remainder) |
3631 if (setup->bRequestType & USB_DIR_IN)
3632 field |= TRB_DIR_IN;
3633 queue_trb(xhci, ep_ring, true,
3634 lower_32_bits(addr),
3635 upper_32_bits(addr),
3637 field | ep_ring->cycle_state);
3640 /* Save the DMA address of the last TRB in the TD */
3641 td->last_trb = ep_ring->enqueue;
3642 td->last_trb_seg = ep_ring->enq_seg;
3644 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3645 /* If the device sent data, the status stage is an OUT transfer */
3646 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3650 queue_trb(xhci, ep_ring, false,
3654 /* Event on completion */
3655 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3657 giveback_first_trb(xhci, slot_id, ep_index, 0,
3658 start_cycle, start_trb);
3663 * The transfer burst count field of the isochronous TRB defines the number of
3664 * bursts that are required to move all packets in this TD. Only SuperSpeed
3665 * devices can burst up to bMaxBurst number of packets per service interval.
3666 * This field is zero based, meaning a value of zero in the field means one
3667 * burst. Basically, for everything but SuperSpeed devices, this field will be
3668 * zero. Only xHCI 1.0 host controllers support this field.
3670 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3671 struct urb *urb, unsigned int total_packet_count)
3673 unsigned int max_burst;
3675 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3678 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3679 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3683 * Returns the number of packets in the last "burst" of packets. This field is
3684 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3685 * the last burst packet count is equal to the total number of packets in the
3686 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3687 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3688 * contain 1 to (bMaxBurst + 1) packets.
3690 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3691 struct urb *urb, unsigned int total_packet_count)
3693 unsigned int max_burst;
3694 unsigned int residue;
3696 if (xhci->hci_version < 0x100)
3699 if (urb->dev->speed >= USB_SPEED_SUPER) {
3700 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3701 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3702 residue = total_packet_count % (max_burst + 1);
3703 /* If residue is zero, the last burst contains (max_burst + 1)
3704 * number of packets, but the TLBPC field is zero-based.
3710 if (total_packet_count == 0)
3712 return total_packet_count - 1;
3716 * Calculates Frame ID field of the isochronous TRB identifies the
3717 * target frame that the Interval associated with this Isochronous
3718 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3720 * Returns actual frame id on success, negative value on error.
3722 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3723 struct urb *urb, int index)
3725 int start_frame, ist, ret = 0;
3726 int start_frame_id, end_frame_id, current_frame_id;
3728 if (urb->dev->speed == USB_SPEED_LOW ||
3729 urb->dev->speed == USB_SPEED_FULL)
3730 start_frame = urb->start_frame + index * urb->interval;
3732 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3734 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3736 * If bit [3] of IST is cleared to '0', software can add a TRB no
3737 * later than IST[2:0] Microframes before that TRB is scheduled to
3739 * If bit [3] of IST is set to '1', software can add a TRB no later
3740 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3742 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3743 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3746 /* Software shall not schedule an Isoch TD with a Frame ID value that
3747 * is less than the Start Frame ID or greater than the End Frame ID,
3750 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3751 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3753 * Both the End Frame ID and Start Frame ID values are calculated
3754 * in microframes. When software determines the valid Frame ID value;
3755 * The End Frame ID value should be rounded down to the nearest Frame
3756 * boundary, and the Start Frame ID value should be rounded up to the
3757 * nearest Frame boundary.
3759 current_frame_id = readl(&xhci->run_regs->microframe_index);
3760 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3761 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3763 start_frame &= 0x7ff;
3764 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3765 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3767 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3768 __func__, index, readl(&xhci->run_regs->microframe_index),
3769 start_frame_id, end_frame_id, start_frame);
3771 if (start_frame_id < end_frame_id) {
3772 if (start_frame > end_frame_id ||
3773 start_frame < start_frame_id)
3775 } else if (start_frame_id > end_frame_id) {
3776 if ((start_frame > end_frame_id &&
3777 start_frame < start_frame_id))
3784 if (ret == -EINVAL || start_frame == start_frame_id) {
3785 start_frame = start_frame_id + 1;
3786 if (urb->dev->speed == USB_SPEED_LOW ||
3787 urb->dev->speed == USB_SPEED_FULL)
3788 urb->start_frame = start_frame;
3790 urb->start_frame = start_frame << 3;
3796 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3797 start_frame, current_frame_id, index,
3798 start_frame_id, end_frame_id);
3799 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3806 /* Check if we should generate event interrupt for a TD in an isoc URB */
3807 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3809 if (xhci->hci_version < 0x100)
3811 /* always generate an event interrupt for the last TD */
3812 if (i == num_tds - 1)
3815 * If AVOID_BEI is set the host handles full event rings poorly,
3816 * generate an event at least every 8th TD to clear the event ring
3818 if (i && xhci->quirks & XHCI_AVOID_BEI)
3824 /* This is for isoc transfer */
3825 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3826 struct urb *urb, int slot_id, unsigned int ep_index)
3828 struct xhci_ring *ep_ring;
3829 struct urb_priv *urb_priv;
3831 int num_tds, trbs_per_td;
3832 struct xhci_generic_trb *start_trb;
3835 u32 field, length_field;
3836 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3837 u64 start_addr, addr;
3839 bool more_trbs_coming;
3840 struct xhci_virt_ep *xep;
3843 xep = &xhci->devs[slot_id]->eps[ep_index];
3844 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3846 num_tds = urb->number_of_packets;
3848 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3851 start_addr = (u64) urb->transfer_dma;
3852 start_trb = &ep_ring->enqueue->generic;
3853 start_cycle = ep_ring->cycle_state;
3855 urb_priv = urb->hcpriv;
3856 /* Queue the TRBs for each TD, even if they are zero-length */
3857 for (i = 0; i < num_tds; i++) {
3858 unsigned int total_pkt_count, max_pkt;
3859 unsigned int burst_count, last_burst_pkt_count;
3864 addr = start_addr + urb->iso_frame_desc[i].offset;
3865 td_len = urb->iso_frame_desc[i].length;
3866 td_remain_len = td_len;
3867 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3868 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3870 /* A zero-length transfer still involves at least one packet. */
3871 if (total_pkt_count == 0)
3873 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3874 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3875 urb, total_pkt_count);
3877 trbs_per_td = count_isoc_trbs_needed(urb, i);
3879 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3880 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3886 td = &urb_priv->td[i];
3887 td->num_trbs = trbs_per_td;
3888 /* use SIA as default, if frame id is used overwrite it */
3889 sia_frame_id = TRB_SIA;
3890 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3891 HCC_CFC(xhci->hcc_params)) {
3892 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3894 sia_frame_id = TRB_FRAME_ID(frame_id);
3897 * Set isoc specific data for the first TRB in a TD.
3898 * Prevent HW from getting the TRBs by keeping the cycle state
3899 * inverted in the first TDs isoc TRB.
3901 field = TRB_TYPE(TRB_ISOC) |
3902 TRB_TLBPC(last_burst_pkt_count) |
3904 (i ? ep_ring->cycle_state : !start_cycle);
3906 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3907 if (!xep->use_extended_tbc)
3908 field |= TRB_TBC(burst_count);
3910 /* fill the rest of the TRB fields, and remaining normal TRBs */
3911 for (j = 0; j < trbs_per_td; j++) {
3914 /* only first TRB is isoc, overwrite otherwise */
3916 field = TRB_TYPE(TRB_NORMAL) |
3917 ep_ring->cycle_state;
3919 /* Only set interrupt on short packet for IN EPs */
3920 if (usb_urb_dir_in(urb))
3923 /* Set the chain bit for all except the last TRB */
3924 if (j < trbs_per_td - 1) {
3925 more_trbs_coming = true;
3928 more_trbs_coming = false;
3929 td->last_trb = ep_ring->enqueue;
3930 td->last_trb_seg = ep_ring->enq_seg;
3932 if (trb_block_event_intr(xhci, num_tds, i))
3935 /* Calculate TRB length */
3936 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3937 if (trb_buff_len > td_remain_len)
3938 trb_buff_len = td_remain_len;
3940 /* Set the TRB length, TD size, & interrupter fields. */
3941 remainder = xhci_td_remainder(xhci, running_total,
3942 trb_buff_len, td_len,
3943 urb, more_trbs_coming);
3945 length_field = TRB_LEN(trb_buff_len) |
3948 /* xhci 1.1 with ETE uses TD Size field for TBC */
3949 if (first_trb && xep->use_extended_tbc)
3950 length_field |= TRB_TD_SIZE_TBC(burst_count);
3952 length_field |= TRB_TD_SIZE(remainder);
3955 queue_trb(xhci, ep_ring, more_trbs_coming,
3956 lower_32_bits(addr),
3957 upper_32_bits(addr),
3960 running_total += trb_buff_len;
3962 addr += trb_buff_len;
3963 td_remain_len -= trb_buff_len;
3966 /* Check TD length */
3967 if (running_total != td_len) {
3968 xhci_err(xhci, "ISOC TD length unmatch\n");
3974 /* store the next frame id */
3975 if (HCC_CFC(xhci->hcc_params))
3976 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3978 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3979 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3980 usb_amd_quirk_pll_disable();
3982 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3984 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3985 start_cycle, start_trb);
3988 /* Clean up a partially enqueued isoc transfer. */
3990 for (i--; i >= 0; i--)
3991 list_del_init(&urb_priv->td[i].td_list);
3993 /* Use the first TD as a temporary variable to turn the TDs we've queued
3994 * into No-ops with a software-owned cycle bit. That way the hardware
3995 * won't accidentally start executing bogus TDs when we partially
3996 * overwrite them. td->first_trb and td->start_seg are already set.
3998 urb_priv->td[0].last_trb = ep_ring->enqueue;
3999 /* Every TRB except the first & last will have its cycle bit flipped. */
4000 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4002 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4003 ep_ring->enqueue = urb_priv->td[0].first_trb;
4004 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4005 ep_ring->cycle_state = start_cycle;
4006 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4007 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4012 * Check transfer ring to guarantee there is enough room for the urb.
4013 * Update ISO URB start_frame and interval.
4014 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4015 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4016 * Contiguous Frame ID is not supported by HC.
4018 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4019 struct urb *urb, int slot_id, unsigned int ep_index)
4021 struct xhci_virt_device *xdev;
4022 struct xhci_ring *ep_ring;
4023 struct xhci_ep_ctx *ep_ctx;
4025 int num_tds, num_trbs, i;
4027 struct xhci_virt_ep *xep;
4030 xdev = xhci->devs[slot_id];
4031 xep = &xhci->devs[slot_id]->eps[ep_index];
4032 ep_ring = xdev->eps[ep_index].ring;
4033 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4036 num_tds = urb->number_of_packets;
4037 for (i = 0; i < num_tds; i++)
4038 num_trbs += count_isoc_trbs_needed(urb, i);
4040 /* Check the ring to guarantee there is enough room for the whole urb.
4041 * Do not insert any td of the urb to the ring if the check failed.
4043 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4044 num_trbs, mem_flags);
4049 * Check interval value. This should be done before we start to
4050 * calculate the start frame value.
4052 check_interval(xhci, urb, ep_ctx);
4054 /* Calculate the start frame and put it in urb->start_frame. */
4055 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4056 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4057 urb->start_frame = xep->next_frame_id;
4058 goto skip_start_over;
4062 start_frame = readl(&xhci->run_regs->microframe_index);
4063 start_frame &= 0x3fff;
4065 * Round up to the next frame and consider the time before trb really
4066 * gets scheduled by hardare.
4068 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4069 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4071 start_frame += ist + XHCI_CFC_DELAY;
4072 start_frame = roundup(start_frame, 8);
4075 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4076 * is greate than 8 microframes.
4078 if (urb->dev->speed == USB_SPEED_LOW ||
4079 urb->dev->speed == USB_SPEED_FULL) {
4080 start_frame = roundup(start_frame, urb->interval << 3);
4081 urb->start_frame = start_frame >> 3;
4083 start_frame = roundup(start_frame, urb->interval);
4084 urb->start_frame = start_frame;
4088 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4090 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4093 /**** Command Ring Operations ****/
4095 /* Generic function for queueing a command TRB on the command ring.
4096 * Check to make sure there's room on the command ring for one command TRB.
4097 * Also check that there's room reserved for commands that must not fail.
4098 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4099 * then only check for the number of reserved spots.
4100 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4101 * because the command event handler may want to resubmit a failed command.
4103 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4104 u32 field1, u32 field2,
4105 u32 field3, u32 field4, bool command_must_succeed)
4107 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4110 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4111 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4112 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4116 if (!command_must_succeed)
4119 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4120 reserved_trbs, GFP_ATOMIC);
4122 xhci_err(xhci, "ERR: No room for command on command ring\n");
4123 if (command_must_succeed)
4124 xhci_err(xhci, "ERR: Reserved TRB counting for "
4125 "unfailable commands failed.\n");
4129 cmd->command_trb = xhci->cmd_ring->enqueue;
4131 /* if there are no other commands queued we start the timeout timer */
4132 if (list_empty(&xhci->cmd_list)) {
4133 xhci->current_cmd = cmd;
4134 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4137 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4139 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4140 field4 | xhci->cmd_ring->cycle_state);
4144 /* Queue a slot enable or disable request on the command ring */
4145 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4146 u32 trb_type, u32 slot_id)
4148 return queue_command(xhci, cmd, 0, 0, 0,
4149 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4152 /* Queue an address device command TRB */
4153 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4154 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4156 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4157 upper_32_bits(in_ctx_ptr), 0,
4158 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4159 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4162 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4163 u32 field1, u32 field2, u32 field3, u32 field4)
4165 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4168 /* Queue a reset device command TRB */
4169 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4172 return queue_command(xhci, cmd, 0, 0, 0,
4173 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4177 /* Queue a configure endpoint command TRB */
4178 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4179 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4180 u32 slot_id, bool command_must_succeed)
4182 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4183 upper_32_bits(in_ctx_ptr), 0,
4184 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4185 command_must_succeed);
4188 /* Queue an evaluate context command TRB */
4189 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4190 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4192 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4193 upper_32_bits(in_ctx_ptr), 0,
4194 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4195 command_must_succeed);
4199 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4200 * activity on an endpoint that is about to be suspended.
4202 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4203 int slot_id, unsigned int ep_index, int suspend)
4205 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4206 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4207 u32 type = TRB_TYPE(TRB_STOP_RING);
4208 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4210 return queue_command(xhci, cmd, 0, 0, 0,
4211 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4214 /* Set Transfer Ring Dequeue Pointer command */
4215 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4216 unsigned int slot_id, unsigned int ep_index,
4217 struct xhci_dequeue_state *deq_state)
4220 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4221 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4222 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4224 u32 type = TRB_TYPE(TRB_SET_DEQ);
4225 struct xhci_virt_ep *ep;
4226 struct xhci_command *cmd;
4229 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4230 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4231 deq_state->new_deq_seg,
4232 (unsigned long long)deq_state->new_deq_seg->dma,
4233 deq_state->new_deq_ptr,
4234 (unsigned long long)xhci_trb_virt_to_dma(
4235 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4236 deq_state->new_cycle_state);
4238 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4239 deq_state->new_deq_ptr);
4241 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4242 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4243 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4246 ep = &xhci->devs[slot_id]->eps[ep_index];
4247 if ((ep->ep_state & SET_DEQ_PENDING)) {
4248 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4249 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4253 /* This function gets called from contexts where it cannot sleep */
4254 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4258 ep->queued_deq_seg = deq_state->new_deq_seg;
4259 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4260 if (deq_state->stream_id)
4261 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4262 ret = queue_command(xhci, cmd,
4263 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4264 upper_32_bits(addr), trb_stream_id,
4265 trb_slot_id | trb_ep_index | type, false);
4267 xhci_free_command(xhci, cmd);
4271 /* Stop the TD queueing code from ringing the doorbell until
4272 * this command completes. The HC won't set the dequeue pointer
4273 * if the ring is running, and ringing the doorbell starts the
4276 ep->ep_state |= SET_DEQ_PENDING;
4279 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4280 int slot_id, unsigned int ep_index,
4281 enum xhci_ep_reset_type reset_type)
4283 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4284 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4285 u32 type = TRB_TYPE(TRB_RESET_EP);
4287 if (reset_type == EP_SOFT_RESET)
4290 return queue_command(xhci, cmd, 0, 0, 0,
4291 trb_slot_id | trb_ep_index | type, false);